hda_intel.c 66.4 KB
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/*
 *
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 *  hda_intel.c - Implementation of primary alsa driver code base
 *                for Intel HD Audio.
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 *
 *  Copyright(c) 2004 Intel Corporation. All rights reserved.
 *
 *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
 *                     PeiSen Hou <pshou@realtek.com.tw>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the Free
 *  Software Foundation; either version 2 of the License, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *
 *  You should have received a copy of the GNU General Public License along with
 *  this program; if not, write to the Free Software Foundation, Inc., 59
 *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 *  CONTACTS:
 *
 *  Matt Jared		matt.jared@intel.com
 *  Andy Kopp		andy.kopp@intel.com
 *  Dan Kogan		dan.d.kogan@intel.com
 *
 *  CHANGES:
 *
 *  2004.12.01	Major rewrite by tiwai, merged the work of pshou
 * 
 */

#include <asm/io.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/dma-mapping.h>
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#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/pci.h>
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#include <linux/mutex.h>
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#include <linux/reboot.h>
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#include <sound/core.h>
#include <sound/initval.h>
#include "hda_codec.h"


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static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
static char *model[SNDRV_CARDS];
static int position_fix[SNDRV_CARDS];
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static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
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static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
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static int probe_only[SNDRV_CARDS];
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static int single_cmd;
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static int enable_msi;
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module_param_array(index, int, NULL, 0444);
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MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
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module_param_array(id, charp, NULL, 0444);
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MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
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module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
module_param_array(model, charp, NULL, 0444);
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MODULE_PARM_DESC(model, "Use the given board model.");
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module_param_array(position_fix, int, NULL, 0444);
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MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
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		 "(0 = auto, 1 = none, 2 = POSBUF).");
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module_param_array(bdl_pos_adj, int, NULL, 0644);
MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
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module_param_array(probe_mask, int, NULL, 0444);
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MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
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module_param_array(probe_only, bool, NULL, 0444);
MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
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module_param(single_cmd, bool, 0444);
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MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
		 "(for debugging only).");
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module_param(enable_msi, int, 0444);
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MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
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#ifdef CONFIG_SND_HDA_POWER_SAVE
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static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
module_param(power_save, int, 0644);
MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
		 "(in second, 0 = disable).");
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/* reset the HD-audio controller in power save mode.
 * this may give more power-saving, but will take longer time to
 * wake up.
 */
static int power_save_controller = 1;
module_param(power_save_controller, bool, 0644);
MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
#endif

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MODULE_LICENSE("GPL");
MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
			 "{Intel, ICH6M},"
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			 "{Intel, ICH7},"
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			 "{Intel, ESB2},"
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			 "{Intel, ICH8},"
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			 "{Intel, ICH9},"
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			 "{Intel, ICH10},"
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			 "{Intel, PCH},"
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			 "{Intel, SCH},"
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			 "{ATI, SB450},"
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			 "{ATI, SB600},"
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			 "{ATI, RS600},"
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			 "{ATI, RS690},"
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			 "{ATI, RS780},"
			 "{ATI, R600},"
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			 "{ATI, RV630},"
			 "{ATI, RV610},"
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			 "{ATI, RV670},"
			 "{ATI, RV635},"
			 "{ATI, RV620},"
			 "{ATI, RV770},"
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			 "{VIA, VT8251},"
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			 "{VIA, VT8237A},"
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			 "{SiS, SIS966},"
			 "{ULI, M5461}}");
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MODULE_DESCRIPTION("Intel HDA driver");

#define SFX	"hda-intel: "

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/*
 * registers
 */
#define ICH6_REG_GCAP			0x00
#define ICH6_REG_VMIN			0x02
#define ICH6_REG_VMAJ			0x03
#define ICH6_REG_OUTPAY			0x04
#define ICH6_REG_INPAY			0x06
#define ICH6_REG_GCTL			0x08
#define ICH6_REG_WAKEEN			0x0c
#define ICH6_REG_STATESTS		0x0e
#define ICH6_REG_GSTS			0x10
#define ICH6_REG_INTCTL			0x20
#define ICH6_REG_INTSTS			0x24
#define ICH6_REG_WALCLK			0x30
#define ICH6_REG_SYNC			0x34	
#define ICH6_REG_CORBLBASE		0x40
#define ICH6_REG_CORBUBASE		0x44
#define ICH6_REG_CORBWP			0x48
#define ICH6_REG_CORBRP			0x4A
#define ICH6_REG_CORBCTL		0x4c
#define ICH6_REG_CORBSTS		0x4d
#define ICH6_REG_CORBSIZE		0x4e

#define ICH6_REG_RIRBLBASE		0x50
#define ICH6_REG_RIRBUBASE		0x54
#define ICH6_REG_RIRBWP			0x58
#define ICH6_REG_RINTCNT		0x5a
#define ICH6_REG_RIRBCTL		0x5c
#define ICH6_REG_RIRBSTS		0x5d
#define ICH6_REG_RIRBSIZE		0x5e

#define ICH6_REG_IC			0x60
#define ICH6_REG_IR			0x64
#define ICH6_REG_IRS			0x68
#define   ICH6_IRS_VALID	(1<<1)
#define   ICH6_IRS_BUSY		(1<<0)

#define ICH6_REG_DPLBASE		0x70
#define ICH6_REG_DPUBASE		0x74
#define   ICH6_DPLBASE_ENABLE	0x1	/* Enable position buffer */

/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };

/* stream register offsets from stream base */
#define ICH6_REG_SD_CTL			0x00
#define ICH6_REG_SD_STS			0x03
#define ICH6_REG_SD_LPIB		0x04
#define ICH6_REG_SD_CBL			0x08
#define ICH6_REG_SD_LVI			0x0c
#define ICH6_REG_SD_FIFOW		0x0e
#define ICH6_REG_SD_FIFOSIZE		0x10
#define ICH6_REG_SD_FORMAT		0x12
#define ICH6_REG_SD_BDLPL		0x18
#define ICH6_REG_SD_BDLPU		0x1c

/* PCI space */
#define ICH6_PCIREG_TCSEL	0x44

/*
 * other constants
 */

/* max number of SDs */
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/* ICH, ATI and VIA have 4 playback and 4 capture */
#define ICH6_NUM_CAPTURE	4
#define ICH6_NUM_PLAYBACK	4

/* ULI has 6 playback and 5 capture */
#define ULI_NUM_CAPTURE		5
#define ULI_NUM_PLAYBACK	6

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/* ATI HDMI has 1 playback and 0 capture */
#define ATIHDMI_NUM_CAPTURE	0
#define ATIHDMI_NUM_PLAYBACK	1

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/* TERA has 4 playback and 3 capture */
#define TERA_NUM_CAPTURE	3
#define TERA_NUM_PLAYBACK	4

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/* this number is statically defined for simplicity */
#define MAX_AZX_DEV		16

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/* max number of fragments - we may use more if allocating more pages for BDL */
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#define BDL_SIZE		4096
#define AZX_MAX_BDL_ENTRIES	(BDL_SIZE / 16)
#define AZX_MAX_FRAG		32
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/* max buffer size - no h/w limit, you can increase as you like */
#define AZX_MAX_BUF_SIZE	(1024*1024*1024)
/* max number of PCM devics per card */
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#define AZX_MAX_PCMS		8
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/* RIRB int mask: overrun[2], response[0] */
#define RIRB_INT_RESPONSE	0x01
#define RIRB_INT_OVERRUN	0x04
#define RIRB_INT_MASK		0x05

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/* STATESTS int mask: S3,SD2,SD1,SD0 */
#define AZX_MAX_CODECS		4
#define STATESTS_INT_MASK	0x0f
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/* SD_CTL bits */
#define SD_CTL_STREAM_RESET	0x01	/* stream reset bit */
#define SD_CTL_DMA_START	0x02	/* stream DMA start bit */
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#define SD_CTL_STRIPE		(3 << 16)	/* stripe control */
#define SD_CTL_TRAFFIC_PRIO	(1 << 18)	/* traffic priority */
#define SD_CTL_DIR		(1 << 19)	/* bi-directional stream */
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#define SD_CTL_STREAM_TAG_MASK	(0xf << 20)
#define SD_CTL_STREAM_TAG_SHIFT	20

/* SD_CTL and SD_STS */
#define SD_INT_DESC_ERR		0x10	/* descriptor error interrupt */
#define SD_INT_FIFO_ERR		0x08	/* FIFO error interrupt */
#define SD_INT_COMPLETE		0x04	/* completion interrupt */
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#define SD_INT_MASK		(SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
				 SD_INT_COMPLETE)
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/* SD_STS */
#define SD_STS_FIFO_READY	0x20	/* FIFO ready */

/* INTCTL and INTSTS */
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#define ICH6_INT_ALL_STREAM	0xff	   /* all stream interrupts */
#define ICH6_INT_CTRL_EN	0x40000000 /* controller interrupt enable bit */
#define ICH6_INT_GLOBAL_EN	0x80000000 /* global interrupt enable bit */
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/* GCTL unsolicited response enable bit */
#define ICH6_GCTL_UREN		(1<<8)

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/* GCTL reset bit */
#define ICH6_GCTL_RESET		(1<<0)

/* CORB/RIRB control, read/write pointer */
#define ICH6_RBCTL_DMA_EN	0x02	/* enable DMA */
#define ICH6_RBCTL_IRQ_EN	0x01	/* enable IRQ */
#define ICH6_RBRWP_CLR		0x8000	/* read/write pointer clear */
/* below are so far hardcoded - should read registers in future */
#define ICH6_MAX_CORB_ENTRIES	256
#define ICH6_MAX_RIRB_ENTRIES	256

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/* position fix mode */
enum {
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	POS_FIX_AUTO,
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	POS_FIX_LPIB,
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	POS_FIX_POSBUF,
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};
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/* Defines for ATI HD Audio support in SB450 south bridge */
#define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
#define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02

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/* Defines for Nvidia HDA support */
#define NVIDIA_HDA_TRANSREG_ADDR      0x4e
#define NVIDIA_HDA_ENABLE_COHBITS     0x0f
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#define NVIDIA_HDA_ISTRM_COH          0x4d
#define NVIDIA_HDA_OSTRM_COH          0x4c
#define NVIDIA_HDA_ENABLE_COHBIT      0x01
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/* Defines for Intel SCH HDA snoop control */
#define INTEL_SCH_HDA_DEVC      0x78
#define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)

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/* Define IN stream 0 FIFO size offset in VIA controller */
#define VIA_IN_STREAM0_FIFO_SIZE_OFFSET	0x90
/* Define VIA HD Audio Device ID*/
#define VIA_HDAC_DEVICE_ID		0x3288

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/* HD Audio class code */
#define PCI_CLASS_MULTIMEDIA_HD_AUDIO	0x0403
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/*
 */

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struct azx_dev {
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	struct snd_dma_buffer bdl; /* BDL buffer */
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	u32 *posbuf;		/* position buffer pointer */
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	unsigned int bufsize;	/* size of the play buffer in bytes */
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	unsigned int period_bytes; /* size of the period in bytes */
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	unsigned int frags;	/* number for period in the play buffer */
	unsigned int fifo_size;	/* FIFO size */
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	void __iomem *sd_addr;	/* stream descriptor pointer */
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	u32 sd_int_sta_mask;	/* stream int status mask */
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	/* pcm support */
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	struct snd_pcm_substream *substream;	/* assigned substream,
						 * set in PCM open
						 */
	unsigned int format_val;	/* format value to be set in the
					 * controller and the codec
					 */
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	unsigned char stream_tag;	/* assigned stream */
	unsigned char index;		/* stream index */

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	unsigned int opened :1;
	unsigned int running :1;
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	unsigned int irq_pending :1;
	unsigned int irq_ignore :1;
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	/*
	 * For VIA:
	 *  A flag to ensure DMA position is 0
	 *  when link position is not greater than FIFO size
	 */
	unsigned int insufficient :1;
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};

/* CORB/RIRB */
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struct azx_rb {
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	u32 *buf;		/* CORB/RIRB buffer
				 * Each CORB entry is 4byte, RIRB is 8byte
				 */
	dma_addr_t addr;	/* physical address of CORB/RIRB buffer */
	/* for RIRB */
	unsigned short rp, wp;	/* read/write pointers */
	int cmds;		/* number of pending requests */
	u32 res;		/* last read value */
};

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struct azx {
	struct snd_card *card;
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	struct pci_dev *pci;
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	int dev_index;
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	/* chip type specific */
	int driver_type;
	int playback_streams;
	int playback_index_offset;
	int capture_streams;
	int capture_index_offset;
	int num_streams;

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	/* pci resources */
	unsigned long addr;
	void __iomem *remap_addr;
	int irq;

	/* locks */
	spinlock_t reg_lock;
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	struct mutex open_mutex;
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	/* streams (x num_streams) */
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	struct azx_dev *azx_dev;
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	/* PCM */
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	struct snd_pcm *pcm[AZX_MAX_PCMS];
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	/* HD codec */
	unsigned short codec_mask;
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	int  codec_probe_mask; /* copied from probe_mask option */
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	struct hda_bus *bus;

	/* CORB/RIRB */
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	struct azx_rb corb;
	struct azx_rb rirb;
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	/* CORB/RIRB and position buffers */
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	struct snd_dma_buffer rb;
	struct snd_dma_buffer posbuf;
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	/* flags */
	int position_fix;
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	unsigned int running :1;
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	unsigned int initialized :1;
	unsigned int single_cmd :1;
	unsigned int polling_mode :1;
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	unsigned int msi :1;
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	unsigned int irq_pending_warned :1;
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	unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
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	unsigned int probing :1; /* codec probing phase */
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	/* for debugging */
	unsigned int last_cmd;	/* last issued command (to sync) */
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	/* for pending irqs */
	struct work_struct irq_pending_work;
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	/* reboot notifier (for mysterious hangup problem at power-down) */
	struct notifier_block reboot_notifier;
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};

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/* driver types */
enum {
	AZX_DRIVER_ICH,
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	AZX_DRIVER_SCH,
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	AZX_DRIVER_ATI,
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	AZX_DRIVER_ATIHDMI,
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	AZX_DRIVER_VIA,
	AZX_DRIVER_SIS,
	AZX_DRIVER_ULI,
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	AZX_DRIVER_NVIDIA,
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	AZX_DRIVER_TERA,
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	AZX_DRIVER_GENERIC,
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	AZX_NUM_DRIVERS, /* keep this as last entry */
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};

static char *driver_short_names[] __devinitdata = {
	[AZX_DRIVER_ICH] = "HDA Intel",
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	[AZX_DRIVER_SCH] = "HDA Intel MID",
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	[AZX_DRIVER_ATI] = "HDA ATI SB",
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	[AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
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	[AZX_DRIVER_VIA] = "HDA VIA VT82xx",
	[AZX_DRIVER_SIS] = "HDA SIS966",
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	[AZX_DRIVER_ULI] = "HDA ULI M5461",
	[AZX_DRIVER_NVIDIA] = "HDA NVidia",
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	[AZX_DRIVER_TERA] = "HDA Teradici", 
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	[AZX_DRIVER_GENERIC] = "HD-Audio Generic",
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};

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/*
 * macros for easy use
 */
#define azx_writel(chip,reg,value) \
	writel(value, (chip)->remap_addr + ICH6_REG_##reg)
#define azx_readl(chip,reg) \
	readl((chip)->remap_addr + ICH6_REG_##reg)
#define azx_writew(chip,reg,value) \
	writew(value, (chip)->remap_addr + ICH6_REG_##reg)
#define azx_readw(chip,reg) \
	readw((chip)->remap_addr + ICH6_REG_##reg)
#define azx_writeb(chip,reg,value) \
	writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
#define azx_readb(chip,reg) \
	readb((chip)->remap_addr + ICH6_REG_##reg)

#define azx_sd_writel(dev,reg,value) \
	writel(value, (dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_readl(dev,reg) \
	readl((dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_writew(dev,reg,value) \
	writew(value, (dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_readw(dev,reg) \
	readw((dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_writeb(dev,reg,value) \
	writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
#define azx_sd_readb(dev,reg) \
	readb((dev)->sd_addr + ICH6_REG_##reg)

/* for pcm support */
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#define get_azx_dev(substream) (substream->runtime->private_data)
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static int azx_acquire_irq(struct azx *chip, int do_disconnect);
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/*
 * Interface for HD codec
 */

/*
 * CORB / RIRB interface
 */
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static int azx_alloc_cmd_io(struct azx *chip)
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{
	int err;

	/* single page (at least 4096 bytes) must suffice for both ringbuffes */
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	err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
				  snd_dma_pci_data(chip->pci),
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				  PAGE_SIZE, &chip->rb);
	if (err < 0) {
		snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
		return err;
	}
	return 0;
}

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static void azx_init_cmd_io(struct azx *chip)
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{
	/* CORB set up */
	chip->corb.addr = chip->rb.addr;
	chip->corb.buf = (u32 *)chip->rb.area;
	azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
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	azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
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	/* set the corb size to 256 entries (ULI requires explicitly) */
	azx_writeb(chip, CORBSIZE, 0x02);
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	/* set the corb write pointer to 0 */
	azx_writew(chip, CORBWP, 0);
	/* reset the corb hw read pointer */
	azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
	/* enable corb dma */
	azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);

	/* RIRB set up */
	chip->rirb.addr = chip->rb.addr + 2048;
	chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
	azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
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	azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
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523 524
	/* set the rirb size to 256 entries (ULI requires explicitly) */
	azx_writeb(chip, RIRBSIZE, 0x02);
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	/* reset the rirb hw write pointer */
	azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
	/* set N=1, get RIRB response interrupt for new entry */
	azx_writew(chip, RINTCNT, 1);
	/* enable rirb dma and response irq */
	azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
	chip->rirb.rp = chip->rirb.cmds = 0;
}

534
static void azx_free_cmd_io(struct azx *chip)
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{
	/* disable ringbuffer DMAs */
	azx_writeb(chip, RIRBCTL, 0);
	azx_writeb(chip, CORBCTL, 0);
}

/* send a command */
542
static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
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{
544
	struct azx *chip = bus->private_data;
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	unsigned int wp;

	/* add command to corb */
	wp = azx_readb(chip, CORBWP);
	wp++;
	wp %= ICH6_MAX_CORB_ENTRIES;

	spin_lock_irq(&chip->reg_lock);
	chip->rirb.cmds++;
	chip->corb.buf[wp] = cpu_to_le32(val);
	azx_writel(chip, CORBWP, wp);
	spin_unlock_irq(&chip->reg_lock);

	return 0;
}

#define ICH6_RIRB_EX_UNSOL_EV	(1<<4)

/* retrieve RIRB entry - called from interrupt handler */
564
static void azx_update_rirb(struct azx *chip)
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{
	unsigned int rp, wp;
	u32 res, res_ex;

	wp = azx_readb(chip, RIRBWP);
	if (wp == chip->rirb.wp)
		return;
	chip->rirb.wp = wp;
		
	while (chip->rirb.rp != wp) {
		chip->rirb.rp++;
		chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;

		rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
		res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
		res = le32_to_cpu(chip->rirb.buf[rp]);
		if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
			snd_hda_queue_unsol_event(chip->bus, res, res_ex);
		else if (chip->rirb.cmds) {
			chip->rirb.res = res;
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			smp_wmb();
			chip->rirb.cmds--;
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		}
	}
}

/* receive a response */
592
static unsigned int azx_rirb_get_response(struct hda_bus *bus)
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{
594
	struct azx *chip = bus->private_data;
595
	unsigned long timeout;
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597 598
 again:
	timeout = jiffies + msecs_to_jiffies(1000);
599
	for (;;) {
600 601 602 603 604
		if (chip->polling_mode) {
			spin_lock_irq(&chip->reg_lock);
			azx_update_rirb(chip);
			spin_unlock_irq(&chip->reg_lock);
		}
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		if (!chip->rirb.cmds) {
			smp_rmb();
607
			return chip->rirb.res; /* the last value */
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		}
609 610
		if (time_after(jiffies, timeout))
			break;
611
		if (bus->needs_damn_long_delay)
612 613 614 615 616
			msleep(2); /* temporary workaround */
		else {
			udelay(10);
			cond_resched();
		}
617
	}
618

619 620
	if (chip->msi) {
		snd_printk(KERN_WARNING "hda_intel: No response from codec, "
621
			   "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
622 623 624 625 626 627 628 629 630
		free_irq(chip->irq, chip);
		chip->irq = -1;
		pci_disable_msi(chip->pci);
		chip->msi = 0;
		if (azx_acquire_irq(chip, 1) < 0)
			return -1;
		goto again;
	}

631 632
	if (!chip->polling_mode) {
		snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
633 634
			   "switching to polling mode: last cmd=0x%08x\n",
			   chip->last_cmd);
635 636
		chip->polling_mode = 1;
		goto again;
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	}
638

639 640 641 642 643 644 645 646
	if (chip->probing) {
		/* If this critical timeout happens during the codec probing
		 * phase, this is likely an access to a non-existing codec
		 * slot.  Better to return an error and reset the system.
		 */
		return -1;
	}

647
	snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
648 649
		   "switching to single_cmd mode: last cmd=0x%08x\n",
		   chip->last_cmd);
650 651 652 653 654 655
	chip->rirb.rp = azx_readb(chip, RIRBWP);
	chip->rirb.cmds = 0;
	/* switch to single_cmd mode */
	chip->single_cmd = 1;
	azx_free_cmd_io(chip);
	return -1;
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}

/*
 * Use the single immediate command instead of CORB/RIRB for simplicity
 *
 * Note: according to Intel, this is not preferred use.  The command was
 *       intended for the BIOS only, and may get confused with unsolicited
 *       responses.  So, we shouldn't use it for normal operation from the
 *       driver.
 *       I left the codes, however, for debugging/testing purposes.
 */

/* send a command */
669
static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
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{
671
	struct azx *chip = bus->private_data;
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	int timeout = 50;

	while (timeout--) {
		/* check ICB busy bit */
676
		if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
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			/* Clear IRV valid bit */
678 679
			azx_writew(chip, IRS, azx_readw(chip, IRS) |
				   ICH6_IRS_VALID);
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			azx_writel(chip, IC, val);
681 682
			azx_writew(chip, IRS, azx_readw(chip, IRS) |
				   ICH6_IRS_BUSY);
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			return 0;
		}
		udelay(1);
	}
687 688 689
	if (printk_ratelimit())
		snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
			   azx_readw(chip, IRS), val);
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	return -EIO;
}

/* receive a response */
694
static unsigned int azx_single_get_response(struct hda_bus *bus)
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{
696
	struct azx *chip = bus->private_data;
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	int timeout = 50;

	while (timeout--) {
		/* check IRV busy bit */
		if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
			return azx_readl(chip, IR);
		udelay(1);
	}
705 706 707
	if (printk_ratelimit())
		snd_printd(SFX "get_response timeout: IRS=0x%x\n",
			   azx_readw(chip, IRS));
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	return (unsigned int)-1;
}

711 712 713 714 715 716 717 718
/*
 * The below are the main callbacks from hda_codec.
 *
 * They are just the skeleton to call sub-callbacks according to the
 * current setting of chip->single_cmd.
 */

/* send a command */
719
static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
720
{
721
	struct azx *chip = bus->private_data;
722

723
	chip->last_cmd = val;
724
	if (chip->single_cmd)
725
		return azx_single_send_cmd(bus, val);
726
	else
727
		return azx_corb_send_cmd(bus, val);
728 729 730
}

/* get a response */
731
static unsigned int azx_get_response(struct hda_bus *bus)
732
{
733
	struct azx *chip = bus->private_data;
734
	if (chip->single_cmd)
735
		return azx_single_get_response(bus);
736
	else
737
		return azx_rirb_get_response(bus);
738 739
}

740
#ifdef CONFIG_SND_HDA_POWER_SAVE
741
static void azx_power_notify(struct hda_bus *bus);
742
#endif
743

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/* reset codec link */
745
static int azx_reset(struct azx *chip)
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{
	int count;

749 750 751
	/* clear STATESTS */
	azx_writeb(chip, STATESTS, STATESTS_INT_MASK);

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	/* reset controller */
	azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);

	count = 50;
	while (azx_readb(chip, GCTL) && --count)
		msleep(1);

	/* delay for >= 100us for codec PLL to settle per spec
	 * Rev 0.9 section 5.5.1
	 */
	msleep(1);

	/* Bring controller out of reset */
	azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);

	count = 50;
768
	while (!azx_readb(chip, GCTL) && --count)
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		msleep(1);

771
	/* Brent Chartrand said to wait >= 540us for codecs to initialize */
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	msleep(1);

	/* check to see if controller is ready */
775
	if (!azx_readb(chip, GCTL)) {
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		snd_printd("azx_reset: controller not ready!\n");
		return -EBUSY;
	}

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	/* Accept unsolicited responses */
	azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);

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	/* detect codecs */
784
	if (!chip->codec_mask) {
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		chip->codec_mask = azx_readw(chip, STATESTS);
		snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
	}

	return 0;
}


/*
 * Lowlevel interface
 */  

/* enable interrupts */
798
static void azx_int_enable(struct azx *chip)
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{
	/* enable controller CIE and GIE */
	azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
		   ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
}

/* disable interrupts */
806
static void azx_int_disable(struct azx *chip)
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{
	int i;

	/* disable interrupts in stream descriptor */
811
	for (i = 0; i < chip->num_streams; i++) {
812
		struct azx_dev *azx_dev = &chip->azx_dev[i];
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		azx_sd_writeb(azx_dev, SD_CTL,
			      azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
	}

	/* disable SIE for all streams */
	azx_writeb(chip, INTCTL, 0);

	/* disable controller CIE and GIE */
	azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
		   ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
}

/* clear interrupts */
826
static void azx_int_clear(struct azx *chip)
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{
	int i;

	/* clear stream status */
831
	for (i = 0; i < chip->num_streams; i++) {
832
		struct azx_dev *azx_dev = &chip->azx_dev[i];
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		azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
	}

	/* clear STATESTS */
	azx_writeb(chip, STATESTS, STATESTS_INT_MASK);

	/* clear rirb status */
	azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);

	/* clear int status */
	azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
}

/* start a stream */
847
static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
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{
849 850 851 852 853
	/*
	 * Before stream start, initialize parameter
	 */
	azx_dev->insufficient = 1;

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	/* enable SIE */
	azx_writeb(chip, INTCTL,
		   azx_readb(chip, INTCTL) | (1 << azx_dev->index));
	/* set DMA start and interrupt mask */
	azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
		      SD_CTL_DMA_START | SD_INT_MASK);
}

/* stop a stream */
863
static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
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{
	/* stop DMA */
	azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
		      ~(SD_CTL_DMA_START | SD_INT_MASK));
	azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
	/* disable SIE */
	azx_writeb(chip, INTCTL,
		   azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
}


/*
876
 * reset and start the controller registers
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 */
878
static void azx_init_chip(struct azx *chip)
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879
{
880 881
	if (chip->initialized)
		return;
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	/* reset controller */
	azx_reset(chip);

	/* initialize interrupts */
	azx_int_clear(chip);
	azx_int_enable(chip);

	/* initialize the codec command I/O */
891
	if (!chip->single_cmd)
892
		azx_init_cmd_io(chip);
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894 895
	/* program the position buffer */
	azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
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	azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
897

898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917
	chip->initialized = 1;
}

/*
 * initialize the PCI registers
 */
/* update bits in a PCI register byte */
static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
			    unsigned char mask, unsigned char val)
{
	unsigned char data;

	pci_read_config_byte(pci, reg, &data);
	data &= ~mask;
	data |= (val & mask);
	pci_write_config_byte(pci, reg, data);
}

static void azx_init_pci(struct azx *chip)
{
T
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	unsigned short snoop;

920 921 922 923 924 925 926
	/* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
	 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
	 * Ensuring these bits are 0 clears playback static on some HD Audio
	 * codecs
	 */
	update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);

V
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	switch (chip->driver_type) {
	case AZX_DRIVER_ATI:
		/* For ATI SB450 azalia HD audio, we need to enable snoop */
930 931 932
		update_pci_byte(chip->pci,
				ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 
				0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
V
Vinod G 已提交
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		break;
	case AZX_DRIVER_NVIDIA:
		/* For NVIDIA HDA, enable snoop */
936 937 938
		update_pci_byte(chip->pci,
				NVIDIA_HDA_TRANSREG_ADDR,
				0x0f, NVIDIA_HDA_ENABLE_COHBITS);
939 940 941 942 943 944
		update_pci_byte(chip->pci,
				NVIDIA_HDA_ISTRM_COH,
				0x01, NVIDIA_HDA_ENABLE_COHBIT);
		update_pci_byte(chip->pci,
				NVIDIA_HDA_OSTRM_COH,
				0x01, NVIDIA_HDA_ENABLE_COHBIT);
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		break;
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	case AZX_DRIVER_SCH:
		pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
		if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
			pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
				snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
			pci_read_config_word(chip->pci,
				INTEL_SCH_HDA_DEVC, &snoop);
			snd_printdd("HDA snoop disabled, enabling ... %s\n",\
				(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
				? "Failed" : "OK");
		}
		break;

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        }
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}


963 964
static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);

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/*
 * interrupt handler
 */
968
static irqreturn_t azx_interrupt(int irq, void *dev_id)
L
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969
{
970 971
	struct azx *chip = dev_id;
	struct azx_dev *azx_dev;
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	u32 status;
	int i;

	spin_lock(&chip->reg_lock);

	status = azx_readl(chip, INTSTS);
	if (status == 0) {
		spin_unlock(&chip->reg_lock);
		return IRQ_NONE;
	}
	
983
	for (i = 0; i < chip->num_streams; i++) {
L
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		azx_dev = &chip->azx_dev[i];
		if (status & azx_dev->sd_int_sta_mask) {
			azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
987 988
			if (!azx_dev->substream || !azx_dev->running)
				continue;
989 990 991 992 993
			/* ignore the first dummy IRQ (due to pos_adj) */
			if (azx_dev->irq_ignore) {
				azx_dev->irq_ignore = 0;
				continue;
			}
994 995 996
			/* check whether this IRQ is really acceptable */
			if (azx_position_ok(chip, azx_dev)) {
				azx_dev->irq_pending = 0;
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				spin_unlock(&chip->reg_lock);
				snd_pcm_period_elapsed(azx_dev->substream);
				spin_lock(&chip->reg_lock);
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Takashi Iwai 已提交
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			} else if (chip->bus && chip->bus->workq) {
1001 1002
				/* bogus IRQ, process it later */
				azx_dev->irq_pending = 1;
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				queue_work(chip->bus->workq,
					   &chip->irq_pending_work);
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			}
		}
	}

	/* clear rirb int */
	status = azx_readb(chip, RIRBSTS);
	if (status & RIRB_INT_MASK) {
1012
		if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
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1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027
			azx_update_rirb(chip);
		azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
	}

#if 0
	/* clear state status int */
	if (azx_readb(chip, STATESTS) & 0x04)
		azx_writeb(chip, STATESTS, 0x04);
#endif
	spin_unlock(&chip->reg_lock);
	
	return IRQ_HANDLED;
}


1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043
/*
 * set up a BDL entry
 */
static int setup_bdle(struct snd_pcm_substream *substream,
		      struct azx_dev *azx_dev, u32 **bdlp,
		      int ofs, int size, int with_ioc)
{
	u32 *bdl = *bdlp;

	while (size > 0) {
		dma_addr_t addr;
		int chunk;

		if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
			return -EINVAL;

1044
		addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1045 1046
		/* program the address field of the BDL entry */
		bdl[0] = cpu_to_le32((u32)addr);
T
Takashi Iwai 已提交
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		bdl[1] = cpu_to_le32(upper_32_bits(addr));
1048
		/* program the size field of the BDL entry */
T
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		chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063
		bdl[2] = cpu_to_le32(chunk);
		/* program the IOC to enable interrupt
		 * only when the whole fragment is processed
		 */
		size -= chunk;
		bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
		bdl += 4;
		azx_dev->frags++;
		ofs += chunk;
	}
	*bdlp = bdl;
	return ofs;
}

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/*
 * set up BDL entries
 */
1067 1068
static int azx_setup_periods(struct azx *chip,
			     struct snd_pcm_substream *substream,
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			     struct azx_dev *azx_dev)
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{
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	u32 *bdl;
	int i, ofs, periods, period_bytes;
1073
	int pos_adj;
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	/* reset BDL address */
	azx_sd_writel(azx_dev, SD_BDLPL, 0);
	azx_sd_writel(azx_dev, SD_BDLPU, 0);

1079
	period_bytes = azx_dev->period_bytes;
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	periods = azx_dev->bufsize / period_bytes;

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	/* program the initial BDL entries */
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	bdl = (u32 *)azx_dev->bdl.area;
	ofs = 0;
	azx_dev->frags = 0;
1086
	azx_dev->irq_ignore = 0;
1087 1088
	pos_adj = bdl_pos_adj[chip->dev_index];
	if (pos_adj > 0) {
1089
		struct snd_pcm_runtime *runtime = substream->runtime;
1090
		int pos_align = pos_adj;
1091
		pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1092
		if (!pos_adj)
1093 1094 1095 1096
			pos_adj = pos_align;
		else
			pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
				pos_align;
1097 1098 1099
		pos_adj = frames_to_bytes(runtime, pos_adj);
		if (pos_adj >= period_bytes) {
			snd_printk(KERN_WARNING "Too big adjustment %d\n",
1100
				   bdl_pos_adj[chip->dev_index]);
1101 1102 1103 1104 1105 1106 1107
			pos_adj = 0;
		} else {
			ofs = setup_bdle(substream, azx_dev,
					 &bdl, ofs, pos_adj, 1);
			if (ofs < 0)
				goto error;
			azx_dev->irq_ignore = 1;
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		}
1109 1110
	} else
		pos_adj = 0;
1111 1112 1113 1114 1115 1116 1117 1118 1119
	for (i = 0; i < periods; i++) {
		if (i == periods - 1 && pos_adj)
			ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
					 period_bytes - pos_adj, 0);
		else
			ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
					 period_bytes, 1);
		if (ofs < 0)
			goto error;
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	}
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	return 0;
1122 1123 1124 1125 1126

 error:
	snd_printk(KERN_ERR "Too many BDL entries: buffer=%d, period=%d\n",
		   azx_dev->bufsize, period_bytes);
	return -EINVAL;
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}

/*
 * set up the SD for streaming
 */
1132
static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
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{
	unsigned char val;
	int timeout;

	/* make sure the run bit is zero for SD */
1138 1139
	azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
		      ~SD_CTL_DMA_START);
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	/* reset stream */
1141 1142
	azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
		      SD_CTL_STREAM_RESET);
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	udelay(3);
	timeout = 300;
	while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
	       --timeout)
		;
	val &= ~SD_CTL_STREAM_RESET;
	azx_sd_writeb(azx_dev, SD_CTL, val);
	udelay(3);

	timeout = 300;
	/* waiting for hardware to report that the stream is out of reset */
	while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
	       --timeout)
		;

	/* program the stream_tag */
	azx_sd_writel(azx_dev, SD_CTL,
1160
		      (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
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		      (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));

	/* program the length of samples in cyclic buffer */
	azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);

	/* program the stream format */
	/* this value needs to be the same as the one programmed */
	azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);

	/* program the stream LVI (last valid index) of the BDL */
	azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);

	/* program the BDL address */
	/* lower BDL address */
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	azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
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	/* upper BDL address */
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	azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
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1179
	/* enable the position buffer */
1180
	if (chip->position_fix == POS_FIX_POSBUF ||
1181 1182
	    chip->position_fix == POS_FIX_AUTO ||
	    chip->via_dmapos_patch) {
1183 1184 1185 1186
		if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
			azx_writel(chip, DPLBASE,
				(u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
	}
1187

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	/* set the interrupt enable bits in the descriptor control register */
1189 1190
	azx_sd_writel(azx_dev, SD_CTL,
		      azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
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	return 0;
}

1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213
/*
 * Probe the given codec address
 */
static int probe_codec(struct azx *chip, int addr)
{
	unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
		(AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
	unsigned int res;

	chip->probing = 1;
	azx_send_cmd(chip->bus, cmd);
	res = azx_get_response(chip->bus);
	chip->probing = 0;
	if (res == -1)
		return -EIO;
	snd_printdd("hda_intel: codec #%d probed OK\n", addr);
	return 0;
}

1214 1215
static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
				 struct hda_pcm *cpcm);
1216
static void azx_stop_chip(struct azx *chip);
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/*
 * Codec initialization
 */

1222 1223
/* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1224
	[AZX_DRIVER_TERA] = 1,
1225 1226
};

1227
static int __devinit azx_codec_create(struct azx *chip, const char *model,
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				      int no_init)
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{
	struct hda_bus_template bus_temp;
1231 1232
	int c, codecs, err;
	int max_slots;
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	memset(&bus_temp, 0, sizeof(bus_temp));
	bus_temp.private_data = chip;
	bus_temp.modelname = model;
	bus_temp.pci = chip->pci;
1238 1239
	bus_temp.ops.command = azx_send_cmd;
	bus_temp.ops.get_response = azx_get_response;
1240
	bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1241
#ifdef CONFIG_SND_HDA_POWER_SAVE
1242
	bus_temp.power_save = &power_save;
1243 1244
	bus_temp.ops.pm_notify = azx_power_notify;
#endif
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1246 1247
	err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
	if (err < 0)
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		return err;

1250 1251 1252
	if (chip->driver_type == AZX_DRIVER_NVIDIA)
		chip->bus->needs_damn_long_delay = 1;

1253
	codecs = 0;
1254 1255 1256
	max_slots = azx_max_codecs[chip->driver_type];
	if (!max_slots)
		max_slots = AZX_MAX_CODECS;
1257 1258 1259

	/* First try to probe all given codec slots */
	for (c = 0; c < max_slots; c++) {
1260
		if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282
			if (probe_codec(chip, c) < 0) {
				/* Some BIOSen give you wrong codec addresses
				 * that don't exist
				 */
				snd_printk(KERN_WARNING
					   "hda_intel: Codec #%d probe error; "
					   "disabling it...\n", c);
				chip->codec_mask &= ~(1 << c);
				/* More badly, accessing to a non-existing
				 * codec often screws up the controller chip,
				 * and distrubs the further communications.
				 * Thus if an error occurs during probing,
				 * better to reset the controller chip to
				 * get back to the sanity state.
				 */
				azx_stop_chip(chip);
				azx_init_chip(chip);
			}
		}
	}

	/* Then create codec instances */
1283
	for (c = 0; c < max_slots; c++) {
1284
		if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1285
			struct hda_codec *codec;
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			err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
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			if (err < 0)
				continue;
			codecs++;
1290 1291 1292
		}
	}
	if (!codecs) {
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		snd_printk(KERN_ERR SFX "no codecs initialized\n");
		return -ENXIO;
	}

	return 0;
}


/*
 * PCM support
 */

/* assign a stream for the PCM */
1306
static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
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{
1308 1309 1310 1311 1312 1313 1314 1315 1316
	int dev, i, nums;
	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
		dev = chip->playback_index_offset;
		nums = chip->playback_streams;
	} else {
		dev = chip->capture_index_offset;
		nums = chip->capture_streams;
	}
	for (i = 0; i < nums; i++, dev++)
1317
		if (!chip->azx_dev[dev].opened) {
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			chip->azx_dev[dev].opened = 1;
			return &chip->azx_dev[dev];
		}
	return NULL;
}

/* release the assigned stream */
1325
static inline void azx_release_device(struct azx_dev *azx_dev)
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{
	azx_dev->opened = 0;
}

1330
static struct snd_pcm_hardware azx_pcm_hw = {
1331 1332
	.info =			(SNDRV_PCM_INFO_MMAP |
				 SNDRV_PCM_INFO_INTERLEAVED |
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				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
				 SNDRV_PCM_INFO_MMAP_VALID |
1335 1336
				 /* No full-resume yet implemented */
				 /* SNDRV_PCM_INFO_RESUME |*/
1337 1338
				 SNDRV_PCM_INFO_PAUSE |
				 SNDRV_PCM_INFO_SYNC_START),
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	.formats =		SNDRV_PCM_FMTBIT_S16_LE,
	.rates =		SNDRV_PCM_RATE_48000,
	.rate_min =		48000,
	.rate_max =		48000,
	.channels_min =		2,
	.channels_max =		2,
	.buffer_bytes_max =	AZX_MAX_BUF_SIZE,
	.period_bytes_min =	128,
	.period_bytes_max =	AZX_MAX_BUF_SIZE / 2,
	.periods_min =		2,
	.periods_max =		AZX_MAX_FRAG,
	.fifo_size =		0,
};

struct azx_pcm {
1354
	struct azx *chip;
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	struct hda_codec *codec;
	struct hda_pcm_stream *hinfo[2];
};

1359
static int azx_pcm_open(struct snd_pcm_substream *substream)
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{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1363 1364 1365
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev;
	struct snd_pcm_runtime *runtime = substream->runtime;
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	unsigned long flags;
	int err;

1369
	mutex_lock(&chip->open_mutex);
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	azx_dev = azx_assign_device(chip, substream->stream);
	if (azx_dev == NULL) {
1372
		mutex_unlock(&chip->open_mutex);
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		return -EBUSY;
	}
	runtime->hw = azx_pcm_hw;
	runtime->hw.channels_min = hinfo->channels_min;
	runtime->hw.channels_max = hinfo->channels_max;
	runtime->hw.formats = hinfo->formats;
	runtime->hw.rates = hinfo->rates;
	snd_pcm_limit_hw_rates(runtime);
	snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1382 1383 1384 1385
	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
				   128);
	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
				   128);
1386
	snd_hda_power_up(apcm->codec);
1387 1388
	err = hinfo->ops.open(hinfo, apcm->codec, substream);
	if (err < 0) {
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		azx_release_device(azx_dev);
1390
		snd_hda_power_down(apcm->codec);
1391
		mutex_unlock(&chip->open_mutex);
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		return err;
	}
	spin_lock_irqsave(&chip->reg_lock, flags);
	azx_dev->substream = substream;
	azx_dev->running = 0;
	spin_unlock_irqrestore(&chip->reg_lock, flags);

	runtime->private_data = azx_dev;
1400
	snd_pcm_set_sync(substream);
1401
	mutex_unlock(&chip->open_mutex);
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	return 0;
}

1405
static int azx_pcm_close(struct snd_pcm_substream *substream)
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{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1409 1410
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev = get_azx_dev(substream);
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	unsigned long flags;

1413
	mutex_lock(&chip->open_mutex);
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	spin_lock_irqsave(&chip->reg_lock, flags);
	azx_dev->substream = NULL;
	azx_dev->running = 0;
	spin_unlock_irqrestore(&chip->reg_lock, flags);
	azx_release_device(azx_dev);
	hinfo->ops.close(hinfo, apcm->codec, substream);
1420
	snd_hda_power_down(apcm->codec);
1421
	mutex_unlock(&chip->open_mutex);
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	return 0;
}

1425 1426
static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
			     struct snd_pcm_hw_params *hw_params)
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{
1428 1429 1430 1431 1432
	struct azx_dev *azx_dev = get_azx_dev(substream);

	azx_dev->bufsize = 0;
	azx_dev->period_bytes = 0;
	azx_dev->format_val = 0;
1433 1434
	return snd_pcm_lib_malloc_pages(substream,
					params_buffer_bytes(hw_params));
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}

1437
static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
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{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1440
	struct azx_dev *azx_dev = get_azx_dev(substream);
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	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];

	/* reset BDL address */
	azx_sd_writel(azx_dev, SD_BDLPL, 0);
	azx_sd_writel(azx_dev, SD_BDLPU, 0);
	azx_sd_writel(azx_dev, SD_CTL, 0);
1447 1448 1449
	azx_dev->bufsize = 0;
	azx_dev->period_bytes = 0;
	azx_dev->format_val = 0;
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	hinfo->ops.cleanup(hinfo, apcm->codec, substream);

	return snd_pcm_lib_free_pages(substream);
}

1456
static int azx_pcm_prepare(struct snd_pcm_substream *substream)
L
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1457 1458
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1459 1460
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev = get_azx_dev(substream);
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	struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1462
	struct snd_pcm_runtime *runtime = substream->runtime;
1463 1464
	unsigned int bufsize, period_bytes, format_val;
	int err;
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1466 1467 1468 1469 1470
	format_val = snd_hda_calc_stream_format(runtime->rate,
						runtime->channels,
						runtime->format,
						hinfo->maxbps);
	if (!format_val) {
1471 1472
		snd_printk(KERN_ERR SFX
			   "invalid format_val, rate=%d, ch=%d, format=%d\n",
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			   runtime->rate, runtime->channels, runtime->format);
		return -EINVAL;
	}

1477 1478 1479
	bufsize = snd_pcm_lib_buffer_bytes(substream);
	period_bytes = snd_pcm_lib_period_bytes(substream);

1480
	snd_printdd("azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493
		    bufsize, format_val);

	if (bufsize != azx_dev->bufsize ||
	    period_bytes != azx_dev->period_bytes ||
	    format_val != azx_dev->format_val) {
		azx_dev->bufsize = bufsize;
		azx_dev->period_bytes = period_bytes;
		azx_dev->format_val = format_val;
		err = azx_setup_periods(chip, substream, azx_dev);
		if (err < 0)
			return err;
	}

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	azx_setup_controller(chip, azx_dev);
	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
		azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
	else
		azx_dev->fifo_size = 0;

	return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
				  azx_dev->format_val, substream);
}

1504
static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
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{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1507
	struct azx *chip = apcm->chip;
1508 1509 1510 1511
	struct azx_dev *azx_dev;
	struct snd_pcm_substream *s;
	int start, nsync = 0, sbits = 0;
	int nwait, timeout;
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	switch (cmd) {
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
	case SNDRV_PCM_TRIGGER_START:
1517
		start = 1;
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		break;
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1520
	case SNDRV_PCM_TRIGGER_SUSPEND:
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	case SNDRV_PCM_TRIGGER_STOP:
1522
		start = 0;
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		break;
	default:
1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550
		return -EINVAL;
	}

	snd_pcm_group_for_each_entry(s, substream) {
		if (s->pcm->card != substream->pcm->card)
			continue;
		azx_dev = get_azx_dev(s);
		sbits |= 1 << azx_dev->index;
		nsync++;
		snd_pcm_trigger_done(s, substream);
	}

	spin_lock(&chip->reg_lock);
	if (nsync > 1) {
		/* first, set SYNC bits of corresponding streams */
		azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
	}
	snd_pcm_group_for_each_entry(s, substream) {
		if (s->pcm->card != substream->pcm->card)
			continue;
		azx_dev = get_azx_dev(s);
		if (start)
			azx_stream_start(chip, azx_dev);
		else
			azx_stream_stop(chip, azx_dev);
		azx_dev->running = start;
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	}
	spin_unlock(&chip->reg_lock);
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	if (start) {
		if (nsync == 1)
			return 0;
		/* wait until all FIFOs get ready */
		for (timeout = 5000; timeout; timeout--) {
			nwait = 0;
			snd_pcm_group_for_each_entry(s, substream) {
				if (s->pcm->card != substream->pcm->card)
					continue;
				azx_dev = get_azx_dev(s);
				if (!(azx_sd_readb(azx_dev, SD_STS) &
				      SD_STS_FIFO_READY))
					nwait++;
			}
			if (!nwait)
				break;
			cpu_relax();
		}
	} else {
		/* wait until all RUN bits are cleared */
		for (timeout = 5000; timeout; timeout--) {
			nwait = 0;
			snd_pcm_group_for_each_entry(s, substream) {
				if (s->pcm->card != substream->pcm->card)
					continue;
				azx_dev = get_azx_dev(s);
				if (azx_sd_readb(azx_dev, SD_CTL) &
				    SD_CTL_DMA_START)
					nwait++;
			}
			if (!nwait)
				break;
			cpu_relax();
		}
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	}
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	if (nsync > 1) {
		spin_lock(&chip->reg_lock);
		/* reset SYNC bits */
		azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
		spin_unlock(&chip->reg_lock);
	}
	return 0;
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}

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/* get the current DMA position with correction on VIA chips */
static unsigned int azx_via_get_position(struct azx *chip,
					 struct azx_dev *azx_dev)
{
	unsigned int link_pos, mini_pos, bound_pos;
	unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
	unsigned int fifo_size;

	link_pos = azx_sd_readl(azx_dev, SD_LPIB);
	if (azx_dev->index >= 4) {
		/* Playback, no problem using link position */
		return link_pos;
	}

	/* Capture */
	/* For new chipset,
	 * use mod to get the DMA position just like old chipset
	 */
	mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
	mod_dma_pos %= azx_dev->period_bytes;

	/* azx_dev->fifo_size can't get FIFO size of in stream.
	 * Get from base address + offset.
	 */
	fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);

	if (azx_dev->insufficient) {
		/* Link position never gather than FIFO size */
		if (link_pos <= fifo_size)
			return 0;

		azx_dev->insufficient = 0;
	}

	if (link_pos <= fifo_size)
		mini_pos = azx_dev->bufsize + link_pos - fifo_size;
	else
		mini_pos = link_pos - fifo_size;

	/* Find nearest previous boudary */
	mod_mini_pos = mini_pos % azx_dev->period_bytes;
	mod_link_pos = link_pos % azx_dev->period_bytes;
	if (mod_link_pos >= fifo_size)
		bound_pos = link_pos - mod_link_pos;
	else if (mod_dma_pos >= mod_mini_pos)
		bound_pos = mini_pos - mod_mini_pos;
	else {
		bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
		if (bound_pos >= azx_dev->bufsize)
			bound_pos = 0;
	}

	/* Calculate real DMA position we want */
	return bound_pos + mod_dma_pos;
}

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static unsigned int azx_get_position(struct azx *chip,
				     struct azx_dev *azx_dev)
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{
	unsigned int pos;

1658 1659 1660 1661
	if (chip->via_dmapos_patch)
		pos = azx_via_get_position(chip, azx_dev);
	else if (chip->position_fix == POS_FIX_POSBUF ||
		 chip->position_fix == POS_FIX_AUTO) {
1662
		/* use the position buffer */
1663
		pos = le32_to_cpu(*azx_dev->posbuf);
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	} else {
		/* read LPIB */
		pos = azx_sd_readl(azx_dev, SD_LPIB);
	}
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	if (pos >= azx_dev->bufsize)
		pos = 0;
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	return pos;
}

static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev = get_azx_dev(substream);
	return bytes_to_frames(substream->runtime,
			       azx_get_position(chip, azx_dev));
}

/*
 * Check whether the current DMA position is acceptable for updating
 * periods.  Returns non-zero if it's OK.
 *
 * Many HD-audio controllers appear pretty inaccurate about
 * the update-IRQ timing.  The IRQ is issued before actually the
 * data is processed.  So, we need to process it afterwords in a
 * workqueue.
 */
static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
{
	unsigned int pos;

	pos = azx_get_position(chip, azx_dev);
	if (chip->position_fix == POS_FIX_AUTO) {
		if (!pos) {
			printk(KERN_WARNING
			       "hda-intel: Invalid position buffer, "
			       "using LPIB read method instead.\n");
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			chip->position_fix = POS_FIX_LPIB;
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			pos = azx_get_position(chip, azx_dev);
		} else
			chip->position_fix = POS_FIX_POSBUF;
	}

1707 1708
	if (!bdl_pos_adj[chip->dev_index])
		return 1; /* no delayed ack */
1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721
	if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
		return 0; /* NG - it's below the period boundary */
	return 1; /* OK, it's fine */
}

/*
 * The work for pending PCM period updates.
 */
static void azx_irq_pending_work(struct work_struct *work)
{
	struct azx *chip = container_of(work, struct azx, irq_pending_work);
	int i, pending;

1722 1723 1724 1725 1726 1727 1728 1729
	if (!chip->irq_pending_warned) {
		printk(KERN_WARNING
		       "hda-intel: IRQ timing workaround is activated "
		       "for card #%d. Suggest a bigger bdl_pos_adj.\n",
		       chip->card->number);
		chip->irq_pending_warned = 1;
	}

1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762
	for (;;) {
		pending = 0;
		spin_lock_irq(&chip->reg_lock);
		for (i = 0; i < chip->num_streams; i++) {
			struct azx_dev *azx_dev = &chip->azx_dev[i];
			if (!azx_dev->irq_pending ||
			    !azx_dev->substream ||
			    !azx_dev->running)
				continue;
			if (azx_position_ok(chip, azx_dev)) {
				azx_dev->irq_pending = 0;
				spin_unlock(&chip->reg_lock);
				snd_pcm_period_elapsed(azx_dev->substream);
				spin_lock(&chip->reg_lock);
			} else
				pending++;
		}
		spin_unlock_irq(&chip->reg_lock);
		if (!pending)
			return;
		cond_resched();
	}
}

/* clear irq_pending flags and assure no on-going workq */
static void azx_clear_irq_pending(struct azx *chip)
{
	int i;

	spin_lock_irq(&chip->reg_lock);
	for (i = 0; i < chip->num_streams; i++)
		chip->azx_dev[i].irq_pending = 0;
	spin_unlock_irq(&chip->reg_lock);
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}

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static struct snd_pcm_ops azx_pcm_ops = {
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	.open = azx_pcm_open,
	.close = azx_pcm_close,
	.ioctl = snd_pcm_lib_ioctl,
	.hw_params = azx_pcm_hw_params,
	.hw_free = azx_pcm_hw_free,
	.prepare = azx_pcm_prepare,
	.trigger = azx_pcm_trigger,
	.pointer = azx_pcm_pointer,
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	.page = snd_pcm_sgbuf_ops_page,
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};

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static void azx_pcm_free(struct snd_pcm *pcm)
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{
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	struct azx_pcm *apcm = pcm->private_data;
	if (apcm) {
		apcm->chip->pcm[pcm->device] = NULL;
		kfree(apcm);
	}
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}

1786
static int
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azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
		      struct hda_pcm *cpcm)
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{
1790
	struct azx *chip = bus->private_data;
1791
	struct snd_pcm *pcm;
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	struct azx_pcm *apcm;
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	int pcm_dev = cpcm->device;
	int s, err;
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	if (pcm_dev >= AZX_MAX_PCMS) {
		snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
			   pcm_dev);
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		return -EINVAL;
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	}
	if (chip->pcm[pcm_dev]) {
		snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
		return -EBUSY;
	}
	err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
			  cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
			  cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
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			  &pcm);
	if (err < 0)
		return err;
	strcpy(pcm->name, cpcm->name);
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	apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
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	if (apcm == NULL)
		return -ENOMEM;
	apcm->chip = chip;
	apcm->codec = codec;
	pcm->private_data = apcm;
	pcm->private_free = azx_pcm_free;
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	if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
		pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
	chip->pcm[pcm_dev] = pcm;
	cpcm->pcm = pcm;
	for (s = 0; s < 2; s++) {
		apcm->hinfo[s] = &cpcm->stream[s];
		if (cpcm->stream[s].substreams)
			snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
	}
	/* buffer pre-allocation */
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	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
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					      snd_dma_pci_data(chip->pci),
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					      1024 * 64, 32 * 1024 * 1024);
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	return 0;
}

/*
 * mixer creation - all stuff is implemented in hda module
 */
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static int __devinit azx_mixer_create(struct azx *chip)
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{
	return snd_hda_build_controls(chip->bus);
}


/*
 * initialize SD streams
 */
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static int __devinit azx_init_stream(struct azx *chip)
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{
	int i;

	/* initialize each stream (aka device)
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	 * assign the starting bdl address to each stream (device)
	 * and initialize
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	 */
1855
	for (i = 0; i < chip->num_streams; i++) {
1856
		struct azx_dev *azx_dev = &chip->azx_dev[i];
1857
		azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
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		/* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
		azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
		/* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
		azx_dev->sd_int_sta_mask = 1 << i;
		/* stream tag: must be non-zero and unique */
		azx_dev->index = i;
		azx_dev->stream_tag = i + 1;
	}

	return 0;
}

1870 1871
static int azx_acquire_irq(struct azx *chip, int do_disconnect)
{
1872 1873
	if (request_irq(chip->pci->irq, azx_interrupt,
			chip->msi ? 0 : IRQF_SHARED,
1874 1875 1876 1877 1878 1879 1880 1881
			"HDA Intel", chip)) {
		printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
		       "disabling device\n", chip->pci->irq);
		if (do_disconnect)
			snd_card_disconnect(chip->card);
		return -1;
	}
	chip->irq = chip->pci->irq;
1882
	pci_intx(chip->pci, !chip->msi);
1883 1884 1885
	return 0;
}

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static void azx_stop_chip(struct azx *chip)
{
1889
	if (!chip->initialized)
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		return;

	/* disable interrupts */
	azx_int_disable(chip);
	azx_int_clear(chip);

	/* disable CORB/RIRB */
	azx_free_cmd_io(chip);

	/* disable position buffer */
	azx_writel(chip, DPLBASE, 0);
	azx_writel(chip, DPUBASE, 0);

	chip->initialized = 0;
}

#ifdef CONFIG_SND_HDA_POWER_SAVE
/* power-up/down the controller */
1908
static void azx_power_notify(struct hda_bus *bus)
1909
{
1910
	struct azx *chip = bus->private_data;
1911 1912 1913
	struct hda_codec *c;
	int power_on = 0;

1914
	list_for_each_entry(c, &bus->codec_list, list) {
1915 1916 1917 1918 1919 1920 1921
		if (c->power_on) {
			power_on = 1;
			break;
		}
	}
	if (power_on)
		azx_init_chip(chip);
1922
	else if (chip->running && power_save_controller)
1923 1924
		azx_stop_chip(chip);
}
1925 1926 1927 1928 1929 1930
#endif /* CONFIG_SND_HDA_POWER_SAVE */

#ifdef CONFIG_PM
/*
 * power management
 */
1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941

static int snd_hda_codecs_inuse(struct hda_bus *bus)
{
	struct hda_codec *codec;

	list_for_each_entry(codec, &bus->codec_list, list) {
		if (snd_hda_codec_needs_resume(codec))
			return 1;
	}
	return 0;
}
1942

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static int azx_suspend(struct pci_dev *pci, pm_message_t state)
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{
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	struct snd_card *card = pci_get_drvdata(pci);
	struct azx *chip = card->private_data;
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	int i;

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	snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1950
	azx_clear_irq_pending(chip);
1951
	for (i = 0; i < AZX_MAX_PCMS; i++)
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		snd_pcm_suspend_all(chip->pcm[i]);
1953 1954
	if (chip->initialized)
		snd_hda_suspend(chip->bus, state);
1955
	azx_stop_chip(chip);
1956
	if (chip->irq >= 0) {
1957
		free_irq(chip->irq, chip);
1958 1959
		chip->irq = -1;
	}
1960
	if (chip->msi)
1961
		pci_disable_msi(chip->pci);
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	pci_disable_device(pci);
	pci_save_state(pci);
1964
	pci_set_power_state(pci, pci_choose_state(pci, state));
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	return 0;
}

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static int azx_resume(struct pci_dev *pci)
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{
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	struct snd_card *card = pci_get_drvdata(pci);
	struct azx *chip = card->private_data;
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1973 1974
	pci_set_power_state(pci, PCI_D0);
	pci_restore_state(pci);
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	if (pci_enable_device(pci) < 0) {
		printk(KERN_ERR "hda-intel: pci_enable_device failed, "
		       "disabling device\n");
		snd_card_disconnect(card);
		return -EIO;
	}
	pci_set_master(pci);
1982 1983 1984 1985
	if (chip->msi)
		if (pci_enable_msi(pci) < 0)
			chip->msi = 0;
	if (azx_acquire_irq(chip, 1) < 0)
1986
		return -EIO;
1987
	azx_init_pci(chip);
1988 1989 1990 1991

	if (snd_hda_codecs_inuse(chip->bus))
		azx_init_chip(chip);

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	snd_hda_resume(chip->bus);
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	snd_power_change_state(card, SNDRV_CTL_POWER_D0);
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	return 0;
}
#endif /* CONFIG_PM */


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/*
 * reboot notifier for hang-up problem at power-down
 */
static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
{
	struct azx *chip = container_of(nb, struct azx, reboot_notifier);
	azx_stop_chip(chip);
	return NOTIFY_OK;
}

static void azx_notifier_register(struct azx *chip)
{
	chip->reboot_notifier.notifier_call = azx_halt;
	register_reboot_notifier(&chip->reboot_notifier);
}

static void azx_notifier_unregister(struct azx *chip)
{
	if (chip->reboot_notifier.notifier_call)
		unregister_reboot_notifier(&chip->reboot_notifier);
}

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/*
 * destructor
 */
2024
static int azx_free(struct azx *chip)
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{
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	int i;

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	azx_notifier_unregister(chip);

2030
	if (chip->initialized) {
2031
		azx_clear_irq_pending(chip);
2032
		for (i = 0; i < chip->num_streams; i++)
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			azx_stream_stop(chip, &chip->azx_dev[i]);
2034
		azx_stop_chip(chip);
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	}

2037
	if (chip->irq >= 0)
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		free_irq(chip->irq, (void*)chip);
2039
	if (chip->msi)
2040
		pci_disable_msi(chip->pci);
2041 2042
	if (chip->remap_addr)
		iounmap(chip->remap_addr);
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	if (chip->azx_dev) {
		for (i = 0; i < chip->num_streams; i++)
			if (chip->azx_dev[i].bdl.area)
				snd_dma_free_pages(&chip->azx_dev[i].bdl);
	}
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	if (chip->rb.area)
		snd_dma_free_pages(&chip->rb);
	if (chip->posbuf.area)
		snd_dma_free_pages(&chip->posbuf);
	pci_release_regions(chip->pci);
	pci_disable_device(chip->pci);
2055
	kfree(chip->azx_dev);
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	kfree(chip);

	return 0;
}

2061
static int azx_dev_free(struct snd_device *device)
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{
	return azx_free(device->device_data);
}

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/*
 * white/black-listing for position_fix
 */
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static struct snd_pci_quirk position_fix_list[] __devinitdata = {
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	SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
	SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
	SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
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	{}
};

static int __devinit check_position_fix(struct azx *chip, int fix)
{
	const struct snd_pci_quirk *q;

2080 2081 2082 2083 2084 2085 2086 2087 2088 2089
	switch (fix) {
	case POS_FIX_LPIB:
	case POS_FIX_POSBUF:
		return fix;
	}

	/* Check VIA/ATI HD Audio Controller exist */
	switch (chip->driver_type) {
	case AZX_DRIVER_VIA:
	case AZX_DRIVER_ATI:
2090 2091 2092 2093 2094 2095
		chip->via_dmapos_patch = 1;
		/* Use link position directly, avoid any transfer problem. */
		return POS_FIX_LPIB;
	}
	chip->via_dmapos_patch = 0;

2096 2097 2098 2099 2100 2101 2102
	q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
	if (q) {
		printk(KERN_INFO
		       "hda_intel: position_fix set to %d "
		       "for device %04x:%04x\n",
		       q->value, q->subvendor, q->subdevice);
		return q->value;
2103
	}
2104
	return POS_FIX_AUTO;
2105 2106
}

2107 2108 2109 2110 2111 2112 2113 2114 2115 2116
/*
 * black-lists for probe_mask
 */
static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
	/* Thinkpad often breaks the controller communication when accessing
	 * to the non-working (or non-existing) modem codec slot.
	 */
	SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
	SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
	SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2117 2118
	/* broken BIOS */
	SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2119 2120
	/* including bogus ALC268 in slot#2 that conflicts with ALC888 */
	SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2121 2122
	/* forced codec slots */
	SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2123 2124 2125
	{}
};

2126 2127
#define AZX_FORCE_CODEC_MASK	0x100

2128
static void __devinit check_probe_mask(struct azx *chip, int dev)
2129 2130 2131
{
	const struct snd_pci_quirk *q;

2132 2133
	chip->codec_probe_mask = probe_mask[dev];
	if (chip->codec_probe_mask == -1) {
2134 2135 2136 2137 2138 2139
		q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
		if (q) {
			printk(KERN_INFO
			       "hda_intel: probe_mask set to 0x%x "
			       "for device %04x:%04x\n",
			       q->value, q->subvendor, q->subdevice);
2140
			chip->codec_probe_mask = q->value;
2141 2142
		}
	}
2143 2144 2145 2146 2147 2148 2149 2150

	/* check forced option */
	if (chip->codec_probe_mask != -1 &&
	    (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
		chip->codec_mask = chip->codec_probe_mask & 0xff;
		printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
		       chip->codec_mask);
	}
2151 2152 2153
}


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2154 2155 2156
/*
 * constructor
 */
2157
static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2158
				int dev, int driver_type,
2159
				struct azx **rchip)
L
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2160
{
2161
	struct azx *chip;
T
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2162
	int i, err;
2163
	unsigned short gcap;
2164
	static struct snd_device_ops ops = {
L
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2165 2166 2167 2168
		.dev_free = azx_dev_free,
	};

	*rchip = NULL;
2169

2170 2171
	err = pci_enable_device(pci);
	if (err < 0)
L
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2172 2173
		return err;

2174
	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2175
	if (!chip) {
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2176 2177 2178 2179 2180 2181
		snd_printk(KERN_ERR SFX "cannot allocate chip\n");
		pci_disable_device(pci);
		return -ENOMEM;
	}

	spin_lock_init(&chip->reg_lock);
2182
	mutex_init(&chip->open_mutex);
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2183 2184 2185
	chip->card = card;
	chip->pci = pci;
	chip->irq = -1;
2186
	chip->driver_type = driver_type;
2187
	chip->msi = enable_msi;
2188
	chip->dev_index = dev;
2189
	INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
L
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2190

2191 2192
	chip->position_fix = check_position_fix(chip, position_fix[dev]);
	check_probe_mask(chip, dev);
2193

2194
	chip->single_cmd = single_cmd;
2195

2196 2197
	if (bdl_pos_adj[dev] < 0) {
		switch (chip->driver_type) {
2198 2199
		case AZX_DRIVER_ICH:
			bdl_pos_adj[dev] = 1;
2200 2201
			break;
		default:
2202
			bdl_pos_adj[dev] = 32;
2203 2204 2205 2206
			break;
		}
	}

2207 2208 2209 2210 2211 2212 2213 2214 2215 2216
#if BITS_PER_LONG != 64
	/* Fix up base address on ULI M5461 */
	if (chip->driver_type == AZX_DRIVER_ULI) {
		u16 tmp3;
		pci_read_config_word(pci, 0x40, &tmp3);
		pci_write_config_word(pci, 0x40, tmp3 | 0x10);
		pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
	}
#endif

2217 2218
	err = pci_request_regions(pci, "ICH HD audio");
	if (err < 0) {
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2219 2220 2221 2222 2223
		kfree(chip);
		pci_disable_device(pci);
		return err;
	}

2224
	chip->addr = pci_resource_start(pci, 0);
2225
	chip->remap_addr = pci_ioremap_bar(pci, 0);
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2226 2227 2228 2229 2230 2231
	if (chip->remap_addr == NULL) {
		snd_printk(KERN_ERR SFX "ioremap error\n");
		err = -ENXIO;
		goto errout;
	}

2232 2233 2234
	if (chip->msi)
		if (pci_enable_msi(pci) < 0)
			chip->msi = 0;
2235

2236
	if (azx_acquire_irq(chip, 0) < 0) {
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2237 2238 2239 2240 2241 2242 2243
		err = -EBUSY;
		goto errout;
	}

	pci_set_master(pci);
	synchronize_irq(chip->irq);

2244 2245 2246
	gcap = azx_readw(chip, GCAP);
	snd_printdd("chipset global capabilities = 0x%x\n", gcap);

2247 2248 2249 2250
	/* ATI chips seems buggy about 64bit DMA addresses */
	if (chip->driver_type == AZX_DRIVER_ATI)
		gcap &= ~0x01;

2251 2252 2253
	/* allow 64bit DMA address if supported by H/W */
	if ((gcap & 0x01) && !pci_set_dma_mask(pci, DMA_64BIT_MASK))
		pci_set_consistent_dma_mask(pci, DMA_64BIT_MASK);
2254 2255 2256 2257
	else {
		pci_set_dma_mask(pci, DMA_32BIT_MASK);
		pci_set_consistent_dma_mask(pci, DMA_32BIT_MASK);
	}
2258

2259 2260 2261 2262 2263 2264
	/* read number of streams from GCAP register instead of using
	 * hardcoded value
	 */
	chip->capture_streams = (gcap >> 8) & 0x0f;
	chip->playback_streams = (gcap >> 12) & 0x0f;
	if (!chip->playback_streams && !chip->capture_streams) {
2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275
		/* gcap didn't give any info, switching to old method */

		switch (chip->driver_type) {
		case AZX_DRIVER_ULI:
			chip->playback_streams = ULI_NUM_PLAYBACK;
			chip->capture_streams = ULI_NUM_CAPTURE;
			break;
		case AZX_DRIVER_ATIHDMI:
			chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
			chip->capture_streams = ATIHDMI_NUM_CAPTURE;
			break;
2276
		case AZX_DRIVER_GENERIC:
2277 2278 2279 2280 2281
		default:
			chip->playback_streams = ICH6_NUM_PLAYBACK;
			chip->capture_streams = ICH6_NUM_CAPTURE;
			break;
		}
2282
	}
2283 2284
	chip->capture_index_offset = 0;
	chip->playback_index_offset = chip->capture_streams;
2285
	chip->num_streams = chip->playback_streams + chip->capture_streams;
2286 2287
	chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
				GFP_KERNEL);
2288
	if (!chip->azx_dev) {
2289 2290 2291 2292
		snd_printk(KERN_ERR "cannot malloc azx_dev\n");
		goto errout;
	}

T
Takashi Iwai 已提交
2293 2294 2295 2296 2297 2298 2299 2300 2301
	for (i = 0; i < chip->num_streams; i++) {
		/* allocate memory for the BDL for each stream */
		err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
					  snd_dma_pci_data(chip->pci),
					  BDL_SIZE, &chip->azx_dev[i].bdl);
		if (err < 0) {
			snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
			goto errout;
		}
L
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2302
	}
2303
	/* allocate memory for the position buffer */
2304 2305 2306 2307
	err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
				  snd_dma_pci_data(chip->pci),
				  chip->num_streams * 8, &chip->posbuf);
	if (err < 0) {
2308 2309
		snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
		goto errout;
L
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2310 2311
	}
	/* allocate CORB/RIRB */
2312 2313 2314
	if (!chip->single_cmd) {
		err = azx_alloc_cmd_io(chip);
		if (err < 0)
2315
			goto errout;
2316
	}
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2317 2318 2319 2320 2321

	/* initialize streams */
	azx_init_stream(chip);

	/* initialize chip */
2322
	azx_init_pci(chip);
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2323 2324 2325
	azx_init_chip(chip);

	/* codec detection */
2326
	if (!chip->codec_mask) {
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2327 2328 2329 2330 2331
		snd_printk(KERN_ERR SFX "no codecs found!\n");
		err = -ENODEV;
		goto errout;
	}

2332 2333
	err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
	if (err <0) {
L
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2334 2335 2336 2337
		snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
		goto errout;
	}

2338 2339
	strcpy(card->driver, "HDA-Intel");
	strcpy(card->shortname, driver_short_names[chip->driver_type]);
2340 2341
	sprintf(card->longname, "%s at 0x%lx irq %i",
		card->shortname, chip->addr, chip->irq);
2342

L
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2343 2344 2345 2346 2347 2348 2349 2350
	*rchip = chip;
	return 0;

 errout:
	azx_free(chip);
	return err;
}

2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363
static void power_down_all_codecs(struct azx *chip)
{
#ifdef CONFIG_SND_HDA_POWER_SAVE
	/* The codecs were powered up in snd_hda_codec_new().
	 * Now all initialization done, so turn them down if possible
	 */
	struct hda_codec *codec;
	list_for_each_entry(codec, &chip->bus->codec_list, list) {
		snd_hda_power_down(codec);
	}
#endif
}

2364 2365
static int __devinit azx_probe(struct pci_dev *pci,
			       const struct pci_device_id *pci_id)
L
Linus Torvalds 已提交
2366
{
2367
	static int dev;
2368 2369
	struct snd_card *card;
	struct azx *chip;
2370
	int err;
L
Linus Torvalds 已提交
2371

2372 2373 2374 2375 2376 2377 2378 2379
	if (dev >= SNDRV_CARDS)
		return -ENODEV;
	if (!enable[dev]) {
		dev++;
		return -ENOENT;
	}

	card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
2380
	if (!card) {
L
Linus Torvalds 已提交
2381 2382 2383 2384
		snd_printk(KERN_ERR SFX "Error creating card!\n");
		return -ENOMEM;
	}

2385
	err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
W
Wu Fengguang 已提交
2386 2387
	if (err < 0)
		goto out_free;
T
Takashi Iwai 已提交
2388
	card->private_data = chip;
L
Linus Torvalds 已提交
2389 2390

	/* create codec instances */
2391
	err = azx_codec_create(chip, model[dev], probe_only[dev]);
W
Wu Fengguang 已提交
2392 2393
	if (err < 0)
		goto out_free;
L
Linus Torvalds 已提交
2394 2395

	/* create PCM streams */
2396
	err = snd_hda_build_pcms(chip->bus);
W
Wu Fengguang 已提交
2397 2398
	if (err < 0)
		goto out_free;
L
Linus Torvalds 已提交
2399 2400

	/* create mixer controls */
2401
	err = azx_mixer_create(chip);
W
Wu Fengguang 已提交
2402 2403
	if (err < 0)
		goto out_free;
L
Linus Torvalds 已提交
2404 2405 2406

	snd_card_set_dev(card, &pci->dev);

2407
	err = snd_card_register(card);
W
Wu Fengguang 已提交
2408 2409
	if (err < 0)
		goto out_free;
L
Linus Torvalds 已提交
2410 2411

	pci_set_drvdata(pci, card);
2412 2413
	chip->running = 1;
	power_down_all_codecs(chip);
T
Takashi Iwai 已提交
2414
	azx_notifier_register(chip);
L
Linus Torvalds 已提交
2415

2416
	dev++;
L
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2417
	return err;
W
Wu Fengguang 已提交
2418 2419 2420
out_free:
	snd_card_free(card);
	return err;
L
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2421 2422 2423 2424 2425 2426 2427 2428 2429
}

static void __devexit azx_remove(struct pci_dev *pci)
{
	snd_card_free(pci_get_drvdata(pci));
	pci_set_drvdata(pci, NULL);
}

/* PCI IDs */
2430
static struct pci_device_id azx_ids[] = {
2431 2432 2433 2434 2435
	/* ICH 6..10 */
	{ PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
	{ PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
	{ PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
	{ PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2436
	{ PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2437 2438 2439 2440
	{ PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
	{ PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
	{ PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
	{ PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2441 2442
	/* PCH */
	{ PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2443 2444 2445 2446 2447 2448 2449 2450 2451
	/* SCH */
	{ PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
	/* ATI SB 450/600 */
	{ PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
	{ PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
	/* ATI HDMI */
	{ PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
	{ PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
	{ PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2452
	{ PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487
	{ PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
	{ PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
	{ PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
	{ PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
	{ PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
	{ PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
	{ PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
	{ PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
	{ PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
	{ PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
	/* VIA VT8251/VT8237A */
	{ PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
	/* SIS966 */
	{ PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
	/* ULI M5461 */
	{ PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
	/* NVIDIA MCP */
	{ PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2488 2489 2490 2491
	{ PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
	{ PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2492 2493
	/* Teradici */
	{ PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2494 2495 2496 2497 2498
	/* AMD Generic, PCI class code and Vendor ID for HD Audio */
	{ PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
	  .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
	  .class_mask = 0xffffff,
	  .driver_data = AZX_DRIVER_GENERIC },
L
Linus Torvalds 已提交
2499 2500 2501 2502 2503 2504 2505 2506 2507 2508
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, azx_ids);

/* pci_driver definition */
static struct pci_driver driver = {
	.name = "HDA Intel",
	.id_table = azx_ids,
	.probe = azx_probe,
	.remove = __devexit_p(azx_remove),
T
Takashi Iwai 已提交
2509 2510 2511 2512
#ifdef CONFIG_PM
	.suspend = azx_suspend,
	.resume = azx_resume,
#endif
L
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2513 2514 2515 2516
};

static int __init alsa_card_azx_init(void)
{
2517
	return pci_register_driver(&driver);
L
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2518 2519 2520 2521 2522 2523 2524 2525 2526
}

static void __exit alsa_card_azx_exit(void)
{
	pci_unregister_driver(&driver);
}

module_init(alsa_card_azx_init)
module_exit(alsa_card_azx_exit)