at91sam9g45.dtsi 35.4 KB
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/*
 * at91sam9g45.dtsi - Device Tree Include file for AT91SAM9G45 family SoC
 *                    applies to AT91SAM9G45, AT91SAM9M10,
 *                    AT91SAM9G46, AT91SAM9M11 SoC
 *
 *  Copyright (C) 2011 Atmel,
 *                2011 Nicolas Ferre <nicolas.ferre@atmel.com>
 *
 * Licensed under GPLv2 or later.
 */

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#include "skeleton.dtsi"
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clock/at91.h>
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/ {
	model = "Atmel AT91SAM9G45 family SoC";
	compatible = "atmel,at91sam9g45";
	interrupt-parent = <&aic>;

	aliases {
		serial0 = &dbgu;
		serial1 = &usart0;
		serial2 = &usart1;
		serial3 = &usart2;
		serial4 = &usart3;
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		gpio0 = &pioA;
		gpio1 = &pioB;
		gpio2 = &pioC;
		gpio3 = &pioD;
		gpio4 = &pioE;
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		tcb0 = &tcb0;
		tcb1 = &tcb1;
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		i2c0 = &i2c0;
		i2c1 = &i2c1;
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		ssc0 = &ssc0;
		ssc1 = &ssc1;
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		pwm0 = &pwm0;
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	};
	cpus {
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		#address-cells = <0>;
		#size-cells = <0>;

		cpu {
			compatible = "arm,arm926ej-s";
			device_type = "cpu";
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		};
	};

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	memory {
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		reg = <0x70000000 0x10000000>;
	};

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	clocks {
		slow_xtal: slow_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		main_xtal: main_xtal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		adc_op_clk: adc_op_clk{
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <300000>;
		};
	};

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	sram: sram@00300000 {
		compatible = "mmio-sram";
		reg = <0x00300000 0x10000>;
	};

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	ahb {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		apb {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			aic: interrupt-controller@fffff000 {
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				#interrupt-cells = <3>;
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				compatible = "atmel,at91rm9200-aic";
				interrupt-controller;
				reg = <0xfffff000 0x200>;
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				atmel,external-irqs = <31>;
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			};

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			ramc0: ramc@ffffe400 {
				compatible = "atmel,at91sam9g45-ddramc";
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				reg = <0xffffe400 0x200>;
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				clocks = <&ddrck>;
				clock-names = "ddrck";
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			};

			ramc1: ramc@ffffe600 {
				compatible = "atmel,at91sam9g45-ddramc";
				reg = <0xffffe600 0x200>;
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				clocks = <&ddrck>;
				clock-names = "ddrck";
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			};

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			pmc: pmc@fffffc00 {
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				compatible = "atmel,at91sam9g45-pmc";
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				reg = <0xfffffc00 0x100>;
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				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;
				#interrupt-cells = <1>;

				main_osc: main_osc {
					compatible = "atmel,at91rm9200-clk-main-osc";
					#clock-cells = <0>;
					interrupts-extended = <&pmc AT91_PMC_MOSCS>;
					clocks = <&main_xtal>;
				};

				main: mainck {
					compatible = "atmel,at91rm9200-clk-main";
					#clock-cells = <0>;
					clocks = <&main_osc>;
				};

				plla: pllack {
					compatible = "atmel,at91rm9200-clk-pll";
					#clock-cells = <0>;
					interrupts-extended = <&pmc AT91_PMC_LOCKA>;
					clocks = <&main>;
					reg = <0>;
					atmel,clk-input-range = <2000000 32000000>;
					#atmel,pll-clk-output-range-cells = <4>;
					atmel,pll-clk-output-ranges = <745000000 800000000 0 0
								       695000000 750000000 1 0
								       645000000 700000000 2 0
								       595000000 650000000 3 0
								       545000000 600000000 0 1
								       495000000 555000000 1 1
								       445000000 500000000 2 1
								       400000000 450000000 3 1>;
				};

				plladiv: plladivck {
					compatible = "atmel,at91sam9x5-clk-plldiv";
					#clock-cells = <0>;
					clocks = <&plla>;
				};

				utmi: utmick {
					compatible = "atmel,at91sam9x5-clk-utmi";
					#clock-cells = <0>;
					interrupts-extended = <&pmc AT91_PMC_LOCKU>;
					clocks = <&main>;
				};

				mck: masterck {
					compatible = "atmel,at91rm9200-clk-master";
					#clock-cells = <0>;
					interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
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					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
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					atmel,clk-output-range = <0 133333333>;
					atmel,clk-divisors = <1 2 4 3>;
				};

				usb: usbck {
					compatible = "atmel,at91sam9x5-clk-usb";
					#clock-cells = <0>;
					clocks = <&plladiv>, <&utmi>;
				};

				prog: progck {
					compatible = "atmel,at91sam9g45-clk-programmable";
					#address-cells = <1>;
					#size-cells = <0>;
					interrupt-parent = <&pmc>;
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					clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
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					prog0: prog0 {
						#clock-cells = <0>;
						reg = <0>;
						interrupts = <AT91_PMC_PCKRDY(0)>;
					};

					prog1: prog1 {
						#clock-cells = <0>;
						reg = <1>;
						interrupts = <AT91_PMC_PCKRDY(1)>;
					};
				};

				systemck {
					compatible = "atmel,at91rm9200-clk-system";
					#address-cells = <1>;
					#size-cells = <0>;

					ddrck: ddrck {
						#clock-cells = <0>;
						reg = <2>;
						clocks = <&mck>;
					};

					uhpck: uhpck {
						#clock-cells = <0>;
						reg = <6>;
						clocks = <&usb>;
					};

					pck0: pck0 {
						#clock-cells = <0>;
						reg = <8>;
						clocks = <&prog0>;
					};

					pck1: pck1 {
						#clock-cells = <0>;
						reg = <9>;
						clocks = <&prog1>;
					};
				};

				periphck {
					compatible = "atmel,at91rm9200-clk-peripheral";
					#address-cells = <1>;
					#size-cells = <0>;
					clocks = <&mck>;

					pioA_clk: pioA_clk {
						#clock-cells = <0>;
						reg = <2>;
					};

					pioB_clk: pioB_clk {
						#clock-cells = <0>;
						reg = <3>;
					};

					pioC_clk: pioC_clk {
						#clock-cells = <0>;
						reg = <4>;
					};

					pioDE_clk: pioDE_clk {
						#clock-cells = <0>;
						reg = <5>;
					};

					trng_clk: trng_clk {
						#clock-cells = <0>;
						reg = <6>;
					};

					usart0_clk: usart0_clk {
						#clock-cells = <0>;
						reg = <7>;
					};

					usart1_clk: usart1_clk {
						#clock-cells = <0>;
						reg = <8>;
					};

					usart2_clk: usart2_clk {
						#clock-cells = <0>;
						reg = <9>;
					};

					usart3_clk: usart3_clk {
						#clock-cells = <0>;
						reg = <10>;
					};

					mci0_clk: mci0_clk {
						#clock-cells = <0>;
						reg = <11>;
					};

					twi0_clk: twi0_clk {
						#clock-cells = <0>;
						reg = <12>;
					};

					twi1_clk: twi1_clk {
						#clock-cells = <0>;
						reg = <13>;
					};

					spi0_clk: spi0_clk {
						#clock-cells = <0>;
						reg = <14>;
					};

					spi1_clk: spi1_clk {
						#clock-cells = <0>;
						reg = <15>;
					};

					ssc0_clk: ssc0_clk {
						#clock-cells = <0>;
						reg = <16>;
					};

					ssc1_clk: ssc1_clk {
						#clock-cells = <0>;
						reg = <17>;
					};

					tcb0_clk: tcb0_clk {
						#clock-cells = <0>;
						reg = <18>;
					};

					pwm_clk: pwm_clk {
						#clock-cells = <0>;
						reg = <19>;
					};

					adc_clk: adc_clk {
						#clock-cells = <0>;
						reg = <20>;
					};

					dma0_clk: dma0_clk {
						#clock-cells = <0>;
						reg = <21>;
					};

					uhphs_clk: uhphs_clk {
						#clock-cells = <0>;
						reg = <22>;
					};

					lcd_clk: lcd_clk {
						#clock-cells = <0>;
						reg = <23>;
					};

					ac97_clk: ac97_clk {
						#clock-cells = <0>;
						reg = <24>;
					};

					macb0_clk: macb0_clk {
						#clock-cells = <0>;
						reg = <25>;
					};

					isi_clk: isi_clk {
						#clock-cells = <0>;
						reg = <26>;
					};

					udphs_clk: udphs_clk {
						#clock-cells = <0>;
						reg = <27>;
					};

					aestdessha_clk: aestdessha_clk {
						#clock-cells = <0>;
						reg = <28>;
					};

					mci1_clk: mci1_clk {
						#clock-cells = <0>;
						reg = <29>;
					};

					vdec_clk: vdec_clk {
						#clock-cells = <0>;
						reg = <30>;
					};
				};
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			};

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			rstc@fffffd00 {
				compatible = "atmel,at91sam9g45-rstc";
				reg = <0xfffffd00 0x10>;
			};

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			pit: timer@fffffd30 {
				compatible = "atmel,at91sam9260-pit";
				reg = <0xfffffd30 0xf>;
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				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
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				clocks = <&mck>;
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			};

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			shdwc@fffffd10 {
				compatible = "atmel,at91sam9rl-shdwc";
				reg = <0xfffffd10 0x10>;
			};

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			tcb0: timer@fff7c000 {
				compatible = "atmel,at91rm9200-tcb";
				reg = <0xfff7c000 0x100>;
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				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
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				clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>;
				clock-names = "t0_clk", "t1_clk", "t2_clk";
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			};

			tcb1: timer@fffd4000 {
				compatible = "atmel,at91rm9200-tcb";
				reg = <0xfffd4000 0x100>;
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				interrupts = <18 IRQ_TYPE_LEVEL_HIGH 0>;
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				clocks = <&tcb0_clk>, <&tcb0_clk>, <&tcb0_clk>;
				clock-names = "t0_clk", "t1_clk", "t2_clk";
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			};

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			dma: dma-controller@ffffec00 {
				compatible = "atmel,at91sam9g45-dma";
				reg = <0xffffec00 0x200>;
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				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
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				#dma-cells = <2>;
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				clocks = <&dma0_clk>;
				clock-names = "dma_clk";
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			};

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			pinctrl@fffff200 {
				#address-cells = <1>;
				#size-cells = <1>;
				compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
				ranges = <0xfffff200 0xfffff200 0xa00>;

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				atmel,mux-mask = <
				      /*    A         B     */
				       0xffffffff 0xffc003ff  /* pioA */
				       0xffffffff 0x800f8f00  /* pioB */
				       0xffffffff 0x00000e00  /* pioC */
				       0xffffffff 0xff0c1381  /* pioD */
				       0xffffffff 0x81ffff81  /* pioE */
				      >;

				/* shared pinctrl settings */
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				adc0 {
					pinctrl_adc0_adtrg: adc0_adtrg {
						atmel,pins = <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad0: adc0_ad0 {
						atmel,pins = <AT91_PIOD 20 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad1: adc0_ad1 {
						atmel,pins = <AT91_PIOD 21 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad2: adc0_ad2 {
						atmel,pins = <AT91_PIOD 22 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad3: adc0_ad3 {
						atmel,pins = <AT91_PIOD 23 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad4: adc0_ad4 {
						atmel,pins = <AT91_PIOD 24 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad5: adc0_ad5 {
						atmel,pins = <AT91_PIOD 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad6: adc0_ad6 {
						atmel,pins = <AT91_PIOD 26 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
					pinctrl_adc0_ad7: adc0_ad7 {
						atmel,pins = <AT91_PIOD 27 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
					};
				};

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				dbgu {
					pinctrl_dbgu: dbgu-0 {
						atmel,pins =
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							<AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB12 periph A */
							 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB13 periph A */
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					};
				};

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				i2c0 {
					pinctrl_i2c0: i2c0-0 {
						atmel,pins =
							<AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA21 periph A TWCK0 */
							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA20 periph A TWD0 */
					};
				};

				i2c1 {
					pinctrl_i2c1: i2c1-0 {
						atmel,pins =
							<AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB11 periph A TWCK1 */
							 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB10 periph A TWD1 */
					};
				};

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				isi {
					pinctrl_isi: isi-0 {
						atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
							      AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* D9 */
							      AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
							      AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* D11 */
							      AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
							      AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
							      AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
							      AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
							      AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
							      AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
							      AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
							      AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
							      AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
							      AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
							      AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* HSYNC */
							      AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* MCK */>;
					};
				};

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				usart0 {
					pinctrl_usart0: usart0-0 {
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						atmel,pins =
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							<AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB19 periph A with pullup */
							 AT91_PIOB 18 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB18 periph A */
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					};

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					pinctrl_usart0_rts: usart0_rts-0 {
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						atmel,pins =
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							<AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB17 periph B */
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					};

					pinctrl_usart0_cts: usart0_cts-0 {
						atmel,pins =
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							<AT91_PIOB 15 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PB15 periph B */
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					};
				};

				uart1 {
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					pinctrl_usart1: usart1-0 {
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						atmel,pins =
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							<AT91_PIOB 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB4 periph A with pullup */
							 AT91_PIOB 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB5 periph A */
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					};

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					pinctrl_usart1_rts: usart1_rts-0 {
						atmel,pins =
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							<AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD16 periph A */
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					};

					pinctrl_usart1_cts: usart1_cts-0 {
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						atmel,pins =
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							<AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD17 periph A */
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					};
				};

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				usart2 {
					pinctrl_usart2: usart2-0 {
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						atmel,pins =
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							<AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB6 periph A with pullup */
							 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB7 periph A */
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					};

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					pinctrl_usart2_rts: usart2_rts-0 {
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						atmel,pins =
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							<AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC9 periph B */
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					};

					pinctrl_usart2_cts: usart2_cts-0 {
						atmel,pins =
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							<AT91_PIOC 11 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PC11 periph B */
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					};
				};

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				usart3 {
					pinctrl_usart3: usart3-0 {
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						atmel,pins =
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							<AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PB9 periph A with pullup */
							 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB8 periph A */
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					};

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					pinctrl_usart3_rts: usart3_rts-0 {
						atmel,pins =
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							<AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA23 periph B */
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					};

					pinctrl_usart3_cts: usart3_cts-0 {
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						atmel,pins =
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							<AT91_PIOA 24 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA24 periph B */
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					};
				};
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				nand {
					pinctrl_nand: nand-0 {
						atmel,pins =
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							<AT91_PIOC 8 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP	/* PC8 gpio RDY pin pull_up*/
							 AT91_PIOC 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;	/* PC14 gpio enable pin pull_up */
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					};
				};

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				macb {
					pinctrl_macb_rmii: macb_rmii-0 {
						atmel,pins =
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							<AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA10 periph A */
							 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA11 periph A */
							 AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA12 periph A */
							 AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA13 periph A */
							 AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA14 periph A */
							 AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA15 periph A */
							 AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA16 periph A */
							 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA17 periph A */
							 AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA18 periph A */
							 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PA19 periph A */
614 615 616 617
					};

					pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
						atmel,pins =
618 619 620 621 622 623 624 625
							<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA6 periph B */
							 AT91_PIOA 7 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA7 periph B */
							 AT91_PIOA 8 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA8 periph B */
							 AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA9 periph B */
							 AT91_PIOA 27 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA27 periph B */
							 AT91_PIOA 28 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA28 periph B */
							 AT91_PIOA 29 AT91_PERIPH_B AT91_PINCTRL_NONE	/* PA29 periph B */
							 AT91_PIOA 30 AT91_PERIPH_B AT91_PINCTRL_NONE>;	/* PA30 periph B */
626 627 628
					};
				};

629 630 631
				mmc0 {
					pinctrl_mmc0_slot0_clk_cmd_dat0: mmc0_slot0_clk_cmd_dat0-0 {
						atmel,pins =
632 633 634
							<AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA0 periph A */
							 AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA1 periph A with pullup */
							 AT91_PIOA 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA2 periph A with pullup */
635 636 637 638
					};

					pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
						atmel,pins =
639 640 641
							<AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA3 periph A with pullup */
							 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA4 periph A with pullup */
							 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA5 periph A with pullup */
642 643 644 645
					};

					pinctrl_mmc0_slot0_dat4_7: mmc0_slot0_dat4_7-0 {
						atmel,pins =
646 647 648 649
							<AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA6 periph A with pullup */
							 AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA7 periph A with pullup */
							 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA8 periph A with pullup */
							 AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA9 periph A with pullup */
650 651 652 653 654 655
					};
				};

				mmc1 {
					pinctrl_mmc1_slot0_clk_cmd_dat0: mmc1_slot0_clk_cmd_dat0-0 {
						atmel,pins =
656 657 658
							<AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PA31 periph A */
							 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA22 periph A with pullup */
							 AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA23 periph A with pullup */
659 660 661 662
					};

					pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
						atmel,pins =
663 664 665
							<AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA24 periph A with pullup */
							 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA25 periph A with pullup */
							 AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA26 periph A with pullup */
666 667 668 669
					};

					pinctrl_mmc1_slot0_dat4_7: mmc1_slot0_dat4_7-0 {
						atmel,pins =
670 671 672 673
							<AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA27 periph A with pullup */
							 AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA28 periph A with pullup */
							 AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP	/* PA29 periph A with pullup */
							 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;	/* PA30 periph A with pullup */
674 675 676
					};
				};

677 678 679
				ssc0 {
					pinctrl_ssc0_tx: ssc0_tx-0 {
						atmel,pins =
680 681 682
							<AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD0 periph A */
							 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD1 periph A */
							 AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD2 periph A */
683 684 685 686
					};

					pinctrl_ssc0_rx: ssc0_rx-0 {
						atmel,pins =
687 688 689
							<AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD3 periph A */
							 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD4 periph A */
							 AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD5 periph A */
690 691 692 693 694 695
					};
				};

				ssc1 {
					pinctrl_ssc1_tx: ssc1_tx-0 {
						atmel,pins =
696 697 698
							<AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD10 periph A */
							 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD11 periph A */
							 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD12 periph A */
699 700 701 702
					};

					pinctrl_ssc1_rx: ssc1_rx-0 {
						atmel,pins =
703 704 705
							<AT91_PIOD 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD13 periph A */
							 AT91_PIOD 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PD14 periph A */
							 AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PD15 periph A */
706 707 708
					};
				};

709 710 711
				spi0 {
					pinctrl_spi0: spi0-0 {
						atmel,pins =
712 713 714
							<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB0 periph A SPI0_MISO pin */
							 AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB1 periph A SPI0_MOSI pin */
							 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB2 periph A SPI0_SPCK pin */
715 716 717 718 719 720
					};
				};

				spi1 {
					pinctrl_spi1: spi1-0 {
						atmel,pins =
721 722 723
							<AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB14 periph A SPI1_MISO pin */
							 AT91_PIOB 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PB15 periph A SPI1_MOSI pin */
							 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PB16 periph A SPI1_SPCK pin */
724 725 726
					};
				};

727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802
				tcb0 {
					pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
						atmel,pins = <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
						atmel,pins = <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
						atmel,pins = <AT91_PIOC 10 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
						atmel,pins = <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
						atmel,pins = <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
						atmel,pins = <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
						atmel,pins = <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
						atmel,pins = <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
						atmel,pins = <AT91_PIOA 26 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};
				};

				tcb1 {
					pinctrl_tcb1_tclk0: tcb1_tclk0-0 {
						atmel,pins = <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tclk1: tcb1_tclk1-0 {
						atmel,pins = <AT91_PIOA 3 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tclk2: tcb1_tclk2-0 {
						atmel,pins = <AT91_PIOD 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tioa0: tcb1_tioa0-0 {
						atmel,pins = <AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tioa1: tcb1_tioa1-0 {
						atmel,pins = <AT91_PIOA 4 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tioa2: tcb1_tioa2-0 {
						atmel,pins = <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tiob0: tcb1_tiob0-0 {
						atmel,pins = <AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tiob1: tcb1_tiob1-0 {
						atmel,pins = <AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};

					pinctrl_tcb1_tiob2: tcb1_tiob2-0 {
						atmel,pins = <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
					};
				};

803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838
				fb {
					pinctrl_fb: fb-0 {
						atmel,pins =
							<AT91_PIOE 0 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE0 periph A */
							 AT91_PIOE 2 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE2 periph A */
							 AT91_PIOE 3 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE3 periph A */
							 AT91_PIOE 4 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE4 periph A */
							 AT91_PIOE 5 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE5 periph A */
							 AT91_PIOE 6 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE6 periph A */
							 AT91_PIOE 7 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE7 periph A */
							 AT91_PIOE 8 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE8 periph A */
							 AT91_PIOE 9 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE9 periph A */
							 AT91_PIOE 10 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE10 periph A */
							 AT91_PIOE 11 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE11 periph A */
							 AT91_PIOE 12 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE12 periph A */
							 AT91_PIOE 13 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE13 periph A */
							 AT91_PIOE 14 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE14 periph A */
							 AT91_PIOE 15 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE15 periph A */
							 AT91_PIOE 16 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE16 periph A */
							 AT91_PIOE 17 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE17 periph A */
							 AT91_PIOE 18 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE18 periph A */
							 AT91_PIOE 19 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE19 periph A */
							 AT91_PIOE 20 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE20 periph A */
							 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE21 periph A */
							 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE22 periph A */
							 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE23 periph A */
							 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE24 periph A */
							 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE25 periph A */
							 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE26 periph A */
							 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE27 periph A */
							 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE28 periph A */
							 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE	/* PE29 periph A */
							 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;	/* PE30 periph A */
					};
				};

839 840 841
				pioA: gpio@fffff200 {
					compatible = "atmel,at91rm9200-gpio";
					reg = <0xfffff200 0x200>;
842
					interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
843 844 845 846
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
847
					clocks = <&pioA_clk>;
848 849 850 851 852
				};

				pioB: gpio@fffff400 {
					compatible = "atmel,at91rm9200-gpio";
					reg = <0xfffff400 0x200>;
853
					interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
854 855 856 857
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
858
					clocks = <&pioB_clk>;
859 860 861 862 863
				};

				pioC: gpio@fffff600 {
					compatible = "atmel,at91rm9200-gpio";
					reg = <0xfffff600 0x200>;
864
					interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
865 866 867 868
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
869
					clocks = <&pioC_clk>;
870 871 872 873 874
				};

				pioD: gpio@fffff800 {
					compatible = "atmel,at91rm9200-gpio";
					reg = <0xfffff800 0x200>;
875
					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
876 877 878 879
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
880
					clocks = <&pioDE_clk>;
881 882 883 884 885
				};

				pioE: gpio@fffffa00 {
					compatible = "atmel,at91rm9200-gpio";
					reg = <0xfffffa00 0x200>;
886
					interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>;
887 888 889 890
					#gpio-cells = <2>;
					gpio-controller;
					interrupt-controller;
					#interrupt-cells = <2>;
891
					clocks = <&pioDE_clk>;
892
				};
893 894
			};

895 896 897
			dbgu: serial@ffffee00 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xffffee00 0x200>;
898
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
899 900
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_dbgu>;
901 902
				clocks = <&mck>;
				clock-names = "usart";
903 904 905 906 907 908
				status = "disabled";
			};

			usart0: serial@fff8c000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfff8c000 0x200>;
909
				interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
910 911
				atmel,use-dma-rx;
				atmel,use-dma-tx;
912
				pinctrl-names = "default";
913
				pinctrl-0 = <&pinctrl_usart0>;
914 915
				clocks = <&usart0_clk>;
				clock-names = "usart";
916 917 918 919 920 921
				status = "disabled";
			};

			usart1: serial@fff90000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfff90000 0x200>;
922
				interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
923 924
				atmel,use-dma-rx;
				atmel,use-dma-tx;
925
				pinctrl-names = "default";
926
				pinctrl-0 = <&pinctrl_usart1>;
927 928
				clocks = <&usart1_clk>;
				clock-names = "usart";
929 930 931 932 933 934
				status = "disabled";
			};

			usart2: serial@fff94000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfff94000 0x200>;
935
				interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
936 937
				atmel,use-dma-rx;
				atmel,use-dma-tx;
938
				pinctrl-names = "default";
939
				pinctrl-0 = <&pinctrl_usart2>;
940 941
				clocks = <&usart2_clk>;
				clock-names = "usart";
942 943 944 945 946 947
				status = "disabled";
			};

			usart3: serial@fff98000 {
				compatible = "atmel,at91sam9260-usart";
				reg = <0xfff98000 0x200>;
948
				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 5>;
949 950
				atmel,use-dma-rx;
				atmel,use-dma-tx;
951
				pinctrl-names = "default";
952
				pinctrl-0 = <&pinctrl_usart3>;
953 954
				clocks = <&usart3_clk>;
				clock-names = "usart";
955 956
				status = "disabled";
			};
957 958 959 960

			macb0: ethernet@fffbc000 {
				compatible = "cdns,at32ap7000-macb", "cdns,macb";
				reg = <0xfffbc000 0x100>;
961
				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
962 963
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_macb_rmii>;
964 965
				clocks = <&macb0_clk>, <&macb0_clk>;
				clock-names = "hclk", "pclk";
966 967
				status = "disabled";
			};
968

969 970 971 972 973 974 975
			trng@fffcc000 {
				compatible = "atmel,at91sam9g45-trng";
				reg = <0xfffcc000 0x4000>;
				interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
				clocks = <&trng_clk>;
			};

976 977 978
			i2c0: i2c@fff84000 {
				compatible = "atmel,at91sam9g10-i2c";
				reg = <0xfff84000 0x100>;
979
				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 6>;
980 981
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_i2c0>;
982 983
				#address-cells = <1>;
				#size-cells = <0>;
984
				clocks = <&twi0_clk>;
985 986 987 988 989 990
				status = "disabled";
			};

			i2c1: i2c@fff88000 {
				compatible = "atmel,at91sam9g10-i2c";
				reg = <0xfff88000 0x100>;
991
				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
992 993
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_i2c1>;
994 995
				#address-cells = <1>;
				#size-cells = <0>;
996
				clocks = <&twi1_clk>;
997 998 999
				status = "disabled";
			};

1000 1001 1002
			ssc0: ssc@fff9c000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xfff9c000 0x4000>;
1003
				interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
1004 1005
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
1006 1007
				clocks = <&ssc0_clk>;
				clock-names = "pclk";
1008
				status = "disabled";
1009 1010 1011 1012 1013
			};

			ssc1: ssc@fffa0000 {
				compatible = "atmel,at91sam9g45-ssc";
				reg = <0xfffa0000 0x4000>;
1014
				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
1015 1016
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
1017 1018
				clocks = <&ssc1_clk>;
				clock-names = "pclk";
1019
				status = "disabled";
1020 1021
			};

1022
			adc0: adc@fffb0000 {
1023 1024
				#address-cells = <1>;
				#size-cells = <0>;
1025
				compatible = "atmel,at91sam9g45-adc";
1026
				reg = <0xfffb0000 0x100>;
1027
				interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>;
1028 1029
				clocks = <&adc_clk>, <&adc_op_clk>;
				clock-names = "adc_clk", "adc_op_clk";
1030 1031 1032
				atmel,adc-channels-used = <0xff>;
				atmel,adc-vref = <3300>;
				atmel,adc-startup-time = <40>;
1033 1034 1035
				atmel,adc-res = <8 10>;
				atmel,adc-res-names = "lowres", "highres";
				atmel,adc-use-res = "highres";
1036 1037

				trigger@0 {
1038
					reg = <0>;
1039 1040 1041 1042 1043
					trigger-name = "external-rising";
					trigger-value = <0x1>;
					trigger-external;
				};
				trigger@1 {
1044
					reg = <1>;
1045 1046 1047 1048 1049 1050
					trigger-name = "external-falling";
					trigger-value = <0x2>;
					trigger-external;
				};

				trigger@2 {
1051
					reg = <2>;
1052 1053 1054 1055 1056 1057
					trigger-name = "external-any";
					trigger-value = <0x3>;
					trigger-external;
				};

				trigger@3 {
1058
					reg = <3>;
1059 1060 1061 1062
					trigger-name = "continuous";
					trigger-value = <0x6>;
				};
			};
1063

1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074
			isi@fffb4000 {
				compatible = "atmel,at91sam9g45-isi";
				reg = <0xfffb4000 0x4000>;
				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
				clocks = <&isi_clk>;
				clock-names = "isi_clk";
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_isi>;
				status = "disabled";
			};

B
Bo Shen 已提交
1075 1076 1077 1078 1079
			pwm0: pwm@fffb8000 {
				compatible = "atmel,at91sam9rl-pwm";
				reg = <0xfffb8000 0x300>;
				interrupts = <19 IRQ_TYPE_LEVEL_HIGH 4>;
				#pwm-cells = <3>;
1080
				clocks = <&pwm_clk>;
B
Bo Shen 已提交
1081 1082 1083
				status = "disabled";
			};

1084 1085 1086
			mmc0: mmc@fff80000 {
				compatible = "atmel,hsmci";
				reg = <0xfff80000 0x600>;
1087
				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1088
				pinctrl-names = "default";
1089
				dmas = <&dma 1 AT91_DMA_CFG_PER_ID(0)>;
1090
				dma-names = "rxtx";
1091 1092
				#address-cells = <1>;
				#size-cells = <0>;
1093 1094
				clocks = <&mci0_clk>;
				clock-names = "mci_clk";
1095 1096 1097 1098 1099 1100
				status = "disabled";
			};

			mmc1: mmc@fffd0000 {
				compatible = "atmel,hsmci";
				reg = <0xfffd0000 0x600>;
1101
				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>;
1102
				pinctrl-names = "default";
1103
				dmas = <&dma 1 AT91_DMA_CFG_PER_ID(13)>;
1104
				dma-names = "rxtx";
1105 1106
				#address-cells = <1>;
				#size-cells = <0>;
1107 1108
				clocks = <&mci1_clk>;
				clock-names = "mci_clk";
1109
				status = "disabled";
1110 1111
			};

1112 1113 1114
			watchdog@fffffd40 {
				compatible = "atmel,at91sam9260-wdt";
				reg = <0xfffffd40 0x10>;
1115 1116 1117 1118 1119
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				atmel,watchdog-type = "hardware";
				atmel,reset-type = "all";
				atmel,dbg-halt;
				atmel,idle-halt;
1120
				status = "disabled";
1121 1122 1123 1124 1125 1126 1127 1128
			};

			spi0: spi@fffa4000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xfffa4000 0x200>;
				interrupts = <14 4 3>;
1129 1130
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi0>;
1131 1132
				clocks = <&spi0_clk>;
				clock-names = "spi_clk";
1133 1134 1135 1136 1137 1138 1139 1140 1141
				status = "disabled";
			};

			spi1: spi@fffa8000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91rm9200-spi";
				reg = <0xfffa8000 0x200>;
				interrupts = <15 4 3>;
1142 1143
				pinctrl-names = "default";
				pinctrl-0 = <&pinctrl_spi1>;
1144 1145
				clocks = <&spi1_clk>;
				clock-names = "spi_clk";
1146
				status = "disabled";
1147
			};
1148 1149 1150 1151 1152 1153 1154 1155

			usb2: gadget@fff78000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "atmel,at91sam9rl-udc";
				reg = <0x00600000 0x80000
				       0xfff78000 0x400>;
				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 0>;
1156 1157
				clocks = <&udphs_clk>, <&utmi>;
				clock-names = "pclk", "hclk";
1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211
				status = "disabled";

				ep0 {
					reg = <0>;
					atmel,fifo-size = <64>;
					atmel,nb-banks = <1>;
				};

				ep1 {
					reg = <1>;
					atmel,fifo-size = <1024>;
					atmel,nb-banks = <2>;
					atmel,can-dma;
					atmel,can-isoc;
				};

				ep2 {
					reg = <2>;
					atmel,fifo-size = <1024>;
					atmel,nb-banks = <2>;
					atmel,can-dma;
					atmel,can-isoc;
				};

				ep3 {
					reg = <3>;
					atmel,fifo-size = <1024>;
					atmel,nb-banks = <3>;
					atmel,can-dma;
				};

				ep4 {
					reg = <4>;
					atmel,fifo-size = <1024>;
					atmel,nb-banks = <3>;
					atmel,can-dma;
				};

				ep5 {
					reg = <5>;
					atmel,fifo-size = <1024>;
					atmel,nb-banks = <3>;
					atmel,can-dma;
					atmel,can-isoc;
				};

				ep6 {
					reg = <6>;
					atmel,fifo-size = <1024>;
					atmel,nb-banks = <3>;
					atmel,can-dma;
					atmel,can-isoc;
				};
			};
1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237

			sckc@fffffd50 {
				compatible = "atmel,at91sam9x5-sckc";
				reg = <0xfffffd50 0x4>;

				slow_osc: slow_osc {
					compatible = "atmel,at91sam9x5-clk-slow-osc";
					#clock-cells = <0>;
					atmel,startup-time-usec = <1200000>;
					clocks = <&slow_xtal>;
				};

				slow_rc_osc: slow_rc_osc {
					compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
					#clock-cells = <0>;
					atmel,startup-time-usec = <75>;
					clock-frequency = <32768>;
					clock-accuracy = <50000000>;
				};

				clk32k: slck {
					compatible = "atmel,at91sam9x5-clk-slow";
					#clock-cells = <0>;
					clocks = <&slow_rc_osc &slow_osc>;
				};
			};
1238

1239 1240 1241 1242 1243 1244 1245 1246
			rtc@fffffd20 {
				compatible = "atmel,at91sam9260-rtt";
				reg = <0xfffffd20 0x10>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				clocks = <&clk32k>;
				status = "disabled";
			};

1247 1248 1249 1250 1251 1252
			rtc@fffffdb0 {
				compatible = "atmel,at91rm9200-rtc";
				reg = <0xfffffdb0 0x30>;
				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
				status = "disabled";
			};
B
Boris Brezillon 已提交
1253 1254 1255 1256 1257 1258

			gpbr: syscon@fffffd60 {
				compatible = "atmel,at91sam9260-gpbr", "syscon";
				reg = <0xfffffd60 0x10>;
				status = "disabled";
			};
1259
		};
1260

1261 1262 1263 1264 1265 1266
		fb0: fb@0x00500000 {
			compatible = "atmel,at91sam9g45-lcdc";
			reg = <0x00500000 0x1000>;
			interrupts = <23 IRQ_TYPE_LEVEL_HIGH 3>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_fb>;
1267 1268
			clocks = <&lcd_clk>, <&lcd_clk>;
			clock-names = "hclk", "lcdc_clk";
1269 1270 1271
			status = "disabled";
		};

1272 1273 1274 1275 1276 1277 1278 1279 1280
		nand0: nand@40000000 {
			compatible = "atmel,at91rm9200-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40000000 0x10000000
			       0xffffe200 0x200
			      >;
			atmel,nand-addr-offset = <21>;
			atmel,nand-cmd-offset = <22>;
1281
			atmel,nand-has-dma;
1282 1283
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_nand>;
1284 1285
			gpios = <&pioC 8 GPIO_ACTIVE_HIGH
				 &pioC 14 GPIO_ACTIVE_HIGH
1286 1287 1288 1289
				 0
				>;
			status = "disabled";
		};
1290 1291 1292 1293

		usb0: ohci@00700000 {
			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
			reg = <0x00700000 0x100000>;
1294
			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1295 1296
			clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
			clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
1297 1298
			status = "disabled";
		};
1299 1300 1301 1302

		usb1: ehci@00800000 {
			compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
			reg = <0x00800000 0x100000>;
1303
			interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
1304 1305
			clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
			clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
1306 1307
			status = "disabled";
		};
1308
	};
1309 1310 1311

	i2c@0 {
		compatible = "i2c-gpio";
1312 1313
		gpios = <&pioA 20 GPIO_ACTIVE_HIGH /* sda */
			 &pioA 21 GPIO_ACTIVE_HIGH /* scl */
1314 1315 1316 1317 1318 1319 1320 1321
			>;
		i2c-gpio,sda-open-drain;
		i2c-gpio,scl-open-drain;
		i2c-gpio,delay-us = <5>;	/* ~100 kHz */
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};
1322
};