saa7115.c 54.8 KB
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/* saa711x - Philips SAA711x video decoder driver
 * This driver can work with saa7111, saa7111a, saa7113, saa7114,
 *			     saa7115 and saa7118.
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 *
 * Based on saa7114 driver by Maxim Yevtyushkin, which is based on
 * the saa7111 driver by Dave Perks.
 *
 * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
 * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com>
 *
 * Slight changes for video timing and attachment output by
 * Wolfgang Scherr <scherr@net4you.net>
 *
 * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003)
 * by Ronald Bultje <rbultje@ronald.bitfreak.net>
 *
 * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com>
 * (2/17/2003)
 *
 * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl>
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 *
 * Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
 *	SAA7111, SAA7113 and SAA7118 support
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 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

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#include "saa711x_regs.h"
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#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-ctrls.h>
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#include <media/saa7115.h>
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#include <asm/div64.h>
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#define VRES_60HZ	(480+16)
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MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver");
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MODULE_AUTHOR(  "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, "
		"Hans Verkuil, Mauro Carvalho Chehab");
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MODULE_LICENSE("GPL");

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static bool debug;
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module_param(debug, bool, 0644);
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MODULE_PARM_DESC(debug, "Debug level (0-1)");


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enum saa711x_model {
	SAA7111A,
	SAA7111,
	SAA7113,
	GM7113C,
	SAA7114,
	SAA7115,
	SAA7118,
};

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struct saa711x_state {
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	struct v4l2_subdev sd;
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	struct v4l2_ctrl_handler hdl;

	struct {
		/* chroma gain control cluster */
		struct v4l2_ctrl *agc;
		struct v4l2_ctrl *gain;
	};

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	v4l2_std_id std;
	int input;
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	int output;
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	int enable;
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	int radio;
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	int width;
	int height;
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	enum saa711x_model ident;
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	u32 audclk_freq;
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	u32 crystal_freq;
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	bool ucgc;
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	u8 cgcdiv;
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	bool apll;
	bool double_asclk;
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};

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static inline struct saa711x_state *to_state(struct v4l2_subdev *sd)
{
	return container_of(sd, struct saa711x_state, sd);
}

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static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
{
	return &container_of(ctrl->handler, struct saa711x_state, hdl)->sd;
}

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/* ----------------------------------------------------------------------- */

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static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value)
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{
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	struct i2c_client *client = v4l2_get_subdevdata(sd);

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	return i2c_smbus_write_byte_data(client, reg, value);
}

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/* Sanity routine to check if a register is present */
static int saa711x_has_reg(const int id, const u8 reg)
{
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	if (id == SAA7111)
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		return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
		       (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e;
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	if (id == SAA7111A)
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		return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
		       reg != 0x14 && reg != 0x18 && reg != 0x19 &&
		       reg != 0x1d && reg != 0x1e;
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	/* common for saa7113/4/5/8 */
	if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f ||
	    reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) ||
	    reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) ||
	    reg == 0x82 || (reg >= 0x89 && reg <= 0x8e)))
		return 0;

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	switch (id) {
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	case GM7113C:
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		return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && reg < 0x20;
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	case SAA7113:
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		return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) &&
		       reg != 0x5d && reg < 0x63;
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	case SAA7114:
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		return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) &&
		       (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 &&
		       reg != 0x81 && reg < 0xf0;
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	case SAA7115:
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		return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe);
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	case SAA7118:
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		return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) &&
		       (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 &&
		       (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0;
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	}
	return 1;
}

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static int saa711x_writeregs(struct v4l2_subdev *sd, const unsigned char *regs)
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{
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	struct saa711x_state *state = to_state(sd);
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	unsigned char reg, data;

	while (*regs != 0x00) {
		reg = *(regs++);
		data = *(regs++);
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		/* According with datasheets, reserved regs should be
		   filled with 0 - seems better not to touch on they */
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		if (saa711x_has_reg(state->ident, reg)) {
			if (saa711x_write(sd, reg, data) < 0)
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				return -1;
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		} else {
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			v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg);
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		}
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	}
	return 0;
}

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static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg)
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{
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	struct i2c_client *client = v4l2_get_subdevdata(sd);

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	return i2c_smbus_read_byte_data(client, reg);
}

/* ----------------------------------------------------------------------- */

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/* SAA7111 initialization table */
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static const unsigned char saa7111_init[] = {
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	R_01_INC_DELAY, 0x00,		/* reserved */

	/*front end */
	R_02_INPUT_CNTL_1, 0xd0,	/* FUSE=3, GUDL=2, MODE=0 */
	R_03_INPUT_CNTL_2, 0x23,	/* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0,
					 * GAFIX=0, GAI1=256, GAI2=256 */
	R_04_INPUT_CNTL_3, 0x00,	/* GAI1=256 */
	R_05_INPUT_CNTL_4, 0x00,	/* GAI2=256 */

	/* decoder */
	R_06_H_SYNC_START, 0xf3,	/* HSB at  13(50Hz) /  17(60Hz)
					 * pixels after end of last line */
	R_07_H_SYNC_STOP, 0xe8,		/* HSS seems to be needed to
					 * work with NTSC, too */
	R_08_SYNC_CNTL, 0xc8,		/* AUFD=1, FSEL=1, EXFIL=0,
					 * VTRC=1, HPLL=0, VNOI=0 */
	R_09_LUMA_CNTL, 0x01,		/* BYPS=0, PREF=0, BPSS=0,
					 * VBLB=0, UPTCV=0, APER=1 */
	R_0A_LUMA_BRIGHT_CNTL, 0x80,
	R_0B_LUMA_CONTRAST_CNTL, 0x47,	/* 0b - CONT=1.109 */
	R_0C_CHROMA_SAT_CNTL, 0x40,
	R_0D_CHROMA_HUE_CNTL, 0x00,
	R_0E_CHROMA_CNTL_1, 0x01,	/* 0e - CDTO=0, CSTD=0, DCCF=0,
					 * FCTC=0, CHBW=1 */
	R_0F_CHROMA_GAIN_CNTL, 0x00,	/* reserved */
	R_10_CHROMA_CNTL_2, 0x48,	/* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */
	R_11_MODE_DELAY_CNTL, 0x1c,	/* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1,
					 * OEYC=1, OEHV=1, VIPB=0, COLO=0 */
	R_12_RT_SIGNAL_CNTL, 0x00,	/* 12 - output control 2 */
	R_13_RT_X_PORT_OUT_CNTL, 0x00,	/* 13 - output control 3 */
	R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
	R_15_VGATE_START_FID_CHG, 0x00,
	R_16_VGATE_STOP, 0x00,
	R_17_MISC_VGATE_CONF_AND_MSB, 0x00,

	0x00, 0x00
};

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/*
 * This table has one illegal value, and some values that are not
 * correct according to the datasheet initialization table.
 *
 *  If you need a table with legal/default values tell the driver in
 *  i2c_board_info.platform_data, and you will get the gm7113c_init
 *  table instead.
 */
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/* SAA7113 Init codes */
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static const unsigned char saa7113_init[] = {
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	R_01_INC_DELAY, 0x08,
	R_02_INPUT_CNTL_1, 0xc2,
	R_03_INPUT_CNTL_2, 0x30,
	R_04_INPUT_CNTL_3, 0x00,
	R_05_INPUT_CNTL_4, 0x00,
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	R_06_H_SYNC_START, 0x89,	/* Illegal value -119,
					 * min. value = -108 (0x94) */
	R_07_H_SYNC_STOP, 0x0d,
	R_08_SYNC_CNTL, 0x88,		/* Not datasheet default.
					 * HTC = VTR mode, should be 0x98 */
	R_09_LUMA_CNTL, 0x01,
	R_0A_LUMA_BRIGHT_CNTL, 0x80,
	R_0B_LUMA_CONTRAST_CNTL, 0x47,
	R_0C_CHROMA_SAT_CNTL, 0x40,
	R_0D_CHROMA_HUE_CNTL, 0x00,
	R_0E_CHROMA_CNTL_1, 0x01,
	R_0F_CHROMA_GAIN_CNTL, 0x2a,
	R_10_CHROMA_CNTL_2, 0x08,	/* Not datsheet default.
					 * VRLN enabled, should be 0x00 */
	R_11_MODE_DELAY_CNTL, 0x0c,
	R_12_RT_SIGNAL_CNTL, 0x07,	/* Not datasheet default,
					 * should be 0x01 */
	R_13_RT_X_PORT_OUT_CNTL, 0x00,
	R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
	R_15_VGATE_START_FID_CHG, 0x00,
	R_16_VGATE_STOP, 0x00,
	R_17_MISC_VGATE_CONF_AND_MSB, 0x00,

	0x00, 0x00
};

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/*
 * GM7113C is a clone of the SAA7113 chip
 *  This init table is copied out of the saa7113 datasheet.
 *  In R_08 we enable "Automatic Field Detection" [AUFD],
 *  this is disabled when saa711x_set_v4lstd is called.
 */
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static const unsigned char gm7113c_init[] = {
	R_01_INC_DELAY, 0x08,
	R_02_INPUT_CNTL_1, 0xc0,
	R_03_INPUT_CNTL_2, 0x33,
	R_04_INPUT_CNTL_3, 0x00,
	R_05_INPUT_CNTL_4, 0x00,
	R_06_H_SYNC_START, 0xe9,
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	R_07_H_SYNC_STOP, 0x0d,
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	R_08_SYNC_CNTL, 0x98,
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	R_09_LUMA_CNTL, 0x01,
	R_0A_LUMA_BRIGHT_CNTL, 0x80,
	R_0B_LUMA_CONTRAST_CNTL, 0x47,
	R_0C_CHROMA_SAT_CNTL, 0x40,
	R_0D_CHROMA_HUE_CNTL, 0x00,
	R_0E_CHROMA_CNTL_1, 0x01,
	R_0F_CHROMA_GAIN_CNTL, 0x2a,
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	R_10_CHROMA_CNTL_2, 0x00,
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	R_11_MODE_DELAY_CNTL, 0x0c,
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	R_12_RT_SIGNAL_CNTL, 0x01,
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	R_13_RT_X_PORT_OUT_CNTL, 0x00,
	R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
	R_15_VGATE_START_FID_CHG, 0x00,
	R_16_VGATE_STOP, 0x00,
	R_17_MISC_VGATE_CONF_AND_MSB, 0x00,

	0x00, 0x00
};

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/* If a value differs from the Hauppauge driver values, then the comment starts with
   'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
   Hauppauge driver sets. */

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/* SAA7114 and SAA7115 initialization table */
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static const unsigned char saa7115_init_auto_input[] = {
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		/* Front-End Part */
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	R_01_INC_DELAY, 0x48,			/* white peak control disabled */
	R_03_INPUT_CNTL_2, 0x20,		/* was 0x30. 0x20: long vertical blanking */
	R_04_INPUT_CNTL_3, 0x90,		/* analog gain set to 0 */
	R_05_INPUT_CNTL_4, 0x90,		/* analog gain set to 0 */
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		/* Decoder Part */
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	R_06_H_SYNC_START, 0xeb,		/* horiz sync begin = -21 */
	R_07_H_SYNC_STOP, 0xe0,			/* horiz sync stop = -17 */
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	R_09_LUMA_CNTL, 0x53,			/* 0x53, was 0x56 for 60hz. luminance control */
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	R_0A_LUMA_BRIGHT_CNTL, 0x80,		/* was 0x88. decoder brightness, 0x80 is itu standard */
	R_0B_LUMA_CONTRAST_CNTL, 0x44,		/* was 0x48. decoder contrast, 0x44 is itu standard */
	R_0C_CHROMA_SAT_CNTL, 0x40,		/* was 0x47. decoder saturation, 0x40 is itu standard */
	R_0D_CHROMA_HUE_CNTL, 0x00,
	R_0F_CHROMA_GAIN_CNTL, 0x00,		/* use automatic gain  */
	R_10_CHROMA_CNTL_2, 0x06,		/* chroma: active adaptive combfilter */
	R_11_MODE_DELAY_CNTL, 0x00,
	R_12_RT_SIGNAL_CNTL, 0x9d,		/* RTS0 output control: VGATE */
	R_13_RT_X_PORT_OUT_CNTL, 0x80,		/* ITU656 standard mode, RTCO output enable RTCE */
	R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
	R_18_RAW_DATA_GAIN_CNTL, 0x40,		/* gain 0x00 = nominal */
	R_19_RAW_DATA_OFF_CNTL, 0x80,
	R_1A_COLOR_KILL_LVL_CNTL, 0x77,		/* recommended value */
	R_1B_MISC_TVVCRDET, 0x42,		/* recommended value */
	R_1C_ENHAN_COMB_CTRL1, 0xa9,		/* recommended value */
	R_1D_ENHAN_COMB_CTRL2, 0x01,		/* recommended value */
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	R_80_GLOBAL_CNTL_1, 0x0,		/* No tasks enabled at init */

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		/* Power Device Control */
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	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,	/* reset device */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,	/* set device programmed, all in operational mode */
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	0x00, 0x00
};

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/* Used to reset saa7113, saa7114 and saa7115 */
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static const unsigned char saa7115_cfg_reset_scaler[] = {
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	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00,	/* disable I-port output */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,		/* activate scaler */
	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,	/* enable I-port output */
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	0x00, 0x00
};

/* ============== SAA7715 VIDEO templates =============  */

static const unsigned char saa7115_cfg_60hz_video[] = {
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	R_80_GLOBAL_CNTL_1, 0x00,			/* reset tasks */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
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	R_15_VGATE_START_FID_CHG, 0x03,
	R_16_VGATE_STOP, 0x11,
	R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
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	R_08_SYNC_CNTL, 0x68,			/* 0xBO: auto detection, 0x68 = NTSC */
	R_0E_CHROMA_CNTL_1, 0x07,		/* video autodetection is on */
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	R_5A_V_OFF_FOR_SLICER, 0x06,		/* standard 60hz value for ITU656 line counting */
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	/* Task A */
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	R_90_A_TASK_HANDLING_CNTL, 0x80,
	R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
	R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
	R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,

	/* hoffset low (input), 0x0002 is minimum */
	R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
	R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,

	/* hsize low (input), 0x02d0 = 720 */
	R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
	R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,

	R_98_A_VERT_INPUT_WINDOW_START, 0x05,
	R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,

	R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
	R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,

	R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
	R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,

	R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
	R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
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	/* Task B */
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	R_C0_B_TASK_HANDLING_CNTL, 0x00,
	R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
	R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
	R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,

	/* 0x0002 is minimum */
	R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
	R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,

	/* 0x02d0 = 720 */
	R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
	R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,

	/* vwindow start 0x12 = 18 */
	R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
	R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,

	/* vwindow length 0xf8 = 248 */
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	R_CA_B_VERT_INPUT_WINDOW_LENGTH, VRES_60HZ>>1,
	R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, VRES_60HZ>>9,
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	/* hwindow 0x02d0 = 720 */
	R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
	R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,

	R_F0_LFCO_PER_LINE, 0xad,		/* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
	R_F1_P_I_PARAM_SELECT, 0x05,		/* low bit with 0xF0 */
	R_F5_PULSGEN_LINE_LENGTH, 0xad,
	R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,

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	0x00, 0x00
};

static const unsigned char saa7115_cfg_50hz_video[] = {
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	R_80_GLOBAL_CNTL_1, 0x00,
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,	/* reset scaler */
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	R_15_VGATE_START_FID_CHG, 0x37,		/* VGATE start */
	R_16_VGATE_STOP, 0x16,
	R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
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	R_08_SYNC_CNTL, 0x28,			/* 0x28 = PAL */
	R_0E_CHROMA_CNTL_1, 0x07,
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	R_5A_V_OFF_FOR_SLICER, 0x03,		/* standard 50hz value */
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	/* Task A */
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	R_90_A_TASK_HANDLING_CNTL, 0x81,
	R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
	R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
	R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,

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	/* This is weird: the datasheet says that you should use 2 as the minimum value, */
	/* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
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	/* hoffset low (input), 0x0002 is minimum */
	R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
	R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,

	/* hsize low (input), 0x02d0 = 720 */
	R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
	R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,

	R_98_A_VERT_INPUT_WINDOW_START, 0x03,
	R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,

	/* vsize 0x12 = 18 */
	R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
	R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,

	/* hsize 0x05a0 = 1440 */
	R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
	R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,	/* hsize hi (output) */
	R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12,		/* vsize low (output), 0x12 = 18 */
	R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,	/* vsize hi (output) */
470 471

	/* Task B */
472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503
	R_C0_B_TASK_HANDLING_CNTL, 0x00,
	R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
	R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
	R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,

	/* This is weird: the datasheet says that you should use 2 as the minimum value, */
	/* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
	/* hoffset low (input), 0x0002 is minimum. See comment above. */
	R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
	R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,

	/* hsize 0x02d0 = 720 */
	R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
	R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,

	/* voffset 0x16 = 22 */
	R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
	R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,

	/* vsize 0x0120 = 288 */
	R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
	R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,

	/* hsize 0x02d0 = 720 */
	R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
	R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,

	R_F0_LFCO_PER_LINE, 0xb0,		/* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
	R_F1_P_I_PARAM_SELECT, 0x05,		/* low bit with 0xF0, (was 0x05) */
	R_F5_PULSGEN_LINE_LENGTH, 0xb0,
	R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,

504 505 506 507 508 509
	0x00, 0x00
};

/* ============== SAA7715 VIDEO templates (end) =======  */

static const unsigned char saa7115_cfg_vbi_on[] = {
510 511 512 513 514 515
	R_80_GLOBAL_CNTL_1, 0x00,			/* reset tasks */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
	R_80_GLOBAL_CNTL_1, 0x30,			/* Activate both tasks */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,		/* activate scaler */
	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,	/* Enable I-port output */

516 517 518 519
	0x00, 0x00
};

static const unsigned char saa7115_cfg_vbi_off[] = {
520 521 522 523 524 525
	R_80_GLOBAL_CNTL_1, 0x00,			/* reset tasks */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
	R_80_GLOBAL_CNTL_1, 0x20,			/* Activate only task "B" */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,		/* activate scaler */
	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,	/* Enable I-port output */

526 527 528
	0x00, 0x00
};

529

530
static const unsigned char saa7115_init_misc[] = {
531 532 533 534 535 536
	R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
	R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
	R_84_I_PORT_SIGNAL_DEF, 0x20,
	R_85_I_PORT_SIGNAL_POLAR, 0x21,
	R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
537 538

	/* Task A */
539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577
	R_A0_A_HORIZ_PRESCALING, 0x01,
	R_A1_A_ACCUMULATION_LENGTH, 0x00,
	R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,

	/* Configure controls at nominal value*/
	R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
	R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
	R_A6_A_CHROMA_SATURATION_CNTL, 0x40,

	/* note: 2 x zoom ensures that VBI lines have same length as video lines. */
	R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
	R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,

	R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,

	/* must be horiz lum scaling / 2 */
	R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
	R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,

	/* must be offset luma / 2 */
	R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,

	R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
	R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,

	R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
	R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,

	R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,

	R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
	R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
	R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
	R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,

	R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
	R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
	R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
	R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
578 579

	/* Task B */
580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630
	R_D0_B_HORIZ_PRESCALING, 0x01,
	R_D1_B_ACCUMULATION_LENGTH, 0x00,
	R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,

	/* Configure controls at nominal value*/
	R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
	R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
	R_D6_B_CHROMA_SATURATION_CNTL, 0x40,

	/* hor lum scaling 0x0400 = 1 */
	R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
	R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,

	R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,

	/* must be hor lum scaling / 2 */
	R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
	R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,

	/* must be offset luma / 2 */
	R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,

	R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
	R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,

	R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
	R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,

	R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,

	R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
	R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
	R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
	R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,

	R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
	R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
	R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
	R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,

	R_F2_NOMINAL_PLL2_DTO, 0x50,		/* crystal clock = 24.576 MHz, target = 27MHz */
	R_F3_PLL_INCREMENT, 0x46,
	R_F4_PLL2_STATUS, 0x00,
	R_F7_PULSE_A_POS_MSB, 0x4b,		/* not the recommended settings! */
	R_F8_PULSE_B_POS, 0x00,
	R_F9_PULSE_B_POS_MSB, 0x4b,
	R_FA_PULSE_C_POS, 0x00,
	R_FB_PULSE_C_POS_MSB, 0x4b,

	/* PLL2 lock detection settings: 71 lines 50% phase error */
	R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
631 632

	/* Turn off VBI */
633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662
	R_40_SLICER_CNTL_1, 0x20,             /* No framing code errors allowed. */
	R_41_LCR_BASE, 0xff,
	R_41_LCR_BASE+1, 0xff,
	R_41_LCR_BASE+2, 0xff,
	R_41_LCR_BASE+3, 0xff,
	R_41_LCR_BASE+4, 0xff,
	R_41_LCR_BASE+5, 0xff,
	R_41_LCR_BASE+6, 0xff,
	R_41_LCR_BASE+7, 0xff,
	R_41_LCR_BASE+8, 0xff,
	R_41_LCR_BASE+9, 0xff,
	R_41_LCR_BASE+10, 0xff,
	R_41_LCR_BASE+11, 0xff,
	R_41_LCR_BASE+12, 0xff,
	R_41_LCR_BASE+13, 0xff,
	R_41_LCR_BASE+14, 0xff,
	R_41_LCR_BASE+15, 0xff,
	R_41_LCR_BASE+16, 0xff,
	R_41_LCR_BASE+17, 0xff,
	R_41_LCR_BASE+18, 0xff,
	R_41_LCR_BASE+19, 0xff,
	R_41_LCR_BASE+20, 0xff,
	R_41_LCR_BASE+21, 0xff,
	R_41_LCR_BASE+22, 0xff,
	R_58_PROGRAM_FRAMING_CODE, 0x40,
	R_59_H_OFF_FOR_SLICER, 0x47,
	R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
	R_5D_DID, 0xbd,
	R_5E_SDID, 0x35,

663
	R_02_INPUT_CNTL_1, 0xc4, /* input tuner -> input 4, amplifier active */
664 665 666 667

	R_80_GLOBAL_CNTL_1, 0x20,		/* enable task B */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
668 669 670
	0x00, 0x00
};

671
static int saa711x_odd_parity(u8 c)
672 673 674 675 676 677 678 679
{
	c ^= (c >> 4);
	c ^= (c >> 2);
	c ^= (c >> 1);

	return c & 1;
}

680
static int saa711x_decode_vps(u8 *dst, u8 *p)
681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726
{
	static const u8 biphase_tbl[] = {
		0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
		0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
		0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
		0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
		0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
		0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
		0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
		0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
		0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
		0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
		0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
		0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
		0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
		0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
		0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
		0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
		0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
		0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
		0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
		0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
		0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
		0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
		0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
		0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
		0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
		0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
		0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
		0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
		0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
		0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
		0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
		0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
	};
	int i;
	u8 c, err = 0;

	for (i = 0; i < 2 * 13; i += 2) {
		err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
		c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4);
		dst[i / 2] = c;
	}
	return err & 0xf0;
}

727
static int saa711x_decode_wss(u8 *p)
728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753
{
	static const int wss_bits[8] = {
		0, 0, 0, 1, 0, 1, 1, 1
	};
	unsigned char parity;
	int wss = 0;
	int i;

	for (i = 0; i < 16; i++) {
		int b1 = wss_bits[p[i] & 7];
		int b2 = wss_bits[(p[i] >> 3) & 7];

		if (b1 == b2)
			return -1;
		wss |= b2 << i;
	}
	parity = wss & 15;
	parity ^= parity >> 2;
	parity ^= parity >> 1;

	if (!(parity & 1))
		return -1;

	return wss;
}

754
static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
755
{
756
	struct saa711x_state *state = to_state(sd);
757 758 759 760
	u32 acpf;
	u32 acni;
	u32 hz;
	u64 f;
761
	u8 acc = 0; 	/* reg 0x3a, audio clock control */
762

763
	/* Checks for chips that don't have audio clock (saa7111, saa7113) */
764
	if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD))
765 766
		return 0;

767
	v4l2_dbg(1, debug, sd, "set audio clock freq: %d\n", freq);
768 769 770 771 772 773 774 775 776 777 778

	/* sanity check */
	if (freq < 32000 || freq > 48000)
		return -EINVAL;

	/* hz is the refresh rate times 100 */
	hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000;
	/* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */
	acpf = (25600 * freq) / hz;
	/* acni = (256 * freq * 2^23) / crystal_frequency =
		  (freq * 2^(8+23)) / crystal_frequency =
779
		  (freq << 31) / crystal_frequency */
780 781
	f = freq;
	f = f << 31;
782
	do_div(f, state->crystal_freq);
783
	acni = f;
784 785 786 787 788 789 790 791 792
	if (state->ucgc) {
		acpf = acpf * state->cgcdiv / 16;
		acni = acni * state->cgcdiv / 16;
		acc = 0x80;
		if (state->cgcdiv == 3)
			acc |= 0x40;
	}
	if (state->apll)
		acc |= 0x08;
793

794 795 796 797
	if (state->double_asclk) {
		acpf <<= 1;
		acni <<= 1;
	}
798
	saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
799
	saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10 << state->double_asclk);
800
	saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
801

802 803
	saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
	saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
804
							(acpf >> 8) & 0xff);
805
	saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
806 807
							(acpf >> 16) & 0x03);

808 809 810
	saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
	saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
	saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
811 812 813 814
	state->audclk_freq = freq;
	return 0;
}

815
static int saa711x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
816
{
817
	struct v4l2_subdev *sd = to_sd(ctrl);
818
	struct saa711x_state *state = to_state(sd);
819 820

	switch (ctrl->id) {
821
	case V4L2_CID_CHROMA_AGC:
822
		/* chroma gain cluster */
823 824
		if (state->agc->val)
			state->gain->val =
825
				saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL) & 0x7f;
826
		break;
827 828 829 830
	}
	return 0;
}

831
static int saa711x_s_ctrl(struct v4l2_ctrl *ctrl)
832
{
833
	struct v4l2_subdev *sd = to_sd(ctrl);
834
	struct saa711x_state *state = to_state(sd);
835 836 837

	switch (ctrl->id) {
	case V4L2_CID_BRIGHTNESS:
838
		saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val);
839
		break;
840

841
	case V4L2_CID_CONTRAST:
842
		saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val);
843
		break;
844

845
	case V4L2_CID_SATURATION:
846
		saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val);
847
		break;
848

849
	case V4L2_CID_HUE:
850
		saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val);
851
		break;
852

853
	case V4L2_CID_CHROMA_AGC:
854 855 856 857 858
		/* chroma gain cluster */
		if (state->agc->val)
			saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val);
		else
			saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80);
859
		break;
860

861 862 863 864 865 866 867
	default:
		return -EINVAL;
	}

	return 0;
}

868
static int saa711x_set_size(struct v4l2_subdev *sd, int width, int height)
869
{
870
	struct saa711x_state *state = to_state(sd);
871 872 873 874 875 876
	int HPSC, HFSC;
	int VSCY;
	int res;
	int is_50hz = state->std & V4L2_STD_625_50;
	int Vsrc = is_50hz ? 576 : 480;

877
	v4l2_dbg(1, debug, sd, "decoder set size to %ix%i\n", width, height);
878 879 880 881 882 883 884

	/* FIXME need better bounds checking here */
	if ((width < 1) || (width > 1440))
		return -EINVAL;
	if ((height < 1) || (height > Vsrc))
		return -EINVAL;

885
	if (!saa711x_has_reg(state->ident, R_D0_B_HORIZ_PRESCALING)) {
886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902
		/* Decoder only supports 720 columns and 480 or 576 lines */
		if (width != 720)
			return -EINVAL;
		if (height != Vsrc)
			return -EINVAL;
	}

	state->width = width;
	state->height = height;

	if (!saa711x_has_reg(state->ident, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH))
		return 0;

	/* probably have a valid size, let's set it */
	/* Set output width/height */
	/* width */

903
	saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
904
					(u8) (width & 0xff));
905
	saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
906 907 908
					(u8) ((width >> 8) & 0xff));

	/* Vertical Scaling uses height/2 */
909
	res = height / 2;
910 911 912

	/* On 60Hz, it is using a higher Vertical Output Size */
	if (!is_50hz)
913
		res += (VRES_60HZ - 480) >> 1;
914 915

		/* height */
916
	saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
917
					(u8) (res & 0xff));
918
	saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
919 920 921 922 923 924 925 926 927 928
					(u8) ((res >> 8) & 0xff));

	/* Scaling settings */
	/* Hprescaler is floor(inres/outres) */
	HPSC = (int)(720 / width);
	/* 0 is not allowed (div. by zero) */
	HPSC = HPSC ? HPSC : 1;
	HFSC = (int)((1024 * 720) / (HPSC * width));
	/* FIXME hardcodes to "Task B"
	 * write H prescaler integer */
929
	saa711x_write(sd, R_D0_B_HORIZ_PRESCALING,
930 931
				(u8) (HPSC & 0x3f));

932
	v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
933
	/* write H fine-scaling (luminance) */
934
	saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC,
935
				(u8) (HFSC & 0xff));
936
	saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
937 938 939
				(u8) ((HFSC >> 8) & 0xff));
	/* write H fine-scaling (chrominance)
	 * must be lum/2, so i'll just bitshift :) */
940
	saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING,
941
				(u8) ((HFSC >> 1) & 0xff));
942
	saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
943 944 945
				(u8) ((HFSC >> 9) & 0xff));

	VSCY = (int)((1024 * Vsrc) / height);
946
	v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
947 948

	/* Correct Contrast and Luminance */
949
	saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL,
950
					(u8) (64 * 1024 / VSCY));
951
	saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL,
952 953 954
					(u8) (64 * 1024 / VSCY));

		/* write V fine-scaling (luminance) */
955
	saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC,
956
					(u8) (VSCY & 0xff));
957
	saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
958 959
					(u8) ((VSCY >> 8) & 0xff));
		/* write V fine-scaling (chrominance) */
960
	saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC,
961
					(u8) (VSCY & 0xff));
962
	saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
963 964
					(u8) ((VSCY >> 8) & 0xff));

965
	saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
966 967

	/* Activates task "B" */
968 969
	saa711x_write(sd, R_80_GLOBAL_CNTL_1,
				saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20);
970 971 972 973

	return 0;
}

974
static void saa711x_set_v4lstd(struct v4l2_subdev *sd, v4l2_std_id std)
975
{
976
	struct saa711x_state *state = to_state(sd);
977

978 979 980
	/* Prevent unnecessary standard changes. During a standard
	   change the I-Port is temporarily disabled. Any devices
	   reading from that port can get confused.
981 982
	   Note that s_std is also used to switch from
	   radio to TV mode, so if a s_std is broadcast to
983 984 985 986 987
	   all I2C devices then you do not want to have an unwanted
	   side-effect here. */
	if (std == state->std)
		return;

988 989
	state->std = std;

990 991
	// This works for NTSC-M, SECAM-L and the 50Hz PAL variants.
	if (std & V4L2_STD_525_60) {
992
		v4l2_dbg(1, debug, sd, "decoder set standard 60 Hz\n");
993 994 995 996 997 998
		if (state->ident == GM7113C) {
			u8 reg = saa711x_read(sd, R_08_SYNC_CNTL);
			reg &= ~(SAA7113_R_08_FSEL | SAA7113_R_08_AUFD);
			reg |= SAA7113_R_08_FSEL;
			saa711x_write(sd, R_08_SYNC_CNTL, reg);
		} else {
999
			saa711x_writeregs(sd, saa7115_cfg_60hz_video);
1000
		}
1001
		saa711x_set_size(sd, 720, 480);
1002
	} else {
1003
		v4l2_dbg(1, debug, sd, "decoder set standard 50 Hz\n");
1004 1005 1006 1007 1008
		if (state->ident == GM7113C) {
			u8 reg = saa711x_read(sd, R_08_SYNC_CNTL);
			reg &= ~(SAA7113_R_08_FSEL | SAA7113_R_08_AUFD);
			saa711x_write(sd, R_08_SYNC_CNTL, reg);
		} else {
1009
			saa711x_writeregs(sd, saa7115_cfg_50hz_video);
1010
		}
1011
		saa711x_set_size(sd, 720, 576);
1012 1013
	}

1014
	/* Register 0E - Bits D6-D4 on NO-AUTO mode
1015
		(SAA7111 and SAA7113 doesn't have auto mode)
1016 1017 1018 1019 1020 1021 1022
	    50 Hz / 625 lines           60 Hz / 525 lines
	000 PAL BGDHI (4.43Mhz)         NTSC M (3.58MHz)
	001 NTSC 4.43 (50 Hz)           PAL 4.43 (60 Hz)
	010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz)
	011 NTSC N (3.58MHz)            PAL M (3.58MHz)
	100 reserved                    NTSC-Japan (3.58MHz)
	*/
1023 1024
	if (state->ident <= SAA7113 ||
	    state->ident == GM7113C) {
1025
		u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f;
1026

1027
		if (std == V4L2_STD_PAL_M) {
1028
			reg |= 0x30;
1029
		} else if (std == V4L2_STD_PAL_Nc) {
1030
			reg |= 0x20;
1031
		} else if (std == V4L2_STD_PAL_60) {
1032
			reg |= 0x10;
1033
		} else if (std == V4L2_STD_NTSC_M_JP) {
1034
			reg |= 0x40;
1035
		} else if (std & V4L2_STD_SECAM) {
1036
			reg |= 0x50;
1037
		}
1038
		saa711x_write(sd, R_0E_CHROMA_CNTL_1, reg);
1039 1040
	} else {
		/* restart task B if needed */
1041
		int taskb = saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10;
1042

1043
		if (taskb && state->ident == SAA7114)
1044
			saa711x_writeregs(sd, saa7115_cfg_vbi_on);
1045

1046
		/* switch audio mode too! */
1047
		saa711x_s_clock_freq(sd, state->audclk_freq);
1048
	}
1049 1050 1051
}

/* setup the sliced VBI lcr registers according to the sliced VBI format */
1052
static void saa711x_set_lcr(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
1053
{
1054
	struct saa711x_state *state = to_state(sd);
1055 1056 1057 1058
	int is_50hz = (state->std & V4L2_STD_625_50);
	u8 lcr[24];
	int i, x;

1059 1060
#if 1
	/* saa7113/7114/7118 VBI support are experimental */
1061
	if (!saa711x_has_reg(state->ident, R_41_LCR_BASE))
1062 1063 1064 1065
		return;

#else
	/* SAA7113 and SAA7118 also should support VBI - Need testing */
1066
	if (state->ident != SAA7115)
1067
		return;
1068
#endif
1069 1070 1071 1072

	for (i = 0; i <= 23; i++)
		lcr[i] = 0xff;

1073
	if (fmt == NULL) {
1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105
		/* raw VBI */
		if (is_50hz)
			for (i = 6; i <= 23; i++)
				lcr[i] = 0xdd;
		else
			for (i = 10; i <= 21; i++)
				lcr[i] = 0xdd;
	} else {
		/* sliced VBI */
		/* first clear lines that cannot be captured */
		if (is_50hz) {
			for (i = 0; i <= 5; i++)
				fmt->service_lines[0][i] =
					fmt->service_lines[1][i] = 0;
		}
		else {
			for (i = 0; i <= 9; i++)
				fmt->service_lines[0][i] =
					fmt->service_lines[1][i] = 0;
			for (i = 22; i <= 23; i++)
				fmt->service_lines[0][i] =
					fmt->service_lines[1][i] = 0;
		}

		/* Now set the lcr values according to the specified service */
		for (i = 6; i <= 23; i++) {
			lcr[i] = 0;
			for (x = 0; x <= 1; x++) {
				switch (fmt->service_lines[1-x][i]) {
					case 0:
						lcr[i] |= 0xf << (4 * x);
						break;
1106
					case V4L2_SLICED_TELETEXT_B:
1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124
						lcr[i] |= 1 << (4 * x);
						break;
					case V4L2_SLICED_CAPTION_525:
						lcr[i] |= 4 << (4 * x);
						break;
					case V4L2_SLICED_WSS_625:
						lcr[i] |= 5 << (4 * x);
						break;
					case V4L2_SLICED_VPS:
						lcr[i] |= 7 << (4 * x);
						break;
				}
			}
		}
	}

	/* write the lcr registers */
	for (i = 2; i <= 23; i++) {
1125
		saa711x_write(sd, i - 2 + R_41_LCR_BASE, lcr[i]);
1126 1127 1128
	}

	/* enable/disable raw VBI capturing */
1129
	saa711x_writeregs(sd, fmt == NULL ?
1130 1131
				saa7115_cfg_vbi_on :
				saa7115_cfg_vbi_off);
1132 1133
}

1134
static int saa711x_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *sliced)
1135 1136
{
	static u16 lcr2vbi[] = {
1137
		0, V4L2_SLICED_TELETEXT_B, 0,	/* 1 */
1138 1139 1140 1141 1142 1143 1144
		0, V4L2_SLICED_CAPTION_525,	/* 4 */
		V4L2_SLICED_WSS_625, 0,		/* 5 */
		V4L2_SLICED_VPS, 0, 0, 0, 0,	/* 7 */
		0, 0, 0, 0
	};
	int i;

1145 1146
	memset(sliced->service_lines, 0, sizeof(sliced->service_lines));
	sliced->service_set = 0;
1147
	/* done if using raw VBI */
1148
	if (saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10)
1149 1150
		return 0;
	for (i = 2; i <= 23; i++) {
1151
		u8 v = saa711x_read(sd, i - 2 + R_41_LCR_BASE);
1152 1153 1154 1155 1156 1157 1158 1159 1160

		sliced->service_lines[0][i] = lcr2vbi[v >> 4];
		sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
		sliced->service_set |=
			sliced->service_lines[0][i] | sliced->service_lines[1][i];
	}
	return 0;
}

1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172
static int saa711x_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
{
	saa711x_set_lcr(sd, NULL);
	return 0;
}

static int saa711x_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
{
	saa711x_set_lcr(sd, fmt);
	return 0;
}

1173 1174 1175 1176 1177 1178 1179 1180 1181
static int saa711x_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
{
	if (fmt->code != V4L2_MBUS_FMT_FIXED)
		return -EINVAL;
	fmt->field = V4L2_FIELD_INTERLACED;
	fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
	return saa711x_set_size(sd, fmt->width, fmt->height);
}

1182 1183 1184 1185
/* Decode the sliced VBI data stream as created by the saa7115.
   The format is described in the saa7115 datasheet in Tables 25 and 26
   and in Figure 33.
   The current implementation uses SAV/EAV codes and not the ancillary data
1186
   headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV
1187
   code. */
1188
static int saa711x_decode_vbi_line(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi)
1189
{
1190
	struct saa711x_state *state = to_state(sd);
1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219
	static const char vbi_no_data_pattern[] = {
		0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0
	};
	u8 *p = vbi->p;
	u32 wss;
	int id1, id2;   /* the ID1 and ID2 bytes from the internal header */

	vbi->type = 0;  /* mark result as a failure */
	id1 = p[2];
	id2 = p[3];
	/* Note: the field bit is inverted for 60 Hz video */
	if (state->std & V4L2_STD_525_60)
		id1 ^= 0x40;

	/* Skip internal header, p now points to the start of the payload */
	p += 4;
	vbi->p = p;

	/* calculate field and line number of the VBI packet (1-23) */
	vbi->is_second_field = ((id1 & 0x40) != 0);
	vbi->line = (id1 & 0x3f) << 3;
	vbi->line |= (id2 & 0x70) >> 4;

	/* Obtain data type */
	id2 &= 0xf;

	/* If the VBI slicer does not detect any signal it will fill up
	   the payload buffer with 0xa0 bytes. */
	if (!memcmp(p, vbi_no_data_pattern, sizeof(vbi_no_data_pattern)))
1220
		return 0;
1221 1222 1223 1224

	/* decode payloads */
	switch (id2) {
	case 1:
1225
		vbi->type = V4L2_SLICED_TELETEXT_B;
1226 1227
		break;
	case 4:
1228
		if (!saa711x_odd_parity(p[0]) || !saa711x_odd_parity(p[1]))
1229
			return 0;
1230 1231 1232
		vbi->type = V4L2_SLICED_CAPTION_525;
		break;
	case 5:
1233
		wss = saa711x_decode_wss(p);
1234
		if (wss == -1)
1235
			return 0;
1236 1237 1238 1239 1240
		p[0] = wss & 0xff;
		p[1] = wss >> 8;
		vbi->type = V4L2_SLICED_WSS_625;
		break;
	case 7:
1241
		if (saa711x_decode_vps(p, p) != 0)
1242
			return 0;
1243 1244 1245
		vbi->type = V4L2_SLICED_VPS;
		break;
	default:
1246
		break;
1247
	}
1248
	return 0;
1249 1250 1251 1252
}

/* ============ SAA7115 AUDIO settings (end) ============= */

1253
static int saa711x_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1254
{
1255 1256
	struct saa711x_state *state = to_state(sd);
	int status;
1257

1258 1259 1260
	if (state->radio)
		return 0;
	status = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1261

1262 1263 1264 1265
	v4l2_dbg(1, debug, sd, "status: 0x%02x\n", status);
	vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0;
	return 0;
}
1266

1267 1268 1269
static int saa711x_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
{
	struct saa711x_state *state = to_state(sd);
1270

1271 1272 1273 1274
	state->radio = 0;
	saa711x_set_v4lstd(sd, std);
	return 0;
}
1275

1276 1277 1278
static int saa711x_s_radio(struct v4l2_subdev *sd)
{
	struct saa711x_state *state = to_state(sd);
1279

1280 1281 1282
	state->radio = 1;
	return 0;
}
1283

1284 1285
static int saa711x_s_routing(struct v4l2_subdev *sd,
			     u32 input, u32 output, u32 config)
1286 1287
{
	struct saa711x_state *state = to_state(sd);
1288
	u8 mask = (state->ident <= SAA7111A) ? 0xf8 : 0xf0;
1289

1290 1291 1292
	v4l2_dbg(1, debug, sd, "decoder set input %d output %d\n",
		input, output);

1293
	/* saa7111/3 does not have these inputs */
1294 1295
	if ((state->ident <= SAA7113 ||
	     state->ident == GM7113C) &&
1296 1297
	    (input == SAA7115_COMPOSITE4 ||
	     input == SAA7115_COMPOSITE5)) {
1298 1299
		return -EINVAL;
	}
1300
	if (input > SAA7115_SVIDEO3)
1301
		return -EINVAL;
1302
	if (state->input == input && state->output == output)
1303 1304
		return 0;
	v4l2_dbg(1, debug, sd, "now setting %s input %s output\n",
1305 1306 1307
		(input >= SAA7115_SVIDEO0) ? "S-Video" : "Composite",
		(output == SAA7115_IPORT_ON) ? "iport on" : "iport off");
	state->input = input;
1308 1309

	/* saa7111 has slightly different input numbering */
1310
	if (state->ident <= SAA7111A) {
1311 1312 1313 1314 1315
		if (input >= SAA7115_COMPOSITE4)
			input -= 2;
		/* saa7111 specific */
		saa711x_write(sd, R_10_CHROMA_CNTL_2,
				(saa711x_read(sd, R_10_CHROMA_CNTL_2) & 0x3f) |
1316
				((output & 0xc0) ^ 0x40));
1317 1318
		saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL,
				(saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL) & 0xf0) |
1319
				((output & 2) ? 0x0a : 0));
1320
	}
1321

1322 1323 1324 1325
	/* select mode */
	saa711x_write(sd, R_02_INPUT_CNTL_1,
		      (saa711x_read(sd, R_02_INPUT_CNTL_1) & mask) |
		       input);
1326

1327 1328 1329 1330
	/* bypass chrominance trap for S-Video modes */
	saa711x_write(sd, R_09_LUMA_CNTL,
			(saa711x_read(sd, R_09_LUMA_CNTL) & 0x7f) |
			(state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0));
1331

1332
	state->output = output;
1333 1334
	if (state->ident == SAA7114 ||
			state->ident == SAA7115) {
1335 1336 1337
		saa711x_write(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK,
				(saa711x_read(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK) & 0xfe) |
				(state->output & 0x01));
1338
	}
1339
	if (state->ident > SAA7111A) {
1340 1341 1342 1343 1344
		if (config & SAA7115_IDQ_IS_DEFAULT)
			saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x20);
		else
			saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x21);
	}
1345 1346
	return 0;
}
1347

1348 1349 1350
static int saa711x_s_gpio(struct v4l2_subdev *sd, u32 val)
{
	struct saa711x_state *state = to_state(sd);
1351

1352
	if (state->ident > SAA7111A)
1353 1354 1355 1356 1357
		return -EINVAL;
	saa711x_write(sd, 0x11, (saa711x_read(sd, 0x11) & 0x7f) |
		(val ? 0x80 : 0));
	return 0;
}
1358

1359 1360 1361
static int saa711x_s_stream(struct v4l2_subdev *sd, int enable)
{
	struct saa711x_state *state = to_state(sd);
1362

1363 1364
	v4l2_dbg(1, debug, sd, "%s output\n",
			enable ? "enable" : "disable");
1365

1366 1367 1368 1369 1370 1371
	if (state->enable == enable)
		return 0;
	state->enable = enable;
	if (!saa711x_has_reg(state->ident, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED))
		return 0;
	saa711x_write(sd, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, state->enable);
1372 1373
	return 0;
}
1374

1375
static int saa711x_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags)
1376 1377
{
	struct saa711x_state *state = to_state(sd);
1378

1379
	if (freq != SAA7115_FREQ_32_11_MHZ && freq != SAA7115_FREQ_24_576_MHZ)
1380
		return -EINVAL;
1381
	state->crystal_freq = freq;
1382
	state->double_asclk = flags & SAA7115_FREQ_FL_DOUBLE_ASCLK;
1383
	state->cgcdiv = (flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4;
1384 1385
	state->ucgc = flags & SAA7115_FREQ_FL_UCGC;
	state->apll = flags & SAA7115_FREQ_FL_APLL;
1386 1387 1388
	saa711x_s_clock_freq(sd, state->audclk_freq);
	return 0;
}
1389

1390 1391 1392 1393 1394 1395
static int saa711x_reset(struct v4l2_subdev *sd, u32 val)
{
	v4l2_dbg(1, debug, sd, "decoder RESET\n");
	saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
	return 0;
}
1396

1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416
static int saa711x_g_vbi_data(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_data *data)
{
	/* Note: the internal field ID is inverted for NTSC,
	   so data->field 0 maps to the saa7115 even field,
	   whereas for PAL it maps to the saa7115 odd field. */
	switch (data->id) {
	case V4L2_SLICED_WSS_625:
		if (saa711x_read(sd, 0x6b) & 0xc0)
			return -EIO;
		data->data[0] = saa711x_read(sd, 0x6c);
		data->data[1] = saa711x_read(sd, 0x6d);
		return 0;
	case V4L2_SLICED_CAPTION_525:
		if (data->field == 0) {
			/* CC */
			if (saa711x_read(sd, 0x66) & 0x30)
				return -EIO;
			data->data[0] = saa711x_read(sd, 0x69);
			data->data[1] = saa711x_read(sd, 0x6a);
			return 0;
1417
		}
1418 1419 1420 1421 1422 1423 1424 1425
		/* XDS */
		if (saa711x_read(sd, 0x66) & 0xc0)
			return -EIO;
		data->data[0] = saa711x_read(sd, 0x67);
		data->data[1] = saa711x_read(sd, 0x68);
		return 0;
	default:
		return -EINVAL;
1426
	}
1427
}
1428

1429 1430 1431
static int saa711x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
{
	struct saa711x_state *state = to_state(sd);
1432 1433
	int reg1f, reg1e;

1434 1435 1436 1437 1438 1439
	/*
	 * The V4L2 core already initializes std with all supported
	 * Standards. All driver needs to do is to mask it, to remove
	 * standards that don't apply from the mask
	 */

1440
	reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1441

1442
	if (state->ident == SAA7115) {
1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463
		reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);

		v4l2_dbg(1, debug, sd, "Status byte 1 (0x1e)=0x%02x\n", reg1e);

		switch (reg1e & 0x03) {
		case 1:
			*std &= V4L2_STD_NTSC;
			break;
		case 2:
			/*
			 * V4L2_STD_PAL just cover the european PAL standards.
			 * This is wrong, as the device could also be using an
			 * other PAL standard.
			 */
			*std &= V4L2_STD_PAL   | V4L2_STD_PAL_N  | V4L2_STD_PAL_Nc |
				V4L2_STD_PAL_M | V4L2_STD_PAL_60;
			break;
		case 3:
			*std &= V4L2_STD_SECAM;
			break;
		default:
H
Hans Verkuil 已提交
1464
			*std = V4L2_STD_UNKNOWN;
1465 1466 1467 1468 1469
			/* Can't detect anything */
			break;
		}
	}

1470
	v4l2_dbg(1, debug, sd, "Status byte 2 (0x1f)=0x%02x\n", reg1f);
1471 1472

	/* horizontal/vertical not locked */
H
Hans Verkuil 已提交
1473 1474
	if (reg1f & 0x40) {
		*std = V4L2_STD_UNKNOWN;
1475
		goto ret;
H
Hans Verkuil 已提交
1476
	}
1477

1478
	if (reg1f & 0x20)
1479
		*std &= V4L2_STD_525_60;
1480
	else
1481
		*std &= V4L2_STD_625_50;
1482 1483 1484 1485

ret:
	v4l2_dbg(1, debug, sd, "detected std mask = %08Lx\n", *std);

1486 1487 1488 1489 1490 1491 1492 1493 1494 1495
	return 0;
}

static int saa711x_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
	struct saa711x_state *state = to_state(sd);
	int reg1e = 0x80;
	int reg1f;

	*status = V4L2_IN_ST_NO_SIGNAL;
1496
	if (state->ident == SAA7115)
1497 1498 1499 1500 1501 1502 1503
		reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
	reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
	if ((reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80)
		*status = 0;
	return 0;
}

1504
#ifdef CONFIG_VIDEO_ADV_DEBUG
1505
static int saa711x_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1506 1507
{
	reg->val = saa711x_read(sd, reg->reg & 0xff);
1508
	reg->size = 1;
1509 1510
	return 0;
}
1511

1512
static int saa711x_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1513 1514 1515 1516 1517
{
	saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff);
	return 0;
}
#endif
1518

1519 1520 1521 1522 1523 1524
static int saa711x_log_status(struct v4l2_subdev *sd)
{
	struct saa711x_state *state = to_state(sd);
	int reg1e, reg1f;
	int signalOk;
	int vcr;
1525

1526
	v4l2_info(sd, "Audio frequency: %d Hz\n", state->audclk_freq);
1527
	if (state->ident != SAA7115) {
1528 1529 1530 1531 1532 1533
		/* status for the saa7114 */
		reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
		signalOk = (reg1f & 0xc1) == 0x81;
		v4l2_info(sd, "Video signal:    %s\n", signalOk ? "ok" : "bad");
		v4l2_info(sd, "Frequency:       %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
		return 0;
1534 1535
	}

1536 1537 1538
	/* status for the saa7115 */
	reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
	reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1539

1540 1541
	signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80;
	vcr = !(reg1f & 0x10);
1542

1543 1544 1545 1546 1547 1548
	if (state->input >= 6)
		v4l2_info(sd, "Input:           S-Video %d\n", state->input - 6);
	else
		v4l2_info(sd, "Input:           Composite %d\n", state->input);
	v4l2_info(sd, "Video signal:    %s\n", signalOk ? (vcr ? "VCR" : "broadcast/DVD") : "bad");
	v4l2_info(sd, "Frequency:       %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
1549

1550 1551 1552 1553 1554 1555 1556 1557 1558 1559
	switch (reg1e & 0x03) {
	case 1:
		v4l2_info(sd, "Detected format: NTSC\n");
		break;
	case 2:
		v4l2_info(sd, "Detected format: PAL\n");
		break;
	case 3:
		v4l2_info(sd, "Detected format: SECAM\n");
		break;
1560
	default:
1561 1562
		v4l2_info(sd, "Detected format: BW/No color\n");
		break;
1563
	}
1564
	v4l2_info(sd, "Width, Height:   %d, %d\n", state->width, state->height);
1565
	v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
1566 1567 1568
	return 0;
}

1569 1570
/* ----------------------------------------------------------------------- */

1571 1572 1573 1574 1575
static const struct v4l2_ctrl_ops saa711x_ctrl_ops = {
	.s_ctrl = saa711x_s_ctrl,
	.g_volatile_ctrl = saa711x_g_volatile_ctrl,
};

1576 1577
static const struct v4l2_subdev_core_ops saa711x_core_ops = {
	.log_status = saa711x_log_status,
1578 1579 1580 1581 1582 1583 1584
	.g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
	.try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
	.s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
	.g_ctrl = v4l2_subdev_g_ctrl,
	.s_ctrl = v4l2_subdev_s_ctrl,
	.queryctrl = v4l2_subdev_queryctrl,
	.querymenu = v4l2_subdev_querymenu,
1585
	.s_std = saa711x_s_std,
1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605
	.reset = saa711x_reset,
	.s_gpio = saa711x_s_gpio,
#ifdef CONFIG_VIDEO_ADV_DEBUG
	.g_register = saa711x_g_register,
	.s_register = saa711x_s_register,
#endif
};

static const struct v4l2_subdev_tuner_ops saa711x_tuner_ops = {
	.s_radio = saa711x_s_radio,
	.g_tuner = saa711x_g_tuner,
};

static const struct v4l2_subdev_audio_ops saa711x_audio_ops = {
	.s_clock_freq = saa711x_s_clock_freq,
};

static const struct v4l2_subdev_video_ops saa711x_video_ops = {
	.s_routing = saa711x_s_routing,
	.s_crystal_freq = saa711x_s_crystal_freq,
1606
	.s_mbus_fmt = saa711x_s_mbus_fmt,
1607
	.s_stream = saa711x_s_stream,
1608 1609
	.querystd = saa711x_querystd,
	.g_input_status = saa711x_g_input_status,
1610 1611
};

1612 1613 1614
static const struct v4l2_subdev_vbi_ops saa711x_vbi_ops = {
	.g_vbi_data = saa711x_g_vbi_data,
	.decode_vbi_line = saa711x_decode_vbi_line,
1615 1616 1617
	.g_sliced_fmt = saa711x_g_sliced_fmt,
	.s_sliced_fmt = saa711x_s_sliced_fmt,
	.s_raw_fmt = saa711x_s_raw_fmt,
1618 1619
};

1620 1621 1622 1623 1624
static const struct v4l2_subdev_ops saa711x_ops = {
	.core = &saa711x_core_ops,
	.tuner = &saa711x_tuner_ops,
	.audio = &saa711x_audio_ops,
	.video = &saa711x_video_ops,
1625
	.vbi = &saa711x_vbi_ops,
1626 1627
};

1628 1629
#define CHIP_VER_SIZE	16

1630 1631
/* ----------------------------------------------------------------------- */

1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690
static void saa711x_write_platform_data(struct saa711x_state *state,
					struct saa7115_platform_data *data)
{
	struct v4l2_subdev *sd = &state->sd;
	u8 work;

	if (state->ident != GM7113C &&
	    state->ident != SAA7113)
		return;

	if (data->saa7113_r08_htc) {
		work = saa711x_read(sd, R_08_SYNC_CNTL);
		work &= ~SAA7113_R_08_HTC_MASK;
		work |= ((*data->saa7113_r08_htc) << SAA7113_R_08_HTC_OFFSET);
		saa711x_write(sd, R_08_SYNC_CNTL, work);
	}

	if (data->saa7113_r10_vrln) {
		work = saa711x_read(sd, R_10_CHROMA_CNTL_2);
		work &= ~SAA7113_R_10_VRLN_MASK;
		if (*data->saa7113_r10_vrln)
			work |= (1 << SAA7113_R_10_VRLN_OFFSET);
		saa711x_write(sd, R_10_CHROMA_CNTL_2, work);
	}

	if (data->saa7113_r10_ofts) {
		work = saa711x_read(sd, R_10_CHROMA_CNTL_2);
		work &= ~SAA7113_R_10_OFTS_MASK;
		work |= (*data->saa7113_r10_ofts << SAA7113_R_10_OFTS_OFFSET);
		saa711x_write(sd, R_10_CHROMA_CNTL_2, work);
	}

	if (data->saa7113_r12_rts0) {
		work = saa711x_read(sd, R_12_RT_SIGNAL_CNTL);
		work &= ~SAA7113_R_12_RTS0_MASK;
		work |= (*data->saa7113_r12_rts0 << SAA7113_R_12_RTS0_OFFSET);

		/* According to the datasheet,
		 * SAA7113_RTS_DOT_IN should only be used on RTS1 */
		WARN_ON(*data->saa7113_r12_rts0 == SAA7113_RTS_DOT_IN);
		saa711x_write(sd, R_12_RT_SIGNAL_CNTL, work);
	}

	if (data->saa7113_r12_rts1) {
		work = saa711x_read(sd, R_12_RT_SIGNAL_CNTL);
		work &= ~SAA7113_R_12_RTS1_MASK;
		work |= (*data->saa7113_r12_rts1 << SAA7113_R_12_RTS1_OFFSET);
		saa711x_write(sd, R_12_RT_SIGNAL_CNTL, work);
	}

	if (data->saa7113_r13_adlsb) {
		work = saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL);
		work &= ~SAA7113_R_13_ADLSB_MASK;
		if (*data->saa7113_r13_adlsb)
			work |= (1 << SAA7113_R_13_ADLSB_OFFSET);
		saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL, work);
	}
}

1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701
/**
 * saa711x_detect_chip - Detects the saa711x (or clone) variant
 * @client:		I2C client structure.
 * @id:			I2C device ID structure.
 * @name:		Name of the device to be filled.
 *
 * Detects the Philips/NXP saa711x chip, or some clone of it.
 * if 'id' is NULL or id->driver_data is equal to 1, it auto-probes
 * the analog demod.
 * If the tuner is not found, it returns -ENODEV.
 * If auto-detection is disabled and the tuner doesn't match what it was
1702
 *	required, it returns -EINVAL and fills 'name'.
1703 1704 1705 1706
 * If the chip is found, it returns the chip ID and fills 'name'.
 */
static int saa711x_detect_chip(struct i2c_client *client,
			       const struct i2c_device_id *id,
1707
			       char *name)
1708
{
1709
	char chip_ver[CHIP_VER_SIZE];
1710 1711 1712 1713 1714 1715 1716
	char chip_id;
	int i;
	int autodetect;

	autodetect = !id || id->driver_data == 1;

	/* Read the chip version register */
1717
	for (i = 0; i < CHIP_VER_SIZE; i++) {
1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728
		i2c_smbus_write_byte_data(client, 0, i);
		chip_ver[i] = i2c_smbus_read_byte_data(client, 0);
		name[i] = (chip_ver[i] & 0x0f) + '0';
		if (name[i] > '9')
			name[i] += 'a' - '9' - 1;
	}
	name[i] = '\0';

	/* Check if it is a Philips/NXP chip */
	if (!memcmp(name + 1, "f711", 4)) {
		chip_id = name[5];
1729
		snprintf(name, CHIP_VER_SIZE, "saa711%c", chip_id);
1730 1731 1732 1733 1734 1735 1736

		if (!autodetect && strcmp(name, id->name))
			return -EINVAL;

		switch (chip_id) {
		case '1':
			if (chip_ver[0] & 0xf0) {
1737
				snprintf(name, CHIP_VER_SIZE, "saa711%ca", chip_id);
1738
				v4l_info(client, "saa7111a variant found\n");
1739
				return SAA7111A;
1740
			}
1741
			return SAA7111;
1742
		case '3':
1743
			return SAA7113;
1744
		case '4':
1745
			return SAA7114;
1746
		case '5':
1747
			return SAA7115;
1748
		case '8':
1749
			return SAA7118;
1750 1751 1752
		default:
			v4l2_info(client,
				  "WARNING: Philips/NXP chip unknown - Falling back to saa7111\n");
1753
			return SAA7111;
1754 1755 1756
		}
	}

1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774
	/* Check if it is a gm7113c */
	if (!memcmp(name, "0000", 4)) {
		chip_id = 0;
		for (i = 0; i < 4; i++) {
			chip_id = chip_id << 1;
			chip_id |= (chip_ver[i] & 0x80) ? 1 : 0;
		}

		/*
		 * Note: From the datasheet, only versions 1 and 2
		 * exists. However, tests on a device labeled as:
		 * "GM7113C 1145" returned "10" on all 16 chip
		 * version (reg 0x00) reads. So, we need to also
		 * accept at least verion 0. For now, let's just
		 * assume that a device that returns "0000" for
		 * the lower nibble is a gm7113c.
		 */

1775
		strlcpy(name, "gm7113c", CHIP_VER_SIZE);
1776 1777 1778 1779 1780 1781 1782 1783

		if (!autodetect && strcmp(name, id->name))
			return -EINVAL;

		v4l_dbg(1, debug, client,
			"It seems to be a %s chip (%*ph) @ 0x%x.\n",
			name, 16, chip_ver, client->addr << 1);

1784
		return GM7113C;
1785 1786
	}

1787 1788 1789 1790 1791 1792
	/* Chip was not discovered. Return its ID and don't bind */
	v4l_dbg(1, debug, client, "chip %*ph @ 0x%x is unknown.\n",
		16, chip_ver, client->addr << 1);
	return -ENODEV;
}

1793
static int saa711x_probe(struct i2c_client *client,
1794
			 const struct i2c_device_id *id)
1795
{
1796
	struct saa711x_state *state;
1797
	struct v4l2_subdev *sd;
1798
	struct v4l2_ctrl_handler *hdl;
1799
	struct saa7115_platform_data *pdata;
1800
	int ident;
1801
	char name[CHIP_VER_SIZE + 1];
1802 1803

	/* Check if the adapter supports the needed features */
1804
	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1805
		return -EIO;
1806

1807
	ident = saa711x_detect_chip(client, id, name);
1808 1809 1810 1811
	if (ident == -EINVAL) {
		/* Chip exists, but doesn't match */
		v4l_warn(client, "found %s while %s was expected\n",
			 name, id->name);
1812
		return -ENODEV;
1813
	}
1814 1815
	if (ident < 0)
		return ident;
1816

1817
	strlcpy(client->name, name, sizeof(client->name));
1818

1819
	state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
1820
	if (state == NULL)
1821
		return -ENOMEM;
1822 1823
	sd = &state->sd;
	v4l2_i2c_subdev_init(sd, client, &saa711x_ops);
1824

1825 1826
	v4l_info(client, "%s found @ 0x%x (%s)\n", name,
		 client->addr << 1, client->adapter->name);
1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848
	hdl = &state->hdl;
	v4l2_ctrl_handler_init(hdl, 6);
	/* add in ascending ID order */
	v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
	v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
			V4L2_CID_CONTRAST, 0, 127, 1, 64);
	v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
			V4L2_CID_SATURATION, 0, 127, 1, 64);
	v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
			V4L2_CID_HUE, -128, 127, 1, 0);
	state->agc = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
			V4L2_CID_CHROMA_AGC, 0, 1, 1, 1);
	state->gain = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
			V4L2_CID_CHROMA_GAIN, 0, 127, 1, 40);
	sd->ctrl_handler = hdl;
	if (hdl->error) {
		int err = hdl->error;

		v4l2_ctrl_handler_free(hdl);
		return err;
	}
1849
	v4l2_ctrl_auto_cluster(2, &state->agc, 0, true);
1850

1851
	state->input = -1;
1852
	state->output = SAA7115_IPORT_ON;
1853
	state->enable = 1;
1854
	state->radio = 0;
1855
	state->ident = ident;
1856

1857
	state->audclk_freq = 48000;
1858

1859
	v4l2_dbg(1, debug, sd, "writing init values\n");
1860 1861

	/* init to 60hz/48khz */
1862
	state->crystal_freq = SAA7115_FREQ_24_576_MHZ;
1863
	pdata = client->dev.platform_data;
1864
	switch (state->ident) {
1865 1866
	case SAA7111:
	case SAA7111A:
1867
		saa711x_writeregs(sd, saa7111_init);
1868
		break;
1869
	case GM7113C:
1870 1871
		saa711x_writeregs(sd, gm7113c_init);
		break;
1872
	case SAA7113:
1873 1874 1875 1876
		if (pdata && pdata->saa7113_force_gm7113c_init)
			saa711x_writeregs(sd, gm7113c_init);
		else
			saa711x_writeregs(sd, saa7113_init);
1877 1878
		break;
	default:
1879
		state->crystal_freq = SAA7115_FREQ_32_11_MHZ;
1880
		saa711x_writeregs(sd, saa7115_init_auto_input);
1881
	}
1882
	if (state->ident > SAA7111A && state->ident != GM7113C)
1883
		saa711x_writeregs(sd, saa7115_init_misc);
1884 1885 1886 1887

	if (pdata)
		saa711x_write_platform_data(state, pdata);

1888
	saa711x_set_v4lstd(sd, V4L2_STD_NTSC);
1889
	v4l2_ctrl_handler_setup(hdl);
1890

1891 1892 1893
	v4l2_dbg(1, debug, sd, "status: (1E) 0x%02x, (1F) 0x%02x\n",
		saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC),
		saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC));
1894 1895 1896
	return 0;
}

1897
/* ----------------------------------------------------------------------- */
1898

1899
static int saa711x_remove(struct i2c_client *client)
1900
{
1901 1902 1903
	struct v4l2_subdev *sd = i2c_get_clientdata(client);

	v4l2_device_unregister_subdev(sd);
1904
	v4l2_ctrl_handler_free(sd->ctrl_handler);
1905 1906 1907
	return 0;
}

1908
static const struct i2c_device_id saa711x_id[] = {
1909
	{ "saa7115_auto", 1 }, /* autodetect */
1910 1911 1912 1913 1914
	{ "saa7111", 0 },
	{ "saa7113", 0 },
	{ "saa7114", 0 },
	{ "saa7115", 0 },
	{ "saa7118", 0 },
1915
	{ "gm7113c", 0 },
1916 1917
	{ }
};
1918 1919 1920 1921 1922 1923 1924 1925 1926 1927
MODULE_DEVICE_TABLE(i2c, saa711x_id);

static struct i2c_driver saa711x_driver = {
	.driver = {
		.owner	= THIS_MODULE,
		.name	= "saa7115",
	},
	.probe		= saa711x_probe,
	.remove		= saa711x_remove,
	.id_table	= saa711x_id,
1928
};
1929

1930
module_i2c_driver(saa711x_driver);