saa7115.c 49.7 KB
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/* saa711x - Philips SAA711x video decoder driver
 * This driver can work with saa7111, saa7111a, saa7113, saa7114,
 *			     saa7115 and saa7118.
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 *
 * Based on saa7114 driver by Maxim Yevtyushkin, which is based on
 * the saa7111 driver by Dave Perks.
 *
 * Copyright (C) 1998 Dave Perks <dperks@ibm.net>
 * Copyright (C) 2002 Maxim Yevtyushkin <max@linuxmedialabs.com>
 *
 * Slight changes for video timing and attachment output by
 * Wolfgang Scherr <scherr@net4you.net>
 *
 * Moved over to the linux >= 2.4.x i2c protocol (1/1/2003)
 * by Ronald Bultje <rbultje@ronald.bitfreak.net>
 *
 * Added saa7115 support by Kevin Thayer <nufan_wfk at yahoo.com>
 * (2/17/2003)
 *
 * VBI support (2004) and cleanups (2005) by Hans Verkuil <hverkuil@xs4all.nl>
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 *
 * Copyright (c) 2005-2006 Mauro Carvalho Chehab <mchehab@infradead.org>
 *	SAA7111, SAA7113 and SAA7118 support
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 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
 */

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#include "saa711x_regs.h"
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#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/i2c.h>
#include <linux/videodev2.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-chip-ident.h>
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#include <media/saa7115.h>
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#include <asm/div64.h>
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#define VRES_60HZ	(480+16)
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MODULE_DESCRIPTION("Philips SAA7111/SAA7113/SAA7114/SAA7115/SAA7118 video decoder driver");
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MODULE_AUTHOR(  "Maxim Yevtyushkin, Kevin Thayer, Chris Kennedy, "
		"Hans Verkuil, Mauro Carvalho Chehab");
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MODULE_LICENSE("GPL");

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static bool debug;
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module_param(debug, bool, 0644);
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MODULE_PARM_DESC(debug, "Debug level (0-1)");


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struct saa711x_state {
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	struct v4l2_subdev sd;
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	struct v4l2_ctrl_handler hdl;

	struct {
		/* chroma gain control cluster */
		struct v4l2_ctrl *agc;
		struct v4l2_ctrl *gain;
	};

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	v4l2_std_id std;
	int input;
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	int output;
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	int enable;
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	int radio;
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	int width;
	int height;
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	u32 ident;
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	u32 audclk_freq;
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	u32 crystal_freq;
	u8 ucgc;
	u8 cgcdiv;
	u8 apll;
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};

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static inline struct saa711x_state *to_state(struct v4l2_subdev *sd)
{
	return container_of(sd, struct saa711x_state, sd);
}

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static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
{
	return &container_of(ctrl->handler, struct saa711x_state, hdl)->sd;
}

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/* ----------------------------------------------------------------------- */

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static inline int saa711x_write(struct v4l2_subdev *sd, u8 reg, u8 value)
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{
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	struct i2c_client *client = v4l2_get_subdevdata(sd);

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	return i2c_smbus_write_byte_data(client, reg, value);
}

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/* Sanity routine to check if a register is present */
static int saa711x_has_reg(const int id, const u8 reg)
{
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	if (id == V4L2_IDENT_SAA7111)
		return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
		       (reg < 0x13 || reg > 0x19) && reg != 0x1d && reg != 0x1e;
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	if (id == V4L2_IDENT_SAA7111A)
		return reg < 0x20 && reg != 0x01 && reg != 0x0f &&
		       reg != 0x14 && reg != 0x18 && reg != 0x19 &&
		       reg != 0x1d && reg != 0x1e;
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	/* common for saa7113/4/5/8 */
	if (unlikely((reg >= 0x3b && reg <= 0x3f) || reg == 0x5c || reg == 0x5f ||
	    reg == 0xa3 || reg == 0xa7 || reg == 0xab || reg == 0xaf || (reg >= 0xb5 && reg <= 0xb7) ||
	    reg == 0xd3 || reg == 0xd7 || reg == 0xdb || reg == 0xdf || (reg >= 0xe5 && reg <= 0xe7) ||
	    reg == 0x82 || (reg >= 0x89 && reg <= 0x8e)))
		return 0;

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	switch (id) {
	case V4L2_IDENT_SAA7113:
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		return reg != 0x14 && (reg < 0x18 || reg > 0x1e) && (reg < 0x20 || reg > 0x3f) &&
		       reg != 0x5d && reg < 0x63;
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	case V4L2_IDENT_SAA7114:
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		return (reg < 0x1a || reg > 0x1e) && (reg < 0x20 || reg > 0x2f) &&
		       (reg < 0x63 || reg > 0x7f) && reg != 0x33 && reg != 0x37 &&
		       reg != 0x81 && reg < 0xf0;
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	case V4L2_IDENT_SAA7115:
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		return (reg < 0x20 || reg > 0x2f) && reg != 0x65 && (reg < 0xfc || reg > 0xfe);
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	case V4L2_IDENT_SAA7118:
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		return (reg < 0x1a || reg > 0x1d) && (reg < 0x20 || reg > 0x22) &&
		       (reg < 0x26 || reg > 0x28) && reg != 0x33 && reg != 0x37 &&
		       (reg < 0x63 || reg > 0x7f) && reg != 0x81 && reg < 0xf0;
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	}
	return 1;
}

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static int saa711x_writeregs(struct v4l2_subdev *sd, const unsigned char *regs)
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{
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	struct saa711x_state *state = to_state(sd);
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	unsigned char reg, data;

	while (*regs != 0x00) {
		reg = *(regs++);
		data = *(regs++);
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		/* According with datasheets, reserved regs should be
		   filled with 0 - seems better not to touch on they */
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		if (saa711x_has_reg(state->ident, reg)) {
			if (saa711x_write(sd, reg, data) < 0)
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				return -1;
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		} else {
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			v4l2_dbg(1, debug, sd, "tried to access reserved reg 0x%02x\n", reg);
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		}
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	}
	return 0;
}

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static inline int saa711x_read(struct v4l2_subdev *sd, u8 reg)
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{
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	struct i2c_client *client = v4l2_get_subdevdata(sd);

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	return i2c_smbus_read_byte_data(client, reg);
}

/* ----------------------------------------------------------------------- */

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/* SAA7111 initialization table */
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static const unsigned char saa7111_init[] = {
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	R_01_INC_DELAY, 0x00,		/* reserved */

	/*front end */
	R_02_INPUT_CNTL_1, 0xd0,	/* FUSE=3, GUDL=2, MODE=0 */
	R_03_INPUT_CNTL_2, 0x23,	/* HLNRS=0, VBSL=1, WPOFF=0, HOLDG=0,
					 * GAFIX=0, GAI1=256, GAI2=256 */
	R_04_INPUT_CNTL_3, 0x00,	/* GAI1=256 */
	R_05_INPUT_CNTL_4, 0x00,	/* GAI2=256 */

	/* decoder */
	R_06_H_SYNC_START, 0xf3,	/* HSB at  13(50Hz) /  17(60Hz)
					 * pixels after end of last line */
	R_07_H_SYNC_STOP, 0xe8,		/* HSS seems to be needed to
					 * work with NTSC, too */
	R_08_SYNC_CNTL, 0xc8,		/* AUFD=1, FSEL=1, EXFIL=0,
					 * VTRC=1, HPLL=0, VNOI=0 */
	R_09_LUMA_CNTL, 0x01,		/* BYPS=0, PREF=0, BPSS=0,
					 * VBLB=0, UPTCV=0, APER=1 */
	R_0A_LUMA_BRIGHT_CNTL, 0x80,
	R_0B_LUMA_CONTRAST_CNTL, 0x47,	/* 0b - CONT=1.109 */
	R_0C_CHROMA_SAT_CNTL, 0x40,
	R_0D_CHROMA_HUE_CNTL, 0x00,
	R_0E_CHROMA_CNTL_1, 0x01,	/* 0e - CDTO=0, CSTD=0, DCCF=0,
					 * FCTC=0, CHBW=1 */
	R_0F_CHROMA_GAIN_CNTL, 0x00,	/* reserved */
	R_10_CHROMA_CNTL_2, 0x48,	/* 10 - OFTS=1, HDEL=0, VRLN=1, YDEL=0 */
	R_11_MODE_DELAY_CNTL, 0x1c,	/* 11 - GPSW=0, CM99=0, FECO=0, COMPO=1,
					 * OEYC=1, OEHV=1, VIPB=0, COLO=0 */
	R_12_RT_SIGNAL_CNTL, 0x00,	/* 12 - output control 2 */
	R_13_RT_X_PORT_OUT_CNTL, 0x00,	/* 13 - output control 3 */
	R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
	R_15_VGATE_START_FID_CHG, 0x00,
	R_16_VGATE_STOP, 0x00,
	R_17_MISC_VGATE_CONF_AND_MSB, 0x00,

	0x00, 0x00
};

/* SAA7113 init codes */
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static const unsigned char saa7113_init[] = {
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	R_01_INC_DELAY, 0x08,
	R_02_INPUT_CNTL_1, 0xc2,
	R_03_INPUT_CNTL_2, 0x30,
	R_04_INPUT_CNTL_3, 0x00,
	R_05_INPUT_CNTL_4, 0x00,
	R_06_H_SYNC_START, 0x89,
	R_07_H_SYNC_STOP, 0x0d,
	R_08_SYNC_CNTL, 0x88,
	R_09_LUMA_CNTL, 0x01,
	R_0A_LUMA_BRIGHT_CNTL, 0x80,
	R_0B_LUMA_CONTRAST_CNTL, 0x47,
	R_0C_CHROMA_SAT_CNTL, 0x40,
	R_0D_CHROMA_HUE_CNTL, 0x00,
	R_0E_CHROMA_CNTL_1, 0x01,
	R_0F_CHROMA_GAIN_CNTL, 0x2a,
	R_10_CHROMA_CNTL_2, 0x08,
	R_11_MODE_DELAY_CNTL, 0x0c,
	R_12_RT_SIGNAL_CNTL, 0x07,
	R_13_RT_X_PORT_OUT_CNTL, 0x00,
	R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
	R_15_VGATE_START_FID_CHG, 0x00,
	R_16_VGATE_STOP, 0x00,
	R_17_MISC_VGATE_CONF_AND_MSB, 0x00,

	0x00, 0x00
};

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/* If a value differs from the Hauppauge driver values, then the comment starts with
   'was 0xXX' to denote the Hauppauge value. Otherwise the value is identical to what the
   Hauppauge driver sets. */

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/* SAA7114 and SAA7115 initialization table */
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static const unsigned char saa7115_init_auto_input[] = {
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		/* Front-End Part */
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	R_01_INC_DELAY, 0x48,			/* white peak control disabled */
	R_03_INPUT_CNTL_2, 0x20,		/* was 0x30. 0x20: long vertical blanking */
	R_04_INPUT_CNTL_3, 0x90,		/* analog gain set to 0 */
	R_05_INPUT_CNTL_4, 0x90,		/* analog gain set to 0 */
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		/* Decoder Part */
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	R_06_H_SYNC_START, 0xeb,		/* horiz sync begin = -21 */
	R_07_H_SYNC_STOP, 0xe0,			/* horiz sync stop = -17 */
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	R_09_LUMA_CNTL, 0x53,			/* 0x53, was 0x56 for 60hz. luminance control */
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	R_0A_LUMA_BRIGHT_CNTL, 0x80,		/* was 0x88. decoder brightness, 0x80 is itu standard */
	R_0B_LUMA_CONTRAST_CNTL, 0x44,		/* was 0x48. decoder contrast, 0x44 is itu standard */
	R_0C_CHROMA_SAT_CNTL, 0x40,		/* was 0x47. decoder saturation, 0x40 is itu standard */
	R_0D_CHROMA_HUE_CNTL, 0x00,
	R_0F_CHROMA_GAIN_CNTL, 0x00,		/* use automatic gain  */
	R_10_CHROMA_CNTL_2, 0x06,		/* chroma: active adaptive combfilter */
	R_11_MODE_DELAY_CNTL, 0x00,
	R_12_RT_SIGNAL_CNTL, 0x9d,		/* RTS0 output control: VGATE */
	R_13_RT_X_PORT_OUT_CNTL, 0x80,		/* ITU656 standard mode, RTCO output enable RTCE */
	R_14_ANAL_ADC_COMPAT_CNTL, 0x00,
	R_18_RAW_DATA_GAIN_CNTL, 0x40,		/* gain 0x00 = nominal */
	R_19_RAW_DATA_OFF_CNTL, 0x80,
	R_1A_COLOR_KILL_LVL_CNTL, 0x77,		/* recommended value */
	R_1B_MISC_TVVCRDET, 0x42,		/* recommended value */
	R_1C_ENHAN_COMB_CTRL1, 0xa9,		/* recommended value */
	R_1D_ENHAN_COMB_CTRL2, 0x01,		/* recommended value */
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	R_80_GLOBAL_CNTL_1, 0x0,		/* No tasks enabled at init */

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		/* Power Device Control */
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	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,	/* reset device */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,	/* set device programmed, all in operational mode */
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	0x00, 0x00
};

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/* Used to reset saa7113, saa7114 and saa7115 */
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static const unsigned char saa7115_cfg_reset_scaler[] = {
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	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x00,	/* disable I-port output */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,		/* activate scaler */
	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,	/* enable I-port output */
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	0x00, 0x00
};

/* ============== SAA7715 VIDEO templates =============  */

static const unsigned char saa7115_cfg_60hz_video[] = {
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	R_80_GLOBAL_CNTL_1, 0x00,			/* reset tasks */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
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	R_15_VGATE_START_FID_CHG, 0x03,
	R_16_VGATE_STOP, 0x11,
	R_17_MISC_VGATE_CONF_AND_MSB, 0x9c,
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	R_08_SYNC_CNTL, 0x68,			/* 0xBO: auto detection, 0x68 = NTSC */
	R_0E_CHROMA_CNTL_1, 0x07,		/* video autodetection is on */
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	R_5A_V_OFF_FOR_SLICER, 0x06,		/* standard 60hz value for ITU656 line counting */
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	/* Task A */
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	R_90_A_TASK_HANDLING_CNTL, 0x80,
	R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
	R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
	R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,

	/* hoffset low (input), 0x0002 is minimum */
	R_94_A_HORIZ_INPUT_WINDOW_START, 0x01,
	R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,

	/* hsize low (input), 0x02d0 = 720 */
	R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
	R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,

	R_98_A_VERT_INPUT_WINDOW_START, 0x05,
	R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,

	R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x0c,
	R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,

	R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
	R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,

	R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x0c,
	R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,
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	/* Task B */
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	R_C0_B_TASK_HANDLING_CNTL, 0x00,
	R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
	R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
	R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,

	/* 0x0002 is minimum */
	R_C4_B_HORIZ_INPUT_WINDOW_START, 0x02,
	R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,

	/* 0x02d0 = 720 */
	R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
	R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,

	/* vwindow start 0x12 = 18 */
	R_C8_B_VERT_INPUT_WINDOW_START, 0x12,
	R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,

	/* vwindow length 0xf8 = 248 */
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	R_CA_B_VERT_INPUT_WINDOW_LENGTH, VRES_60HZ>>1,
	R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, VRES_60HZ>>9,
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	/* hwindow 0x02d0 = 720 */
	R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
	R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,

	R_F0_LFCO_PER_LINE, 0xad,		/* Set PLL Register. 60hz 525 lines per frame, 27 MHz */
	R_F1_P_I_PARAM_SELECT, 0x05,		/* low bit with 0xF0 */
	R_F5_PULSGEN_LINE_LENGTH, 0xad,
	R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,

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	0x00, 0x00
};

static const unsigned char saa7115_cfg_50hz_video[] = {
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	R_80_GLOBAL_CNTL_1, 0x00,
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,	/* reset scaler */
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	R_15_VGATE_START_FID_CHG, 0x37,		/* VGATE start */
	R_16_VGATE_STOP, 0x16,
	R_17_MISC_VGATE_CONF_AND_MSB, 0x99,
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	R_08_SYNC_CNTL, 0x28,			/* 0x28 = PAL */
	R_0E_CHROMA_CNTL_1, 0x07,
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	R_5A_V_OFF_FOR_SLICER, 0x03,		/* standard 50hz value */
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	/* Task A */
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	R_90_A_TASK_HANDLING_CNTL, 0x81,
	R_91_A_X_PORT_FORMATS_AND_CONF, 0x48,
	R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL, 0x40,
	R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF, 0x84,

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	/* This is weird: the datasheet says that you should use 2 as the minimum value, */
	/* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
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	/* hoffset low (input), 0x0002 is minimum */
	R_94_A_HORIZ_INPUT_WINDOW_START, 0x00,
	R_95_A_HORIZ_INPUT_WINDOW_START_MSB, 0x00,

	/* hsize low (input), 0x02d0 = 720 */
	R_96_A_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
	R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,

	R_98_A_VERT_INPUT_WINDOW_START, 0x03,
	R_99_A_VERT_INPUT_WINDOW_START_MSB, 0x00,

	/* vsize 0x12 = 18 */
	R_9A_A_VERT_INPUT_WINDOW_LENGTH, 0x12,
	R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB, 0x00,

	/* hsize 0x05a0 = 1440 */
	R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH, 0xa0,
	R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x05,	/* hsize hi (output) */
	R_9E_A_VERT_OUTPUT_WINDOW_LENGTH, 0x12,		/* vsize low (output), 0x12 = 18 */
	R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB, 0x00,	/* vsize hi (output) */
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	/* Task B */
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	R_C0_B_TASK_HANDLING_CNTL, 0x00,
	R_C1_B_X_PORT_FORMATS_AND_CONF, 0x08,
	R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION, 0x00,
	R_C3_B_I_PORT_FORMATS_AND_CONF, 0x80,

	/* This is weird: the datasheet says that you should use 2 as the minimum value, */
	/* but Hauppauge uses 0, and changing that to 2 causes indeed problems (for 50hz) */
	/* hoffset low (input), 0x0002 is minimum. See comment above. */
	R_C4_B_HORIZ_INPUT_WINDOW_START, 0x00,
	R_C5_B_HORIZ_INPUT_WINDOW_START_MSB, 0x00,

	/* hsize 0x02d0 = 720 */
	R_C6_B_HORIZ_INPUT_WINDOW_LENGTH, 0xd0,
	R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB, 0x02,

	/* voffset 0x16 = 22 */
	R_C8_B_VERT_INPUT_WINDOW_START, 0x16,
	R_C9_B_VERT_INPUT_WINDOW_START_MSB, 0x00,

	/* vsize 0x0120 = 288 */
	R_CA_B_VERT_INPUT_WINDOW_LENGTH, 0x20,
	R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB, 0x01,

	/* hsize 0x02d0 = 720 */
	R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH, 0xd0,
	R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB, 0x02,

	R_F0_LFCO_PER_LINE, 0xb0,		/* Set PLL Register. 50hz 625 lines per frame, 27 MHz */
	R_F1_P_I_PARAM_SELECT, 0x05,		/* low bit with 0xF0, (was 0x05) */
	R_F5_PULSGEN_LINE_LENGTH, 0xb0,
	R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG, 0x01,

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	0x00, 0x00
};

/* ============== SAA7715 VIDEO templates (end) =======  */

static const unsigned char saa7115_cfg_vbi_on[] = {
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	R_80_GLOBAL_CNTL_1, 0x00,			/* reset tasks */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
	R_80_GLOBAL_CNTL_1, 0x30,			/* Activate both tasks */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,		/* activate scaler */
	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,	/* Enable I-port output */

457 458 459 460
	0x00, 0x00
};

static const unsigned char saa7115_cfg_vbi_off[] = {
461 462 463 464 465 466
	R_80_GLOBAL_CNTL_1, 0x00,			/* reset tasks */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,		/* reset scaler */
	R_80_GLOBAL_CNTL_1, 0x20,			/* Activate only task "B" */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,		/* activate scaler */
	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,	/* Enable I-port output */

467 468 469
	0x00, 0x00
};

470

471
static const unsigned char saa7115_init_misc[] = {
472 473 474 475 476 477
	R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F, 0x01,
	R_83_X_PORT_I_O_ENA_AND_OUT_CLK, 0x01,
	R_84_I_PORT_SIGNAL_DEF, 0x20,
	R_85_I_PORT_SIGNAL_POLAR, 0x21,
	R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT, 0xc5,
	R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 0x01,
478 479

	/* Task A */
480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518
	R_A0_A_HORIZ_PRESCALING, 0x01,
	R_A1_A_ACCUMULATION_LENGTH, 0x00,
	R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,

	/* Configure controls at nominal value*/
	R_A4_A_LUMA_BRIGHTNESS_CNTL, 0x80,
	R_A5_A_LUMA_CONTRAST_CNTL, 0x40,
	R_A6_A_CHROMA_SATURATION_CNTL, 0x40,

	/* note: 2 x zoom ensures that VBI lines have same length as video lines. */
	R_A8_A_HORIZ_LUMA_SCALING_INC, 0x00,
	R_A9_A_HORIZ_LUMA_SCALING_INC_MSB, 0x02,

	R_AA_A_HORIZ_LUMA_PHASE_OFF, 0x00,

	/* must be horiz lum scaling / 2 */
	R_AC_A_HORIZ_CHROMA_SCALING_INC, 0x00,
	R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB, 0x01,

	/* must be offset luma / 2 */
	R_AE_A_HORIZ_CHROMA_PHASE_OFF, 0x00,

	R_B0_A_VERT_LUMA_SCALING_INC, 0x00,
	R_B1_A_VERT_LUMA_SCALING_INC_MSB, 0x04,

	R_B2_A_VERT_CHROMA_SCALING_INC, 0x00,
	R_B3_A_VERT_CHROMA_SCALING_INC_MSB, 0x04,

	R_B4_A_VERT_SCALING_MODE_CNTL, 0x01,

	R_B8_A_VERT_CHROMA_PHASE_OFF_00, 0x00,
	R_B9_A_VERT_CHROMA_PHASE_OFF_01, 0x00,
	R_BA_A_VERT_CHROMA_PHASE_OFF_10, 0x00,
	R_BB_A_VERT_CHROMA_PHASE_OFF_11, 0x00,

	R_BC_A_VERT_LUMA_PHASE_OFF_00, 0x00,
	R_BD_A_VERT_LUMA_PHASE_OFF_01, 0x00,
	R_BE_A_VERT_LUMA_PHASE_OFF_10, 0x00,
	R_BF_A_VERT_LUMA_PHASE_OFF_11, 0x00,
519 520

	/* Task B */
521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571
	R_D0_B_HORIZ_PRESCALING, 0x01,
	R_D1_B_ACCUMULATION_LENGTH, 0x00,
	R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER, 0x00,

	/* Configure controls at nominal value*/
	R_D4_B_LUMA_BRIGHTNESS_CNTL, 0x80,
	R_D5_B_LUMA_CONTRAST_CNTL, 0x40,
	R_D6_B_CHROMA_SATURATION_CNTL, 0x40,

	/* hor lum scaling 0x0400 = 1 */
	R_D8_B_HORIZ_LUMA_SCALING_INC, 0x00,
	R_D9_B_HORIZ_LUMA_SCALING_INC_MSB, 0x04,

	R_DA_B_HORIZ_LUMA_PHASE_OFF, 0x00,

	/* must be hor lum scaling / 2 */
	R_DC_B_HORIZ_CHROMA_SCALING, 0x00,
	R_DD_B_HORIZ_CHROMA_SCALING_MSB, 0x02,

	/* must be offset luma / 2 */
	R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA, 0x00,

	R_E0_B_VERT_LUMA_SCALING_INC, 0x00,
	R_E1_B_VERT_LUMA_SCALING_INC_MSB, 0x04,

	R_E2_B_VERT_CHROMA_SCALING_INC, 0x00,
	R_E3_B_VERT_CHROMA_SCALING_INC_MSB, 0x04,

	R_E4_B_VERT_SCALING_MODE_CNTL, 0x01,

	R_E8_B_VERT_CHROMA_PHASE_OFF_00, 0x00,
	R_E9_B_VERT_CHROMA_PHASE_OFF_01, 0x00,
	R_EA_B_VERT_CHROMA_PHASE_OFF_10, 0x00,
	R_EB_B_VERT_CHROMA_PHASE_OFF_11, 0x00,

	R_EC_B_VERT_LUMA_PHASE_OFF_00, 0x00,
	R_ED_B_VERT_LUMA_PHASE_OFF_01, 0x00,
	R_EE_B_VERT_LUMA_PHASE_OFF_10, 0x00,
	R_EF_B_VERT_LUMA_PHASE_OFF_11, 0x00,

	R_F2_NOMINAL_PLL2_DTO, 0x50,		/* crystal clock = 24.576 MHz, target = 27MHz */
	R_F3_PLL_INCREMENT, 0x46,
	R_F4_PLL2_STATUS, 0x00,
	R_F7_PULSE_A_POS_MSB, 0x4b,		/* not the recommended settings! */
	R_F8_PULSE_B_POS, 0x00,
	R_F9_PULSE_B_POS_MSB, 0x4b,
	R_FA_PULSE_C_POS, 0x00,
	R_FB_PULSE_C_POS_MSB, 0x4b,

	/* PLL2 lock detection settings: 71 lines 50% phase error */
	R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES, 0x88,
572 573

	/* Turn off VBI */
574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603
	R_40_SLICER_CNTL_1, 0x20,             /* No framing code errors allowed. */
	R_41_LCR_BASE, 0xff,
	R_41_LCR_BASE+1, 0xff,
	R_41_LCR_BASE+2, 0xff,
	R_41_LCR_BASE+3, 0xff,
	R_41_LCR_BASE+4, 0xff,
	R_41_LCR_BASE+5, 0xff,
	R_41_LCR_BASE+6, 0xff,
	R_41_LCR_BASE+7, 0xff,
	R_41_LCR_BASE+8, 0xff,
	R_41_LCR_BASE+9, 0xff,
	R_41_LCR_BASE+10, 0xff,
	R_41_LCR_BASE+11, 0xff,
	R_41_LCR_BASE+12, 0xff,
	R_41_LCR_BASE+13, 0xff,
	R_41_LCR_BASE+14, 0xff,
	R_41_LCR_BASE+15, 0xff,
	R_41_LCR_BASE+16, 0xff,
	R_41_LCR_BASE+17, 0xff,
	R_41_LCR_BASE+18, 0xff,
	R_41_LCR_BASE+19, 0xff,
	R_41_LCR_BASE+20, 0xff,
	R_41_LCR_BASE+21, 0xff,
	R_41_LCR_BASE+22, 0xff,
	R_58_PROGRAM_FRAMING_CODE, 0x40,
	R_59_H_OFF_FOR_SLICER, 0x47,
	R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF, 0x83,
	R_5D_DID, 0xbd,
	R_5E_SDID, 0x35,

604
	R_02_INPUT_CNTL_1, 0xc4, /* input tuner -> input 4, amplifier active */
605 606 607 608

	R_80_GLOBAL_CNTL_1, 0x20,		/* enable task B */
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xd0,
	R_88_POWER_SAVE_ADC_PORT_CNTL, 0xf0,
609 610 611
	0x00, 0x00
};

612
static int saa711x_odd_parity(u8 c)
613 614 615 616 617 618 619 620
{
	c ^= (c >> 4);
	c ^= (c >> 2);
	c ^= (c >> 1);

	return c & 1;
}

621
static int saa711x_decode_vps(u8 *dst, u8 *p)
622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667
{
	static const u8 biphase_tbl[] = {
		0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
		0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
		0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
		0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
		0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
		0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
		0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
		0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
		0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
		0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
		0xc3, 0x4b, 0x43, 0xc3, 0x87, 0x0f, 0x07, 0x87,
		0x83, 0x0b, 0x03, 0x83, 0xc3, 0x4b, 0x43, 0xc3,
		0xc1, 0x49, 0x41, 0xc1, 0x85, 0x0d, 0x05, 0x85,
		0x81, 0x09, 0x01, 0x81, 0xc1, 0x49, 0x41, 0xc1,
		0xe1, 0x69, 0x61, 0xe1, 0xa5, 0x2d, 0x25, 0xa5,
		0xa1, 0x29, 0x21, 0xa1, 0xe1, 0x69, 0x61, 0xe1,
		0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
		0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
		0xc2, 0x4a, 0x42, 0xc2, 0x86, 0x0e, 0x06, 0x86,
		0x82, 0x0a, 0x02, 0x82, 0xc2, 0x4a, 0x42, 0xc2,
		0xc0, 0x48, 0x40, 0xc0, 0x84, 0x0c, 0x04, 0x84,
		0x80, 0x08, 0x00, 0x80, 0xc0, 0x48, 0x40, 0xc0,
		0xe0, 0x68, 0x60, 0xe0, 0xa4, 0x2c, 0x24, 0xa4,
		0xa0, 0x28, 0x20, 0xa0, 0xe0, 0x68, 0x60, 0xe0,
		0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
		0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
		0xd2, 0x5a, 0x52, 0xd2, 0x96, 0x1e, 0x16, 0x96,
		0x92, 0x1a, 0x12, 0x92, 0xd2, 0x5a, 0x52, 0xd2,
		0xd0, 0x58, 0x50, 0xd0, 0x94, 0x1c, 0x14, 0x94,
		0x90, 0x18, 0x10, 0x90, 0xd0, 0x58, 0x50, 0xd0,
		0xf0, 0x78, 0x70, 0xf0, 0xb4, 0x3c, 0x34, 0xb4,
		0xb0, 0x38, 0x30, 0xb0, 0xf0, 0x78, 0x70, 0xf0,
	};
	int i;
	u8 c, err = 0;

	for (i = 0; i < 2 * 13; i += 2) {
		err |= biphase_tbl[p[i]] | biphase_tbl[p[i + 1]];
		c = (biphase_tbl[p[i + 1]] & 0xf) | ((biphase_tbl[p[i]] & 0xf) << 4);
		dst[i / 2] = c;
	}
	return err & 0xf0;
}

668
static int saa711x_decode_wss(u8 *p)
669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694
{
	static const int wss_bits[8] = {
		0, 0, 0, 1, 0, 1, 1, 1
	};
	unsigned char parity;
	int wss = 0;
	int i;

	for (i = 0; i < 16; i++) {
		int b1 = wss_bits[p[i] & 7];
		int b2 = wss_bits[(p[i] >> 3) & 7];

		if (b1 == b2)
			return -1;
		wss |= b2 << i;
	}
	parity = wss & 15;
	parity ^= parity >> 2;
	parity ^= parity >> 1;

	if (!(parity & 1))
		return -1;

	return wss;
}

695
static int saa711x_s_clock_freq(struct v4l2_subdev *sd, u32 freq)
696
{
697
	struct saa711x_state *state = to_state(sd);
698 699 700 701
	u32 acpf;
	u32 acni;
	u32 hz;
	u64 f;
702
	u8 acc = 0; 	/* reg 0x3a, audio clock control */
703

704
	/* Checks for chips that don't have audio clock (saa7111, saa7113) */
705
	if (!saa711x_has_reg(state->ident, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD))
706 707
		return 0;

708
	v4l2_dbg(1, debug, sd, "set audio clock freq: %d\n", freq);
709 710 711 712 713 714 715 716 717 718 719

	/* sanity check */
	if (freq < 32000 || freq > 48000)
		return -EINVAL;

	/* hz is the refresh rate times 100 */
	hz = (state->std & V4L2_STD_525_60) ? 5994 : 5000;
	/* acpf = (256 * freq) / field_frequency == (256 * 100 * freq) / hz */
	acpf = (25600 * freq) / hz;
	/* acni = (256 * freq * 2^23) / crystal_frequency =
		  (freq * 2^(8+23)) / crystal_frequency =
720
		  (freq << 31) / crystal_frequency */
721 722
	f = freq;
	f = f << 31;
723
	do_div(f, state->crystal_freq);
724
	acni = f;
725 726 727 728 729 730 731 732 733
	if (state->ucgc) {
		acpf = acpf * state->cgcdiv / 16;
		acni = acni * state->cgcdiv / 16;
		acc = 0x80;
		if (state->cgcdiv == 3)
			acc |= 0x40;
	}
	if (state->apll)
		acc |= 0x08;
734

735 736 737
	saa711x_write(sd, R_38_CLK_RATIO_AMXCLK_TO_ASCLK, 0x03);
	saa711x_write(sd, R_39_CLK_RATIO_ASCLK_TO_ALRCLK, 0x10);
	saa711x_write(sd, R_3A_AUD_CLK_GEN_BASIC_SETUP, acc);
738

739 740
	saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD, acpf & 0xff);
	saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+1,
741
							(acpf >> 8) & 0xff);
742
	saa711x_write(sd, R_30_AUD_MAST_CLK_CYCLES_PER_FIELD+2,
743 744
							(acpf >> 16) & 0x03);

745 746 747
	saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC, acni & 0xff);
	saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+1, (acni >> 8) & 0xff);
	saa711x_write(sd, R_34_AUD_MAST_CLK_NOMINAL_INC+2, (acni >> 16) & 0x3f);
748 749 750 751
	state->audclk_freq = freq;
	return 0;
}

752
static int saa711x_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
753
{
754
	struct v4l2_subdev *sd = to_sd(ctrl);
755
	struct saa711x_state *state = to_state(sd);
756 757

	switch (ctrl->id) {
758
	case V4L2_CID_CHROMA_AGC:
759
		/* chroma gain cluster */
760 761
		if (state->agc->val)
			state->gain->val =
762
				saa711x_read(sd, R_0F_CHROMA_GAIN_CNTL) & 0x7f;
763
		break;
764 765 766 767
	}
	return 0;
}

768
static int saa711x_s_ctrl(struct v4l2_ctrl *ctrl)
769
{
770
	struct v4l2_subdev *sd = to_sd(ctrl);
771
	struct saa711x_state *state = to_state(sd);
772 773 774

	switch (ctrl->id) {
	case V4L2_CID_BRIGHTNESS:
775
		saa711x_write(sd, R_0A_LUMA_BRIGHT_CNTL, ctrl->val);
776
		break;
777

778
	case V4L2_CID_CONTRAST:
779
		saa711x_write(sd, R_0B_LUMA_CONTRAST_CNTL, ctrl->val);
780
		break;
781

782
	case V4L2_CID_SATURATION:
783
		saa711x_write(sd, R_0C_CHROMA_SAT_CNTL, ctrl->val);
784
		break;
785

786
	case V4L2_CID_HUE:
787
		saa711x_write(sd, R_0D_CHROMA_HUE_CNTL, ctrl->val);
788
		break;
789

790
	case V4L2_CID_CHROMA_AGC:
791 792 793 794 795
		/* chroma gain cluster */
		if (state->agc->val)
			saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val);
		else
			saa711x_write(sd, R_0F_CHROMA_GAIN_CNTL, state->gain->val | 0x80);
796
		break;
797

798 799 800 801 802 803 804
	default:
		return -EINVAL;
	}

	return 0;
}

805
static int saa711x_set_size(struct v4l2_subdev *sd, int width, int height)
806
{
807
	struct saa711x_state *state = to_state(sd);
808 809 810 811 812 813
	int HPSC, HFSC;
	int VSCY;
	int res;
	int is_50hz = state->std & V4L2_STD_625_50;
	int Vsrc = is_50hz ? 576 : 480;

814
	v4l2_dbg(1, debug, sd, "decoder set size to %ix%i\n", width, height);
815 816 817 818 819 820 821

	/* FIXME need better bounds checking here */
	if ((width < 1) || (width > 1440))
		return -EINVAL;
	if ((height < 1) || (height > Vsrc))
		return -EINVAL;

822
	if (!saa711x_has_reg(state->ident, R_D0_B_HORIZ_PRESCALING)) {
823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839
		/* Decoder only supports 720 columns and 480 or 576 lines */
		if (width != 720)
			return -EINVAL;
		if (height != Vsrc)
			return -EINVAL;
	}

	state->width = width;
	state->height = height;

	if (!saa711x_has_reg(state->ident, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH))
		return 0;

	/* probably have a valid size, let's set it */
	/* Set output width/height */
	/* width */

840
	saa711x_write(sd, R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,
841
					(u8) (width & 0xff));
842
	saa711x_write(sd, R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB,
843 844 845
					(u8) ((width >> 8) & 0xff));

	/* Vertical Scaling uses height/2 */
846
	res = height / 2;
847 848 849

	/* On 60Hz, it is using a higher Vertical Output Size */
	if (!is_50hz)
850
		res += (VRES_60HZ - 480) >> 1;
851 852

		/* height */
853
	saa711x_write(sd, R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,
854
					(u8) (res & 0xff));
855
	saa711x_write(sd, R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB,
856 857 858 859 860 861 862 863 864 865
					(u8) ((res >> 8) & 0xff));

	/* Scaling settings */
	/* Hprescaler is floor(inres/outres) */
	HPSC = (int)(720 / width);
	/* 0 is not allowed (div. by zero) */
	HPSC = HPSC ? HPSC : 1;
	HFSC = (int)((1024 * 720) / (HPSC * width));
	/* FIXME hardcodes to "Task B"
	 * write H prescaler integer */
866
	saa711x_write(sd, R_D0_B_HORIZ_PRESCALING,
867 868
				(u8) (HPSC & 0x3f));

869
	v4l2_dbg(1, debug, sd, "Hpsc: 0x%05x, Hfsc: 0x%05x\n", HPSC, HFSC);
870
	/* write H fine-scaling (luminance) */
871
	saa711x_write(sd, R_D8_B_HORIZ_LUMA_SCALING_INC,
872
				(u8) (HFSC & 0xff));
873
	saa711x_write(sd, R_D9_B_HORIZ_LUMA_SCALING_INC_MSB,
874 875 876
				(u8) ((HFSC >> 8) & 0xff));
	/* write H fine-scaling (chrominance)
	 * must be lum/2, so i'll just bitshift :) */
877
	saa711x_write(sd, R_DC_B_HORIZ_CHROMA_SCALING,
878
				(u8) ((HFSC >> 1) & 0xff));
879
	saa711x_write(sd, R_DD_B_HORIZ_CHROMA_SCALING_MSB,
880 881 882
				(u8) ((HFSC >> 9) & 0xff));

	VSCY = (int)((1024 * Vsrc) / height);
883
	v4l2_dbg(1, debug, sd, "Vsrc: %d, Vscy: 0x%05x\n", Vsrc, VSCY);
884 885

	/* Correct Contrast and Luminance */
886
	saa711x_write(sd, R_D5_B_LUMA_CONTRAST_CNTL,
887
					(u8) (64 * 1024 / VSCY));
888
	saa711x_write(sd, R_D6_B_CHROMA_SATURATION_CNTL,
889 890 891
					(u8) (64 * 1024 / VSCY));

		/* write V fine-scaling (luminance) */
892
	saa711x_write(sd, R_E0_B_VERT_LUMA_SCALING_INC,
893
					(u8) (VSCY & 0xff));
894
	saa711x_write(sd, R_E1_B_VERT_LUMA_SCALING_INC_MSB,
895 896
					(u8) ((VSCY >> 8) & 0xff));
		/* write V fine-scaling (chrominance) */
897
	saa711x_write(sd, R_E2_B_VERT_CHROMA_SCALING_INC,
898
					(u8) (VSCY & 0xff));
899
	saa711x_write(sd, R_E3_B_VERT_CHROMA_SCALING_INC_MSB,
900 901
					(u8) ((VSCY >> 8) & 0xff));

902
	saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
903 904

	/* Activates task "B" */
905 906
	saa711x_write(sd, R_80_GLOBAL_CNTL_1,
				saa711x_read(sd, R_80_GLOBAL_CNTL_1) | 0x20);
907 908 909 910

	return 0;
}

911
static void saa711x_set_v4lstd(struct v4l2_subdev *sd, v4l2_std_id std)
912
{
913
	struct saa711x_state *state = to_state(sd);
914

915 916 917
	/* Prevent unnecessary standard changes. During a standard
	   change the I-Port is temporarily disabled. Any devices
	   reading from that port can get confused.
918 919
	   Note that s_std is also used to switch from
	   radio to TV mode, so if a s_std is broadcast to
920 921 922 923 924
	   all I2C devices then you do not want to have an unwanted
	   side-effect here. */
	if (std == state->std)
		return;

925 926
	state->std = std;

927 928
	// This works for NTSC-M, SECAM-L and the 50Hz PAL variants.
	if (std & V4L2_STD_525_60) {
929 930 931
		v4l2_dbg(1, debug, sd, "decoder set standard 60 Hz\n");
		saa711x_writeregs(sd, saa7115_cfg_60hz_video);
		saa711x_set_size(sd, 720, 480);
932
	} else {
933 934 935
		v4l2_dbg(1, debug, sd, "decoder set standard 50 Hz\n");
		saa711x_writeregs(sd, saa7115_cfg_50hz_video);
		saa711x_set_size(sd, 720, 576);
936 937
	}

938
	/* Register 0E - Bits D6-D4 on NO-AUTO mode
939
		(SAA7111 and SAA7113 doesn't have auto mode)
940 941 942 943 944 945 946
	    50 Hz / 625 lines           60 Hz / 525 lines
	000 PAL BGDHI (4.43Mhz)         NTSC M (3.58MHz)
	001 NTSC 4.43 (50 Hz)           PAL 4.43 (60 Hz)
	010 Combination-PAL N (3.58MHz) NTSC 4.43 (60 Hz)
	011 NTSC N (3.58MHz)            PAL M (3.58MHz)
	100 reserved                    NTSC-Japan (3.58MHz)
	*/
947
	if (state->ident <= V4L2_IDENT_SAA7113) {
948
		u8 reg = saa711x_read(sd, R_0E_CHROMA_CNTL_1) & 0x8f;
949

950
		if (std == V4L2_STD_PAL_M) {
951
			reg |= 0x30;
952
		} else if (std == V4L2_STD_PAL_Nc) {
953
			reg |= 0x20;
954
		} else if (std == V4L2_STD_PAL_60) {
955
			reg |= 0x10;
956
		} else if (std == V4L2_STD_NTSC_M_JP) {
957
			reg |= 0x40;
958
		} else if (std & V4L2_STD_SECAM) {
959
			reg |= 0x50;
960
		}
961
		saa711x_write(sd, R_0E_CHROMA_CNTL_1, reg);
962 963
	} else {
		/* restart task B if needed */
964
		int taskb = saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10;
965

966
		if (taskb && state->ident == V4L2_IDENT_SAA7114) {
967
			saa711x_writeregs(sd, saa7115_cfg_vbi_on);
968
		}
969

970
		/* switch audio mode too! */
971
		saa711x_s_clock_freq(sd, state->audclk_freq);
972
	}
973 974 975
}

/* setup the sliced VBI lcr registers according to the sliced VBI format */
976
static void saa711x_set_lcr(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
977
{
978
	struct saa711x_state *state = to_state(sd);
979 980 981 982
	int is_50hz = (state->std & V4L2_STD_625_50);
	u8 lcr[24];
	int i, x;

983 984
#if 1
	/* saa7113/7114/7118 VBI support are experimental */
985
	if (!saa711x_has_reg(state->ident, R_41_LCR_BASE))
986 987 988 989
		return;

#else
	/* SAA7113 and SAA7118 also should support VBI - Need testing */
990
	if (state->ident != V4L2_IDENT_SAA7115)
991
		return;
992
#endif
993 994 995 996

	for (i = 0; i <= 23; i++)
		lcr[i] = 0xff;

997
	if (fmt == NULL) {
998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029
		/* raw VBI */
		if (is_50hz)
			for (i = 6; i <= 23; i++)
				lcr[i] = 0xdd;
		else
			for (i = 10; i <= 21; i++)
				lcr[i] = 0xdd;
	} else {
		/* sliced VBI */
		/* first clear lines that cannot be captured */
		if (is_50hz) {
			for (i = 0; i <= 5; i++)
				fmt->service_lines[0][i] =
					fmt->service_lines[1][i] = 0;
		}
		else {
			for (i = 0; i <= 9; i++)
				fmt->service_lines[0][i] =
					fmt->service_lines[1][i] = 0;
			for (i = 22; i <= 23; i++)
				fmt->service_lines[0][i] =
					fmt->service_lines[1][i] = 0;
		}

		/* Now set the lcr values according to the specified service */
		for (i = 6; i <= 23; i++) {
			lcr[i] = 0;
			for (x = 0; x <= 1; x++) {
				switch (fmt->service_lines[1-x][i]) {
					case 0:
						lcr[i] |= 0xf << (4 * x);
						break;
1030
					case V4L2_SLICED_TELETEXT_B:
1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048
						lcr[i] |= 1 << (4 * x);
						break;
					case V4L2_SLICED_CAPTION_525:
						lcr[i] |= 4 << (4 * x);
						break;
					case V4L2_SLICED_WSS_625:
						lcr[i] |= 5 << (4 * x);
						break;
					case V4L2_SLICED_VPS:
						lcr[i] |= 7 << (4 * x);
						break;
				}
			}
		}
	}

	/* write the lcr registers */
	for (i = 2; i <= 23; i++) {
1049
		saa711x_write(sd, i - 2 + R_41_LCR_BASE, lcr[i]);
1050 1051 1052
	}

	/* enable/disable raw VBI capturing */
1053
	saa711x_writeregs(sd, fmt == NULL ?
1054 1055
				saa7115_cfg_vbi_on :
				saa7115_cfg_vbi_off);
1056 1057
}

1058
static int saa711x_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *sliced)
1059 1060
{
	static u16 lcr2vbi[] = {
1061
		0, V4L2_SLICED_TELETEXT_B, 0,	/* 1 */
1062 1063 1064 1065 1066 1067 1068
		0, V4L2_SLICED_CAPTION_525,	/* 4 */
		V4L2_SLICED_WSS_625, 0,		/* 5 */
		V4L2_SLICED_VPS, 0, 0, 0, 0,	/* 7 */
		0, 0, 0, 0
	};
	int i;

1069 1070
	memset(sliced->service_lines, 0, sizeof(sliced->service_lines));
	sliced->service_set = 0;
1071
	/* done if using raw VBI */
1072
	if (saa711x_read(sd, R_80_GLOBAL_CNTL_1) & 0x10)
1073 1074
		return 0;
	for (i = 2; i <= 23; i++) {
1075
		u8 v = saa711x_read(sd, i - 2 + R_41_LCR_BASE);
1076 1077 1078 1079 1080 1081 1082 1083 1084

		sliced->service_lines[0][i] = lcr2vbi[v >> 4];
		sliced->service_lines[1][i] = lcr2vbi[v & 0xf];
		sliced->service_set |=
			sliced->service_lines[0][i] | sliced->service_lines[1][i];
	}
	return 0;
}

1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096
static int saa711x_s_raw_fmt(struct v4l2_subdev *sd, struct v4l2_vbi_format *fmt)
{
	saa711x_set_lcr(sd, NULL);
	return 0;
}

static int saa711x_s_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
{
	saa711x_set_lcr(sd, fmt);
	return 0;
}

1097 1098 1099 1100 1101 1102 1103 1104 1105
static int saa711x_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
{
	if (fmt->code != V4L2_MBUS_FMT_FIXED)
		return -EINVAL;
	fmt->field = V4L2_FIELD_INTERLACED;
	fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
	return saa711x_set_size(sd, fmt->width, fmt->height);
}

1106 1107 1108 1109
/* Decode the sliced VBI data stream as created by the saa7115.
   The format is described in the saa7115 datasheet in Tables 25 and 26
   and in Figure 33.
   The current implementation uses SAV/EAV codes and not the ancillary data
1110
   headers. The vbi->p pointer points to the R_5E_SDID byte right after the SAV
1111
   code. */
1112
static int saa711x_decode_vbi_line(struct v4l2_subdev *sd, struct v4l2_decode_vbi_line *vbi)
1113
{
1114
	struct saa711x_state *state = to_state(sd);
1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143
	static const char vbi_no_data_pattern[] = {
		0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0
	};
	u8 *p = vbi->p;
	u32 wss;
	int id1, id2;   /* the ID1 and ID2 bytes from the internal header */

	vbi->type = 0;  /* mark result as a failure */
	id1 = p[2];
	id2 = p[3];
	/* Note: the field bit is inverted for 60 Hz video */
	if (state->std & V4L2_STD_525_60)
		id1 ^= 0x40;

	/* Skip internal header, p now points to the start of the payload */
	p += 4;
	vbi->p = p;

	/* calculate field and line number of the VBI packet (1-23) */
	vbi->is_second_field = ((id1 & 0x40) != 0);
	vbi->line = (id1 & 0x3f) << 3;
	vbi->line |= (id2 & 0x70) >> 4;

	/* Obtain data type */
	id2 &= 0xf;

	/* If the VBI slicer does not detect any signal it will fill up
	   the payload buffer with 0xa0 bytes. */
	if (!memcmp(p, vbi_no_data_pattern, sizeof(vbi_no_data_pattern)))
1144
		return 0;
1145 1146 1147 1148

	/* decode payloads */
	switch (id2) {
	case 1:
1149
		vbi->type = V4L2_SLICED_TELETEXT_B;
1150 1151
		break;
	case 4:
1152
		if (!saa711x_odd_parity(p[0]) || !saa711x_odd_parity(p[1]))
1153
			return 0;
1154 1155 1156
		vbi->type = V4L2_SLICED_CAPTION_525;
		break;
	case 5:
1157
		wss = saa711x_decode_wss(p);
1158
		if (wss == -1)
1159
			return 0;
1160 1161 1162 1163 1164
		p[0] = wss & 0xff;
		p[1] = wss >> 8;
		vbi->type = V4L2_SLICED_WSS_625;
		break;
	case 7:
1165
		if (saa711x_decode_vps(p, p) != 0)
1166
			return 0;
1167 1168 1169
		vbi->type = V4L2_SLICED_VPS;
		break;
	default:
1170
		break;
1171
	}
1172
	return 0;
1173 1174 1175 1176
}

/* ============ SAA7115 AUDIO settings (end) ============= */

1177
static int saa711x_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
1178
{
1179 1180
	struct saa711x_state *state = to_state(sd);
	int status;
1181

1182 1183 1184
	if (state->radio)
		return 0;
	status = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1185

1186 1187 1188 1189
	v4l2_dbg(1, debug, sd, "status: 0x%02x\n", status);
	vt->signal = ((status & (1 << 6)) == 0) ? 0xffff : 0x0;
	return 0;
}
1190

1191 1192 1193
static int saa711x_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
{
	struct saa711x_state *state = to_state(sd);
1194

1195 1196 1197 1198
	state->radio = 0;
	saa711x_set_v4lstd(sd, std);
	return 0;
}
1199

1200 1201 1202
static int saa711x_s_radio(struct v4l2_subdev *sd)
{
	struct saa711x_state *state = to_state(sd);
1203

1204 1205 1206
	state->radio = 1;
	return 0;
}
1207

1208 1209
static int saa711x_s_routing(struct v4l2_subdev *sd,
			     u32 input, u32 output, u32 config)
1210 1211
{
	struct saa711x_state *state = to_state(sd);
1212
	u8 mask = (state->ident <= V4L2_IDENT_SAA7111A) ? 0xf8 : 0xf0;
1213

1214 1215 1216
	v4l2_dbg(1, debug, sd, "decoder set input %d output %d\n",
		input, output);

1217
	/* saa7111/3 does not have these inputs */
1218
	if (state->ident <= V4L2_IDENT_SAA7113 &&
1219 1220
	    (input == SAA7115_COMPOSITE4 ||
	     input == SAA7115_COMPOSITE5)) {
1221 1222
		return -EINVAL;
	}
1223
	if (input > SAA7115_SVIDEO3)
1224
		return -EINVAL;
1225
	if (state->input == input && state->output == output)
1226 1227
		return 0;
	v4l2_dbg(1, debug, sd, "now setting %s input %s output\n",
1228 1229 1230
		(input >= SAA7115_SVIDEO0) ? "S-Video" : "Composite",
		(output == SAA7115_IPORT_ON) ? "iport on" : "iport off");
	state->input = input;
1231 1232

	/* saa7111 has slightly different input numbering */
1233
	if (state->ident <= V4L2_IDENT_SAA7111A) {
1234 1235 1236 1237 1238
		if (input >= SAA7115_COMPOSITE4)
			input -= 2;
		/* saa7111 specific */
		saa711x_write(sd, R_10_CHROMA_CNTL_2,
				(saa711x_read(sd, R_10_CHROMA_CNTL_2) & 0x3f) |
1239
				((output & 0xc0) ^ 0x40));
1240 1241
		saa711x_write(sd, R_13_RT_X_PORT_OUT_CNTL,
				(saa711x_read(sd, R_13_RT_X_PORT_OUT_CNTL) & 0xf0) |
1242
				((output & 2) ? 0x0a : 0));
1243
	}
1244

1245 1246 1247 1248
	/* select mode */
	saa711x_write(sd, R_02_INPUT_CNTL_1,
		      (saa711x_read(sd, R_02_INPUT_CNTL_1) & mask) |
		       input);
1249

1250 1251 1252 1253
	/* bypass chrominance trap for S-Video modes */
	saa711x_write(sd, R_09_LUMA_CNTL,
			(saa711x_read(sd, R_09_LUMA_CNTL) & 0x7f) |
			(state->input >= SAA7115_SVIDEO0 ? 0x80 : 0x0));
1254

1255
	state->output = output;
1256 1257 1258 1259 1260
	if (state->ident == V4L2_IDENT_SAA7114 ||
			state->ident == V4L2_IDENT_SAA7115) {
		saa711x_write(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK,
				(saa711x_read(sd, R_83_X_PORT_I_O_ENA_AND_OUT_CLK) & 0xfe) |
				(state->output & 0x01));
1261
	}
1262 1263 1264 1265 1266 1267
	if (state->ident > V4L2_IDENT_SAA7111A) {
		if (config & SAA7115_IDQ_IS_DEFAULT)
			saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x20);
		else
			saa711x_write(sd, R_85_I_PORT_SIGNAL_POLAR, 0x21);
	}
1268 1269
	return 0;
}
1270

1271 1272 1273
static int saa711x_s_gpio(struct v4l2_subdev *sd, u32 val)
{
	struct saa711x_state *state = to_state(sd);
1274

1275
	if (state->ident > V4L2_IDENT_SAA7111A)
1276 1277 1278 1279 1280
		return -EINVAL;
	saa711x_write(sd, 0x11, (saa711x_read(sd, 0x11) & 0x7f) |
		(val ? 0x80 : 0));
	return 0;
}
1281

1282 1283 1284
static int saa711x_s_stream(struct v4l2_subdev *sd, int enable)
{
	struct saa711x_state *state = to_state(sd);
1285

1286 1287
	v4l2_dbg(1, debug, sd, "%s output\n",
			enable ? "enable" : "disable");
1288

1289 1290 1291 1292 1293 1294
	if (state->enable == enable)
		return 0;
	state->enable = enable;
	if (!saa711x_has_reg(state->ident, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED))
		return 0;
	saa711x_write(sd, R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, state->enable);
1295 1296
	return 0;
}
1297

1298
static int saa711x_s_crystal_freq(struct v4l2_subdev *sd, u32 freq, u32 flags)
1299 1300
{
	struct saa711x_state *state = to_state(sd);
1301

1302
	if (freq != SAA7115_FREQ_32_11_MHZ && freq != SAA7115_FREQ_24_576_MHZ)
1303
		return -EINVAL;
1304 1305 1306 1307
	state->crystal_freq = freq;
	state->cgcdiv = (flags & SAA7115_FREQ_FL_CGCDIV) ? 3 : 4;
	state->ucgc = (flags & SAA7115_FREQ_FL_UCGC) ? 1 : 0;
	state->apll = (flags & SAA7115_FREQ_FL_APLL) ? 1 : 0;
1308 1309 1310
	saa711x_s_clock_freq(sd, state->audclk_freq);
	return 0;
}
1311

1312 1313 1314 1315 1316 1317
static int saa711x_reset(struct v4l2_subdev *sd, u32 val)
{
	v4l2_dbg(1, debug, sd, "decoder RESET\n");
	saa711x_writeregs(sd, saa7115_cfg_reset_scaler);
	return 0;
}
1318

1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338
static int saa711x_g_vbi_data(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_data *data)
{
	/* Note: the internal field ID is inverted for NTSC,
	   so data->field 0 maps to the saa7115 even field,
	   whereas for PAL it maps to the saa7115 odd field. */
	switch (data->id) {
	case V4L2_SLICED_WSS_625:
		if (saa711x_read(sd, 0x6b) & 0xc0)
			return -EIO;
		data->data[0] = saa711x_read(sd, 0x6c);
		data->data[1] = saa711x_read(sd, 0x6d);
		return 0;
	case V4L2_SLICED_CAPTION_525:
		if (data->field == 0) {
			/* CC */
			if (saa711x_read(sd, 0x66) & 0x30)
				return -EIO;
			data->data[0] = saa711x_read(sd, 0x69);
			data->data[1] = saa711x_read(sd, 0x6a);
			return 0;
1339
		}
1340 1341 1342 1343 1344 1345 1346 1347
		/* XDS */
		if (saa711x_read(sd, 0x66) & 0xc0)
			return -EIO;
		data->data[0] = saa711x_read(sd, 0x67);
		data->data[1] = saa711x_read(sd, 0x68);
		return 0;
	default:
		return -EINVAL;
1348
	}
1349
}
1350

1351 1352 1353
static int saa711x_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
{
	struct saa711x_state *state = to_state(sd);
1354 1355
	int reg1f, reg1e;

1356 1357 1358 1359 1360 1361
	/*
	 * The V4L2 core already initializes std with all supported
	 * Standards. All driver needs to do is to mask it, to remove
	 * standards that don't apply from the mask
	 */

1362
	reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390

	if (state->ident == V4L2_IDENT_SAA7115) {
		reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);

		v4l2_dbg(1, debug, sd, "Status byte 1 (0x1e)=0x%02x\n", reg1e);

		switch (reg1e & 0x03) {
		case 1:
			*std &= V4L2_STD_NTSC;
			break;
		case 2:
			/*
			 * V4L2_STD_PAL just cover the european PAL standards.
			 * This is wrong, as the device could also be using an
			 * other PAL standard.
			 */
			*std &= V4L2_STD_PAL   | V4L2_STD_PAL_N  | V4L2_STD_PAL_Nc |
				V4L2_STD_PAL_M | V4L2_STD_PAL_60;
			break;
		case 3:
			*std &= V4L2_STD_SECAM;
			break;
		default:
			/* Can't detect anything */
			break;
		}
	}

1391
	v4l2_dbg(1, debug, sd, "Status byte 2 (0x1f)=0x%02x\n", reg1f);
1392 1393 1394

	/* horizontal/vertical not locked */
	if (reg1f & 0x40)
1395
		goto ret;
1396

1397
	if (reg1f & 0x20)
1398
		*std &= V4L2_STD_525_60;
1399
	else
1400
		*std &= V4L2_STD_625_50;
1401 1402 1403 1404

ret:
	v4l2_dbg(1, debug, sd, "detected std mask = %08Lx\n", *std);

1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422
	return 0;
}

static int saa711x_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
	struct saa711x_state *state = to_state(sd);
	int reg1e = 0x80;
	int reg1f;

	*status = V4L2_IN_ST_NO_SIGNAL;
	if (state->ident == V4L2_IDENT_SAA7115)
		reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
	reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
	if ((reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80)
		*status = 0;
	return 0;
}

1423
#ifdef CONFIG_VIDEO_ADV_DEBUG
1424
static int saa711x_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1425 1426
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
1427

1428
	if (!v4l2_chip_match_i2c_client(client, &reg->match))
1429 1430 1431 1432
		return -EINVAL;
	if (!capable(CAP_SYS_ADMIN))
		return -EPERM;
	reg->val = saa711x_read(sd, reg->reg & 0xff);
1433
	reg->size = 1;
1434 1435
	return 0;
}
1436

1437
static int saa711x_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1438 1439
{
	struct i2c_client *client = v4l2_get_subdevdata(sd);
1440

1441
	if (!v4l2_chip_match_i2c_client(client, &reg->match))
1442 1443 1444 1445 1446 1447 1448
		return -EINVAL;
	if (!capable(CAP_SYS_ADMIN))
		return -EPERM;
	saa711x_write(sd, reg->reg & 0xff, reg->val & 0xff);
	return 0;
}
#endif
1449

1450
static int saa711x_g_chip_ident(struct v4l2_subdev *sd, struct v4l2_dbg_chip_ident *chip)
1451 1452 1453
{
	struct saa711x_state *state = to_state(sd);
	struct i2c_client *client = v4l2_get_subdevdata(sd);
1454

1455 1456
	return v4l2_chip_ident_i2c_client(client, chip, state->ident, 0);
}
1457

1458 1459 1460 1461 1462 1463
static int saa711x_log_status(struct v4l2_subdev *sd)
{
	struct saa711x_state *state = to_state(sd);
	int reg1e, reg1f;
	int signalOk;
	int vcr;
1464

1465 1466 1467 1468 1469 1470 1471 1472
	v4l2_info(sd, "Audio frequency: %d Hz\n", state->audclk_freq);
	if (state->ident != V4L2_IDENT_SAA7115) {
		/* status for the saa7114 */
		reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
		signalOk = (reg1f & 0xc1) == 0x81;
		v4l2_info(sd, "Video signal:    %s\n", signalOk ? "ok" : "bad");
		v4l2_info(sd, "Frequency:       %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
		return 0;
1473 1474
	}

1475 1476 1477
	/* status for the saa7115 */
	reg1e = saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC);
	reg1f = saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC);
1478

1479 1480
	signalOk = (reg1f & 0xc1) == 0x81 && (reg1e & 0xc0) == 0x80;
	vcr = !(reg1f & 0x10);
1481

1482 1483 1484 1485 1486 1487
	if (state->input >= 6)
		v4l2_info(sd, "Input:           S-Video %d\n", state->input - 6);
	else
		v4l2_info(sd, "Input:           Composite %d\n", state->input);
	v4l2_info(sd, "Video signal:    %s\n", signalOk ? (vcr ? "VCR" : "broadcast/DVD") : "bad");
	v4l2_info(sd, "Frequency:       %s\n", (reg1f & 0x20) ? "60 Hz" : "50 Hz");
1488

1489 1490 1491 1492 1493 1494 1495 1496 1497 1498
	switch (reg1e & 0x03) {
	case 1:
		v4l2_info(sd, "Detected format: NTSC\n");
		break;
	case 2:
		v4l2_info(sd, "Detected format: PAL\n");
		break;
	case 3:
		v4l2_info(sd, "Detected format: SECAM\n");
		break;
1499
	default:
1500 1501
		v4l2_info(sd, "Detected format: BW/No color\n");
		break;
1502
	}
1503
	v4l2_info(sd, "Width, Height:   %d, %d\n", state->width, state->height);
1504
	v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
1505 1506 1507
	return 0;
}

1508 1509
/* ----------------------------------------------------------------------- */

1510 1511 1512 1513 1514
static const struct v4l2_ctrl_ops saa711x_ctrl_ops = {
	.s_ctrl = saa711x_s_ctrl,
	.g_volatile_ctrl = saa711x_g_volatile_ctrl,
};

1515 1516 1517
static const struct v4l2_subdev_core_ops saa711x_core_ops = {
	.log_status = saa711x_log_status,
	.g_chip_ident = saa711x_g_chip_ident,
1518 1519 1520 1521 1522 1523 1524
	.g_ext_ctrls = v4l2_subdev_g_ext_ctrls,
	.try_ext_ctrls = v4l2_subdev_try_ext_ctrls,
	.s_ext_ctrls = v4l2_subdev_s_ext_ctrls,
	.g_ctrl = v4l2_subdev_g_ctrl,
	.s_ctrl = v4l2_subdev_s_ctrl,
	.queryctrl = v4l2_subdev_queryctrl,
	.querymenu = v4l2_subdev_querymenu,
1525
	.s_std = saa711x_s_std,
1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545
	.reset = saa711x_reset,
	.s_gpio = saa711x_s_gpio,
#ifdef CONFIG_VIDEO_ADV_DEBUG
	.g_register = saa711x_g_register,
	.s_register = saa711x_s_register,
#endif
};

static const struct v4l2_subdev_tuner_ops saa711x_tuner_ops = {
	.s_radio = saa711x_s_radio,
	.g_tuner = saa711x_g_tuner,
};

static const struct v4l2_subdev_audio_ops saa711x_audio_ops = {
	.s_clock_freq = saa711x_s_clock_freq,
};

static const struct v4l2_subdev_video_ops saa711x_video_ops = {
	.s_routing = saa711x_s_routing,
	.s_crystal_freq = saa711x_s_crystal_freq,
1546
	.s_mbus_fmt = saa711x_s_mbus_fmt,
1547
	.s_stream = saa711x_s_stream,
1548 1549
	.querystd = saa711x_querystd,
	.g_input_status = saa711x_g_input_status,
1550 1551
};

1552 1553 1554
static const struct v4l2_subdev_vbi_ops saa711x_vbi_ops = {
	.g_vbi_data = saa711x_g_vbi_data,
	.decode_vbi_line = saa711x_decode_vbi_line,
1555 1556 1557
	.g_sliced_fmt = saa711x_g_sliced_fmt,
	.s_sliced_fmt = saa711x_s_sliced_fmt,
	.s_raw_fmt = saa711x_s_raw_fmt,
1558 1559
};

1560 1561 1562 1563 1564
static const struct v4l2_subdev_ops saa711x_ops = {
	.core = &saa711x_core_ops,
	.tuner = &saa711x_tuner_ops,
	.audio = &saa711x_audio_ops,
	.video = &saa711x_video_ops,
1565
	.vbi = &saa711x_vbi_ops,
1566 1567
};

1568 1569
/* ----------------------------------------------------------------------- */

1570
static int saa711x_probe(struct i2c_client *client,
1571
			 const struct i2c_device_id *id)
1572
{
1573
	struct saa711x_state *state;
1574
	struct v4l2_subdev *sd;
1575 1576 1577
	struct v4l2_ctrl_handler *hdl;
	int i;
	char name[17];
1578 1579
	char chip_id;
	int autodetect = !id || id->driver_data == 1;
1580 1581

	/* Check if the adapter supports the needed features */
1582
	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
1583
		return -EIO;
1584

1585
	for (i = 0; i < 0x0f; i++) {
1586 1587
		i2c_smbus_write_byte_data(client, 0, i);
		name[i] = (i2c_smbus_read_byte_data(client, 0) & 0x0f) + '0';
1588 1589
		if (name[i] > '9')
			name[i] += 'a' - '9' - 1;
1590
	}
1591
	name[i] = '\0';
1592

1593
	chip_id = name[5];
1594

1595
	/* Check whether this chip is part of the saa711x series */
R
Russell King 已提交
1596
	if (memcmp(name + 1, "f711", 4)) {
1597
		v4l_dbg(1, debug, client, "chip found @ 0x%x (ID %s) does not match a known saa711x chip.\n",
1598
			client->addr << 1, name);
1599
		return -ENODEV;
1600 1601
	}

1602 1603 1604 1605 1606 1607 1608 1609
	/* Safety check */
	if (!autodetect && id->name[6] != chip_id) {
		v4l_warn(client, "found saa711%c while %s was expected\n",
			 chip_id, id->name);
	}
	snprintf(client->name, sizeof(client->name), "saa711%c", chip_id);
	v4l_info(client, "saa711%c found (%s) @ 0x%x (%s)\n", chip_id, name,
		 client->addr << 1, client->adapter->name);
1610

1611
	state = kzalloc(sizeof(struct saa711x_state), GFP_KERNEL);
1612
	if (state == NULL)
1613
		return -ENOMEM;
1614 1615
	sd = &state->sd;
	v4l2_i2c_subdev_init(sd, client, &saa711x_ops);
1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639

	hdl = &state->hdl;
	v4l2_ctrl_handler_init(hdl, 6);
	/* add in ascending ID order */
	v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
			V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
	v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
			V4L2_CID_CONTRAST, 0, 127, 1, 64);
	v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
			V4L2_CID_SATURATION, 0, 127, 1, 64);
	v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
			V4L2_CID_HUE, -128, 127, 1, 0);
	state->agc = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
			V4L2_CID_CHROMA_AGC, 0, 1, 1, 1);
	state->gain = v4l2_ctrl_new_std(hdl, &saa711x_ctrl_ops,
			V4L2_CID_CHROMA_GAIN, 0, 127, 1, 40);
	sd->ctrl_handler = hdl;
	if (hdl->error) {
		int err = hdl->error;

		v4l2_ctrl_handler_free(hdl);
		kfree(state);
		return err;
	}
1640
	v4l2_ctrl_auto_cluster(2, &state->agc, 0, true);
1641

1642
	state->input = -1;
1643
	state->output = SAA7115_IPORT_ON;
1644
	state->enable = 1;
1645
	state->radio = 0;
1646
	switch (chip_id) {
1647
	case '1':
1648
		state->ident = V4L2_IDENT_SAA7111;
1649 1650 1651 1652
		if (saa711x_read(sd, R_00_CHIP_VERSION) & 0xf0) {
			v4l_info(client, "saa7111a variant found\n");
			state->ident = V4L2_IDENT_SAA7111A;
		}
1653
		break;
1654
	case '3':
1655 1656
		state->ident = V4L2_IDENT_SAA7113;
		break;
1657
	case '4':
1658 1659
		state->ident = V4L2_IDENT_SAA7114;
		break;
1660
	case '5':
1661 1662
		state->ident = V4L2_IDENT_SAA7115;
		break;
1663
	case '8':
1664 1665 1666 1667
		state->ident = V4L2_IDENT_SAA7118;
		break;
	default:
		state->ident = V4L2_IDENT_SAA7111;
1668
		v4l2_info(sd, "WARNING: Chip is not known - Falling back to saa7111\n");
1669
		break;
1670 1671
	}

1672
	state->audclk_freq = 48000;
1673

1674
	v4l2_dbg(1, debug, sd, "writing init values\n");
1675 1676

	/* init to 60hz/48khz */
1677 1678 1679
	state->crystal_freq = SAA7115_FREQ_24_576_MHZ;
	switch (state->ident) {
	case V4L2_IDENT_SAA7111:
1680
	case V4L2_IDENT_SAA7111A:
1681
		saa711x_writeregs(sd, saa7111_init);
1682 1683
		break;
	case V4L2_IDENT_SAA7113:
1684
		saa711x_writeregs(sd, saa7113_init);
1685 1686
		break;
	default:
1687
		state->crystal_freq = SAA7115_FREQ_32_11_MHZ;
1688
		saa711x_writeregs(sd, saa7115_init_auto_input);
1689
	}
1690
	if (state->ident > V4L2_IDENT_SAA7111A)
1691 1692
		saa711x_writeregs(sd, saa7115_init_misc);
	saa711x_set_v4lstd(sd, V4L2_STD_NTSC);
1693
	v4l2_ctrl_handler_setup(hdl);
1694

1695 1696 1697
	v4l2_dbg(1, debug, sd, "status: (1E) 0x%02x, (1F) 0x%02x\n",
		saa711x_read(sd, R_1E_STATUS_BYTE_1_VD_DEC),
		saa711x_read(sd, R_1F_STATUS_BYTE_2_VD_DEC));
1698 1699 1700
	return 0;
}

1701
/* ----------------------------------------------------------------------- */
1702

1703
static int saa711x_remove(struct i2c_client *client)
1704
{
1705 1706 1707
	struct v4l2_subdev *sd = i2c_get_clientdata(client);

	v4l2_device_unregister_subdev(sd);
1708
	v4l2_ctrl_handler_free(sd->ctrl_handler);
1709
	kfree(to_state(sd));
1710 1711 1712
	return 0;
}

1713
static const struct i2c_device_id saa711x_id[] = {
1714
	{ "saa7115_auto", 1 }, /* autodetect */
1715 1716 1717 1718 1719 1720 1721
	{ "saa7111", 0 },
	{ "saa7113", 0 },
	{ "saa7114", 0 },
	{ "saa7115", 0 },
	{ "saa7118", 0 },
	{ }
};
1722 1723 1724 1725 1726 1727 1728 1729 1730 1731
MODULE_DEVICE_TABLE(i2c, saa711x_id);

static struct i2c_driver saa711x_driver = {
	.driver = {
		.owner	= THIS_MODULE,
		.name	= "saa7115",
	},
	.probe		= saa711x_probe,
	.remove		= saa711x_remove,
	.id_table	= saa711x_id,
1732
};
1733

1734
module_i2c_driver(saa711x_driver);