intel_fbc.c 38.6 KB
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/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 */

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/**
 * DOC: Frame Buffer Compression (FBC)
 *
 * FBC tries to save memory bandwidth (and so power consumption) by
 * compressing the amount of memory used by the display. It is total
 * transparent to user space and completely handled in the kernel.
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 *
 * The benefits of FBC are mostly visible with solid backgrounds and
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 * variation-less patterns. It comes from keeping the memory footprint small
 * and having fewer memory pages opened and accessed for refreshing the display.
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 *
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 * i915 is responsible to reserve stolen memory for FBC and configure its
 * offset on proper registers. The hardware takes care of all
 * compress/decompress. However there are many known cases where we have to
 * forcibly disable it to allow proper screen updates.
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 */

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#include "intel_drv.h"
#include "i915_drv.h"

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static inline bool fbc_supported(struct drm_i915_private *dev_priv)
{
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	return HAS_FBC(dev_priv);
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}

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static inline bool fbc_on_pipe_a_only(struct drm_i915_private *dev_priv)
{
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	return IS_HASWELL(dev_priv) || INTEL_GEN(dev_priv) >= 8;
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}

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static inline bool fbc_on_plane_a_only(struct drm_i915_private *dev_priv)
{
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	return INTEL_GEN(dev_priv) < 4;
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}

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static inline bool no_fbc_on_multiple_pipes(struct drm_i915_private *dev_priv)
{
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	return INTEL_GEN(dev_priv) <= 3;
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}

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/*
 * In some platforms where the CRTC's x:0/y:0 coordinates doesn't match the
 * frontbuffer's x:0/y:0 coordinates we lie to the hardware about the plane's
 * origin so the x and y offsets can actually fit the registers. As a
 * consequence, the fence doesn't really start exactly at the display plane
 * address we program because it starts at the real start of the buffer, so we
 * have to take this into consideration here.
 */
static unsigned int get_crtc_fence_y_offset(struct intel_crtc *crtc)
{
	return crtc->base.y - crtc->adjusted_y;
}

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/*
 * For SKL+, the plane source size used by the hardware is based on the value we
 * write to the PLANE_SIZE register. For BDW-, the hardware looks at the value
 * we wrote to PIPESRC.
 */
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static void intel_fbc_get_plane_source_size(struct intel_fbc_state_cache *cache,
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					    int *width, int *height)
{
	int w, h;

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	if (drm_rotation_90_or_270(cache->plane.rotation)) {
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		w = cache->plane.src_h;
		h = cache->plane.src_w;
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	} else {
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		w = cache->plane.src_w;
		h = cache->plane.src_h;
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	}

	if (width)
		*width = w;
	if (height)
		*height = h;
}

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static int intel_fbc_calculate_cfb_size(struct drm_i915_private *dev_priv,
					struct intel_fbc_state_cache *cache)
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{
	int lines;

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	intel_fbc_get_plane_source_size(cache, NULL, &lines);
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	if (INTEL_GEN(dev_priv) == 7)
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		lines = min(lines, 2048);
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	else if (INTEL_GEN(dev_priv) >= 8)
		lines = min(lines, 2560);
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	/* Hardware needs the full buffer stride, not just the active area. */
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	return lines * cache->fb.stride;
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}

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static void i8xx_fbc_deactivate(struct drm_i915_private *dev_priv)
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{
	u32 fbc_ctl;

	/* Disable compression */
	fbc_ctl = I915_READ(FBC_CONTROL);
	if ((fbc_ctl & FBC_CTL_EN) == 0)
		return;

	fbc_ctl &= ~FBC_CTL_EN;
	I915_WRITE(FBC_CONTROL, fbc_ctl);

	/* Wait for compressing bit to clear */
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	if (intel_wait_for_register(dev_priv,
				    FBC_STATUS, FBC_STAT_COMPRESSING, 0,
				    10)) {
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		DRM_DEBUG_KMS("FBC idle timed out\n");
		return;
	}
}

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static void i8xx_fbc_activate(struct drm_i915_private *dev_priv)
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{
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	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
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	int cfb_pitch;
	int i;
	u32 fbc_ctl;

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	/* Note: fbc.threshold == 1 for i8xx */
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	cfb_pitch = params->cfb_size / FBC_LL_SIZE;
	if (params->fb.stride < cfb_pitch)
		cfb_pitch = params->fb.stride;
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	/* FBC_CTL wants 32B or 64B units */
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	if (IS_GEN2(dev_priv))
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		cfb_pitch = (cfb_pitch / 32) - 1;
	else
		cfb_pitch = (cfb_pitch / 64) - 1;

	/* Clear old tags */
	for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
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		I915_WRITE(FBC_TAG(i), 0);
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	if (IS_GEN4(dev_priv)) {
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		u32 fbc_ctl2;

		/* Set it up... */
		fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
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		fbc_ctl2 |= FBC_CTL_PLANE(params->crtc.plane);
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		I915_WRITE(FBC_CONTROL2, fbc_ctl2);
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		I915_WRITE(FBC_FENCE_OFF, params->crtc.fence_y_offset);
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	}

	/* enable it... */
	fbc_ctl = I915_READ(FBC_CONTROL);
	fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT;
	fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
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	if (IS_I945GM(dev_priv))
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		fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
	fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
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	fbc_ctl |= params->fb.fence_reg;
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	I915_WRITE(FBC_CONTROL, fbc_ctl);
}

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static bool i8xx_fbc_is_active(struct drm_i915_private *dev_priv)
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{
	return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
}

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static void g4x_fbc_activate(struct drm_i915_private *dev_priv)
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{
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	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
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	u32 dpfc_ctl;

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	dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane) | DPFC_SR_EN;
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	if (params->fb.format->cpp[0] == 2)
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		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
	else
		dpfc_ctl |= DPFC_CTL_LIMIT_1X;

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	if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
		dpfc_ctl |= DPFC_CTL_FENCE_EN | params->fb.fence_reg;
		I915_WRITE(DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
	} else {
		I915_WRITE(DPFC_FENCE_YOFF, 0);
	}
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	/* enable it... */
	I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
}

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static void g4x_fbc_deactivate(struct drm_i915_private *dev_priv)
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{
	u32 dpfc_ctl;

	/* Disable compression */
	dpfc_ctl = I915_READ(DPFC_CONTROL);
	if (dpfc_ctl & DPFC_CTL_EN) {
		dpfc_ctl &= ~DPFC_CTL_EN;
		I915_WRITE(DPFC_CONTROL, dpfc_ctl);
	}
}

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static bool g4x_fbc_is_active(struct drm_i915_private *dev_priv)
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{
	return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
}

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/* This function forces a CFB recompression through the nuke operation. */
static void intel_fbc_recompress(struct drm_i915_private *dev_priv)
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{
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	I915_WRITE(MSG_FBC_REND_STATE, FBC_REND_NUKE);
	POSTING_READ(MSG_FBC_REND_STATE);
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}

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static void ilk_fbc_activate(struct drm_i915_private *dev_priv)
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{
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	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
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	u32 dpfc_ctl;
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	int threshold = dev_priv->fbc.threshold;
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	dpfc_ctl = DPFC_CTL_PLANE(params->crtc.plane);
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	if (params->fb.format->cpp[0] == 2)
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		threshold++;
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	switch (threshold) {
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	case 4:
	case 3:
		dpfc_ctl |= DPFC_CTL_LIMIT_4X;
		break;
	case 2:
		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
		break;
	case 1:
		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
		break;
	}
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	if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
		dpfc_ctl |= DPFC_CTL_FENCE_EN;
		if (IS_GEN5(dev_priv))
			dpfc_ctl |= params->fb.fence_reg;
		if (IS_GEN6(dev_priv)) {
			I915_WRITE(SNB_DPFC_CTL_SA,
				   SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
			I915_WRITE(DPFC_CPU_FENCE_OFFSET,
				   params->crtc.fence_y_offset);
		}
	} else {
		if (IS_GEN6(dev_priv)) {
			I915_WRITE(SNB_DPFC_CTL_SA, 0);
			I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
		}
	}
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	I915_WRITE(ILK_DPFC_FENCE_YOFF, params->crtc.fence_y_offset);
	I915_WRITE(ILK_FBC_RT_BASE, params->fb.ggtt_offset | ILK_FBC_RT_VALID);
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	/* enable it... */
	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);

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	intel_fbc_recompress(dev_priv);
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}

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static void ilk_fbc_deactivate(struct drm_i915_private *dev_priv)
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{
	u32 dpfc_ctl;

	/* Disable compression */
	dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
	if (dpfc_ctl & DPFC_CTL_EN) {
		dpfc_ctl &= ~DPFC_CTL_EN;
		I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
	}
}

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static bool ilk_fbc_is_active(struct drm_i915_private *dev_priv)
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{
	return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
}

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static void gen7_fbc_activate(struct drm_i915_private *dev_priv)
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{
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	struct intel_fbc_reg_params *params = &dev_priv->fbc.params;
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	u32 dpfc_ctl;
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	int threshold = dev_priv->fbc.threshold;
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	dpfc_ctl = 0;
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	if (IS_IVYBRIDGE(dev_priv))
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		dpfc_ctl |= IVB_DPFC_CTL_PLANE(params->crtc.plane);
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306
	if (params->fb.format->cpp[0] == 2)
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		threshold++;
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309
	switch (threshold) {
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	case 4:
	case 3:
		dpfc_ctl |= DPFC_CTL_LIMIT_4X;
		break;
	case 2:
		dpfc_ctl |= DPFC_CTL_LIMIT_2X;
		break;
	case 1:
		dpfc_ctl |= DPFC_CTL_LIMIT_1X;
		break;
	}

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	if (params->fb.fence_reg != I915_FENCE_REG_NONE) {
		dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN;
		I915_WRITE(SNB_DPFC_CTL_SA,
			   SNB_CPU_FENCE_ENABLE | params->fb.fence_reg);
		I915_WRITE(DPFC_CPU_FENCE_OFFSET, params->crtc.fence_y_offset);
	} else {
		I915_WRITE(SNB_DPFC_CTL_SA,0);
		I915_WRITE(DPFC_CPU_FENCE_OFFSET, 0);
	}
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	if (dev_priv->fbc.false_color)
		dpfc_ctl |= FBC_CTL_FALSE_COLOR;

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	if (IS_IVYBRIDGE(dev_priv)) {
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		/* WaFbcAsynchFlipDisableFbcQueue:ivb */
		I915_WRITE(ILK_DISPLAY_CHICKEN1,
			   I915_READ(ILK_DISPLAY_CHICKEN1) |
			   ILK_FBCQ_DIS);
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	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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		/* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
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		I915_WRITE(CHICKEN_PIPESL_1(params->crtc.pipe),
			   I915_READ(CHICKEN_PIPESL_1(params->crtc.pipe)) |
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			   HSW_FBCQ_DIS);
	}

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	I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);

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	intel_fbc_recompress(dev_priv);
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}

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static bool intel_fbc_hw_is_active(struct drm_i915_private *dev_priv)
{
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	if (INTEL_GEN(dev_priv) >= 5)
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		return ilk_fbc_is_active(dev_priv);
	else if (IS_GM45(dev_priv))
		return g4x_fbc_is_active(dev_priv);
	else
		return i8xx_fbc_is_active(dev_priv);
}

static void intel_fbc_hw_activate(struct drm_i915_private *dev_priv)
{
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	struct intel_fbc *fbc = &dev_priv->fbc;

	fbc->active = true;

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	if (INTEL_GEN(dev_priv) >= 7)
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		gen7_fbc_activate(dev_priv);
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	else if (INTEL_GEN(dev_priv) >= 5)
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		ilk_fbc_activate(dev_priv);
	else if (IS_GM45(dev_priv))
		g4x_fbc_activate(dev_priv);
	else
		i8xx_fbc_activate(dev_priv);
}

static void intel_fbc_hw_deactivate(struct drm_i915_private *dev_priv)
{
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	struct intel_fbc *fbc = &dev_priv->fbc;

	fbc->active = false;

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	if (INTEL_GEN(dev_priv) >= 5)
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		ilk_fbc_deactivate(dev_priv);
	else if (IS_GM45(dev_priv))
		g4x_fbc_deactivate(dev_priv);
	else
		i8xx_fbc_deactivate(dev_priv);
}

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/**
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 * intel_fbc_is_active - Is FBC active?
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 * @dev_priv: i915 device instance
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 *
 * This function is used to verify the current state of FBC.
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 *
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 * FIXME: This should be tracked in the plane config eventually
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 * instead of queried at runtime for most callers.
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 */
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bool intel_fbc_is_active(struct drm_i915_private *dev_priv)
402
{
403
	return dev_priv->fbc.active;
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}

static void intel_fbc_work_fn(struct work_struct *__work)
{
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	struct drm_i915_private *dev_priv =
		container_of(__work, struct drm_i915_private, fbc.work.work);
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	struct intel_fbc *fbc = &dev_priv->fbc;
	struct intel_fbc_work *work = &fbc->work;
	struct intel_crtc *crtc = fbc->crtc;
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	struct drm_vblank_crtc *vblank = &dev_priv->drm.vblank[crtc->pipe];
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	if (drm_crtc_vblank_get(&crtc->base)) {
		DRM_ERROR("vblank not available for FBC on pipe %c\n",
			  pipe_name(crtc->pipe));

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		mutex_lock(&fbc->lock);
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		work->scheduled = false;
421
		mutex_unlock(&fbc->lock);
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		return;
	}
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retry:
	/* Delay the actual enabling to let pageflipping cease and the
	 * display to settle before starting the compression. Note that
	 * this delay also serves a second purpose: it allows for a
	 * vblank to pass after disabling the FBC before we attempt
	 * to modify the control registers.
	 *
	 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
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	 *
	 * It is also worth mentioning that since work->scheduled_vblank can be
	 * updated multiple times by the other threads, hitting the timeout is
	 * not an error condition. We'll just end up hitting the "goto retry"
	 * case below.
438
	 */
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	wait_event_timeout(vblank->queue,
		drm_crtc_vblank_count(&crtc->base) != work->scheduled_vblank,
		msecs_to_jiffies(50));
442

443
	mutex_lock(&fbc->lock);
444

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	/* Were we cancelled? */
	if (!work->scheduled)
		goto out;

	/* Were we delayed again while this function was sleeping? */
450
	if (drm_crtc_vblank_count(&crtc->base) == work->scheduled_vblank) {
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		mutex_unlock(&fbc->lock);
452
		goto retry;
453 454
	}

455
	intel_fbc_hw_activate(dev_priv);
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	work->scheduled = false;

out:
460
	mutex_unlock(&fbc->lock);
461
	drm_crtc_vblank_put(&crtc->base);
462 463
}

464
static void intel_fbc_schedule_activation(struct intel_crtc *crtc)
465
{
466
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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	struct intel_fbc *fbc = &dev_priv->fbc;
	struct intel_fbc_work *work = &fbc->work;
469

470
	WARN_ON(!mutex_is_locked(&fbc->lock));
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	if (drm_crtc_vblank_get(&crtc->base)) {
		DRM_ERROR("vblank not available for FBC on pipe %c\n",
			  pipe_name(crtc->pipe));
		return;
	}

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	/* It is useless to call intel_fbc_cancel_work() or cancel_work() in
	 * this function since we're not releasing fbc.lock, so it won't have an
	 * opportunity to grab it to discover that it was cancelled. So we just
	 * update the expected jiffy count. */
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	work->scheduled = true;
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	work->scheduled_vblank = drm_crtc_vblank_count(&crtc->base);
	drm_crtc_vblank_put(&crtc->base);
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486
	schedule_work(&work->work);
487 488
}

489
static void intel_fbc_deactivate(struct drm_i915_private *dev_priv)
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{
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	struct intel_fbc *fbc = &dev_priv->fbc;

	WARN_ON(!mutex_is_locked(&fbc->lock));
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	/* Calling cancel_work() here won't help due to the fact that the work
	 * function grabs fbc->lock. Just set scheduled to false so the work
	 * function can know it was cancelled. */
	fbc->work.scheduled = false;
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500
	if (fbc->active)
501
		intel_fbc_hw_deactivate(dev_priv);
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}

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static bool multiple_pipes_ok(struct intel_crtc *crtc,
			      struct intel_plane_state *plane_state)
506
{
507
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
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	struct intel_fbc *fbc = &dev_priv->fbc;
	enum pipe pipe = crtc->pipe;
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	/* Don't even bother tracking anything we don't need. */
	if (!no_fbc_on_multiple_pipes(dev_priv))
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		return true;

515
	if (plane_state->base.visible)
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		fbc->visible_pipes_mask |= (1 << pipe);
	else
		fbc->visible_pipes_mask &= ~(1 << pipe);
519

520
	return (fbc->visible_pipes_mask & ~(1 << pipe)) != 0;
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}

523
static int find_compression_threshold(struct drm_i915_private *dev_priv,
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				      struct drm_mm_node *node,
				      int size,
				      int fb_cpp)
{
528
	struct i915_ggtt *ggtt = &dev_priv->ggtt;
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	int compression_threshold = 1;
	int ret;
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	u64 end;

	/* The FBC hardware for BDW/SKL doesn't have access to the stolen
	 * reserved range size, so it always assumes the maximum (8mb) is used.
	 * If we enable FBC using a CFB on that memory range we'll get FIFO
	 * underruns, even if that range is not reserved by the BIOS. */
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	if (IS_BROADWELL(dev_priv) ||
	    IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
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		end = ggtt->stolen_size - 8 * 1024 * 1024;
540
	else
541
		end = ggtt->stolen_usable_size;
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	/* HACK: This code depends on what we will do in *_enable_fbc. If that
	 * code changes, this code needs to change as well.
	 *
	 * The enable_fbc code will attempt to use one of our 2 compression
	 * thresholds, therefore, in that case, we only have 1 resort.
	 */

	/* Try to over-allocate to reduce reallocations and fragmentation. */
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	ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size <<= 1,
						   4096, 0, end);
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	if (ret == 0)
		return compression_threshold;

again:
	/* HW's ability to limit the CFB is 1:4 */
	if (compression_threshold > 4 ||
	    (fb_cpp == 2 && compression_threshold == 2))
		return 0;

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	ret = i915_gem_stolen_insert_node_in_range(dev_priv, node, size >>= 1,
						   4096, 0, end);
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	if (ret && INTEL_GEN(dev_priv) <= 4) {
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		return 0;
	} else if (ret) {
		compression_threshold <<= 1;
		goto again;
	} else {
		return compression_threshold;
	}
}

574
static int intel_fbc_alloc_cfb(struct intel_crtc *crtc)
575
{
576
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
577
	struct intel_fbc *fbc = &dev_priv->fbc;
578
	struct drm_mm_node *uninitialized_var(compressed_llb);
579 580
	int size, fb_cpp, ret;

581
	WARN_ON(drm_mm_node_allocated(&fbc->compressed_fb));
582

583
	size = intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache);
584
	fb_cpp = fbc->state_cache.fb.format->cpp[0];
585

586
	ret = find_compression_threshold(dev_priv, &fbc->compressed_fb,
587 588 589 590 591 592 593 594
					 size, fb_cpp);
	if (!ret)
		goto err_llb;
	else if (ret > 1) {
		DRM_INFO("Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.\n");

	}

595
	fbc->threshold = ret;
596

597
	if (INTEL_GEN(dev_priv) >= 5)
598
		I915_WRITE(ILK_DPFC_CB_BASE, fbc->compressed_fb.start);
599
	else if (IS_GM45(dev_priv)) {
600
		I915_WRITE(DPFC_CB_BASE, fbc->compressed_fb.start);
601 602 603 604 605 606 607 608 609 610
	} else {
		compressed_llb = kzalloc(sizeof(*compressed_llb), GFP_KERNEL);
		if (!compressed_llb)
			goto err_fb;

		ret = i915_gem_stolen_insert_node(dev_priv, compressed_llb,
						  4096, 4096);
		if (ret)
			goto err_fb;

611
		fbc->compressed_llb = compressed_llb;
612 613

		I915_WRITE(FBC_CFB_BASE,
614
			   dev_priv->mm.stolen_base + fbc->compressed_fb.start);
615 616 617 618
		I915_WRITE(FBC_LL_BASE,
			   dev_priv->mm.stolen_base + compressed_llb->start);
	}

619
	DRM_DEBUG_KMS("reserved %llu bytes of contiguous stolen space for FBC, threshold: %d\n",
620
		      fbc->compressed_fb.size, fbc->threshold);
621 622 623 624 625

	return 0;

err_fb:
	kfree(compressed_llb);
626
	i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);
627 628 629 630 631
err_llb:
	pr_info_once("drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this.\n", size);
	return -ENOSPC;
}

632
static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
633
{
634 635 636 637 638 639 640 641
	struct intel_fbc *fbc = &dev_priv->fbc;

	if (drm_mm_node_allocated(&fbc->compressed_fb))
		i915_gem_stolen_remove_node(dev_priv, &fbc->compressed_fb);

	if (fbc->compressed_llb) {
		i915_gem_stolen_remove_node(dev_priv, fbc->compressed_llb);
		kfree(fbc->compressed_llb);
642 643 644
	}
}

645
void intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv)
P
Paulo Zanoni 已提交
646
{
647 648
	struct intel_fbc *fbc = &dev_priv->fbc;

P
Paulo Zanoni 已提交
649
	if (!fbc_supported(dev_priv))
650 651
		return;

652
	mutex_lock(&fbc->lock);
653
	__intel_fbc_cleanup_cfb(dev_priv);
654
	mutex_unlock(&fbc->lock);
P
Paulo Zanoni 已提交
655 656
}

657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677
static bool stride_is_valid(struct drm_i915_private *dev_priv,
			    unsigned int stride)
{
	/* These should have been caught earlier. */
	WARN_ON(stride < 512);
	WARN_ON((stride & (64 - 1)) != 0);

	/* Below are the additional FBC restrictions. */

	if (IS_GEN2(dev_priv) || IS_GEN3(dev_priv))
		return stride == 4096 || stride == 8192;

	if (IS_GEN4(dev_priv) && !IS_G4X(dev_priv) && stride < 2048)
		return false;

	if (stride > 16384)
		return false;

	return true;
}

678 679
static bool pixel_format_is_valid(struct drm_i915_private *dev_priv,
				  uint32_t pixel_format)
680
{
681
	switch (pixel_format) {
682 683 684 685 686 687
	case DRM_FORMAT_XRGB8888:
	case DRM_FORMAT_XBGR8888:
		return true;
	case DRM_FORMAT_XRGB1555:
	case DRM_FORMAT_RGB565:
		/* 16bpp not supported on gen2 */
688
		if (IS_GEN2(dev_priv))
689 690 691 692 693 694 695 696 697 698
			return false;
		/* WaFbcOnly1to1Ratio:ctg */
		if (IS_G4X(dev_priv))
			return false;
		return true;
	default:
		return false;
	}
}

699 700 701 702 703 704 705
/*
 * For some reason, the hardware tracking starts looking at whatever we
 * programmed as the display plane base address register. It does not look at
 * the X and Y offset registers. That's why we look at the crtc->adjusted{x,y}
 * variables instead of just looking at the pipe/plane size.
 */
static bool intel_fbc_hw_tracking_covers_screen(struct intel_crtc *crtc)
706
{
707
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
708
	struct intel_fbc *fbc = &dev_priv->fbc;
709
	unsigned int effective_w, effective_h, max_w, max_h;
710

711
	if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) {
712 713
		max_w = 4096;
		max_h = 4096;
714
	} else if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) {
715 716 717 718 719 720 721
		max_w = 4096;
		max_h = 2048;
	} else {
		max_w = 2048;
		max_h = 1536;
	}

722 723
	intel_fbc_get_plane_source_size(&fbc->state_cache, &effective_w,
					&effective_h);
724 725 726 727
	effective_w += crtc->adjusted_x;
	effective_h += crtc->adjusted_y;

	return effective_w <= max_w && effective_h <= max_h;
728 729
}

730 731 732 733 734 735 736 737
/* XXX replace me when we have VMA tracking for intel_plane_state */
static int get_fence_id(struct drm_framebuffer *fb)
{
	struct i915_vma *vma = i915_gem_object_to_ggtt(intel_fb_obj(fb), NULL);

	return vma && vma->fence ? vma->fence->id : I915_FENCE_REG_NONE;
}

738 739 740
static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
					 struct intel_crtc_state *crtc_state,
					 struct intel_plane_state *plane_state)
741
{
742
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
743
	struct intel_fbc *fbc = &dev_priv->fbc;
744 745
	struct intel_fbc_state_cache *cache = &fbc->state_cache;
	struct drm_framebuffer *fb = plane_state->base.fb;
746 747
	struct drm_i915_gem_object *obj;

748 749 750 751 752 753
	cache->crtc.mode_flags = crtc_state->base.adjusted_mode.flags;
	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
		cache->crtc.hsw_bdw_pixel_rate =
			ilk_pipe_pixel_rate(crtc_state);

	cache->plane.rotation = plane_state->base.rotation;
754 755 756
	cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
	cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
	cache->plane.visible = plane_state->base.visible;
757 758 759

	if (!cache->plane.visible)
		return;
760 761

	obj = intel_fb_obj(fb);
762

763 764
	/* FIXME: We lack the proper locking here, so only run this on the
	 * platforms that need. */
765
	if (IS_GEN(dev_priv, 5, 6))
C
Chris Wilson 已提交
766
		cache->fb.ilk_ggtt_offset = i915_gem_object_ggtt_offset(obj, NULL);
767
	cache->fb.format = fb->format;
768
	cache->fb.stride = fb->pitches[0];
769
	cache->fb.fence_reg = get_fence_id(fb);
770
	cache->fb.tiling_mode = i915_gem_object_get_tiling(obj);
771 772 773 774
}

static bool intel_fbc_can_activate(struct intel_crtc *crtc)
{
775
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
776 777 778
	struct intel_fbc *fbc = &dev_priv->fbc;
	struct intel_fbc_state_cache *cache = &fbc->state_cache;

779 780 781 782 783 784 785 786
	/* We don't need to use a state cache here since this information is
	 * global for all CRTC.
	 */
	if (fbc->underrun_detected) {
		fbc->no_fbc_reason = "underrun detected";
		return false;
	}

787
	if (!cache->plane.visible) {
788
		fbc->no_fbc_reason = "primary plane not visible";
789 790
		return false;
	}
791

792 793
	if ((cache->crtc.mode_flags & DRM_MODE_FLAG_INTERLACE) ||
	    (cache->crtc.mode_flags & DRM_MODE_FLAG_DBLSCAN)) {
794
		fbc->no_fbc_reason = "incompatible mode";
795
		return false;
796 797
	}

798
	if (!intel_fbc_hw_tracking_covers_screen(crtc)) {
799
		fbc->no_fbc_reason = "mode too large for compression";
800
		return false;
801
	}
802

803 804
	/* The use of a CPU fence is mandatory in order to detect writes
	 * by the CPU to the scanout and trigger updates to the FBC.
805 806 807 808
	 *
	 * Note that is possible for a tiled surface to be unmappable (and
	 * so have no fence associated with it) due to aperture constaints
	 * at the time of pinning.
809
	 */
810 811
	if (cache->fb.tiling_mode != I915_TILING_X ||
	    cache->fb.fence_reg == I915_FENCE_REG_NONE) {
812 813
		fbc->no_fbc_reason = "framebuffer not tiled or fenced";
		return false;
814
	}
815
	if (INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv) &&
816
	    cache->plane.rotation != DRM_ROTATE_0) {
817
		fbc->no_fbc_reason = "rotation unsupported";
818
		return false;
819 820
	}

821
	if (!stride_is_valid(dev_priv, cache->fb.stride)) {
822
		fbc->no_fbc_reason = "framebuffer stride not supported";
823
		return false;
824 825
	}

826
	if (!pixel_format_is_valid(dev_priv, cache->fb.format->format)) {
827
		fbc->no_fbc_reason = "pixel format is invalid";
828
		return false;
829 830
	}

831 832
	/* WaFbcExceedCdClockThreshold:hsw,bdw */
	if ((IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) &&
833
	    cache->crtc.hsw_bdw_pixel_rate >= dev_priv->cdclk_freq * 95 / 100) {
834
		fbc->no_fbc_reason = "pixel rate is too big";
835
		return false;
836 837
	}

838 839 840 841 842 843 844 845 846 847
	/* It is possible for the required CFB size change without a
	 * crtc->disable + crtc->enable since it is possible to change the
	 * stride without triggering a full modeset. Since we try to
	 * over-allocate the CFB, there's a chance we may keep FBC enabled even
	 * if this happens, but if we exceed the current CFB size we'll have to
	 * disable FBC. Notice that it would be possible to disable FBC, wait
	 * for a frame, free the stolen node, then try to reenable FBC in case
	 * we didn't get any invalidate/deactivate calls, but this would require
	 * a lot of tracking just for a specific case. If we conclude it's an
	 * important case, we can implement it later. */
848
	if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) >
849
	    fbc->compressed_fb.size * fbc->threshold) {
850
		fbc->no_fbc_reason = "CFB requirements changed";
851 852 853 854 855 856
		return false;
	}

	return true;
}

857
static bool intel_fbc_can_enable(struct drm_i915_private *dev_priv)
858
{
859
	struct intel_fbc *fbc = &dev_priv->fbc;
860

861
	if (intel_vgpu_active(dev_priv)) {
862
		fbc->no_fbc_reason = "VGPU is active";
863 864 865 866
		return false;
	}

	if (!i915.enable_fbc) {
867
		fbc->no_fbc_reason = "disabled per module param or by default";
868 869 870
		return false;
	}

871 872 873 874 875
	if (fbc->underrun_detected) {
		fbc->no_fbc_reason = "underrun detected";
		return false;
	}

876 877 878
	return true;
}

879 880 881
static void intel_fbc_get_reg_params(struct intel_crtc *crtc,
				     struct intel_fbc_reg_params *params)
{
882
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
883 884
	struct intel_fbc *fbc = &dev_priv->fbc;
	struct intel_fbc_state_cache *cache = &fbc->state_cache;
885 886 887 888 889 890 891 892 893 894

	/* Since all our fields are integer types, use memset here so the
	 * comparison function can rely on memcmp because the padding will be
	 * zero. */
	memset(params, 0, sizeof(*params));

	params->crtc.pipe = crtc->pipe;
	params->crtc.plane = crtc->plane;
	params->crtc.fence_y_offset = get_crtc_fence_y_offset(crtc);

895
	params->fb.format = cache->fb.format;
896 897
	params->fb.stride = cache->fb.stride;
	params->fb.fence_reg = cache->fb.fence_reg;
898

899
	params->cfb_size = intel_fbc_calculate_cfb_size(dev_priv, cache);
900

901
	params->fb.ggtt_offset = cache->fb.ilk_ggtt_offset;
902 903 904 905 906 907 908 909 910
}

static bool intel_fbc_reg_params_equal(struct intel_fbc_reg_params *params1,
				       struct intel_fbc_reg_params *params2)
{
	/* We can use this since intel_fbc_get_reg_params() does a memset. */
	return memcmp(params1, params2, sizeof(*params1)) == 0;
}

911 912 913
void intel_fbc_pre_update(struct intel_crtc *crtc,
			  struct intel_crtc_state *crtc_state,
			  struct intel_plane_state *plane_state)
914
{
915
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
916
	struct intel_fbc *fbc = &dev_priv->fbc;
917

918 919 920 921
	if (!fbc_supported(dev_priv))
		return;

	mutex_lock(&fbc->lock);
922

923
	if (!multiple_pipes_ok(crtc, plane_state)) {
924
		fbc->no_fbc_reason = "more than one pipe active";
925
		goto deactivate;
926 927
	}

928
	if (!fbc->enabled || fbc->crtc != crtc)
929
		goto unlock;
930

931
	intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
932

933
deactivate:
934
	intel_fbc_deactivate(dev_priv);
935 936
unlock:
	mutex_unlock(&fbc->lock);
937 938
}

939
static void __intel_fbc_post_update(struct intel_crtc *crtc)
940
{
941
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
942 943 944 945 946 947 948 949 950 951 952 953
	struct intel_fbc *fbc = &dev_priv->fbc;
	struct intel_fbc_reg_params old_params;

	WARN_ON(!mutex_is_locked(&fbc->lock));

	if (!fbc->enabled || fbc->crtc != crtc)
		return;

	if (!intel_fbc_can_activate(crtc)) {
		WARN_ON(fbc->active);
		return;
	}
954

955 956
	old_params = fbc->params;
	intel_fbc_get_reg_params(crtc, &fbc->params);
957

958 959 960 961 962
	/* If the scanout has not changed, don't modify the FBC settings.
	 * Note that we make the fundamental assumption that the fb->obj
	 * cannot be unpinned (and have its GTT offset and fence revoked)
	 * without first being decoupled from the scanout and FBC disabled.
	 */
963 964
	if (fbc->active &&
	    intel_fbc_reg_params_equal(&old_params, &fbc->params))
965 966
		return;

967
	intel_fbc_deactivate(dev_priv);
968
	intel_fbc_schedule_activation(crtc);
969
	fbc->no_fbc_reason = "FBC enabled (active or scheduled)";
P
Paulo Zanoni 已提交
970 971
}

972
void intel_fbc_post_update(struct intel_crtc *crtc)
P
Paulo Zanoni 已提交
973
{
974
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
975
	struct intel_fbc *fbc = &dev_priv->fbc;
976

P
Paulo Zanoni 已提交
977
	if (!fbc_supported(dev_priv))
978 979
		return;

980
	mutex_lock(&fbc->lock);
981
	__intel_fbc_post_update(crtc);
982
	mutex_unlock(&fbc->lock);
983 984
}

985 986 987 988 989 990 991 992
static unsigned int intel_fbc_get_frontbuffer_bit(struct intel_fbc *fbc)
{
	if (fbc->enabled)
		return to_intel_plane(fbc->crtc->base.primary)->frontbuffer_bit;
	else
		return fbc->possible_framebuffer_bits;
}

993 994 995 996
void intel_fbc_invalidate(struct drm_i915_private *dev_priv,
			  unsigned int frontbuffer_bits,
			  enum fb_op_origin origin)
{
997
	struct intel_fbc *fbc = &dev_priv->fbc;
998

P
Paulo Zanoni 已提交
999
	if (!fbc_supported(dev_priv))
1000 1001
		return;

1002
	if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
1003 1004
		return;

1005
	mutex_lock(&fbc->lock);
P
Paulo Zanoni 已提交
1006

1007
	fbc->busy_bits |= intel_fbc_get_frontbuffer_bit(fbc) & frontbuffer_bits;
1008

1009
	if (fbc->enabled && fbc->busy_bits)
1010
		intel_fbc_deactivate(dev_priv);
P
Paulo Zanoni 已提交
1011

1012
	mutex_unlock(&fbc->lock);
1013 1014 1015
}

void intel_fbc_flush(struct drm_i915_private *dev_priv,
1016
		     unsigned int frontbuffer_bits, enum fb_op_origin origin)
1017
{
1018 1019
	struct intel_fbc *fbc = &dev_priv->fbc;

P
Paulo Zanoni 已提交
1020
	if (!fbc_supported(dev_priv))
1021 1022
		return;

1023
	mutex_lock(&fbc->lock);
1024

1025
	fbc->busy_bits &= ~frontbuffer_bits;
1026

1027 1028 1029
	if (origin == ORIGIN_GTT || origin == ORIGIN_FLIP)
		goto out;

1030 1031
	if (!fbc->busy_bits && fbc->enabled &&
	    (frontbuffer_bits & intel_fbc_get_frontbuffer_bit(fbc))) {
1032
		if (fbc->active)
1033
			intel_fbc_recompress(dev_priv);
1034
		else
1035
			__intel_fbc_post_update(fbc->crtc);
1036
	}
P
Paulo Zanoni 已提交
1037

1038
out:
1039
	mutex_unlock(&fbc->lock);
1040 1041
}

1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059
/**
 * intel_fbc_choose_crtc - select a CRTC to enable FBC on
 * @dev_priv: i915 device instance
 * @state: the atomic state structure
 *
 * This function looks at the proposed state for CRTCs and planes, then chooses
 * which pipe is going to have FBC by setting intel_crtc_state->enable_fbc to
 * true.
 *
 * Later, intel_fbc_enable is going to look for state->enable_fbc and then maybe
 * enable FBC for the chosen CRTC. If it does, it will set dev_priv->fbc.crtc.
 */
void intel_fbc_choose_crtc(struct drm_i915_private *dev_priv,
			   struct drm_atomic_state *state)
{
	struct intel_fbc *fbc = &dev_priv->fbc;
	struct drm_plane *plane;
	struct drm_plane_state *plane_state;
1060
	bool crtc_chosen = false;
1061
	int i;
1062 1063 1064

	mutex_lock(&fbc->lock);

1065 1066 1067
	/* Does this atomic commit involve the CRTC currently tied to FBC? */
	if (fbc->crtc &&
	    !drm_atomic_get_existing_crtc_state(state, &fbc->crtc->base))
1068 1069
		goto out;

1070 1071 1072
	if (!intel_fbc_can_enable(dev_priv))
		goto out;

1073 1074 1075 1076 1077 1078 1079
	/* Simply choose the first CRTC that is compatible and has a visible
	 * plane. We could go for fancier schemes such as checking the plane
	 * size, but this would just affect the few platforms that don't tie FBC
	 * to pipe or plane A. */
	for_each_plane_in_state(state, plane, plane_state, i) {
		struct intel_plane_state *intel_plane_state =
			to_intel_plane_state(plane_state);
1080
		struct intel_crtc_state *intel_crtc_state;
1081
		struct intel_crtc *crtc = to_intel_crtc(plane_state->crtc);
1082

1083
		if (!intel_plane_state->base.visible)
1084 1085
			continue;

1086 1087 1088 1089
		if (fbc_on_pipe_a_only(dev_priv) && crtc->pipe != PIPE_A)
			continue;

		if (fbc_on_plane_a_only(dev_priv) && crtc->plane != PLANE_A)
1090 1091
			continue;

1092
		intel_crtc_state = to_intel_crtc_state(
1093
			drm_atomic_get_existing_crtc_state(state, &crtc->base));
1094

1095
		intel_crtc_state->enable_fbc = true;
1096
		crtc_chosen = true;
1097
		break;
1098 1099
	}

1100 1101 1102
	if (!crtc_chosen)
		fbc->no_fbc_reason = "no suitable CRTC for FBC";

1103 1104 1105 1106
out:
	mutex_unlock(&fbc->lock);
}

1107 1108 1109
/**
 * intel_fbc_enable: tries to enable FBC on the CRTC
 * @crtc: the CRTC
1110 1111
 * @crtc_state: corresponding &drm_crtc_state for @crtc
 * @plane_state: corresponding &drm_plane_state for the primary plane of @crtc
1112
 *
1113
 * This function checks if the given CRTC was chosen for FBC, then enables it if
1114 1115 1116
 * possible. Notice that it doesn't activate FBC. It is valid to call
 * intel_fbc_enable multiple times for the same pipe without an
 * intel_fbc_disable in the middle, as long as it is deactivated.
1117
 */
1118 1119 1120
void intel_fbc_enable(struct intel_crtc *crtc,
		      struct intel_crtc_state *crtc_state,
		      struct intel_plane_state *plane_state)
1121
{
1122
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1123
	struct intel_fbc *fbc = &dev_priv->fbc;
1124 1125 1126 1127

	if (!fbc_supported(dev_priv))
		return;

1128
	mutex_lock(&fbc->lock);
1129

1130
	if (fbc->enabled) {
1131 1132
		WARN_ON(fbc->crtc == NULL);
		if (fbc->crtc == crtc) {
1133
			WARN_ON(!crtc_state->enable_fbc);
1134 1135
			WARN_ON(fbc->active);
		}
1136 1137 1138
		goto out;
	}

1139
	if (!crtc_state->enable_fbc)
1140 1141
		goto out;

1142 1143
	WARN_ON(fbc->active);
	WARN_ON(fbc->crtc != NULL);
1144

1145
	intel_fbc_update_state_cache(crtc, crtc_state, plane_state);
1146
	if (intel_fbc_alloc_cfb(crtc)) {
1147
		fbc->no_fbc_reason = "not enough stolen memory";
1148 1149 1150
		goto out;
	}

1151
	DRM_DEBUG_KMS("Enabling FBC on pipe %c\n", pipe_name(crtc->pipe));
1152
	fbc->no_fbc_reason = "FBC enabled but not active yet\n";
1153

1154 1155
	fbc->enabled = true;
	fbc->crtc = crtc;
1156
out:
1157
	mutex_unlock(&fbc->lock);
1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168
}

/**
 * __intel_fbc_disable - disable FBC
 * @dev_priv: i915 device instance
 *
 * This is the low level function that actually disables FBC. Callers should
 * grab the FBC lock.
 */
static void __intel_fbc_disable(struct drm_i915_private *dev_priv)
{
1169 1170
	struct intel_fbc *fbc = &dev_priv->fbc;
	struct intel_crtc *crtc = fbc->crtc;
1171

1172 1173 1174
	WARN_ON(!mutex_is_locked(&fbc->lock));
	WARN_ON(!fbc->enabled);
	WARN_ON(fbc->active);
1175
	WARN_ON(crtc->active);
1176 1177 1178

	DRM_DEBUG_KMS("Disabling FBC on pipe %c\n", pipe_name(crtc->pipe));

1179 1180
	__intel_fbc_cleanup_cfb(dev_priv);

1181 1182
	fbc->enabled = false;
	fbc->crtc = NULL;
1183 1184 1185
}

/**
1186
 * intel_fbc_disable - disable FBC if it's associated with crtc
1187 1188 1189 1190
 * @crtc: the CRTC
 *
 * This function disables FBC if it's associated with the provided CRTC.
 */
1191
void intel_fbc_disable(struct intel_crtc *crtc)
1192
{
1193
	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1194
	struct intel_fbc *fbc = &dev_priv->fbc;
1195 1196 1197 1198

	if (!fbc_supported(dev_priv))
		return;

1199
	mutex_lock(&fbc->lock);
1200
	if (fbc->crtc == crtc)
1201
		__intel_fbc_disable(dev_priv);
1202
	mutex_unlock(&fbc->lock);
1203 1204

	cancel_work_sync(&fbc->work.work);
1205 1206 1207
}

/**
1208
 * intel_fbc_global_disable - globally disable FBC
1209 1210 1211 1212
 * @dev_priv: i915 device instance
 *
 * This function disables FBC regardless of which CRTC is associated with it.
 */
1213
void intel_fbc_global_disable(struct drm_i915_private *dev_priv)
1214
{
1215 1216
	struct intel_fbc *fbc = &dev_priv->fbc;

1217 1218 1219
	if (!fbc_supported(dev_priv))
		return;

1220 1221
	mutex_lock(&fbc->lock);
	if (fbc->enabled)
1222
		__intel_fbc_disable(dev_priv);
1223
	mutex_unlock(&fbc->lock);
1224 1225

	cancel_work_sync(&fbc->work.work);
1226 1227
}

1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280
static void intel_fbc_underrun_work_fn(struct work_struct *work)
{
	struct drm_i915_private *dev_priv =
		container_of(work, struct drm_i915_private, fbc.underrun_work);
	struct intel_fbc *fbc = &dev_priv->fbc;

	mutex_lock(&fbc->lock);

	/* Maybe we were scheduled twice. */
	if (fbc->underrun_detected)
		goto out;

	DRM_DEBUG_KMS("Disabling FBC due to FIFO underrun.\n");
	fbc->underrun_detected = true;

	intel_fbc_deactivate(dev_priv);
out:
	mutex_unlock(&fbc->lock);
}

/**
 * intel_fbc_handle_fifo_underrun_irq - disable FBC when we get a FIFO underrun
 * @dev_priv: i915 device instance
 *
 * Without FBC, most underruns are harmless and don't really cause too many
 * problems, except for an annoying message on dmesg. With FBC, underruns can
 * become black screens or even worse, especially when paired with bad
 * watermarks. So in order for us to be on the safe side, completely disable FBC
 * in case we ever detect a FIFO underrun on any pipe. An underrun on any pipe
 * already suggests that watermarks may be bad, so try to be as safe as
 * possible.
 *
 * This function is called from the IRQ handler.
 */
void intel_fbc_handle_fifo_underrun_irq(struct drm_i915_private *dev_priv)
{
	struct intel_fbc *fbc = &dev_priv->fbc;

	if (!fbc_supported(dev_priv))
		return;

	/* There's no guarantee that underrun_detected won't be set to true
	 * right after this check and before the work is scheduled, but that's
	 * not a problem since we'll check it again under the work function
	 * while FBC is locked. This check here is just to prevent us from
	 * unnecessarily scheduling the work, and it relies on the fact that we
	 * never switch underrun_detect back to false after it's true. */
	if (READ_ONCE(fbc->underrun_detected))
		return;

	schedule_work(&fbc->underrun_work);
}

1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296
/**
 * intel_fbc_init_pipe_state - initialize FBC's CRTC visibility tracking
 * @dev_priv: i915 device instance
 *
 * The FBC code needs to track CRTC visibility since the older platforms can't
 * have FBC enabled while multiple pipes are used. This function does the
 * initial setup at driver load to make sure FBC is matching the real hardware.
 */
void intel_fbc_init_pipe_state(struct drm_i915_private *dev_priv)
{
	struct intel_crtc *crtc;

	/* Don't even bother tracking anything if we don't need. */
	if (!no_fbc_on_multiple_pipes(dev_priv))
		return;

1297
	for_each_intel_crtc(&dev_priv->drm, crtc)
1298
		if (intel_crtc_active(crtc) &&
1299
		    to_intel_plane_state(crtc->base.primary->state)->base.visible)
1300 1301 1302
			dev_priv->fbc.visible_pipes_mask |= (1 << crtc->pipe);
}

1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316
/*
 * The DDX driver changes its behavior depending on the value it reads from
 * i915.enable_fbc, so sanitize it by translating the default value into either
 * 0 or 1 in order to allow it to know what's going on.
 *
 * Notice that this is done at driver initialization and we still allow user
 * space to change the value during runtime without sanitizing it again. IGT
 * relies on being able to change i915.enable_fbc at runtime.
 */
static int intel_sanitize_fbc_option(struct drm_i915_private *dev_priv)
{
	if (i915.enable_fbc >= 0)
		return !!i915.enable_fbc;

1317 1318 1319
	if (!HAS_FBC(dev_priv))
		return 0;

1320 1321 1322 1323 1324 1325
	if (IS_BROADWELL(dev_priv))
		return 1;

	return 0;
}

1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339
static bool need_fbc_vtd_wa(struct drm_i915_private *dev_priv)
{
#ifdef CONFIG_INTEL_IOMMU
	/* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */
	if (intel_iommu_gfx_mapped &&
	    (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))) {
		DRM_INFO("Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n");
		return true;
	}
#endif

	return false;
}

R
Rodrigo Vivi 已提交
1340 1341 1342 1343 1344 1345
/**
 * intel_fbc_init - Initialize FBC
 * @dev_priv: the i915 device
 *
 * This function might be called during PM init process.
 */
1346 1347
void intel_fbc_init(struct drm_i915_private *dev_priv)
{
1348
	struct intel_fbc *fbc = &dev_priv->fbc;
1349 1350
	enum pipe pipe;

1351
	INIT_WORK(&fbc->work.work, intel_fbc_work_fn);
1352
	INIT_WORK(&fbc->underrun_work, intel_fbc_underrun_work_fn);
1353 1354 1355 1356
	mutex_init(&fbc->lock);
	fbc->enabled = false;
	fbc->active = false;
	fbc->work.scheduled = false;
P
Paulo Zanoni 已提交
1357

1358 1359 1360
	if (need_fbc_vtd_wa(dev_priv))
		mkwrite_device_info(dev_priv)->has_fbc = false;

1361 1362 1363
	i915.enable_fbc = intel_sanitize_fbc_option(dev_priv);
	DRM_DEBUG_KMS("Sanitized enable_fbc value: %d\n", i915.enable_fbc);

1364
	if (!HAS_FBC(dev_priv)) {
1365
		fbc->no_fbc_reason = "unsupported by this chipset";
1366 1367 1368
		return;
	}

1369
	for_each_pipe(dev_priv, pipe) {
1370
		fbc->possible_framebuffer_bits |=
1371 1372
				INTEL_FRONTBUFFER_PRIMARY(pipe);

1373
		if (fbc_on_pipe_a_only(dev_priv))
1374 1375 1376
			break;
	}

1377
	/* This value was pulled out of someone's hat */
1378
	if (INTEL_GEN(dev_priv) <= 4 && !IS_GM45(dev_priv))
1379 1380
		I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT);

1381
	/* We still don't have any sort of hardware state readout for FBC, so
1382 1383
	 * deactivate it in case the BIOS activated it to make sure software
	 * matches the hardware state. */
1384 1385
	if (intel_fbc_hw_is_active(dev_priv))
		intel_fbc_hw_deactivate(dev_priv);
1386
}