exynos5420-arndale-octa.dts

/*
 * Samsung's Exynos5420 based Arndale Octa board device tree source
 *
 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

/dts-v1/;
#include "exynos5420.dtsi"

/ {
	model = "Insignal Arndale Octa evaluation board based on EXYNOS5420";
	compatible = "insignal,arndale-octa", "samsung,exynos5420";

	memory {
		reg = <0x20000000 0x80000000>;
	};

	chosen {
		bootargs = "console=ttySAC3,115200";
	};

	fixed-rate-clocks {
		oscclk {
			compatible = "samsung,exynos5420-oscclk";
			clock-frequency = <24000000>;
		};
	};

	rtc@101E0000 {
		status = "okay";
	};

	mmc@12200000 {
		status = "okay";
		broken-cd;
		supports-highspeed;
		card-detect-delay = <200>;
		samsung,dw-mshc-ciu-div = <3>;
		samsung,dw-mshc-sdr-timing = <0 4>;
		samsung,dw-mshc-ddr-timing = <0 2>;
		pinctrl-names = "default";
		pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4 &sd0_bus8>;

		slot@0 {
			reg = <0>;
			bus-width = <8>;
		};
	};

	mmc@12220000 {
		status = "okay";
		supports-highspeed;
		card-detect-delay = <200>;
		samsung,dw-mshc-ciu-div = <3>;
		samsung,dw-mshc-sdr-timing = <2 3>;
		samsung,dw-mshc-ddr-timing = <1 2>;
		pinctrl-names = "default";
		pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;

		slot@0 {
			reg = <0>;
			bus-width = <4>;
		};
	};
};