arm-smmu.c 56.5 KB
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/*
 * IOMMU API for ARM architected SMMU implementations.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Copyright (C) 2013 ARM Limited
 *
 * Author: Will Deacon <will.deacon@arm.com>
 *
 * This driver currently supports:
 *	- SMMUv1 and v2 implementations
 *	- Stream-matching and stream-indexing
 *	- v7/v8 long-descriptor format
 *	- Non-secure access to the SMMU
 *	- Context fault reporting
 */

#define pr_fmt(fmt) "arm-smmu: " fmt

#include <linux/delay.h>
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#include <linux/dma-iommu.h>
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#include <linux/dma-mapping.h>
#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/io.h>
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#include <linux/io-64-nonatomic-hi-lo.h>
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#include <linux/iommu.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
#include <linux/slab.h>
#include <linux/spinlock.h>

#include <linux/amba/bus.h>

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#include "io-pgtable.h"
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/* Maximum number of stream IDs assigned to a single device */
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#define MAX_MASTER_STREAMIDS		128
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/* Maximum number of context banks per SMMU */
#define ARM_SMMU_MAX_CBS		128

/* Maximum number of mapping groups per SMMU */
#define ARM_SMMU_MAX_SMRS		128

/* SMMU global address space */
#define ARM_SMMU_GR0(smmu)		((smmu)->base)
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#define ARM_SMMU_GR1(smmu)		((smmu)->base + (1 << (smmu)->pgshift))
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/*
 * SMMU global address space with conditional offset to access secure
 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
 * nsGFSYNR0: 0x450)
 */
#define ARM_SMMU_GR0_NS(smmu)						\
	((smmu)->base +							\
		((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS)	\
			? 0x400 : 0))

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/*
 * Some 64-bit registers only make sense to write atomically, but in such
 * cases all the data relevant to AArch32 formats lies within the lower word,
 * therefore this actually makes more sense than it might first appear.
 */
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#ifdef CONFIG_64BIT
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#define smmu_write_atomic_lq		writeq_relaxed
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#else
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#define smmu_write_atomic_lq		writel_relaxed
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#endif

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/* Configuration registers */
#define ARM_SMMU_GR0_sCR0		0x0
#define sCR0_CLIENTPD			(1 << 0)
#define sCR0_GFRE			(1 << 1)
#define sCR0_GFIE			(1 << 2)
#define sCR0_GCFGFRE			(1 << 4)
#define sCR0_GCFGFIE			(1 << 5)
#define sCR0_USFCFG			(1 << 10)
#define sCR0_VMIDPNE			(1 << 11)
#define sCR0_PTM			(1 << 12)
#define sCR0_FB				(1 << 13)
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#define sCR0_VMID16EN			(1 << 31)
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#define sCR0_BSU_SHIFT			14
#define sCR0_BSU_MASK			0x3

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/* Auxiliary Configuration register */
#define ARM_SMMU_GR0_sACR		0x10

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/* Identification registers */
#define ARM_SMMU_GR0_ID0		0x20
#define ARM_SMMU_GR0_ID1		0x24
#define ARM_SMMU_GR0_ID2		0x28
#define ARM_SMMU_GR0_ID3		0x2c
#define ARM_SMMU_GR0_ID4		0x30
#define ARM_SMMU_GR0_ID5		0x34
#define ARM_SMMU_GR0_ID6		0x38
#define ARM_SMMU_GR0_ID7		0x3c
#define ARM_SMMU_GR0_sGFSR		0x48
#define ARM_SMMU_GR0_sGFSYNR0		0x50
#define ARM_SMMU_GR0_sGFSYNR1		0x54
#define ARM_SMMU_GR0_sGFSYNR2		0x58

#define ID0_S1TS			(1 << 30)
#define ID0_S2TS			(1 << 29)
#define ID0_NTS				(1 << 28)
#define ID0_SMS				(1 << 27)
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#define ID0_ATOSNS			(1 << 26)
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#define ID0_PTFS_NO_AARCH32		(1 << 25)
#define ID0_PTFS_NO_AARCH32S		(1 << 24)
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#define ID0_CTTW			(1 << 14)
#define ID0_NUMIRPT_SHIFT		16
#define ID0_NUMIRPT_MASK		0xff
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#define ID0_NUMSIDB_SHIFT		9
#define ID0_NUMSIDB_MASK		0xf
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#define ID0_NUMSMRG_SHIFT		0
#define ID0_NUMSMRG_MASK		0xff

#define ID1_PAGESIZE			(1 << 31)
#define ID1_NUMPAGENDXB_SHIFT		28
#define ID1_NUMPAGENDXB_MASK		7
#define ID1_NUMS2CB_SHIFT		16
#define ID1_NUMS2CB_MASK		0xff
#define ID1_NUMCB_SHIFT			0
#define ID1_NUMCB_MASK			0xff

#define ID2_OAS_SHIFT			4
#define ID2_OAS_MASK			0xf
#define ID2_IAS_SHIFT			0
#define ID2_IAS_MASK			0xf
#define ID2_UBS_SHIFT			8
#define ID2_UBS_MASK			0xf
#define ID2_PTFS_4K			(1 << 12)
#define ID2_PTFS_16K			(1 << 13)
#define ID2_PTFS_64K			(1 << 14)
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#define ID2_VMID16			(1 << 15)
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#define ID7_MAJOR_SHIFT			4
#define ID7_MAJOR_MASK			0xf
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/* Global TLB invalidation */
#define ARM_SMMU_GR0_TLBIVMID		0x64
#define ARM_SMMU_GR0_TLBIALLNSNH	0x68
#define ARM_SMMU_GR0_TLBIALLH		0x6c
#define ARM_SMMU_GR0_sTLBGSYNC		0x70
#define ARM_SMMU_GR0_sTLBGSTATUS	0x74
#define sTLBGSTATUS_GSACTIVE		(1 << 0)
#define TLB_LOOP_TIMEOUT		1000000	/* 1s! */

/* Stream mapping registers */
#define ARM_SMMU_GR0_SMR(n)		(0x800 + ((n) << 2))
#define SMR_VALID			(1 << 31)
#define SMR_MASK_SHIFT			16
#define SMR_MASK_MASK			0x7fff
#define SMR_ID_SHIFT			0
#define SMR_ID_MASK			0x7fff

#define ARM_SMMU_GR0_S2CR(n)		(0xc00 + ((n) << 2))
#define S2CR_CBNDX_SHIFT		0
#define S2CR_CBNDX_MASK			0xff
#define S2CR_TYPE_SHIFT			16
#define S2CR_TYPE_MASK			0x3
#define S2CR_TYPE_TRANS			(0 << S2CR_TYPE_SHIFT)
#define S2CR_TYPE_BYPASS		(1 << S2CR_TYPE_SHIFT)
#define S2CR_TYPE_FAULT			(2 << S2CR_TYPE_SHIFT)

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#define S2CR_PRIVCFG_SHIFT		24
#define S2CR_PRIVCFG_UNPRIV		(2 << S2CR_PRIVCFG_SHIFT)

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/* Context bank attribute registers */
#define ARM_SMMU_GR1_CBAR(n)		(0x0 + ((n) << 2))
#define CBAR_VMID_SHIFT			0
#define CBAR_VMID_MASK			0xff
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#define CBAR_S1_BPSHCFG_SHIFT		8
#define CBAR_S1_BPSHCFG_MASK		3
#define CBAR_S1_BPSHCFG_NSH		3
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#define CBAR_S1_MEMATTR_SHIFT		12
#define CBAR_S1_MEMATTR_MASK		0xf
#define CBAR_S1_MEMATTR_WB		0xf
#define CBAR_TYPE_SHIFT			16
#define CBAR_TYPE_MASK			0x3
#define CBAR_TYPE_S2_TRANS		(0 << CBAR_TYPE_SHIFT)
#define CBAR_TYPE_S1_TRANS_S2_BYPASS	(1 << CBAR_TYPE_SHIFT)
#define CBAR_TYPE_S1_TRANS_S2_FAULT	(2 << CBAR_TYPE_SHIFT)
#define CBAR_TYPE_S1_TRANS_S2_TRANS	(3 << CBAR_TYPE_SHIFT)
#define CBAR_IRPTNDX_SHIFT		24
#define CBAR_IRPTNDX_MASK		0xff

#define ARM_SMMU_GR1_CBA2R(n)		(0x800 + ((n) << 2))
#define CBA2R_RW64_32BIT		(0 << 0)
#define CBA2R_RW64_64BIT		(1 << 0)
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#define CBA2R_VMID_SHIFT		16
#define CBA2R_VMID_MASK			0xffff
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/* Translation context bank */
#define ARM_SMMU_CB_BASE(smmu)		((smmu)->base + ((smmu)->size >> 1))
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#define ARM_SMMU_CB(smmu, n)		((n) * (1 << (smmu)->pgshift))
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#define ARM_SMMU_CB_SCTLR		0x0
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#define ARM_SMMU_CB_ACTLR		0x4
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#define ARM_SMMU_CB_RESUME		0x8
#define ARM_SMMU_CB_TTBCR2		0x10
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#define ARM_SMMU_CB_TTBR0		0x20
#define ARM_SMMU_CB_TTBR1		0x28
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#define ARM_SMMU_CB_TTBCR		0x30
#define ARM_SMMU_CB_S1_MAIR0		0x38
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#define ARM_SMMU_CB_S1_MAIR1		0x3c
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#define ARM_SMMU_CB_PAR			0x50
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#define ARM_SMMU_CB_FSR			0x58
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#define ARM_SMMU_CB_FAR			0x60
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#define ARM_SMMU_CB_FSYNR0		0x68
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#define ARM_SMMU_CB_S1_TLBIVA		0x600
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#define ARM_SMMU_CB_S1_TLBIASID		0x610
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#define ARM_SMMU_CB_S1_TLBIVAL		0x620
#define ARM_SMMU_CB_S2_TLBIIPAS2	0x630
#define ARM_SMMU_CB_S2_TLBIIPAS2L	0x638
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#define ARM_SMMU_CB_ATS1PR		0x800
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#define ARM_SMMU_CB_ATSR		0x8f0
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#define SCTLR_S1_ASIDPNE		(1 << 12)
#define SCTLR_CFCFG			(1 << 7)
#define SCTLR_CFIE			(1 << 6)
#define SCTLR_CFRE			(1 << 5)
#define SCTLR_E				(1 << 4)
#define SCTLR_AFE			(1 << 2)
#define SCTLR_TRE			(1 << 1)
#define SCTLR_M				(1 << 0)
#define SCTLR_EAE_SBOP			(SCTLR_AFE | SCTLR_TRE)

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#define ARM_MMU500_ACTLR_CPRE		(1 << 1)

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#define ARM_MMU500_ACR_CACHE_LOCK	(1 << 26)

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#define CB_PAR_F			(1 << 0)

#define ATSR_ACTIVE			(1 << 0)

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#define RESUME_RETRY			(0 << 0)
#define RESUME_TERMINATE		(1 << 0)

#define TTBCR2_SEP_SHIFT		15
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#define TTBCR2_SEP_UPSTREAM		(0x7 << TTBCR2_SEP_SHIFT)
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#define TTBRn_ASID_SHIFT		48
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#define FSR_MULTI			(1 << 31)
#define FSR_SS				(1 << 30)
#define FSR_UUT				(1 << 8)
#define FSR_ASF				(1 << 7)
#define FSR_TLBLKF			(1 << 6)
#define FSR_TLBMCF			(1 << 5)
#define FSR_EF				(1 << 4)
#define FSR_PF				(1 << 3)
#define FSR_AFF				(1 << 2)
#define FSR_TF				(1 << 1)

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#define FSR_IGN				(FSR_AFF | FSR_ASF | \
					 FSR_TLBMCF | FSR_TLBLKF)
#define FSR_FAULT			(FSR_MULTI | FSR_SS | FSR_UUT | \
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					 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
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#define FSYNR0_WNR			(1 << 4)

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static int force_stage;
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module_param(force_stage, int, S_IRUGO);
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MODULE_PARM_DESC(force_stage,
	"Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
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static bool disable_bypass;
module_param(disable_bypass, bool, S_IRUGO);
MODULE_PARM_DESC(disable_bypass,
	"Disable bypass streams such that incoming transactions from devices that are not attached to an iommu domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
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enum arm_smmu_arch_version {
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	ARM_SMMU_V1,
	ARM_SMMU_V1_64K,
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	ARM_SMMU_V2,
};

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enum arm_smmu_implementation {
	GENERIC_SMMU,
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	ARM_MMU500,
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	CAVIUM_SMMUV2,
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};

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struct arm_smmu_smr {
	u8				idx;
	u16				mask;
	u16				id;
};

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struct arm_smmu_master_cfg {
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	int				num_streamids;
	u16				streamids[MAX_MASTER_STREAMIDS];
	struct arm_smmu_smr		*smrs;
};

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struct arm_smmu_master {
	struct device_node		*of_node;
	struct rb_node			node;
	struct arm_smmu_master_cfg	cfg;
};

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struct arm_smmu_device {
	struct device			*dev;

	void __iomem			*base;
	unsigned long			size;
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	unsigned long			pgshift;
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#define ARM_SMMU_FEAT_COHERENT_WALK	(1 << 0)
#define ARM_SMMU_FEAT_STREAM_MATCH	(1 << 1)
#define ARM_SMMU_FEAT_TRANS_S1		(1 << 2)
#define ARM_SMMU_FEAT_TRANS_S2		(1 << 3)
#define ARM_SMMU_FEAT_TRANS_NESTED	(1 << 4)
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#define ARM_SMMU_FEAT_TRANS_OPS		(1 << 5)
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#define ARM_SMMU_FEAT_VMID16		(1 << 6)
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#define ARM_SMMU_FEAT_FMT_AARCH64_4K	(1 << 7)
#define ARM_SMMU_FEAT_FMT_AARCH64_16K	(1 << 8)
#define ARM_SMMU_FEAT_FMT_AARCH64_64K	(1 << 9)
#define ARM_SMMU_FEAT_FMT_AARCH32_L	(1 << 10)
#define ARM_SMMU_FEAT_FMT_AARCH32_S	(1 << 11)
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	u32				features;
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#define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
	u32				options;
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	enum arm_smmu_arch_version	version;
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	enum arm_smmu_implementation	model;
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	u32				num_context_banks;
	u32				num_s2_context_banks;
	DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
	atomic_t			irptndx;

	u32				num_mapping_groups;
	DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);

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	unsigned long			va_size;
	unsigned long			ipa_size;
	unsigned long			pa_size;
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	unsigned long			pgsize_bitmap;
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	u32				num_global_irqs;
	u32				num_context_irqs;
	unsigned int			*irqs;

	struct list_head		list;
	struct rb_root			masters;
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	u32				cavium_id_base; /* Specific to Cavium */
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};

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enum arm_smmu_context_fmt {
	ARM_SMMU_CTX_FMT_NONE,
	ARM_SMMU_CTX_FMT_AARCH64,
	ARM_SMMU_CTX_FMT_AARCH32_L,
	ARM_SMMU_CTX_FMT_AARCH32_S,
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};

struct arm_smmu_cfg {
	u8				cbndx;
	u8				irptndx;
	u32				cbar;
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	enum arm_smmu_context_fmt	fmt;
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};
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#define INVALID_IRPTNDX			0xff
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#define ARM_SMMU_CB_ASID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx)
#define ARM_SMMU_CB_VMID(smmu, cfg) ((u16)(smmu)->cavium_id_base + (cfg)->cbndx + 1)
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enum arm_smmu_domain_stage {
	ARM_SMMU_DOMAIN_S1 = 0,
	ARM_SMMU_DOMAIN_S2,
	ARM_SMMU_DOMAIN_NESTED,
};

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struct arm_smmu_domain {
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	struct arm_smmu_device		*smmu;
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	struct io_pgtable_ops		*pgtbl_ops;
	spinlock_t			pgtbl_lock;
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	struct arm_smmu_cfg		cfg;
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	enum arm_smmu_domain_stage	stage;
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	struct mutex			init_mutex; /* Protects smmu pointer */
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	struct iommu_domain		domain;
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};

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struct arm_smmu_phandle_args {
	struct device_node *np;
	int args_count;
	uint32_t args[MAX_MASTER_STREAMIDS];
};

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static DEFINE_SPINLOCK(arm_smmu_devices_lock);
static LIST_HEAD(arm_smmu_devices);

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struct arm_smmu_option_prop {
	u32 opt;
	const char *prop;
};

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static atomic_t cavium_smmu_context_count = ATOMIC_INIT(0);

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static struct arm_smmu_option_prop arm_smmu_options[] = {
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	{ ARM_SMMU_OPT_SECURE_CFG_ACCESS, "calxeda,smmu-secure-config-access" },
	{ 0, NULL},
};

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static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
{
	return container_of(dom, struct arm_smmu_domain, domain);
}

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static void parse_driver_options(struct arm_smmu_device *smmu)
{
	int i = 0;
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	do {
		if (of_property_read_bool(smmu->dev->of_node,
						arm_smmu_options[i].prop)) {
			smmu->options |= arm_smmu_options[i].opt;
			dev_notice(smmu->dev, "option %s\n",
				arm_smmu_options[i].prop);
		}
	} while (arm_smmu_options[++i].opt);
}

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static struct device_node *dev_get_dev_node(struct device *dev)
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{
	if (dev_is_pci(dev)) {
		struct pci_bus *bus = to_pci_dev(dev)->bus;
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		while (!pci_is_root_bus(bus))
			bus = bus->parent;
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		return bus->bridge->parent->of_node;
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	}

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	return dev->of_node;
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}

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static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
						struct device_node *dev_node)
{
	struct rb_node *node = smmu->masters.rb_node;

	while (node) {
		struct arm_smmu_master *master;
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		master = container_of(node, struct arm_smmu_master, node);

		if (dev_node < master->of_node)
			node = node->rb_left;
		else if (dev_node > master->of_node)
			node = node->rb_right;
		else
			return master;
	}

	return NULL;
}

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static struct arm_smmu_master_cfg *
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find_smmu_master_cfg(struct device *dev)
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{
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	struct arm_smmu_master_cfg *cfg = NULL;
	struct iommu_group *group = iommu_group_get(dev);
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	if (group) {
		cfg = iommu_group_get_iommudata(group);
		iommu_group_put(group);
	}
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	return cfg;
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}

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static int insert_smmu_master(struct arm_smmu_device *smmu,
			      struct arm_smmu_master *master)
{
	struct rb_node **new, *parent;

	new = &smmu->masters.rb_node;
	parent = NULL;
	while (*new) {
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		struct arm_smmu_master *this
			= container_of(*new, struct arm_smmu_master, node);
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		parent = *new;
		if (master->of_node < this->of_node)
			new = &((*new)->rb_left);
		else if (master->of_node > this->of_node)
			new = &((*new)->rb_right);
		else
			return -EEXIST;
	}

	rb_link_node(&master->node, parent, new);
	rb_insert_color(&master->node, &smmu->masters);
	return 0;
}

static int register_smmu_master(struct arm_smmu_device *smmu,
				struct device *dev,
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				struct arm_smmu_phandle_args *masterspec)
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{
	int i;
	struct arm_smmu_master *master;

	master = find_smmu_master(smmu, masterspec->np);
	if (master) {
		dev_err(dev,
			"rejecting multiple registrations for master device %s\n",
			masterspec->np->name);
		return -EBUSY;
	}

	if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
		dev_err(dev,
			"reached maximum number (%d) of stream IDs for master device %s\n",
			MAX_MASTER_STREAMIDS, masterspec->np->name);
		return -ENOSPC;
	}

	master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
	if (!master)
		return -ENOMEM;

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	master->of_node			= masterspec->np;
	master->cfg.num_streamids	= masterspec->args_count;
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	for (i = 0; i < master->cfg.num_streamids; ++i) {
		u16 streamid = masterspec->args[i];
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		if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) &&
		     (streamid >= smmu->num_mapping_groups)) {
			dev_err(dev,
				"stream ID for master device %s greater than maximum allowed (%d)\n",
				masterspec->np->name, smmu->num_mapping_groups);
			return -ERANGE;
		}
		master->cfg.streamids[i] = streamid;
	}
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	return insert_smmu_master(smmu, master);
}

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static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
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{
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	struct arm_smmu_device *smmu;
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	struct arm_smmu_master *master = NULL;
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	struct device_node *dev_node = dev_get_dev_node(dev);
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	spin_lock(&arm_smmu_devices_lock);
564
	list_for_each_entry(smmu, &arm_smmu_devices, list) {
565 566 567 568
		master = find_smmu_master(smmu, dev_node);
		if (master)
			break;
	}
569
	spin_unlock(&arm_smmu_devices_lock);
570

571
	return master ? smmu : NULL;
572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592
}

static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
{
	int idx;

	do {
		idx = find_next_zero_bit(map, end, start);
		if (idx == end)
			return -ENOSPC;
	} while (test_and_set_bit(idx, map));

	return idx;
}

static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
{
	clear_bit(idx, map);
}

/* Wait for any pending TLB invalidations to complete */
593
static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610
{
	int count = 0;
	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);

	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
	while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
	       & sTLBGSTATUS_GSACTIVE) {
		cpu_relax();
		if (++count == TLB_LOOP_TIMEOUT) {
			dev_err_ratelimited(smmu->dev,
			"TLB sync timed out -- SMMU may be deadlocked\n");
			return;
		}
		udelay(1);
	}
}

611 612 613 614 615 616 617
static void arm_smmu_tlb_sync(void *cookie)
{
	struct arm_smmu_domain *smmu_domain = cookie;
	__arm_smmu_tlb_sync(smmu_domain->smmu);
}

static void arm_smmu_tlb_inv_context(void *cookie)
618
{
619
	struct arm_smmu_domain *smmu_domain = cookie;
620 621
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_device *smmu = smmu_domain->smmu;
622
	bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
623
	void __iomem *base;
624 625 626

	if (stage1) {
		base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
627
		writel_relaxed(ARM_SMMU_CB_ASID(smmu, cfg),
628
			       base + ARM_SMMU_CB_S1_TLBIASID);
629 630
	} else {
		base = ARM_SMMU_GR0(smmu);
631
		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg),
632
			       base + ARM_SMMU_GR0_TLBIVMID);
633 634
	}

635 636 637 638
	__arm_smmu_tlb_sync(smmu);
}

static void arm_smmu_tlb_inv_range_nosync(unsigned long iova, size_t size,
639
					  size_t granule, bool leaf, void *cookie)
640 641 642 643 644 645 646 647 648 649 650
{
	struct arm_smmu_domain *smmu_domain = cookie;
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_device *smmu = smmu_domain->smmu;
	bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
	void __iomem *reg;

	if (stage1) {
		reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
		reg += leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;

651
		if (cfg->fmt != ARM_SMMU_CTX_FMT_AARCH64) {
652
			iova &= ~12UL;
653
			iova |= ARM_SMMU_CB_ASID(smmu, cfg);
654 655 656 657
			do {
				writel_relaxed(iova, reg);
				iova += granule;
			} while (size -= granule);
658 659
		} else {
			iova >>= 12;
660
			iova |= (u64)ARM_SMMU_CB_ASID(smmu, cfg) << 48;
661 662 663 664
			do {
				writeq_relaxed(iova, reg);
				iova += granule >> 12;
			} while (size -= granule);
665 666 667 668 669
		}
	} else if (smmu->version == ARM_SMMU_V2) {
		reg = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
		reg += leaf ? ARM_SMMU_CB_S2_TLBIIPAS2L :
			      ARM_SMMU_CB_S2_TLBIIPAS2;
670 671
		iova >>= 12;
		do {
672
			smmu_write_atomic_lq(iova, reg);
673 674
			iova += granule >> 12;
		} while (size -= granule);
675 676
	} else {
		reg = ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_TLBIVMID;
677
		writel_relaxed(ARM_SMMU_CB_VMID(smmu, cfg), reg);
678 679 680 681 682 683 684 685 686
	}
}

static struct iommu_gather_ops arm_smmu_gather_ops = {
	.tlb_flush_all	= arm_smmu_tlb_inv_context,
	.tlb_add_flush	= arm_smmu_tlb_inv_range_nosync,
	.tlb_sync	= arm_smmu_tlb_sync,
};

687 688 689
static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
{
	int flags, ret;
690
	u32 fsr, fsynr, resume;
691 692
	unsigned long iova;
	struct iommu_domain *domain = dev;
693
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
694 695
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_device *smmu = smmu_domain->smmu;
696 697
	void __iomem *cb_base;

698
	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
699 700 701 702 703 704 705
	fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);

	if (!(fsr & FSR_FAULT))
		return IRQ_NONE;

	if (fsr & FSR_IGN)
		dev_err_ratelimited(smmu->dev,
706
				    "Unexpected context fault (fsr 0x%x)\n",
707 708 709 710 711
				    fsr);

	fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
	flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;

712
	iova = readq_relaxed(cb_base + ARM_SMMU_CB_FAR);
713 714 715 716
	if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
		ret = IRQ_HANDLED;
		resume = RESUME_RETRY;
	} else {
717 718
		dev_err_ratelimited(smmu->dev,
		    "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
719
		    iova, fsynr, cfg->cbndx);
720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737
		ret = IRQ_NONE;
		resume = RESUME_TERMINATE;
	}

	/* Clear the faulting FSR */
	writel(fsr, cb_base + ARM_SMMU_CB_FSR);

	/* Retry or terminate any stalled transactions */
	if (fsr & FSR_SS)
		writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);

	return ret;
}

static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
{
	u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
	struct arm_smmu_device *smmu = dev;
738
	void __iomem *gr0_base = ARM_SMMU_GR0_NS(smmu);
739 740 741 742 743 744

	gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
	gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
	gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
	gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);

745 746 747
	if (!gfsr)
		return IRQ_NONE;

748 749 750 751 752 753 754
	dev_err_ratelimited(smmu->dev,
		"Unexpected global fault, this could be serious\n");
	dev_err_ratelimited(smmu->dev,
		"\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
		gfsr, gfsynr0, gfsynr1, gfsynr2);

	writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
755
	return IRQ_HANDLED;
756 757
}

758 759
static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain,
				       struct io_pgtable_cfg *pgtbl_cfg)
760 761
{
	u32 reg;
762
	u64 reg64;
763
	bool stage1;
764 765
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct arm_smmu_device *smmu = smmu_domain->smmu;
766
	void __iomem *cb_base, *gr1_base;
767 768

	gr1_base = ARM_SMMU_GR1(smmu);
769 770
	stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
771

772
	if (smmu->version > ARM_SMMU_V1) {
773 774 775 776
		if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64)
			reg = CBA2R_RW64_64BIT;
		else
			reg = CBA2R_RW64_32BIT;
777 778
		/* 16-bit VMIDs live in CBA2R */
		if (smmu->features & ARM_SMMU_FEAT_VMID16)
779
			reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBA2R_VMID_SHIFT;
780

781 782 783
		writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBA2R(cfg->cbndx));
	}

784
	/* CBAR */
785
	reg = cfg->cbar;
786
	if (smmu->version < ARM_SMMU_V2)
787
		reg |= cfg->irptndx << CBAR_IRPTNDX_SHIFT;
788

789 790 791 792 793 794 795
	/*
	 * Use the weakest shareability/memory types, so they are
	 * overridden by the ttbcr/pte.
	 */
	if (stage1) {
		reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
			(CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
796 797
	} else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) {
		/* 8-bit VMIDs live in CBAR */
798
		reg |= ARM_SMMU_CB_VMID(smmu, cfg) << CBAR_VMID_SHIFT;
799
	}
800
	writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(cfg->cbndx));
801

802 803
	/* TTBRs */
	if (stage1) {
804 805
		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[0];

806
		reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT;
807
		writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR0);
808 809

		reg64 = pgtbl_cfg->arm_lpae_s1_cfg.ttbr[1];
810
		reg64 |= ((u64)ARM_SMMU_CB_ASID(smmu, cfg)) << TTBRn_ASID_SHIFT;
811
		writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR1);
812
	} else {
813
		reg64 = pgtbl_cfg->arm_lpae_s2_cfg.vttbr;
814
		writeq_relaxed(reg64, cb_base + ARM_SMMU_CB_TTBR0);
815
	}
816

817 818 819 820 821 822
	/* TTBCR */
	if (stage1) {
		reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr;
		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
		if (smmu->version > ARM_SMMU_V1) {
			reg = pgtbl_cfg->arm_lpae_s1_cfg.tcr >> 32;
823
			reg |= TTBCR2_SEP_UPSTREAM;
824
			writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
825 826
		}
	} else {
827 828
		reg = pgtbl_cfg->arm_lpae_s2_cfg.vtcr;
		writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
829 830
	}

831
	/* MAIRs (stage-1 only) */
832
	if (stage1) {
833
		reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[0];
834
		writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
835 836
		reg = pgtbl_cfg->arm_lpae_s1_cfg.mair[1];
		writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR1);
837 838 839 840 841 842 843 844 845
	}

	/* SCTLR */
	reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
	if (stage1)
		reg |= SCTLR_S1_ASIDPNE;
#ifdef __BIG_ENDIAN
	reg |= SCTLR_E;
#endif
846
	writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
847 848 849
}

static int arm_smmu_init_domain_context(struct iommu_domain *domain,
850
					struct arm_smmu_device *smmu)
851
{
852
	int irq, start, ret = 0;
853 854 855 856
	unsigned long ias, oas;
	struct io_pgtable_ops *pgtbl_ops;
	struct io_pgtable_cfg pgtbl_cfg;
	enum io_pgtable_fmt fmt;
857
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
858
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
859

860
	mutex_lock(&smmu_domain->init_mutex);
861 862 863
	if (smmu_domain->smmu)
		goto out_unlock;

864 865 866 867 868 869
	/* We're bypassing these SIDs, so don't allocate an actual context */
	if (domain->type == IOMMU_DOMAIN_DMA) {
		smmu_domain->smmu = smmu;
		goto out_unlock;
	}

870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892
	/*
	 * Mapping the requested stage onto what we support is surprisingly
	 * complicated, mainly because the spec allows S1+S2 SMMUs without
	 * support for nested translation. That means we end up with the
	 * following table:
	 *
	 * Requested        Supported        Actual
	 *     S1               N              S1
	 *     S1             S1+S2            S1
	 *     S1               S2             S2
	 *     S1               S1             S1
	 *     N                N              N
	 *     N              S1+S2            S2
	 *     N                S2             S2
	 *     N                S1             S1
	 *
	 * Note that you can't actually request stage-2 mappings.
	 */
	if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1))
		smmu_domain->stage = ARM_SMMU_DOMAIN_S2;
	if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2))
		smmu_domain->stage = ARM_SMMU_DOMAIN_S1;

893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913
	/*
	 * Choosing a suitable context format is even more fiddly. Until we
	 * grow some way for the caller to express a preference, and/or move
	 * the decision into the io-pgtable code where it arguably belongs,
	 * just aim for the closest thing to the rest of the system, and hope
	 * that the hardware isn't esoteric enough that we can't assume AArch64
	 * support to be a superset of AArch32 support...
	 */
	if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L)
		cfg->fmt = ARM_SMMU_CTX_FMT_AARCH32_L;
	if ((IS_ENABLED(CONFIG_64BIT) || cfg->fmt == ARM_SMMU_CTX_FMT_NONE) &&
	    (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K |
			       ARM_SMMU_FEAT_FMT_AARCH64_16K |
			       ARM_SMMU_FEAT_FMT_AARCH64_4K)))
		cfg->fmt = ARM_SMMU_CTX_FMT_AARCH64;

	if (cfg->fmt == ARM_SMMU_CTX_FMT_NONE) {
		ret = -EINVAL;
		goto out_unlock;
	}

914 915 916 917
	switch (smmu_domain->stage) {
	case ARM_SMMU_DOMAIN_S1:
		cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
		start = smmu->num_s2_context_banks;
918 919
		ias = smmu->va_size;
		oas = smmu->ipa_size;
920
		if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) {
921
			fmt = ARM_64_LPAE_S1;
922
		} else {
923
			fmt = ARM_32_LPAE_S1;
924 925 926
			ias = min(ias, 32UL);
			oas = min(oas, 40UL);
		}
927 928
		break;
	case ARM_SMMU_DOMAIN_NESTED:
929 930 931 932
		/*
		 * We will likely want to change this if/when KVM gets
		 * involved.
		 */
933
	case ARM_SMMU_DOMAIN_S2:
934 935
		cfg->cbar = CBAR_TYPE_S2_TRANS;
		start = 0;
936 937
		ias = smmu->ipa_size;
		oas = smmu->pa_size;
938
		if (cfg->fmt == ARM_SMMU_CTX_FMT_AARCH64) {
939
			fmt = ARM_64_LPAE_S2;
940
		} else {
941
			fmt = ARM_32_LPAE_S2;
942 943 944
			ias = min(ias, 40UL);
			oas = min(oas, 40UL);
		}
945 946 947 948
		break;
	default:
		ret = -EINVAL;
		goto out_unlock;
949 950 951 952
	}

	ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
				      smmu->num_context_banks);
953
	if (ret < 0)
954
		goto out_unlock;
955

956
	cfg->cbndx = ret;
957
	if (smmu->version < ARM_SMMU_V2) {
958 959
		cfg->irptndx = atomic_inc_return(&smmu->irptndx);
		cfg->irptndx %= smmu->num_context_irqs;
960
	} else {
961
		cfg->irptndx = cfg->cbndx;
962 963
	}

964
	pgtbl_cfg = (struct io_pgtable_cfg) {
965
		.pgsize_bitmap	= smmu->pgsize_bitmap,
966 967 968
		.ias		= ias,
		.oas		= oas,
		.tlb		= &arm_smmu_gather_ops,
969
		.iommu_dev	= smmu->dev,
970 971 972 973 974 975 976 977 978
	};

	smmu_domain->smmu = smmu;
	pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);
	if (!pgtbl_ops) {
		ret = -ENOMEM;
		goto out_clear_smmu;
	}

979 980
	/* Update the domain's page sizes to reflect the page table format */
	domain->pgsize_bitmap = pgtbl_cfg.pgsize_bitmap;
981

982 983 984 985 986 987 988
	/* Initialise the context bank with our page table cfg */
	arm_smmu_init_context_bank(smmu_domain, &pgtbl_cfg);

	/*
	 * Request context fault interrupt. Do this last to avoid the
	 * handler seeing a half-initialised domain state.
	 */
989
	irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
990 991
	ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
			  "arm-smmu-context-fault", domain);
992
	if (ret < 0) {
993
		dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
994 995
			cfg->irptndx, irq);
		cfg->irptndx = INVALID_IRPTNDX;
996 997
	}

998 999 1000 1001
	mutex_unlock(&smmu_domain->init_mutex);

	/* Publish page table ops for map/unmap */
	smmu_domain->pgtbl_ops = pgtbl_ops;
1002
	return 0;
1003

1004 1005
out_clear_smmu:
	smmu_domain->smmu = NULL;
1006
out_unlock:
1007
	mutex_unlock(&smmu_domain->init_mutex);
1008 1009 1010 1011 1012
	return ret;
}

static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
{
1013
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1014 1015
	struct arm_smmu_device *smmu = smmu_domain->smmu;
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
1016
	void __iomem *cb_base;
1017 1018
	int irq;

1019
	if (!smmu || domain->type == IOMMU_DOMAIN_DMA)
1020 1021
		return;

1022 1023 1024 1025
	/*
	 * Disable the context bank and free the page tables before freeing
	 * it.
	 */
1026
	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
1027 1028
	writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);

1029 1030
	if (cfg->irptndx != INVALID_IRPTNDX) {
		irq = smmu->irqs[smmu->num_global_irqs + cfg->irptndx];
1031 1032 1033
		free_irq(irq, domain);
	}

1034
	free_io_pgtable_ops(smmu_domain->pgtbl_ops);
1035
	__arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx);
1036 1037
}

1038
static struct iommu_domain *arm_smmu_domain_alloc(unsigned type)
1039 1040 1041
{
	struct arm_smmu_domain *smmu_domain;

1042
	if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
1043
		return NULL;
1044 1045 1046 1047 1048 1049 1050
	/*
	 * Allocate the domain and initialise some of its data structures.
	 * We can't really do anything meaningful until we've added a
	 * master.
	 */
	smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
	if (!smmu_domain)
1051
		return NULL;
1052

1053 1054 1055 1056 1057 1058
	if (type == IOMMU_DOMAIN_DMA &&
	    iommu_get_dma_cookie(&smmu_domain->domain)) {
		kfree(smmu_domain);
		return NULL;
	}

1059 1060
	mutex_init(&smmu_domain->init_mutex);
	spin_lock_init(&smmu_domain->pgtbl_lock);
1061 1062

	return &smmu_domain->domain;
1063 1064
}

1065
static void arm_smmu_domain_free(struct iommu_domain *domain)
1066
{
1067
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1068 1069 1070 1071 1072

	/*
	 * Free the domain resources. We assume that all devices have
	 * already been detached.
	 */
1073
	iommu_put_dma_cookie(domain);
1074 1075 1076 1077 1078
	arm_smmu_destroy_domain_context(domain);
	kfree(smmu_domain);
}

static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1079
					  struct arm_smmu_master_cfg *cfg)
1080 1081 1082 1083 1084 1085 1086 1087
{
	int i;
	struct arm_smmu_smr *smrs;
	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);

	if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
		return 0;

1088
	if (cfg->smrs)
1089 1090
		return -EEXIST;

1091
	smrs = kmalloc_array(cfg->num_streamids, sizeof(*smrs), GFP_KERNEL);
1092
	if (!smrs) {
1093 1094
		dev_err(smmu->dev, "failed to allocate %d SMRs\n",
			cfg->num_streamids);
1095 1096 1097
		return -ENOMEM;
	}

1098
	/* Allocate the SMRs on the SMMU */
1099
	for (i = 0; i < cfg->num_streamids; ++i) {
1100 1101
		int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
						  smmu->num_mapping_groups);
1102
		if (idx < 0) {
1103 1104 1105 1106 1107 1108 1109
			dev_err(smmu->dev, "failed to allocate free SMR\n");
			goto err_free_smrs;
		}

		smrs[i] = (struct arm_smmu_smr) {
			.idx	= idx,
			.mask	= 0, /* We don't currently share SMRs */
1110
			.id	= cfg->streamids[i],
1111 1112 1113 1114
		};
	}

	/* It worked! Now, poke the actual hardware */
1115
	for (i = 0; i < cfg->num_streamids; ++i) {
1116 1117 1118 1119 1120
		u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
			  smrs[i].mask << SMR_MASK_SHIFT;
		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
	}

1121
	cfg->smrs = smrs;
1122 1123 1124 1125 1126 1127 1128 1129 1130 1131
	return 0;

err_free_smrs:
	while (--i >= 0)
		__arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
	kfree(smrs);
	return -ENOSPC;
}

static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1132
				      struct arm_smmu_master_cfg *cfg)
1133 1134 1135
{
	int i;
	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1136
	struct arm_smmu_smr *smrs = cfg->smrs;
1137

1138 1139 1140
	if (!smrs)
		return;

1141
	/* Invalidate the SMRs before freeing back to the allocator */
1142
	for (i = 0; i < cfg->num_streamids; ++i) {
1143
		u8 idx = smrs[i].idx;
1144

1145 1146 1147 1148
		writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
		__arm_smmu_free_bitmap(smmu->smr_map, idx);
	}

1149
	cfg->smrs = NULL;
1150 1151 1152 1153
	kfree(smrs);
}

static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1154
				      struct arm_smmu_master_cfg *cfg)
1155 1156
{
	int i, ret;
1157
	struct arm_smmu_device *smmu = smmu_domain->smmu;
1158 1159
	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);

1160 1161
	/*
	 * FIXME: This won't be needed once we have IOMMU-backed DMA ops
1162 1163 1164
	 * for all devices behind the SMMU. Note that we need to take
	 * care configuring SMRs for devices both a platform_device and
	 * and a PCI device (i.e. a PCI host controller)
1165 1166 1167 1168
	 */
	if (smmu_domain->domain.type == IOMMU_DOMAIN_DMA)
		return 0;

1169 1170 1171 1172 1173
	/* Devices in an IOMMU group may already be configured */
	ret = arm_smmu_master_configure_smrs(smmu, cfg);
	if (ret)
		return ret == -EEXIST ? 0 : ret;

1174
	for (i = 0; i < cfg->num_streamids; ++i) {
1175
		u32 idx, s2cr;
1176

1177
		idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1178
		s2cr = S2CR_TYPE_TRANS | S2CR_PRIVCFG_UNPRIV |
1179
		       (smmu_domain->cfg.cbndx << S2CR_CBNDX_SHIFT);
1180 1181 1182 1183 1184 1185 1186
		writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
	}

	return 0;
}

static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1187
					  struct arm_smmu_master_cfg *cfg)
1188
{
1189
	int i;
1190
	struct arm_smmu_device *smmu = smmu_domain->smmu;
1191
	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1192

1193 1194 1195
	/* An IOMMU group is torn down by the first device to be removed */
	if ((smmu->features & ARM_SMMU_FEAT_STREAM_MATCH) && !cfg->smrs)
		return;
1196 1197 1198 1199 1200

	/*
	 * We *must* clear the S2CR first, because freeing the SMR means
	 * that it can be re-allocated immediately.
	 */
1201 1202
	for (i = 0; i < cfg->num_streamids; ++i) {
		u32 idx = cfg->smrs ? cfg->smrs[i].idx : cfg->streamids[i];
1203
		u32 reg = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS;
1204

1205
		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1206 1207
	}

1208
	arm_smmu_master_free_smrs(smmu, cfg);
1209 1210
}

1211 1212 1213 1214 1215 1216 1217 1218 1219 1220
static void arm_smmu_detach_dev(struct device *dev,
				struct arm_smmu_master_cfg *cfg)
{
	struct iommu_domain *domain = dev->archdata.iommu;
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);

	dev->archdata.iommu = NULL;
	arm_smmu_domain_remove_master(smmu_domain, cfg);
}

1221 1222
static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
{
1223
	int ret;
1224
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1225
	struct arm_smmu_device *smmu;
1226
	struct arm_smmu_master_cfg *cfg;
1227

1228
	smmu = find_smmu_for_device(dev);
1229
	if (!smmu) {
1230 1231 1232 1233
		dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
		return -ENXIO;
	}

1234 1235
	/* Ensure that the domain is finalised */
	ret = arm_smmu_init_domain_context(domain, smmu);
1236
	if (ret < 0)
1237 1238
		return ret;

1239
	/*
1240 1241
	 * Sanity check the domain. We don't support domains across
	 * different SMMUs.
1242
	 */
1243
	if (smmu_domain->smmu != smmu) {
1244 1245
		dev_err(dev,
			"cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1246 1247
			dev_name(smmu_domain->smmu->dev), dev_name(smmu->dev));
		return -EINVAL;
1248 1249 1250
	}

	/* Looks ok, so add the device to the domain */
1251
	cfg = find_smmu_master_cfg(dev);
1252
	if (!cfg)
1253 1254
		return -ENODEV;

1255 1256 1257 1258
	/* Detach the dev from its current domain */
	if (dev->archdata.iommu)
		arm_smmu_detach_dev(dev, cfg);

1259 1260 1261
	ret = arm_smmu_domain_add_master(smmu_domain, cfg);
	if (!ret)
		dev->archdata.iommu = domain;
1262 1263 1264 1265
	return ret;
}

static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1266
			phys_addr_t paddr, size_t size, int prot)
1267
{
1268 1269
	int ret;
	unsigned long flags;
1270
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1271
	struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1272

1273
	if (!ops)
1274 1275
		return -ENODEV;

1276 1277 1278 1279
	spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
	ret = ops->map(ops, iova, paddr, size, prot);
	spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
	return ret;
1280 1281 1282 1283 1284
}

static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
			     size_t size)
{
1285 1286
	size_t ret;
	unsigned long flags;
1287
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1288
	struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1289

1290 1291 1292 1293 1294 1295 1296
	if (!ops)
		return 0;

	spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
	ret = ops->unmap(ops, iova, size);
	spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
	return ret;
1297 1298
}

1299 1300 1301
static phys_addr_t arm_smmu_iova_to_phys_hard(struct iommu_domain *domain,
					      dma_addr_t iova)
{
1302
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1303 1304 1305 1306 1307 1308 1309
	struct arm_smmu_device *smmu = smmu_domain->smmu;
	struct arm_smmu_cfg *cfg = &smmu_domain->cfg;
	struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
	struct device *dev = smmu->dev;
	void __iomem *cb_base;
	u32 tmp;
	u64 phys;
1310
	unsigned long va;
1311 1312 1313

	cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);

1314 1315 1316
	/* ATS1 registers can only be written atomically */
	va = iova & ~0xfffUL;
	if (smmu->version == ARM_SMMU_V2)
1317 1318
		smmu_write_atomic_lq(va, cb_base + ARM_SMMU_CB_ATS1PR);
	else /* Register is only 32-bit in v1 */
1319
		writel_relaxed(va, cb_base + ARM_SMMU_CB_ATS1PR);
1320 1321 1322 1323

	if (readl_poll_timeout_atomic(cb_base + ARM_SMMU_CB_ATSR, tmp,
				      !(tmp & ATSR_ACTIVE), 5, 50)) {
		dev_err(dev,
1324
			"iova to phys timed out on %pad. Falling back to software table walk.\n",
1325 1326 1327 1328
			&iova);
		return ops->iova_to_phys(ops, iova);
	}

1329
	phys = readq_relaxed(cb_base + ARM_SMMU_CB_PAR);
1330 1331 1332 1333 1334 1335 1336 1337 1338
	if (phys & CB_PAR_F) {
		dev_err(dev, "translation fault!\n");
		dev_err(dev, "PAR = 0x%llx\n", phys);
		return 0;
	}

	return (phys & GENMASK_ULL(39, 12)) | (iova & 0xfff);
}

1339
static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1340
					dma_addr_t iova)
1341
{
1342 1343
	phys_addr_t ret;
	unsigned long flags;
1344
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1345
	struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
1346

1347
	if (!ops)
1348
		return 0;
1349

1350
	spin_lock_irqsave(&smmu_domain->pgtbl_lock, flags);
1351 1352
	if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS &&
			smmu_domain->stage == ARM_SMMU_DOMAIN_S1) {
1353
		ret = arm_smmu_iova_to_phys_hard(domain, iova);
1354
	} else {
1355
		ret = ops->iova_to_phys(ops, iova);
1356 1357
	}

1358
	spin_unlock_irqrestore(&smmu_domain->pgtbl_lock, flags);
1359

1360
	return ret;
1361 1362
}

1363
static bool arm_smmu_capable(enum iommu_cap cap)
1364
{
1365 1366
	switch (cap) {
	case IOMMU_CAP_CACHE_COHERENCY:
1367 1368 1369 1370 1371
		/*
		 * Return true here as the SMMU can always send out coherent
		 * requests.
		 */
		return true;
1372
	case IOMMU_CAP_INTR_REMAP:
1373
		return true; /* MSIs are just memory writes */
1374 1375
	case IOMMU_CAP_NOEXEC:
		return true;
1376
	default:
1377
		return false;
1378
	}
1379 1380
}

1381 1382 1383 1384
static int __arm_smmu_get_pci_sid(struct pci_dev *pdev, u16 alias, void *data)
{
	*((u16 *)data) = alias;
	return 0; /* Continue walking */
1385 1386
}

1387 1388 1389 1390 1391
static void __arm_smmu_release_pci_iommudata(void *data)
{
	kfree(data);
}

1392 1393
static int arm_smmu_init_pci_device(struct pci_dev *pdev,
				    struct iommu_group *group)
1394
{
1395
	struct arm_smmu_master_cfg *cfg;
1396 1397
	u16 sid;
	int i;
1398

1399 1400
	cfg = iommu_group_get_iommudata(group);
	if (!cfg) {
1401
		cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
1402 1403
		if (!cfg)
			return -ENOMEM;
1404

1405 1406 1407
		iommu_group_set_iommudata(group, cfg,
					  __arm_smmu_release_pci_iommudata);
	}
1408

1409 1410
	if (cfg->num_streamids >= MAX_MASTER_STREAMIDS)
		return -ENOSPC;
1411

1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423
	/*
	 * Assume Stream ID == Requester ID for now.
	 * We need a way to describe the ID mappings in FDT.
	 */
	pci_for_each_dma_alias(pdev, __arm_smmu_get_pci_sid, &sid);
	for (i = 0; i < cfg->num_streamids; ++i)
		if (cfg->streamids[i] == sid)
			break;

	/* Avoid duplicate SIDs, as this can lead to SMR conflicts */
	if (i == cfg->num_streamids)
		cfg->streamids[cfg->num_streamids++] = sid;
1424

1425
	return 0;
1426 1427
}

1428 1429
static int arm_smmu_init_platform_device(struct device *dev,
					 struct iommu_group *group)
1430 1431
{
	struct arm_smmu_device *smmu = find_smmu_for_device(dev);
1432
	struct arm_smmu_master *master;
1433 1434 1435 1436 1437 1438 1439 1440 1441

	if (!smmu)
		return -ENODEV;

	master = find_smmu_master(smmu, dev->of_node);
	if (!master)
		return -ENODEV;

	iommu_group_set_iommudata(group, &master->cfg, NULL);
1442 1443

	return 0;
1444 1445 1446 1447
}

static int arm_smmu_add_device(struct device *dev)
{
1448
	struct iommu_group *group;
1449

1450 1451 1452
	group = iommu_group_get_for_dev(dev);
	if (IS_ERR(group))
		return PTR_ERR(group);
1453

1454
	iommu_group_put(group);
1455
	return 0;
1456 1457
}

1458 1459
static void arm_smmu_remove_device(struct device *dev)
{
1460
	iommu_group_remove_device(dev);
1461 1462
}

1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488
static struct iommu_group *arm_smmu_device_group(struct device *dev)
{
	struct iommu_group *group;
	int ret;

	if (dev_is_pci(dev))
		group = pci_device_group(dev);
	else
		group = generic_device_group(dev);

	if (IS_ERR(group))
		return group;

	if (dev_is_pci(dev))
		ret = arm_smmu_init_pci_device(to_pci_dev(dev), group);
	else
		ret = arm_smmu_init_platform_device(dev, group);

	if (ret) {
		iommu_group_put(group);
		group = ERR_PTR(ret);
	}

	return group;
}

1489 1490 1491
static int arm_smmu_domain_get_attr(struct iommu_domain *domain,
				    enum iommu_attr attr, void *data)
{
1492
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505

	switch (attr) {
	case DOMAIN_ATTR_NESTING:
		*(int *)data = (smmu_domain->stage == ARM_SMMU_DOMAIN_NESTED);
		return 0;
	default:
		return -ENODEV;
	}
}

static int arm_smmu_domain_set_attr(struct iommu_domain *domain,
				    enum iommu_attr attr, void *data)
{
1506
	int ret = 0;
1507
	struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
1508

1509 1510
	mutex_lock(&smmu_domain->init_mutex);

1511 1512
	switch (attr) {
	case DOMAIN_ATTR_NESTING:
1513 1514 1515 1516 1517
		if (smmu_domain->smmu) {
			ret = -EPERM;
			goto out_unlock;
		}

1518 1519 1520 1521 1522
		if (*(int *)data)
			smmu_domain->stage = ARM_SMMU_DOMAIN_NESTED;
		else
			smmu_domain->stage = ARM_SMMU_DOMAIN_S1;

1523
		break;
1524
	default:
1525
		ret = -ENODEV;
1526
	}
1527 1528 1529 1530

out_unlock:
	mutex_unlock(&smmu_domain->init_mutex);
	return ret;
1531 1532
}

1533
static struct iommu_ops arm_smmu_ops = {
1534
	.capable		= arm_smmu_capable,
1535 1536
	.domain_alloc		= arm_smmu_domain_alloc,
	.domain_free		= arm_smmu_domain_free,
1537 1538 1539
	.attach_dev		= arm_smmu_attach_dev,
	.map			= arm_smmu_map,
	.unmap			= arm_smmu_unmap,
1540
	.map_sg			= default_iommu_map_sg,
1541 1542 1543
	.iova_to_phys		= arm_smmu_iova_to_phys,
	.add_device		= arm_smmu_add_device,
	.remove_device		= arm_smmu_remove_device,
1544
	.device_group		= arm_smmu_device_group,
1545 1546
	.domain_get_attr	= arm_smmu_domain_get_attr,
	.domain_set_attr	= arm_smmu_domain_set_attr,
1547
	.pgsize_bitmap		= -1UL, /* Restricted during device attach */
1548 1549 1550 1551 1552
};

static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
{
	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1553
	void __iomem *cb_base;
1554
	int i = 0;
1555
	u32 reg, major;
1556

1557 1558 1559
	/* clear global FSR */
	reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
	writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sGFSR);
1560

1561 1562
	/* Mark all SMRn as invalid and all S2CRn as bypass unless overridden */
	reg = disable_bypass ? S2CR_TYPE_FAULT : S2CR_TYPE_BYPASS;
1563
	for (i = 0; i < smmu->num_mapping_groups; ++i) {
1564
		writel_relaxed(0, gr0_base + ARM_SMMU_GR0_SMR(i));
1565
		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_S2CR(i));
1566 1567
	}

1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580
	/*
	 * Before clearing ARM_MMU500_ACTLR_CPRE, need to
	 * clear CACHE_LOCK bit of ACR first. And, CACHE_LOCK
	 * bit is only present in MMU-500r2 onwards.
	 */
	reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID7);
	major = (reg >> ID7_MAJOR_SHIFT) & ID7_MAJOR_MASK;
	if ((smmu->model == ARM_MMU500) && (major >= 2)) {
		reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sACR);
		reg &= ~ARM_MMU500_ACR_CACHE_LOCK;
		writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sACR);
	}

1581 1582 1583 1584 1585
	/* Make sure all context banks are disabled and clear CB_FSR  */
	for (i = 0; i < smmu->num_context_banks; ++i) {
		cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
		writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
		writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1586 1587 1588 1589 1590 1591 1592 1593 1594
		/*
		 * Disable MMU-500's not-particularly-beneficial next-page
		 * prefetcher for the sake of errata #841119 and #826419.
		 */
		if (smmu->model == ARM_MMU500) {
			reg = readl_relaxed(cb_base + ARM_SMMU_CB_ACTLR);
			reg &= ~ARM_MMU500_ACTLR_CPRE;
			writel_relaxed(reg, cb_base + ARM_SMMU_CB_ACTLR);
		}
1595
	}
1596

1597 1598 1599 1600
	/* Invalidate the TLB, just in case */
	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
	writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);

1601
	reg = readl_relaxed(ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1602

1603
	/* Enable fault reporting */
1604
	reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1605 1606

	/* Disable TLB broadcasting. */
1607
	reg |= (sCR0_VMIDPNE | sCR0_PTM);
1608

1609 1610 1611 1612 1613 1614
	/* Enable client access, handling unmatched streams as appropriate */
	reg &= ~sCR0_CLIENTPD;
	if (disable_bypass)
		reg |= sCR0_USFCFG;
	else
		reg &= ~sCR0_USFCFG;
1615 1616

	/* Disable forced broadcasting */
1617
	reg &= ~sCR0_FB;
1618 1619

	/* Don't upgrade barriers */
1620
	reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1621

1622 1623 1624
	if (smmu->features & ARM_SMMU_FEAT_VMID16)
		reg |= sCR0_VMID16EN;

1625
	/* Push the button */
1626
	__arm_smmu_tlb_sync(smmu);
1627
	writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653
}

static int arm_smmu_id_size_to_bits(int size)
{
	switch (size) {
	case 0:
		return 32;
	case 1:
		return 36;
	case 2:
		return 40;
	case 3:
		return 42;
	case 4:
		return 44;
	case 5:
	default:
		return 48;
	}
}

static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
{
	unsigned long size;
	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
	u32 id;
1654
	bool cttw_dt, cttw_reg;
1655 1656

	dev_notice(smmu->dev, "probing hardware configuration...\n");
1657 1658
	dev_notice(smmu->dev, "SMMUv%d with:\n",
			smmu->version == ARM_SMMU_V2 ? 2 : 1);
1659 1660 1661

	/* ID0 */
	id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1662 1663 1664 1665 1666 1667 1668

	/* Restrict available stages based on module parameter */
	if (force_stage == 1)
		id &= ~(ID0_S2TS | ID0_NTS);
	else if (force_stage == 2)
		id &= ~(ID0_S1TS | ID0_NTS);

1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684
	if (id & ID0_S1TS) {
		smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
		dev_notice(smmu->dev, "\tstage 1 translation\n");
	}

	if (id & ID0_S2TS) {
		smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
		dev_notice(smmu->dev, "\tstage 2 translation\n");
	}

	if (id & ID0_NTS) {
		smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
		dev_notice(smmu->dev, "\tnested translation\n");
	}

	if (!(smmu->features &
1685
		(ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2))) {
1686 1687 1688 1689
		dev_err(smmu->dev, "\tno translation support!\n");
		return -ENODEV;
	}

1690 1691
	if ((id & ID0_S1TS) &&
		((smmu->version < ARM_SMMU_V2) || !(id & ID0_ATOSNS))) {
1692 1693 1694 1695
		smmu->features |= ARM_SMMU_FEAT_TRANS_OPS;
		dev_notice(smmu->dev, "\taddress translation ops\n");
	}

1696 1697 1698 1699 1700 1701 1702 1703 1704
	/*
	 * In order for DMA API calls to work properly, we must defer to what
	 * the DT says about coherency, regardless of what the hardware claims.
	 * Fortunately, this also opens up a workaround for systems where the
	 * ID register value has ended up configured incorrectly.
	 */
	cttw_dt = of_dma_is_coherent(smmu->dev->of_node);
	cttw_reg = !!(id & ID0_CTTW);
	if (cttw_dt)
1705
		smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1706 1707 1708 1709 1710 1711
	if (cttw_dt || cttw_reg)
		dev_notice(smmu->dev, "\t%scoherent table walk\n",
			   cttw_dt ? "" : "non-");
	if (cttw_dt != cttw_reg)
		dev_notice(smmu->dev,
			   "\t(IDR0.CTTW overridden by dma-coherent property)\n");
1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741

	if (id & ID0_SMS) {
		u32 smr, sid, mask;

		smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
		smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
					   ID0_NUMSMRG_MASK;
		if (smmu->num_mapping_groups == 0) {
			dev_err(smmu->dev,
				"stream-matching supported, but no SMRs present!\n");
			return -ENODEV;
		}

		smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
		smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
		writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
		smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));

		mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
		sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
		if ((mask & sid) != sid) {
			dev_err(smmu->dev,
				"SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
				mask, sid);
			return -ENODEV;
		}

		dev_notice(smmu->dev,
			   "\tstream matching with %u register groups, mask 0x%x",
			   smmu->num_mapping_groups, mask);
1742 1743 1744
	} else {
		smmu->num_mapping_groups = (id >> ID0_NUMSIDB_SHIFT) &
					   ID0_NUMSIDB_MASK;
1745 1746
	}

1747 1748 1749 1750 1751 1752
	if (smmu->version < ARM_SMMU_V2 || !(id & ID0_PTFS_NO_AARCH32)) {
		smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_L;
		if (!(id & ID0_PTFS_NO_AARCH32S))
			smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_S;
	}

1753 1754
	/* ID1 */
	id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1755
	smmu->pgshift = (id & ID1_PAGESIZE) ? 16 : 12;
1756

1757
	/* Check for size mismatch of SMMU address space from mapped region */
1758
	size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1759
	size *= 2 << smmu->pgshift;
1760
	if (smmu->size != size)
1761 1762 1763
		dev_warn(smmu->dev,
			"SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
			size, smmu->size);
1764

1765
	smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) & ID1_NUMS2CB_MASK;
1766 1767 1768 1769 1770 1771 1772
	smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
	if (smmu->num_s2_context_banks > smmu->num_context_banks) {
		dev_err(smmu->dev, "impossible number of S2 context banks!\n");
		return -ENODEV;
	}
	dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
		   smmu->num_context_banks, smmu->num_s2_context_banks);
1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783
	/*
	 * Cavium CN88xx erratum #27704.
	 * Ensure ASID and VMID allocation is unique across all SMMUs in
	 * the system.
	 */
	if (smmu->model == CAVIUM_SMMUV2) {
		smmu->cavium_id_base =
			atomic_add_return(smmu->num_context_banks,
					  &cavium_smmu_context_count);
		smmu->cavium_id_base -= smmu->num_context_banks;
	}
1784 1785 1786 1787

	/* ID2 */
	id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
	size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1788
	smmu->ipa_size = size;
1789

1790
	/* The output mask is also applied for bypass */
1791
	size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1792
	smmu->pa_size = size;
1793

1794 1795 1796
	if (id & ID2_VMID16)
		smmu->features |= ARM_SMMU_FEAT_VMID16;

1797 1798 1799 1800 1801 1802 1803 1804 1805
	/*
	 * What the page table walker can address actually depends on which
	 * descriptor format is in use, but since a) we don't know that yet,
	 * and b) it can vary per context bank, this will have to do...
	 */
	if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size)))
		dev_warn(smmu->dev,
			 "failed to set DMA mask for table walker\n");

1806
	if (smmu->version < ARM_SMMU_V2) {
1807
		smmu->va_size = smmu->ipa_size;
1808 1809
		if (smmu->version == ARM_SMMU_V1_64K)
			smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K;
1810 1811
	} else {
		size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1812 1813
		smmu->va_size = arm_smmu_id_size_to_bits(size);
		if (id & ID2_PTFS_4K)
1814
			smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_4K;
1815
		if (id & ID2_PTFS_16K)
1816
			smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_16K;
1817
		if (id & ID2_PTFS_64K)
1818
			smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K;
1819 1820
	}

1821 1822
	/* Now we've corralled the various formats, what'll it do? */
	if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S)
1823
		smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M;
1824 1825
	if (smmu->features &
	    (ARM_SMMU_FEAT_FMT_AARCH32_L | ARM_SMMU_FEAT_FMT_AARCH64_4K))
1826
		smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G;
1827
	if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_16K)
1828
		smmu->pgsize_bitmap |= SZ_16K | SZ_32M;
1829
	if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_64K)
1830 1831 1832 1833 1834 1835 1836 1837
		smmu->pgsize_bitmap |= SZ_64K | SZ_512M;

	if (arm_smmu_ops.pgsize_bitmap == -1UL)
		arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap;
	else
		arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap;
	dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n",
		   smmu->pgsize_bitmap);
1838

1839

1840 1841
	if (smmu->features & ARM_SMMU_FEAT_TRANS_S1)
		dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
1842
			   smmu->va_size, smmu->ipa_size);
1843 1844 1845

	if (smmu->features & ARM_SMMU_FEAT_TRANS_S2)
		dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
1846
			   smmu->ipa_size, smmu->pa_size);
1847

1848 1849 1850
	return 0;
}

1851 1852 1853 1854 1855 1856 1857 1858 1859 1860
struct arm_smmu_match_data {
	enum arm_smmu_arch_version version;
	enum arm_smmu_implementation model;
};

#define ARM_SMMU_MATCH_DATA(name, ver, imp)	\
static struct arm_smmu_match_data name = { .version = ver, .model = imp }

ARM_SMMU_MATCH_DATA(smmu_generic_v1, ARM_SMMU_V1, GENERIC_SMMU);
ARM_SMMU_MATCH_DATA(smmu_generic_v2, ARM_SMMU_V2, GENERIC_SMMU);
1861
ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU);
1862
ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500);
1863
ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2);
1864

1865
static const struct of_device_id arm_smmu_of_match[] = {
1866 1867 1868
	{ .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 },
	{ .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 },
	{ .compatible = "arm,mmu-400", .data = &smmu_generic_v1 },
1869
	{ .compatible = "arm,mmu-401", .data = &arm_mmu401 },
1870
	{ .compatible = "arm,mmu-500", .data = &arm_mmu500 },
1871
	{ .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
1872 1873 1874 1875
	{ },
};
MODULE_DEVICE_TABLE(of, arm_smmu_of_match);

1876 1877
static int arm_smmu_device_dt_probe(struct platform_device *pdev)
{
1878
	const struct of_device_id *of_id;
1879
	const struct arm_smmu_match_data *data;
1880 1881 1882 1883
	struct resource *res;
	struct arm_smmu_device *smmu;
	struct device *dev = &pdev->dev;
	struct rb_node *node;
1884 1885
	struct of_phandle_iterator it;
	struct arm_smmu_phandle_args *masterspec;
1886 1887 1888 1889 1890 1891 1892 1893 1894
	int num_irqs, i, err;

	smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
	if (!smmu) {
		dev_err(dev, "failed to allocate arm_smmu_device\n");
		return -ENOMEM;
	}
	smmu->dev = dev;

1895
	of_id = of_match_node(arm_smmu_of_match, dev->of_node);
1896 1897 1898
	data = of_id->data;
	smmu->version = data->version;
	smmu->model = data->model;
1899

1900
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1901 1902 1903
	smmu->base = devm_ioremap_resource(dev, res);
	if (IS_ERR(smmu->base))
		return PTR_ERR(smmu->base);
1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918
	smmu->size = resource_size(res);

	if (of_property_read_u32(dev->of_node, "#global-interrupts",
				 &smmu->num_global_irqs)) {
		dev_err(dev, "missing #global-interrupts property\n");
		return -ENODEV;
	}

	num_irqs = 0;
	while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
		num_irqs++;
		if (num_irqs > smmu->num_global_irqs)
			smmu->num_context_irqs++;
	}

1919 1920 1921 1922
	if (!smmu->num_context_irqs) {
		dev_err(dev, "found %d interrupts but expected at least %d\n",
			num_irqs, smmu->num_global_irqs + 1);
		return -ENODEV;
1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933
	}

	smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
				  GFP_KERNEL);
	if (!smmu->irqs) {
		dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
		return -ENOMEM;
	}

	for (i = 0; i < num_irqs; ++i) {
		int irq = platform_get_irq(pdev, i);
1934

1935 1936 1937 1938 1939 1940 1941
		if (irq < 0) {
			dev_err(dev, "failed to get irq index %d\n", i);
			return -ENODEV;
		}
		smmu->irqs[i] = irq;
	}

1942 1943 1944 1945
	err = arm_smmu_device_cfg_probe(smmu);
	if (err)
		return err;

1946 1947
	i = 0;
	smmu->masters = RB_ROOT;
1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962

	err = -ENOMEM;
	/* No need to zero the memory for masterspec */
	masterspec = kmalloc(sizeof(*masterspec), GFP_KERNEL);
	if (!masterspec)
		goto out_put_masters;

	of_for_each_phandle(&it, err, dev->of_node,
			    "mmu-masters", "#stream-id-cells", 0) {
		int count = of_phandle_iterator_args(&it, masterspec->args,
						     MAX_MASTER_STREAMIDS);
		masterspec->np		= of_node_get(it.node);
		masterspec->args_count	= count;

		err = register_smmu_master(smmu, dev, masterspec);
1963 1964
		if (err) {
			dev_err(dev, "failed to add master %s\n",
1965 1966
				masterspec->np->name);
			kfree(masterspec);
1967 1968 1969 1970 1971
			goto out_put_masters;
		}

		i++;
	}
1972

1973 1974
	dev_notice(dev, "registered %d master devices\n", i);

1975 1976
	kfree(masterspec);

1977 1978
	parse_driver_options(smmu);

1979
	if (smmu->version == ARM_SMMU_V2 &&
1980 1981 1982 1983
	    smmu->num_context_banks != smmu->num_context_irqs) {
		dev_err(dev,
			"found only %d context interrupt(s) but %d required\n",
			smmu->num_context_irqs, smmu->num_context_banks);
1984
		err = -ENODEV;
1985
		goto out_put_masters;
1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004
	}

	for (i = 0; i < smmu->num_global_irqs; ++i) {
		err = request_irq(smmu->irqs[i],
				  arm_smmu_global_fault,
				  IRQF_SHARED,
				  "arm-smmu global fault",
				  smmu);
		if (err) {
			dev_err(dev, "failed to request global IRQ %d (%u)\n",
				i, smmu->irqs[i]);
			goto out_free_irqs;
		}
	}

	INIT_LIST_HEAD(&smmu->list);
	spin_lock(&arm_smmu_devices_lock);
	list_add(&smmu->list, &arm_smmu_devices);
	spin_unlock(&arm_smmu_devices_lock);
2005 2006

	arm_smmu_device_reset(smmu);
2007 2008 2009 2010 2011 2012 2013 2014
	return 0;

out_free_irqs:
	while (i--)
		free_irq(smmu->irqs[i], smmu);

out_put_masters:
	for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
2015 2016
		struct arm_smmu_master *master
			= container_of(node, struct arm_smmu_master, node);
2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043
		of_node_put(master->of_node);
	}

	return err;
}

static int arm_smmu_device_remove(struct platform_device *pdev)
{
	int i;
	struct device *dev = &pdev->dev;
	struct arm_smmu_device *curr, *smmu = NULL;
	struct rb_node *node;

	spin_lock(&arm_smmu_devices_lock);
	list_for_each_entry(curr, &arm_smmu_devices, list) {
		if (curr->dev == dev) {
			smmu = curr;
			list_del(&smmu->list);
			break;
		}
	}
	spin_unlock(&arm_smmu_devices_lock);

	if (!smmu)
		return -ENODEV;

	for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
2044 2045
		struct arm_smmu_master *master
			= container_of(node, struct arm_smmu_master, node);
2046 2047 2048
		of_node_put(master->of_node);
	}

2049
	if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
2050 2051 2052 2053 2054 2055
		dev_err(dev, "removing device with active domains!\n");

	for (i = 0; i < smmu->num_global_irqs; ++i)
		free_irq(smmu->irqs[i], smmu);

	/* Turn the thing off */
2056
	writel(sCR0_CLIENTPD, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070
	return 0;
}

static struct platform_driver arm_smmu_driver = {
	.driver	= {
		.name		= "arm-smmu",
		.of_match_table	= of_match_ptr(arm_smmu_of_match),
	},
	.probe	= arm_smmu_device_dt_probe,
	.remove	= arm_smmu_device_remove,
};

static int __init arm_smmu_init(void)
{
2071
	struct device_node *np;
2072 2073
	int ret;

2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084
	/*
	 * Play nice with systems that don't have an ARM SMMU by checking that
	 * an ARM SMMU exists in the system before proceeding with the driver
	 * and IOMMU bus operation registration.
	 */
	np = of_find_matching_node(NULL, arm_smmu_of_match);
	if (!np)
		return 0;

	of_node_put(np);

2085 2086 2087 2088 2089
	ret = platform_driver_register(&arm_smmu_driver);
	if (ret)
		return ret;

	/* Oh, for a proper bus abstraction */
2090
	if (!iommu_present(&platform_bus_type))
2091 2092
		bus_set_iommu(&platform_bus_type, &arm_smmu_ops);

2093
#ifdef CONFIG_ARM_AMBA
2094
	if (!iommu_present(&amba_bustype))
2095
		bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2096
#endif
2097

2098
#ifdef CONFIG_PCI
2099 2100
	if (!iommu_present(&pci_bus_type)) {
		pci_request_acs();
2101
		bus_set_iommu(&pci_bus_type, &arm_smmu_ops);
2102
	}
2103 2104
#endif

2105 2106 2107 2108 2109 2110 2111 2112
	return 0;
}

static void __exit arm_smmu_exit(void)
{
	return platform_driver_unregister(&arm_smmu_driver);
}

2113
subsys_initcall(arm_smmu_init);
2114 2115 2116 2117 2118
module_exit(arm_smmu_exit);

MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
MODULE_LICENSE("GPL v2");