igb_main.c 189.9 KB
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/*******************************************************************************

  Intel(R) Gigabit Ethernet Linux driver
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  Copyright(c) 2007-2011 Intel Corporation.
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  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Contact Information:
  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/

#include <linux/module.h>
#include <linux/types.h>
#include <linux/init.h>
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#include <linux/bitops.h>
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#include <linux/vmalloc.h>
#include <linux/pagemap.h>
#include <linux/netdevice.h>
#include <linux/ipv6.h>
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#include <linux/slab.h>
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#include <net/checksum.h>
#include <net/ip6_checksum.h>
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#include <linux/net_tstamp.h>
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#include <linux/mii.h>
#include <linux/ethtool.h>
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#include <linux/if.h>
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#include <linux/if_vlan.h>
#include <linux/pci.h>
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#include <linux/pci-aspm.h>
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#include <linux/delay.h>
#include <linux/interrupt.h>
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#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/sctp.h>
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#include <linux/if_ether.h>
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#include <linux/aer.h>
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#include <linux/prefetch.h>
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#ifdef CONFIG_IGB_DCA
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#include <linux/dca.h>
#endif
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#include "igb.h"

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#define MAJ 3
#define MIN 0
#define BUILD 6
#define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
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__stringify(BUILD) "-k"
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char igb_driver_name[] = "igb";
char igb_driver_version[] = DRV_VERSION;
static const char igb_driver_string[] =
				"Intel(R) Gigabit Ethernet Network Driver";
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static const char igb_copyright[] = "Copyright (c) 2007-2011 Intel Corporation.";
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static const struct e1000_info *igb_info_tbl[] = {
	[board_82575] = &e1000_82575_info,
};

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static DEFINE_PCI_DEVICE_TABLE(igb_pci_tbl) = {
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_COPPER), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_FIBER), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SERDES), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_I350_SGMII), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_FIBER), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_QUAD_FIBER), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SERDES), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_SGMII), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82580_COPPER_DUAL), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SGMII), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SERDES), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_BACKPLANE), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_DH89XXCC_SFP), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_NS_SERDES), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_FIBER), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_SERDES_QUAD), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER_ET2), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82576_QUAD_COPPER), board_82575 },
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	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_COPPER), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575EB_FIBER_SERDES), board_82575 },
	{ PCI_VDEVICE(INTEL, E1000_DEV_ID_82575GB_QUAD_COPPER), board_82575 },
	/* required last entry */
	{0, }
};

MODULE_DEVICE_TABLE(pci, igb_pci_tbl);

void igb_reset(struct igb_adapter *);
static int igb_setup_all_tx_resources(struct igb_adapter *);
static int igb_setup_all_rx_resources(struct igb_adapter *);
static void igb_free_all_tx_resources(struct igb_adapter *);
static void igb_free_all_rx_resources(struct igb_adapter *);
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static void igb_setup_mrqc(struct igb_adapter *);
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static int igb_probe(struct pci_dev *, const struct pci_device_id *);
static void __devexit igb_remove(struct pci_dev *pdev);
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static void igb_init_hw_timer(struct igb_adapter *adapter);
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static int igb_sw_init(struct igb_adapter *);
static int igb_open(struct net_device *);
static int igb_close(struct net_device *);
static void igb_configure_tx(struct igb_adapter *);
static void igb_configure_rx(struct igb_adapter *);
static void igb_clean_all_tx_rings(struct igb_adapter *);
static void igb_clean_all_rx_rings(struct igb_adapter *);
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static void igb_clean_tx_ring(struct igb_ring *);
static void igb_clean_rx_ring(struct igb_ring *);
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static void igb_set_rx_mode(struct net_device *);
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static void igb_update_phy_info(unsigned long);
static void igb_watchdog(unsigned long);
static void igb_watchdog_task(struct work_struct *);
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static netdev_tx_t igb_xmit_frame(struct sk_buff *skb, struct net_device *);
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static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *dev,
						 struct rtnl_link_stats64 *stats);
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static int igb_change_mtu(struct net_device *, int);
static int igb_set_mac(struct net_device *, void *);
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static void igb_set_uta(struct igb_adapter *adapter);
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static irqreturn_t igb_intr(int irq, void *);
static irqreturn_t igb_intr_msi(int irq, void *);
static irqreturn_t igb_msix_other(int irq, void *);
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static irqreturn_t igb_msix_ring(int irq, void *);
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#ifdef CONFIG_IGB_DCA
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static void igb_update_dca(struct igb_q_vector *);
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static void igb_setup_dca(struct igb_adapter *);
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#endif /* CONFIG_IGB_DCA */
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static int igb_poll(struct napi_struct *, int);
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static bool igb_clean_tx_irq(struct igb_q_vector *);
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static bool igb_clean_rx_irq(struct igb_q_vector *, int);
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static int igb_ioctl(struct net_device *, struct ifreq *, int cmd);
static void igb_tx_timeout(struct net_device *);
static void igb_reset_task(struct work_struct *);
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static void igb_vlan_mode(struct net_device *netdev, u32 features);
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static void igb_vlan_rx_add_vid(struct net_device *, u16);
static void igb_vlan_rx_kill_vid(struct net_device *, u16);
static void igb_restore_vlan(struct igb_adapter *);
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static void igb_rar_set_qsel(struct igb_adapter *, u8 *, u32 , u8);
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static void igb_ping_all_vfs(struct igb_adapter *);
static void igb_msg_task(struct igb_adapter *);
static void igb_vmm_control(struct igb_adapter *);
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static int igb_set_vf_mac(struct igb_adapter *, int, unsigned char *);
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static void igb_restore_vf_multicasts(struct igb_adapter *adapter);
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static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac);
static int igb_ndo_set_vf_vlan(struct net_device *netdev,
			       int vf, u16 vlan, u8 qos);
static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate);
static int igb_ndo_get_vf_config(struct net_device *netdev, int vf,
				 struct ifla_vf_info *ivi);
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static void igb_check_vf_rate_limit(struct igb_adapter *);
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#ifdef CONFIG_PM
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static int igb_suspend(struct pci_dev *, pm_message_t);
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static int igb_resume(struct pci_dev *);
#endif
static void igb_shutdown(struct pci_dev *);
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#ifdef CONFIG_IGB_DCA
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static int igb_notify_dca(struct notifier_block *, unsigned long, void *);
static struct notifier_block dca_notifier = {
	.notifier_call	= igb_notify_dca,
	.next		= NULL,
	.priority	= 0
};
#endif
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#ifdef CONFIG_NET_POLL_CONTROLLER
/* for netdump / net console */
static void igb_netpoll(struct net_device *);
#endif
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#ifdef CONFIG_PCI_IOV
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static unsigned int max_vfs = 0;
module_param(max_vfs, uint, 0);
MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate "
                 "per physical function");
#endif /* CONFIG_PCI_IOV */

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static pci_ers_result_t igb_io_error_detected(struct pci_dev *,
		     pci_channel_state_t);
static pci_ers_result_t igb_io_slot_reset(struct pci_dev *);
static void igb_io_resume(struct pci_dev *);

static struct pci_error_handlers igb_err_handler = {
	.error_detected = igb_io_error_detected,
	.slot_reset = igb_io_slot_reset,
	.resume = igb_io_resume,
};


static struct pci_driver igb_driver = {
	.name     = igb_driver_name,
	.id_table = igb_pci_tbl,
	.probe    = igb_probe,
	.remove   = __devexit_p(igb_remove),
#ifdef CONFIG_PM
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	/* Power Management Hooks */
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	.suspend  = igb_suspend,
	.resume   = igb_resume,
#endif
	.shutdown = igb_shutdown,
	.err_handler = &igb_err_handler
};

MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
MODULE_DESCRIPTION("Intel(R) Gigabit Ethernet Network Driver");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);

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struct igb_reg_info {
	u32 ofs;
	char *name;
};

static const struct igb_reg_info igb_reg_info_tbl[] = {

	/* General Registers */
	{E1000_CTRL, "CTRL"},
	{E1000_STATUS, "STATUS"},
	{E1000_CTRL_EXT, "CTRL_EXT"},

	/* Interrupt Registers */
	{E1000_ICR, "ICR"},

	/* RX Registers */
	{E1000_RCTL, "RCTL"},
	{E1000_RDLEN(0), "RDLEN"},
	{E1000_RDH(0), "RDH"},
	{E1000_RDT(0), "RDT"},
	{E1000_RXDCTL(0), "RXDCTL"},
	{E1000_RDBAL(0), "RDBAL"},
	{E1000_RDBAH(0), "RDBAH"},

	/* TX Registers */
	{E1000_TCTL, "TCTL"},
	{E1000_TDBAL(0), "TDBAL"},
	{E1000_TDBAH(0), "TDBAH"},
	{E1000_TDLEN(0), "TDLEN"},
	{E1000_TDH(0), "TDH"},
	{E1000_TDT(0), "TDT"},
	{E1000_TXDCTL(0), "TXDCTL"},
	{E1000_TDFH, "TDFH"},
	{E1000_TDFT, "TDFT"},
	{E1000_TDFHS, "TDFHS"},
	{E1000_TDFPC, "TDFPC"},

	/* List Terminator */
	{}
};

/*
 * igb_regdump - register printout routine
 */
static void igb_regdump(struct e1000_hw *hw, struct igb_reg_info *reginfo)
{
	int n = 0;
	char rname[16];
	u32 regs[8];

	switch (reginfo->ofs) {
	case E1000_RDLEN(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RDLEN(n));
		break;
	case E1000_RDH(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RDH(n));
		break;
	case E1000_RDT(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RDT(n));
		break;
	case E1000_RXDCTL(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RXDCTL(n));
		break;
	case E1000_RDBAL(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RDBAL(n));
		break;
	case E1000_RDBAH(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RDBAH(n));
		break;
	case E1000_TDBAL(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_RDBAL(n));
		break;
	case E1000_TDBAH(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_TDBAH(n));
		break;
	case E1000_TDLEN(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_TDLEN(n));
		break;
	case E1000_TDH(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_TDH(n));
		break;
	case E1000_TDT(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_TDT(n));
		break;
	case E1000_TXDCTL(0):
		for (n = 0; n < 4; n++)
			regs[n] = rd32(E1000_TXDCTL(n));
		break;
	default:
		printk(KERN_INFO "%-15s %08x\n",
			reginfo->name, rd32(reginfo->ofs));
		return;
	}

	snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
	printk(KERN_INFO "%-15s ", rname);
	for (n = 0; n < 4; n++)
		printk(KERN_CONT "%08x ", regs[n]);
	printk(KERN_CONT "\n");
}

/*
 * igb_dump - Print registers, tx-rings and rx-rings
 */
static void igb_dump(struct igb_adapter *adapter)
{
	struct net_device *netdev = adapter->netdev;
	struct e1000_hw *hw = &adapter->hw;
	struct igb_reg_info *reginfo;
	struct igb_ring *tx_ring;
	union e1000_adv_tx_desc *tx_desc;
	struct my_u0 { u64 a; u64 b; } *u0;
	struct igb_ring *rx_ring;
	union e1000_adv_rx_desc *rx_desc;
	u32 staterr;
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	u16 i, n;
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	if (!netif_msg_hw(adapter))
		return;

	/* Print netdevice Info */
	if (netdev) {
		dev_info(&adapter->pdev->dev, "Net device Info\n");
		printk(KERN_INFO "Device Name     state            "
			"trans_start      last_rx\n");
		printk(KERN_INFO "%-15s %016lX %016lX %016lX\n",
		netdev->name,
		netdev->state,
		netdev->trans_start,
		netdev->last_rx);
	}

	/* Print Registers */
	dev_info(&adapter->pdev->dev, "Register Dump\n");
	printk(KERN_INFO " Register Name   Value\n");
	for (reginfo = (struct igb_reg_info *)igb_reg_info_tbl;
	     reginfo->name; reginfo++) {
		igb_regdump(hw, reginfo);
	}

	/* Print TX Ring Summary */
	if (!netdev || !netif_running(netdev))
		goto exit;

	dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
	printk(KERN_INFO "Queue [NTU] [NTC] [bi(ntc)->dma  ]"
		" leng ntw timestamp\n");
	for (n = 0; n < adapter->num_tx_queues; n++) {
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		struct igb_tx_buffer *buffer_info;
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		tx_ring = adapter->tx_ring[n];
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		buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
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		printk(KERN_INFO " %5d %5X %5X %016llX %04X %p %016llX\n",
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			   n, tx_ring->next_to_use, tx_ring->next_to_clean,
			   (u64)buffer_info->dma,
			   buffer_info->length,
			   buffer_info->next_to_watch,
			   (u64)buffer_info->time_stamp);
	}

	/* Print TX Rings */
	if (!netif_msg_tx_done(adapter))
		goto rx_ring_summary;

	dev_info(&adapter->pdev->dev, "TX Rings Dump\n");

	/* Transmit Descriptor Formats
	 *
	 * Advanced Transmit Descriptor
	 *   +--------------------------------------------------------------+
	 * 0 |         Buffer Address [63:0]                                |
	 *   +--------------------------------------------------------------+
	 * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
	 *   +--------------------------------------------------------------+
	 *   63      46 45    40 39 38 36 35 32 31   24             15       0
	 */

	for (n = 0; n < adapter->num_tx_queues; n++) {
		tx_ring = adapter->tx_ring[n];
		printk(KERN_INFO "------------------------------------\n");
		printk(KERN_INFO "TX QUEUE INDEX = %d\n", tx_ring->queue_index);
		printk(KERN_INFO "------------------------------------\n");
		printk(KERN_INFO "T [desc]     [address 63:0  ] "
			"[PlPOCIStDDM Ln] [bi->dma       ] "
			"leng  ntw timestamp        bi->skb\n");

		for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
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			struct igb_tx_buffer *buffer_info;
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			tx_desc = IGB_TX_DESC(tx_ring, i);
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			buffer_info = &tx_ring->tx_buffer_info[i];
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			u0 = (struct my_u0 *)tx_desc;
			printk(KERN_INFO "T [0x%03X]    %016llX %016llX %016llX"
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				" %04X  %p %016llX %p", i,
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				le64_to_cpu(u0->a),
				le64_to_cpu(u0->b),
				(u64)buffer_info->dma,
				buffer_info->length,
				buffer_info->next_to_watch,
				(u64)buffer_info->time_stamp,
				buffer_info->skb);
			if (i == tx_ring->next_to_use &&
				i == tx_ring->next_to_clean)
				printk(KERN_CONT " NTC/U\n");
			else if (i == tx_ring->next_to_use)
				printk(KERN_CONT " NTU\n");
			else if (i == tx_ring->next_to_clean)
				printk(KERN_CONT " NTC\n");
			else
				printk(KERN_CONT "\n");

			if (netif_msg_pktdata(adapter) && buffer_info->dma != 0)
				print_hex_dump(KERN_INFO, "",
					DUMP_PREFIX_ADDRESS,
					16, 1, phys_to_virt(buffer_info->dma),
					buffer_info->length, true);
		}
	}

	/* Print RX Rings Summary */
rx_ring_summary:
	dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
	printk(KERN_INFO "Queue [NTU] [NTC]\n");
	for (n = 0; n < adapter->num_rx_queues; n++) {
		rx_ring = adapter->rx_ring[n];
		printk(KERN_INFO " %5d %5X %5X\n", n,
			   rx_ring->next_to_use, rx_ring->next_to_clean);
	}

	/* Print RX Rings */
	if (!netif_msg_rx_status(adapter))
		goto exit;

	dev_info(&adapter->pdev->dev, "RX Rings Dump\n");

	/* Advanced Receive Descriptor (Read) Format
	 *    63                                           1        0
	 *    +-----------------------------------------------------+
	 *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
	 *    +----------------------------------------------+------+
	 *  8 |       Header Buffer Address [63:1]           |  DD  |
	 *    +-----------------------------------------------------+
	 *
	 *
	 * Advanced Receive Descriptor (Write-Back) Format
	 *
	 *   63       48 47    32 31  30      21 20 17 16   4 3     0
	 *   +------------------------------------------------------+
	 * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
	 *   | Checksum   Ident  |   |           |    | Type | Type |
	 *   +------------------------------------------------------+
	 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
	 *   +------------------------------------------------------+
	 *   63       48 47    32 31            20 19               0
	 */

	for (n = 0; n < adapter->num_rx_queues; n++) {
		rx_ring = adapter->rx_ring[n];
		printk(KERN_INFO "------------------------------------\n");
		printk(KERN_INFO "RX QUEUE INDEX = %d\n", rx_ring->queue_index);
		printk(KERN_INFO "------------------------------------\n");
		printk(KERN_INFO "R  [desc]      [ PktBuf     A0] "
			"[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
			"<-- Adv Rx Read format\n");
		printk(KERN_INFO "RWB[desc]      [PcsmIpSHl PtRs] "
			"[vl er S cks ln] ---------------- [bi->skb] "
			"<-- Adv Rx Write-Back format\n");

		for (i = 0; i < rx_ring->count; i++) {
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			struct igb_rx_buffer *buffer_info;
			buffer_info = &rx_ring->rx_buffer_info[i];
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			rx_desc = IGB_RX_DESC(rx_ring, i);
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			u0 = (struct my_u0 *)rx_desc;
			staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
			if (staterr & E1000_RXD_STAT_DD) {
				/* Descriptor Done */
				printk(KERN_INFO "RWB[0x%03X]     %016llX "
					"%016llX ---------------- %p", i,
					le64_to_cpu(u0->a),
					le64_to_cpu(u0->b),
					buffer_info->skb);
			} else {
				printk(KERN_INFO "R  [0x%03X]     %016llX "
					"%016llX %016llX %p", i,
					le64_to_cpu(u0->a),
					le64_to_cpu(u0->b),
					(u64)buffer_info->dma,
					buffer_info->skb);

				if (netif_msg_pktdata(adapter)) {
					print_hex_dump(KERN_INFO, "",
						DUMP_PREFIX_ADDRESS,
						16, 1,
						phys_to_virt(buffer_info->dma),
524 525 526 527 528 529 530 531
						IGB_RX_HDR_LEN, true);
					print_hex_dump(KERN_INFO, "",
					  DUMP_PREFIX_ADDRESS,
					  16, 1,
					  phys_to_virt(
					    buffer_info->page_dma +
					    buffer_info->page_offset),
					  PAGE_SIZE/2, true);
532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549
				}
			}

			if (i == rx_ring->next_to_use)
				printk(KERN_CONT " NTU\n");
			else if (i == rx_ring->next_to_clean)
				printk(KERN_CONT " NTC\n");
			else
				printk(KERN_CONT "\n");

		}
	}

exit:
	return;
}


P
Patrick Ohly 已提交
550 551 552 553 554 555 556 557
/**
 * igb_read_clock - read raw cycle counter (to be used by time counter)
 */
static cycle_t igb_read_clock(const struct cyclecounter *tc)
{
	struct igb_adapter *adapter =
		container_of(tc, struct igb_adapter, cycles);
	struct e1000_hw *hw = &adapter->hw;
558 559
	u64 stamp = 0;
	int shift = 0;
P
Patrick Ohly 已提交
560

561 562 563 564 565 566 567 568 569 570
	/*
	 * The timestamp latches on lowest register read. For the 82580
	 * the lowest register is SYSTIMR instead of SYSTIML.  However we never
	 * adjusted TIMINCA so SYSTIMR will just read as all 0s so ignore it.
	 */
	if (hw->mac.type == e1000_82580) {
		stamp = rd32(E1000_SYSTIMR) >> 8;
		shift = IGB_82580_TSYNC_SHIFT;
	}

571 572
	stamp |= (u64)rd32(E1000_SYSTIML) << shift;
	stamp |= (u64)rd32(E1000_SYSTIMH) << (shift + 32);
P
Patrick Ohly 已提交
573 574 575
	return stamp;
}

576
/**
577
 * igb_get_hw_dev - return device
578 579
 * used by hardware layer to print debugging information
 **/
580
struct net_device *igb_get_hw_dev(struct e1000_hw *hw)
581 582
{
	struct igb_adapter *adapter = hw->back;
583
	return adapter->netdev;
584
}
P
Patrick Ohly 已提交
585

586 587 588 589 590 591 592 593 594 595 596 597 598 599
/**
 * igb_init_module - Driver Registration Routine
 *
 * igb_init_module is the first routine called when the driver is
 * loaded. All it does is register with the PCI subsystem.
 **/
static int __init igb_init_module(void)
{
	int ret;
	printk(KERN_INFO "%s - version %s\n",
	       igb_driver_string, igb_driver_version);

	printk(KERN_INFO "%s\n", igb_copyright);

600
#ifdef CONFIG_IGB_DCA
J
Jeb Cramer 已提交
601 602
	dca_register_notify(&dca_notifier);
#endif
603
	ret = pci_register_driver(&igb_driver);
604 605 606 607 608 609 610 611 612 613 614 615 616
	return ret;
}

module_init(igb_init_module);

/**
 * igb_exit_module - Driver Exit Cleanup Routine
 *
 * igb_exit_module is called just before the driver is removed
 * from memory.
 **/
static void __exit igb_exit_module(void)
{
617
#ifdef CONFIG_IGB_DCA
J
Jeb Cramer 已提交
618 619
	dca_unregister_notify(&dca_notifier);
#endif
620 621 622 623 624
	pci_unregister_driver(&igb_driver);
}

module_exit(igb_exit_module);

625 626 627 628 629 630 631 632 633 634
#define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
/**
 * igb_cache_ring_register - Descriptor ring to register mapping
 * @adapter: board private structure to initialize
 *
 * Once we know the feature-set enabled for the device, we'll cache
 * the register offset the descriptor ring is assigned to.
 **/
static void igb_cache_ring_register(struct igb_adapter *adapter)
{
635
	int i = 0, j = 0;
636
	u32 rbase_offset = adapter->vfs_allocated_count;
637 638 639 640 641 642 643 644

	switch (adapter->hw.mac.type) {
	case e1000_82576:
		/* The queues are allocated for virtualization such that VF 0
		 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
		 * In order to avoid collision we start at the first free queue
		 * and continue consuming queues in the same sequence
		 */
645
		if (adapter->vfs_allocated_count) {
646
			for (; i < adapter->rss_queues; i++)
647 648
				adapter->rx_ring[i]->reg_idx = rbase_offset +
				                               Q_IDX_82576(i);
649
		}
650
	case e1000_82575:
651
	case e1000_82580:
652
	case e1000_i350:
653
	default:
654
		for (; i < adapter->num_rx_queues; i++)
655
			adapter->rx_ring[i]->reg_idx = rbase_offset + i;
656
		for (; j < adapter->num_tx_queues; j++)
657
			adapter->tx_ring[j]->reg_idx = rbase_offset + j;
658 659 660 661
		break;
	}
}

662 663
static void igb_free_queues(struct igb_adapter *adapter)
{
664
	int i;
665

666 667 668 669 670 671 672 673
	for (i = 0; i < adapter->num_tx_queues; i++) {
		kfree(adapter->tx_ring[i]);
		adapter->tx_ring[i] = NULL;
	}
	for (i = 0; i < adapter->num_rx_queues; i++) {
		kfree(adapter->rx_ring[i]);
		adapter->rx_ring[i] = NULL;
	}
674 675 676 677
	adapter->num_rx_queues = 0;
	adapter->num_tx_queues = 0;
}

678 679 680 681 682 683 684 685 686
/**
 * igb_alloc_queues - Allocate memory for all rings
 * @adapter: board private structure to initialize
 *
 * We allocate one ring per queue at run-time since we don't know the
 * number of queues at compile-time.
 **/
static int igb_alloc_queues(struct igb_adapter *adapter)
{
687
	struct igb_ring *ring;
688
	int i;
689
	int orig_node = adapter->node;
690

691
	for (i = 0; i < adapter->num_tx_queues; i++) {
692 693 694 695 696 697 698 699 700 701
		if (orig_node == -1) {
			int cur_node = next_online_node(adapter->node);
			if (cur_node == MAX_NUMNODES)
				cur_node = first_online_node;
			adapter->node = cur_node;
		}
		ring = kzalloc_node(sizeof(struct igb_ring), GFP_KERNEL,
				    adapter->node);
		if (!ring)
			ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
702 703
		if (!ring)
			goto err;
704
		ring->count = adapter->tx_ring_count;
705
		ring->queue_index = i;
706
		ring->dev = &adapter->pdev->dev;
707
		ring->netdev = adapter->netdev;
708
		ring->numa_node = adapter->node;
709 710
		/* For 82575, context index must be unique per ring. */
		if (adapter->hw.mac.type == e1000_82575)
711
			set_bit(IGB_RING_FLAG_TX_CTX_IDX, &ring->flags);
712
		adapter->tx_ring[i] = ring;
713
	}
714 715
	/* Restore the adapter's original node */
	adapter->node = orig_node;
716

717
	for (i = 0; i < adapter->num_rx_queues; i++) {
718 719 720 721 722 723 724 725 726 727
		if (orig_node == -1) {
			int cur_node = next_online_node(adapter->node);
			if (cur_node == MAX_NUMNODES)
				cur_node = first_online_node;
			adapter->node = cur_node;
		}
		ring = kzalloc_node(sizeof(struct igb_ring), GFP_KERNEL,
				    adapter->node);
		if (!ring)
			ring = kzalloc(sizeof(struct igb_ring), GFP_KERNEL);
728 729
		if (!ring)
			goto err;
730
		ring->count = adapter->rx_ring_count;
P
PJ Waskiewicz 已提交
731
		ring->queue_index = i;
732
		ring->dev = &adapter->pdev->dev;
733
		ring->netdev = adapter->netdev;
734
		ring->numa_node = adapter->node;
735 736
		/* set flag indicating ring supports SCTP checksum offload */
		if (adapter->hw.mac.type >= e1000_82576)
737
			set_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags);
738
		adapter->rx_ring[i] = ring;
739
	}
740 741
	/* Restore the adapter's original node */
	adapter->node = orig_node;
742 743

	igb_cache_ring_register(adapter);
744

745
	return 0;
A
Alexander Duyck 已提交
746

747
err:
748 749
	/* Restore the adapter's original node */
	adapter->node = orig_node;
750
	igb_free_queues(adapter);
751

752
	return -ENOMEM;
A
Alexander Duyck 已提交
753 754
}

A
Alexander Duyck 已提交
755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780
/**
 *  igb_write_ivar - configure ivar for given MSI-X vector
 *  @hw: pointer to the HW structure
 *  @msix_vector: vector number we are allocating to a given ring
 *  @index: row index of IVAR register to write within IVAR table
 *  @offset: column offset of in IVAR, should be multiple of 8
 *
 *  This function is intended to handle the writing of the IVAR register
 *  for adapters 82576 and newer.  The IVAR table consists of 2 columns,
 *  each containing an cause allocation for an Rx and Tx ring, and a
 *  variable number of rows depending on the number of queues supported.
 **/
static void igb_write_ivar(struct e1000_hw *hw, int msix_vector,
			   int index, int offset)
{
	u32 ivar = array_rd32(E1000_IVAR0, index);

	/* clear any bits that are currently set */
	ivar &= ~((u32)0xFF << offset);

	/* write vector and valid bit */
	ivar |= (msix_vector | E1000_IVAR_VALID) << offset;

	array_wr32(E1000_IVAR0, index, ivar);
}

781
#define IGB_N0_QUEUE -1
782
static void igb_assign_vector(struct igb_q_vector *q_vector, int msix_vector)
783
{
784
	struct igb_adapter *adapter = q_vector->adapter;
785
	struct e1000_hw *hw = &adapter->hw;
786 787
	int rx_queue = IGB_N0_QUEUE;
	int tx_queue = IGB_N0_QUEUE;
A
Alexander Duyck 已提交
788
	u32 msixbm = 0;
789

790 791 792 793
	if (q_vector->rx.ring)
		rx_queue = q_vector->rx.ring->reg_idx;
	if (q_vector->tx.ring)
		tx_queue = q_vector->tx.ring->reg_idx;
A
Alexander Duyck 已提交
794 795 796

	switch (hw->mac.type) {
	case e1000_82575:
797 798 799 800
		/* The 82575 assigns vectors using a bitmask, which matches the
		   bitmask for the EICR/EIMS/EIMC registers.  To assign one
		   or more queues to a vector, we write the appropriate bits
		   into the MSIXBM register for that vector. */
801
		if (rx_queue > IGB_N0_QUEUE)
802
			msixbm = E1000_EICR_RX_QUEUE0 << rx_queue;
803
		if (tx_queue > IGB_N0_QUEUE)
804
			msixbm |= E1000_EICR_TX_QUEUE0 << tx_queue;
805 806
		if (!adapter->msix_entries && msix_vector == 0)
			msixbm |= E1000_EIMS_OTHER;
807
		array_wr32(E1000_MSIXBM(0), msix_vector, msixbm);
808
		q_vector->eims_value = msixbm;
A
Alexander Duyck 已提交
809 810
		break;
	case e1000_82576:
A
Alexander Duyck 已提交
811 812 813 814 815 816 817 818 819 820 821 822 823 824
		/*
		 * 82576 uses a table that essentially consists of 2 columns
		 * with 8 rows.  The ordering is column-major so we use the
		 * lower 3 bits as the row index, and the 4th bit as the
		 * column offset.
		 */
		if (rx_queue > IGB_N0_QUEUE)
			igb_write_ivar(hw, msix_vector,
				       rx_queue & 0x7,
				       (rx_queue & 0x8) << 1);
		if (tx_queue > IGB_N0_QUEUE)
			igb_write_ivar(hw, msix_vector,
				       tx_queue & 0x7,
				       ((tx_queue & 0x8) << 1) + 8);
825
		q_vector->eims_value = 1 << msix_vector;
A
Alexander Duyck 已提交
826
		break;
827
	case e1000_82580:
828
	case e1000_i350:
A
Alexander Duyck 已提交
829 830 831 832 833 834 835 836 837 838 839 840 841 842 843
		/*
		 * On 82580 and newer adapters the scheme is similar to 82576
		 * however instead of ordering column-major we have things
		 * ordered row-major.  So we traverse the table by using
		 * bit 0 as the column offset, and the remaining bits as the
		 * row index.
		 */
		if (rx_queue > IGB_N0_QUEUE)
			igb_write_ivar(hw, msix_vector,
				       rx_queue >> 1,
				       (rx_queue & 0x1) << 4);
		if (tx_queue > IGB_N0_QUEUE)
			igb_write_ivar(hw, msix_vector,
				       tx_queue >> 1,
				       ((tx_queue & 0x1) << 4) + 8);
844 845
		q_vector->eims_value = 1 << msix_vector;
		break;
A
Alexander Duyck 已提交
846 847 848 849
	default:
		BUG();
		break;
	}
850 851 852 853 854 855

	/* add q_vector eims value to global eims_enable_mask */
	adapter->eims_enable_mask |= q_vector->eims_value;

	/* configure q_vector to set itr on first interrupt */
	q_vector->set_itr = 1;
856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872
}

/**
 * igb_configure_msix - Configure MSI-X hardware
 *
 * igb_configure_msix sets up the hardware to properly
 * generate MSI-X interrupts.
 **/
static void igb_configure_msix(struct igb_adapter *adapter)
{
	u32 tmp;
	int i, vector = 0;
	struct e1000_hw *hw = &adapter->hw;

	adapter->eims_enable_mask = 0;

	/* set vector for other causes, i.e. link changes */
A
Alexander Duyck 已提交
873 874
	switch (hw->mac.type) {
	case e1000_82575:
875 876 877 878 879 880 881 882 883
		tmp = rd32(E1000_CTRL_EXT);
		/* enable MSI-X PBA support*/
		tmp |= E1000_CTRL_EXT_PBA_CLR;

		/* Auto-Mask interrupts upon ICR read. */
		tmp |= E1000_CTRL_EXT_EIAME;
		tmp |= E1000_CTRL_EXT_IRCA;

		wr32(E1000_CTRL_EXT, tmp);
884 885 886 887

		/* enable msix_other interrupt */
		array_wr32(E1000_MSIXBM(0), vector++,
		                      E1000_EIMS_OTHER);
P
PJ Waskiewicz 已提交
888
		adapter->eims_other = E1000_EIMS_OTHER;
889

A
Alexander Duyck 已提交
890 891 892
		break;

	case e1000_82576:
893
	case e1000_82580:
894
	case e1000_i350:
895 896 897 898 899 900 901 902
		/* Turn on MSI-X capability first, or our settings
		 * won't stick.  And it will take days to debug. */
		wr32(E1000_GPIE, E1000_GPIE_MSIX_MODE |
		                E1000_GPIE_PBA | E1000_GPIE_EIAME |
		                E1000_GPIE_NSICR);

		/* enable msix_other interrupt */
		adapter->eims_other = 1 << vector;
A
Alexander Duyck 已提交
903 904
		tmp = (vector++ | E1000_IVAR_VALID) << 8;

905
		wr32(E1000_IVAR_MISC, tmp);
A
Alexander Duyck 已提交
906 907 908 909 910
		break;
	default:
		/* do nothing, since nothing else supports MSI-X */
		break;
	} /* switch (hw->mac.type) */
911 912 913

	adapter->eims_enable_mask |= adapter->eims_other;

914 915
	for (i = 0; i < adapter->num_q_vectors; i++)
		igb_assign_vector(adapter->q_vector[i], vector++);
916

917 918 919 920 921 922 923 924 925 926 927 928
	wrfl();
}

/**
 * igb_request_msix - Initialize MSI-X interrupts
 *
 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
 * kernel.
 **/
static int igb_request_msix(struct igb_adapter *adapter)
{
	struct net_device *netdev = adapter->netdev;
929
	struct e1000_hw *hw = &adapter->hw;
930 931
	int i, err = 0, vector = 0;

932
	err = request_irq(adapter->msix_entries[vector].vector,
933
	                  igb_msix_other, 0, netdev->name, adapter);
934 935 936 937 938 939 940 941 942
	if (err)
		goto out;
	vector++;

	for (i = 0; i < adapter->num_q_vectors; i++) {
		struct igb_q_vector *q_vector = adapter->q_vector[i];

		q_vector->itr_register = hw->hw_addr + E1000_EITR(vector);

943
		if (q_vector->rx.ring && q_vector->tx.ring)
944
			sprintf(q_vector->name, "%s-TxRx-%u", netdev->name,
945 946
				q_vector->rx.ring->queue_index);
		else if (q_vector->tx.ring)
947
			sprintf(q_vector->name, "%s-tx-%u", netdev->name,
948 949
				q_vector->tx.ring->queue_index);
		else if (q_vector->rx.ring)
950
			sprintf(q_vector->name, "%s-rx-%u", netdev->name,
951
				q_vector->rx.ring->queue_index);
952
		else
953 954
			sprintf(q_vector->name, "%s-unused", netdev->name);

955
		err = request_irq(adapter->msix_entries[vector].vector,
956
		                  igb_msix_ring, 0, q_vector->name,
957
		                  q_vector);
958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974
		if (err)
			goto out;
		vector++;
	}

	igb_configure_msix(adapter);
	return 0;
out:
	return err;
}

static void igb_reset_interrupt_capability(struct igb_adapter *adapter)
{
	if (adapter->msix_entries) {
		pci_disable_msix(adapter->pdev);
		kfree(adapter->msix_entries);
		adapter->msix_entries = NULL;
975
	} else if (adapter->flags & IGB_FLAG_HAS_MSI) {
976
		pci_disable_msi(adapter->pdev);
977
	}
978 979
}

980 981 982 983 984 985 986 987 988 989 990 991 992 993 994
/**
 * igb_free_q_vectors - Free memory allocated for interrupt vectors
 * @adapter: board private structure to initialize
 *
 * This function frees the memory allocated to the q_vectors.  In addition if
 * NAPI is enabled it will delete any references to the NAPI struct prior
 * to freeing the q_vector.
 **/
static void igb_free_q_vectors(struct igb_adapter *adapter)
{
	int v_idx;

	for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
		struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
		adapter->q_vector[v_idx] = NULL;
995 996
		if (!q_vector)
			continue;
997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014
		netif_napi_del(&q_vector->napi);
		kfree(q_vector);
	}
	adapter->num_q_vectors = 0;
}

/**
 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
 *
 * This function resets the device so that it has 0 rx queues, tx queues, and
 * MSI-X interrupts allocated.
 */
static void igb_clear_interrupt_scheme(struct igb_adapter *adapter)
{
	igb_free_queues(adapter);
	igb_free_q_vectors(adapter);
	igb_reset_interrupt_capability(adapter);
}
1015 1016 1017 1018 1019 1020 1021

/**
 * igb_set_interrupt_capability - set MSI or MSI-X if supported
 *
 * Attempt to configure interrupts using the best available
 * capabilities of the hardware and kernel.
 **/
1022
static int igb_set_interrupt_capability(struct igb_adapter *adapter)
1023 1024 1025 1026
{
	int err;
	int numvecs, i;

1027
	/* Number of supported queues. */
1028
	adapter->num_rx_queues = adapter->rss_queues;
1029 1030 1031 1032
	if (adapter->vfs_allocated_count)
		adapter->num_tx_queues = 1;
	else
		adapter->num_tx_queues = adapter->rss_queues;
1033

1034 1035 1036
	/* start with one vector for every rx queue */
	numvecs = adapter->num_rx_queues;

D
Daniel Mack 已提交
1037
	/* if tx handler is separate add 1 for every tx queue */
1038 1039
	if (!(adapter->flags & IGB_FLAG_QUEUE_PAIRS))
		numvecs += adapter->num_tx_queues;
1040 1041 1042 1043 1044 1045

	/* store the number of vectors reserved for queues */
	adapter->num_q_vectors = numvecs;

	/* add 1 vector for link status interrupts */
	numvecs++;
1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057
	adapter->msix_entries = kcalloc(numvecs, sizeof(struct msix_entry),
					GFP_KERNEL);
	if (!adapter->msix_entries)
		goto msi_only;

	for (i = 0; i < numvecs; i++)
		adapter->msix_entries[i].entry = i;

	err = pci_enable_msix(adapter->pdev,
			      adapter->msix_entries,
			      numvecs);
	if (err == 0)
1058
		goto out;
1059 1060 1061 1062 1063

	igb_reset_interrupt_capability(adapter);

	/* If we can't do MSI-X, try MSI */
msi_only:
1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074
#ifdef CONFIG_PCI_IOV
	/* disable SR-IOV for non MSI-X configurations */
	if (adapter->vf_data) {
		struct e1000_hw *hw = &adapter->hw;
		/* disable iov and allow time for transactions to clear */
		pci_disable_sriov(adapter->pdev);
		msleep(500);

		kfree(adapter->vf_data);
		adapter->vf_data = NULL;
		wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
1075
		wrfl();
1076 1077 1078 1079
		msleep(100);
		dev_info(&adapter->pdev->dev, "IOV Disabled\n");
	}
#endif
1080
	adapter->vfs_allocated_count = 0;
1081
	adapter->rss_queues = 1;
1082
	adapter->flags |= IGB_FLAG_QUEUE_PAIRS;
1083
	adapter->num_rx_queues = 1;
1084
	adapter->num_tx_queues = 1;
1085
	adapter->num_q_vectors = 1;
1086
	if (!pci_enable_msi(adapter->pdev))
1087
		adapter->flags |= IGB_FLAG_HAS_MSI;
1088
out:
1089 1090 1091 1092
	/* Notify the stack of the (possibly) reduced queue counts. */
	netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
	return netif_set_real_num_rx_queues(adapter->netdev,
					    adapter->num_rx_queues);
1093 1094
}

1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106
/**
 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
 * @adapter: board private structure to initialize
 *
 * We allocate one q_vector per queue interrupt.  If allocation fails we
 * return -ENOMEM.
 **/
static int igb_alloc_q_vectors(struct igb_adapter *adapter)
{
	struct igb_q_vector *q_vector;
	struct e1000_hw *hw = &adapter->hw;
	int v_idx;
1107
	int orig_node = adapter->node;
1108 1109

	for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124
		if ((adapter->num_q_vectors == (adapter->num_rx_queues +
						adapter->num_tx_queues)) &&
		    (adapter->num_rx_queues == v_idx))
			adapter->node = orig_node;
		if (orig_node == -1) {
			int cur_node = next_online_node(adapter->node);
			if (cur_node == MAX_NUMNODES)
				cur_node = first_online_node;
			adapter->node = cur_node;
		}
		q_vector = kzalloc_node(sizeof(struct igb_q_vector), GFP_KERNEL,
					adapter->node);
		if (!q_vector)
			q_vector = kzalloc(sizeof(struct igb_q_vector),
					   GFP_KERNEL);
1125 1126 1127 1128 1129 1130 1131 1132
		if (!q_vector)
			goto err_out;
		q_vector->adapter = adapter;
		q_vector->itr_register = hw->hw_addr + E1000_EITR(0);
		q_vector->itr_val = IGB_START_ITR;
		netif_napi_add(adapter->netdev, &q_vector->napi, igb_poll, 64);
		adapter->q_vector[v_idx] = q_vector;
	}
1133 1134 1135
	/* Restore the adapter's original node */
	adapter->node = orig_node;

1136 1137 1138
	return 0;

err_out:
1139 1140
	/* Restore the adapter's original node */
	adapter->node = orig_node;
1141
	igb_free_q_vectors(adapter);
1142 1143 1144 1145 1146 1147
	return -ENOMEM;
}

static void igb_map_rx_ring_to_vector(struct igb_adapter *adapter,
                                      int ring_idx, int v_idx)
{
1148
	struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1149

1150 1151 1152
	q_vector->rx.ring = adapter->rx_ring[ring_idx];
	q_vector->rx.ring->q_vector = q_vector;
	q_vector->rx.count++;
1153 1154 1155
	q_vector->itr_val = adapter->rx_itr_setting;
	if (q_vector->itr_val && q_vector->itr_val <= 3)
		q_vector->itr_val = IGB_START_ITR;
1156 1157 1158 1159 1160
}

static void igb_map_tx_ring_to_vector(struct igb_adapter *adapter,
                                      int ring_idx, int v_idx)
{
1161
	struct igb_q_vector *q_vector = adapter->q_vector[v_idx];
1162

1163 1164 1165
	q_vector->tx.ring = adapter->tx_ring[ring_idx];
	q_vector->tx.ring->q_vector = q_vector;
	q_vector->tx.count++;
1166
	q_vector->itr_val = adapter->tx_itr_setting;
1167
	q_vector->tx.work_limit = adapter->tx_work_limit;
1168 1169
	if (q_vector->itr_val && q_vector->itr_val <= 3)
		q_vector->itr_val = IGB_START_ITR;
1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213
}

/**
 * igb_map_ring_to_vector - maps allocated queues to vectors
 *
 * This function maps the recently allocated queues to vectors.
 **/
static int igb_map_ring_to_vector(struct igb_adapter *adapter)
{
	int i;
	int v_idx = 0;

	if ((adapter->num_q_vectors < adapter->num_rx_queues) ||
	    (adapter->num_q_vectors < adapter->num_tx_queues))
		return -ENOMEM;

	if (adapter->num_q_vectors >=
	    (adapter->num_rx_queues + adapter->num_tx_queues)) {
		for (i = 0; i < adapter->num_rx_queues; i++)
			igb_map_rx_ring_to_vector(adapter, i, v_idx++);
		for (i = 0; i < adapter->num_tx_queues; i++)
			igb_map_tx_ring_to_vector(adapter, i, v_idx++);
	} else {
		for (i = 0; i < adapter->num_rx_queues; i++) {
			if (i < adapter->num_tx_queues)
				igb_map_tx_ring_to_vector(adapter, i, v_idx);
			igb_map_rx_ring_to_vector(adapter, i, v_idx++);
		}
		for (; i < adapter->num_tx_queues; i++)
			igb_map_tx_ring_to_vector(adapter, i, v_idx++);
	}
	return 0;
}

/**
 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
 *
 * This function initializes the interrupts and allocates all of the queues.
 **/
static int igb_init_interrupt_scheme(struct igb_adapter *adapter)
{
	struct pci_dev *pdev = adapter->pdev;
	int err;

1214 1215 1216
	err = igb_set_interrupt_capability(adapter);
	if (err)
		return err;
1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246

	err = igb_alloc_q_vectors(adapter);
	if (err) {
		dev_err(&pdev->dev, "Unable to allocate memory for vectors\n");
		goto err_alloc_q_vectors;
	}

	err = igb_alloc_queues(adapter);
	if (err) {
		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
		goto err_alloc_queues;
	}

	err = igb_map_ring_to_vector(adapter);
	if (err) {
		dev_err(&pdev->dev, "Invalid q_vector to ring mapping\n");
		goto err_map_queues;
	}


	return 0;
err_map_queues:
	igb_free_queues(adapter);
err_alloc_queues:
	igb_free_q_vectors(adapter);
err_alloc_q_vectors:
	igb_reset_interrupt_capability(adapter);
	return err;
}

1247 1248 1249 1250 1251 1252 1253 1254 1255
/**
 * igb_request_irq - initialize interrupts
 *
 * Attempts to configure interrupts using the best available
 * capabilities of the hardware and kernel.
 **/
static int igb_request_irq(struct igb_adapter *adapter)
{
	struct net_device *netdev = adapter->netdev;
1256
	struct pci_dev *pdev = adapter->pdev;
1257 1258 1259 1260
	int err = 0;

	if (adapter->msix_entries) {
		err = igb_request_msix(adapter);
P
PJ Waskiewicz 已提交
1261
		if (!err)
1262 1263
			goto request_done;
		/* fall back to MSI */
1264
		igb_clear_interrupt_scheme(adapter);
1265
		if (!pci_enable_msi(adapter->pdev))
1266
			adapter->flags |= IGB_FLAG_HAS_MSI;
1267 1268
		igb_free_all_tx_resources(adapter);
		igb_free_all_rx_resources(adapter);
1269
		adapter->num_tx_queues = 1;
1270
		adapter->num_rx_queues = 1;
1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286
		adapter->num_q_vectors = 1;
		err = igb_alloc_q_vectors(adapter);
		if (err) {
			dev_err(&pdev->dev,
			        "Unable to allocate memory for vectors\n");
			goto request_done;
		}
		err = igb_alloc_queues(adapter);
		if (err) {
			dev_err(&pdev->dev,
			        "Unable to allocate memory for queues\n");
			igb_free_q_vectors(adapter);
			goto request_done;
		}
		igb_setup_all_tx_resources(adapter);
		igb_setup_all_rx_resources(adapter);
P
PJ Waskiewicz 已提交
1287
	} else {
1288
		igb_assign_vector(adapter->q_vector[0], 0);
1289
	}
P
PJ Waskiewicz 已提交
1290

1291
	if (adapter->flags & IGB_FLAG_HAS_MSI) {
1292
		err = request_irq(adapter->pdev->irq, igb_intr_msi, 0,
1293
				  netdev->name, adapter);
1294 1295
		if (!err)
			goto request_done;
1296

1297 1298
		/* fall back to legacy interrupts */
		igb_reset_interrupt_capability(adapter);
1299
		adapter->flags &= ~IGB_FLAG_HAS_MSI;
1300 1301
	}

1302
	err = request_irq(adapter->pdev->irq, igb_intr, IRQF_SHARED,
1303
			  netdev->name, adapter);
1304

A
Andy Gospodarek 已提交
1305
	if (err)
1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317
		dev_err(&adapter->pdev->dev, "Error %d getting interrupt\n",
			err);

request_done:
	return err;
}

static void igb_free_irq(struct igb_adapter *adapter)
{
	if (adapter->msix_entries) {
		int vector = 0, i;

1318
		free_irq(adapter->msix_entries[vector++].vector, adapter);
1319

1320 1321 1322 1323 1324 1325 1326
		for (i = 0; i < adapter->num_q_vectors; i++) {
			struct igb_q_vector *q_vector = adapter->q_vector[i];
			free_irq(adapter->msix_entries[vector++].vector,
			         q_vector);
		}
	} else {
		free_irq(adapter->pdev->irq, adapter);
1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337
	}
}

/**
 * igb_irq_disable - Mask off interrupt generation on the NIC
 * @adapter: board private structure
 **/
static void igb_irq_disable(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;

1338 1339 1340 1341 1342
	/*
	 * we need to be careful when disabling interrupts.  The VFs are also
	 * mapped into these registers and so clearing the bits can cause
	 * issues on the VF drivers so we only need to clear what we set
	 */
1343
	if (adapter->msix_entries) {
1344 1345 1346 1347 1348
		u32 regval = rd32(E1000_EIAM);
		wr32(E1000_EIAM, regval & ~adapter->eims_enable_mask);
		wr32(E1000_EIMC, adapter->eims_enable_mask);
		regval = rd32(E1000_EIAC);
		wr32(E1000_EIAC, regval & ~adapter->eims_enable_mask);
1349
	}
P
PJ Waskiewicz 已提交
1350 1351

	wr32(E1000_IAM, 0);
1352 1353
	wr32(E1000_IMC, ~0);
	wrfl();
1354 1355 1356 1357 1358 1359 1360
	if (adapter->msix_entries) {
		int i;
		for (i = 0; i < adapter->num_q_vectors; i++)
			synchronize_irq(adapter->msix_entries[i].vector);
	} else {
		synchronize_irq(adapter->pdev->irq);
	}
1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371
}

/**
 * igb_irq_enable - Enable default interrupt generation settings
 * @adapter: board private structure
 **/
static void igb_irq_enable(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;

	if (adapter->msix_entries) {
1372
		u32 ims = E1000_IMS_LSC | E1000_IMS_DOUTSYNC;
1373 1374 1375 1376
		u32 regval = rd32(E1000_EIAC);
		wr32(E1000_EIAC, regval | adapter->eims_enable_mask);
		regval = rd32(E1000_EIAM);
		wr32(E1000_EIAM, regval | adapter->eims_enable_mask);
P
PJ Waskiewicz 已提交
1377
		wr32(E1000_EIMS, adapter->eims_enable_mask);
1378
		if (adapter->vfs_allocated_count) {
1379
			wr32(E1000_MBVFIMR, 0xFF);
1380 1381
			ims |= E1000_IMS_VMMB;
		}
1382 1383 1384
		if (adapter->hw.mac.type == e1000_82580)
			ims |= E1000_IMS_DRSTA;

1385
		wr32(E1000_IMS, ims);
P
PJ Waskiewicz 已提交
1386
	} else {
1387 1388 1389 1390
		wr32(E1000_IMS, IMS_ENABLE_MASK |
				E1000_IMS_DRSTA);
		wr32(E1000_IAM, IMS_ENABLE_MASK |
				E1000_IMS_DRSTA);
P
PJ Waskiewicz 已提交
1391
	}
1392 1393 1394 1395
}

static void igb_update_mng_vlan(struct igb_adapter *adapter)
{
1396
	struct e1000_hw *hw = &adapter->hw;
1397 1398
	u16 vid = adapter->hw.mng_cookie.vlan_id;
	u16 old_vid = adapter->mng_vlan_id;
1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409

	if (hw->mng_cookie.status & E1000_MNG_DHCP_COOKIE_STATUS_VLAN) {
		/* add VID to filter table */
		igb_vfta_set(hw, vid, true);
		adapter->mng_vlan_id = vid;
	} else {
		adapter->mng_vlan_id = IGB_MNG_VLAN_NONE;
	}

	if ((old_vid != (u16)IGB_MNG_VLAN_NONE) &&
	    (vid != old_vid) &&
J
Jiri Pirko 已提交
1410
	    !test_bit(old_vid, adapter->active_vlans)) {
1411 1412
		/* remove VID from filter table */
		igb_vfta_set(hw, old_vid, false);
1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465
	}
}

/**
 * igb_release_hw_control - release control of the h/w to f/w
 * @adapter: address of board private structure
 *
 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 * For ASF and Pass Through versions of f/w this means that the
 * driver is no longer loaded.
 *
 **/
static void igb_release_hw_control(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 ctrl_ext;

	/* Let firmware take over control of h/w */
	ctrl_ext = rd32(E1000_CTRL_EXT);
	wr32(E1000_CTRL_EXT,
			ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
}

/**
 * igb_get_hw_control - get control of the h/w from f/w
 * @adapter: address of board private structure
 *
 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 * For ASF and Pass Through versions of f/w this means that
 * the driver is loaded.
 *
 **/
static void igb_get_hw_control(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 ctrl_ext;

	/* Let firmware know the driver has taken over */
	ctrl_ext = rd32(E1000_CTRL_EXT);
	wr32(E1000_CTRL_EXT,
			ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
}

/**
 * igb_configure - configure the hardware for RX and TX
 * @adapter: private board structure
 **/
static void igb_configure(struct igb_adapter *adapter)
{
	struct net_device *netdev = adapter->netdev;
	int i;

	igb_get_hw_control(adapter);
1466
	igb_set_rx_mode(netdev);
1467 1468 1469

	igb_restore_vlan(adapter);

1470
	igb_setup_tctl(adapter);
1471
	igb_setup_mrqc(adapter);
1472
	igb_setup_rctl(adapter);
1473 1474

	igb_configure_tx(adapter);
1475
	igb_configure_rx(adapter);
1476 1477 1478

	igb_rx_fifo_flush_82575(&adapter->hw);

1479
	/* call igb_desc_unused which always leaves
1480 1481 1482
	 * at least 1 descriptor unused to make sure
	 * next_to_use != next_to_clean */
	for (i = 0; i < adapter->num_rx_queues; i++) {
1483
		struct igb_ring *ring = adapter->rx_ring[i];
1484
		igb_alloc_rx_buffers(ring, igb_desc_unused(ring));
1485 1486 1487
	}
}

1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510
/**
 * igb_power_up_link - Power up the phy/serdes link
 * @adapter: address of board private structure
 **/
void igb_power_up_link(struct igb_adapter *adapter)
{
	if (adapter->hw.phy.media_type == e1000_media_type_copper)
		igb_power_up_phy_copper(&adapter->hw);
	else
		igb_power_up_serdes_link_82575(&adapter->hw);
}

/**
 * igb_power_down_link - Power down the phy/serdes link
 * @adapter: address of board private structure
 */
static void igb_power_down_link(struct igb_adapter *adapter)
{
	if (adapter->hw.phy.media_type == e1000_media_type_copper)
		igb_power_down_phy_copper_82575(&adapter->hw);
	else
		igb_shutdown_serdes_link_82575(&adapter->hw);
}
1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525

/**
 * igb_up - Open the interface and prepare it to handle traffic
 * @adapter: board private structure
 **/
int igb_up(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	int i;

	/* hardware has been reset, we need to reload some things */
	igb_configure(adapter);

	clear_bit(__IGB_DOWN, &adapter->state);

1526 1527 1528 1529
	for (i = 0; i < adapter->num_q_vectors; i++) {
		struct igb_q_vector *q_vector = adapter->q_vector[i];
		napi_enable(&q_vector->napi);
	}
P
PJ Waskiewicz 已提交
1530
	if (adapter->msix_entries)
1531
		igb_configure_msix(adapter);
1532 1533
	else
		igb_assign_vector(adapter->q_vector[0], 0);
1534 1535 1536 1537 1538

	/* Clear any pending interrupts. */
	rd32(E1000_ICR);
	igb_irq_enable(adapter);

1539 1540 1541 1542 1543 1544 1545
	/* notify VFs that reset has been completed */
	if (adapter->vfs_allocated_count) {
		u32 reg_data = rd32(E1000_CTRL_EXT);
		reg_data |= E1000_CTRL_EXT_PFRSTD;
		wr32(E1000_CTRL_EXT, reg_data);
	}

1546 1547
	netif_tx_start_all_queues(adapter->netdev);

1548 1549 1550 1551
	/* start the watchdog. */
	hw->mac.get_link_status = 1;
	schedule_work(&adapter->watchdog_task);

1552 1553 1554 1555 1556 1557
	return 0;
}

void igb_down(struct igb_adapter *adapter)
{
	struct net_device *netdev = adapter->netdev;
1558
	struct e1000_hw *hw = &adapter->hw;
1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570
	u32 tctl, rctl;
	int i;

	/* signal that we're down so the interrupt handler does not
	 * reschedule our watchdog timer */
	set_bit(__IGB_DOWN, &adapter->state);

	/* disable receives in the hardware */
	rctl = rd32(E1000_RCTL);
	wr32(E1000_RCTL, rctl & ~E1000_RCTL_EN);
	/* flush and sleep below */

1571
	netif_tx_stop_all_queues(netdev);
1572 1573 1574 1575 1576 1577 1578 1579 1580

	/* disable transmits in the hardware */
	tctl = rd32(E1000_TCTL);
	tctl &= ~E1000_TCTL_EN;
	wr32(E1000_TCTL, tctl);
	/* flush both disables and wait for them to finish */
	wrfl();
	msleep(10);

1581 1582 1583 1584
	for (i = 0; i < adapter->num_q_vectors; i++) {
		struct igb_q_vector *q_vector = adapter->q_vector[i];
		napi_disable(&q_vector->napi);
	}
1585 1586 1587 1588 1589 1590 1591

	igb_irq_disable(adapter);

	del_timer_sync(&adapter->watchdog_timer);
	del_timer_sync(&adapter->phy_info_timer);

	netif_carrier_off(netdev);
1592 1593

	/* record the stats before reset*/
E
Eric Dumazet 已提交
1594 1595 1596
	spin_lock(&adapter->stats64_lock);
	igb_update_stats(adapter, &adapter->stats64);
	spin_unlock(&adapter->stats64_lock);
1597

1598 1599 1600
	adapter->link_speed = 0;
	adapter->link_duplex = 0;

1601 1602
	if (!pci_channel_offline(adapter->pdev))
		igb_reset(adapter);
1603 1604
	igb_clean_all_tx_rings(adapter);
	igb_clean_all_rx_rings(adapter);
1605 1606 1607 1608 1609
#ifdef CONFIG_IGB_DCA

	/* since we reset the hardware DCA settings were cleared */
	igb_setup_dca(adapter);
#endif
1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623
}

void igb_reinit_locked(struct igb_adapter *adapter)
{
	WARN_ON(in_interrupt());
	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
		msleep(1);
	igb_down(adapter);
	igb_up(adapter);
	clear_bit(__IGB_RESETTING, &adapter->state);
}

void igb_reset(struct igb_adapter *adapter)
{
1624
	struct pci_dev *pdev = adapter->pdev;
1625
	struct e1000_hw *hw = &adapter->hw;
A
Alexander Duyck 已提交
1626 1627
	struct e1000_mac_info *mac = &hw->mac;
	struct e1000_fc_info *fc = &hw->fc;
1628 1629 1630 1631 1632 1633
	u32 pba = 0, tx_space, min_tx_space, min_rx_space;
	u16 hwm;

	/* Repartition Pba for greater than 9k mtu
	 * To take effect CTRL.RST is required.
	 */
1634
	switch (mac->type) {
1635
	case e1000_i350:
1636 1637 1638 1639
	case e1000_82580:
		pba = rd32(E1000_RXPBS);
		pba = igb_rxpbs_adjust_82580(pba);
		break;
1640
	case e1000_82576:
1641 1642
		pba = rd32(E1000_RXPBS);
		pba &= E1000_RXPBS_SIZE_MASK_82576;
1643 1644 1645 1646 1647
		break;
	case e1000_82575:
	default:
		pba = E1000_PBA_34K;
		break;
A
Alexander Duyck 已提交
1648
	}
1649

A
Alexander Duyck 已提交
1650 1651
	if ((adapter->max_frame_size > ETH_FRAME_LEN + ETH_FCS_LEN) &&
	    (mac->type < e1000_82576)) {
1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668
		/* adjust PBA for jumbo frames */
		wr32(E1000_PBA, pba);

		/* To maintain wire speed transmits, the Tx FIFO should be
		 * large enough to accommodate two full transmit packets,
		 * rounded up to the next 1KB and expressed in KB.  Likewise,
		 * the Rx FIFO should be large enough to accommodate at least
		 * one full receive packet and is similarly rounded up and
		 * expressed in KB. */
		pba = rd32(E1000_PBA);
		/* upper 16 bits has Tx packet buffer allocation size in KB */
		tx_space = pba >> 16;
		/* lower 16 bits has Rx packet buffer allocation size in KB */
		pba &= 0xffff;
		/* the tx fifo also stores 16 bytes of information about the tx
		 * but don't include ethernet FCS because hardware appends it */
		min_tx_space = (adapter->max_frame_size +
1669
				sizeof(union e1000_adv_tx_desc) -
1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689
				ETH_FCS_LEN) * 2;
		min_tx_space = ALIGN(min_tx_space, 1024);
		min_tx_space >>= 10;
		/* software strips receive CRC, so leave room for it */
		min_rx_space = adapter->max_frame_size;
		min_rx_space = ALIGN(min_rx_space, 1024);
		min_rx_space >>= 10;

		/* If current Tx allocation is less than the min Tx FIFO size,
		 * and the min Tx FIFO size is less than the current Rx FIFO
		 * allocation, take space away from current Rx allocation */
		if (tx_space < min_tx_space &&
		    ((min_tx_space - tx_space) < pba)) {
			pba = pba - (min_tx_space - tx_space);

			/* if short on rx space, rx wins and must trump tx
			 * adjustment */
			if (pba < min_rx_space)
				pba = min_rx_space;
		}
A
Alexander Duyck 已提交
1690
		wr32(E1000_PBA, pba);
1691 1692 1693 1694 1695 1696 1697 1698 1699
	}

	/* flow control settings */
	/* The high water mark must be low enough to fit one full frame
	 * (or the size used for early receive) above it in the Rx FIFO.
	 * Set it to the lower of:
	 * - 90% of the Rx FIFO size, or
	 * - the full Rx FIFO size minus one full frame */
	hwm = min(((pba << 10) * 9 / 10),
A
Alexander Duyck 已提交
1700
			((pba << 10) - 2 * adapter->max_frame_size));
1701

1702 1703
	fc->high_water = hwm & 0xFFF0;	/* 16-byte granularity */
	fc->low_water = fc->high_water - 16;
1704 1705
	fc->pause_time = 0xFFFF;
	fc->send_xon = 1;
1706
	fc->current_mode = fc->requested_mode;
1707

1708 1709 1710 1711
	/* disable receive for all VFs and wait one second */
	if (adapter->vfs_allocated_count) {
		int i;
		for (i = 0 ; i < adapter->vfs_allocated_count; i++)
G
Greg Rose 已提交
1712
			adapter->vf_data[i].flags &= IGB_VF_FLAG_PF_SET_MAC;
1713 1714

		/* ping all the active vfs to let them know we are going down */
1715
		igb_ping_all_vfs(adapter);
1716 1717 1718 1719 1720 1721

		/* disable transmits and receives */
		wr32(E1000_VFRE, 0);
		wr32(E1000_VFTE, 0);
	}

1722
	/* Allow time for pending master requests to run */
1723
	hw->mac.ops.reset_hw(hw);
1724 1725
	wr32(E1000_WUC, 0);

1726
	if (hw->mac.ops.init_hw(hw))
1727
		dev_err(&pdev->dev, "Hardware Error\n");
1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779
	if (hw->mac.type > e1000_82580) {
		if (adapter->flags & IGB_FLAG_DMAC) {
			u32 reg;

			/*
			 * DMA Coalescing high water mark needs to be higher
			 * than * the * Rx threshold.  The Rx threshold is
			 * currently * pba - 6, so we * should use a high water
			 * mark of pba * - 4. */
			hwm = (pba - 4) << 10;

			reg = (((pba-6) << E1000_DMACR_DMACTHR_SHIFT)
			       & E1000_DMACR_DMACTHR_MASK);

			/* transition to L0x or L1 if available..*/
			reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);

			/* watchdog timer= +-1000 usec in 32usec intervals */
			reg |= (1000 >> 5);
			wr32(E1000_DMACR, reg);

			/* no lower threshold to disable coalescing(smart fifb)
			 * -UTRESH=0*/
			wr32(E1000_DMCRTRH, 0);

			/* set hwm to PBA -  2 * max frame size */
			wr32(E1000_FCRTC, hwm);

			/*
			 * This sets the time to wait before requesting tran-
			 * sition to * low power state to number of usecs needed
			 * to receive 1 512 * byte frame at gigabit line rate
			 */
			reg = rd32(E1000_DMCTLX);
			reg |= IGB_DMCTLX_DCFLUSH_DIS;

			/* Delay 255 usec before entering Lx state. */
			reg |= 0xFF;
			wr32(E1000_DMCTLX, reg);

			/* free space in Tx packet buffer to wake from DMAC */
			wr32(E1000_DMCTXTH,
			     (IGB_MIN_TXPBSIZE -
			     (IGB_TX_BUF_4096 + adapter->max_frame_size))
			     >> 6);

			/* make low power state decision controlled by DMAC */
			reg = rd32(E1000_PCIEMISC);
			reg |= E1000_PCIEMISC_LX_DECISION;
			wr32(E1000_PCIEMISC, reg);
		} /* end if IGB_FLAG_DMAC set */
	}
1780 1781 1782 1783 1784
	if (hw->mac.type == e1000_82580) {
		u32 reg = rd32(E1000_PCIEMISC);
		wr32(E1000_PCIEMISC,
		                reg & ~E1000_PCIEMISC_LX_DECISION);
	}
1785 1786 1787
	if (!netif_running(adapter->netdev))
		igb_power_down_link(adapter);

1788 1789 1790 1791 1792
	igb_update_mng_vlan(adapter);

	/* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
	wr32(E1000_VET, ETHERNET_IEEE_VLAN_TYPE);

1793
	igb_get_phy_info(hw);
1794 1795
}

J
Jiri Pirko 已提交
1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809
static u32 igb_fix_features(struct net_device *netdev, u32 features)
{
	/*
	 * Since there is no support for separate rx/tx vlan accel
	 * enable/disable make sure tx flag is always in same state as rx.
	 */
	if (features & NETIF_F_HW_VLAN_RX)
		features |= NETIF_F_HW_VLAN_TX;
	else
		features &= ~NETIF_F_HW_VLAN_TX;

	return features;
}

1810 1811
static int igb_set_features(struct net_device *netdev, u32 features)
{
J
Jiri Pirko 已提交
1812
	u32 changed = netdev->features ^ features;
1813

J
Jiri Pirko 已提交
1814 1815 1816
	if (changed & NETIF_F_HW_VLAN_RX)
		igb_vlan_mode(netdev, features);

1817 1818 1819
	return 0;
}

S
Stephen Hemminger 已提交
1820
static const struct net_device_ops igb_netdev_ops = {
1821
	.ndo_open		= igb_open,
S
Stephen Hemminger 已提交
1822
	.ndo_stop		= igb_close,
1823
	.ndo_start_xmit		= igb_xmit_frame,
E
Eric Dumazet 已提交
1824
	.ndo_get_stats64	= igb_get_stats64,
1825
	.ndo_set_rx_mode	= igb_set_rx_mode,
S
Stephen Hemminger 已提交
1826 1827 1828 1829 1830 1831 1832
	.ndo_set_mac_address	= igb_set_mac,
	.ndo_change_mtu		= igb_change_mtu,
	.ndo_do_ioctl		= igb_ioctl,
	.ndo_tx_timeout		= igb_tx_timeout,
	.ndo_validate_addr	= eth_validate_addr,
	.ndo_vlan_rx_add_vid	= igb_vlan_rx_add_vid,
	.ndo_vlan_rx_kill_vid	= igb_vlan_rx_kill_vid,
1833 1834 1835 1836
	.ndo_set_vf_mac		= igb_ndo_set_vf_mac,
	.ndo_set_vf_vlan	= igb_ndo_set_vf_vlan,
	.ndo_set_vf_tx_rate	= igb_ndo_set_vf_bw,
	.ndo_get_vf_config	= igb_ndo_get_vf_config,
S
Stephen Hemminger 已提交
1837 1838 1839
#ifdef CONFIG_NET_POLL_CONTROLLER
	.ndo_poll_controller	= igb_netpoll,
#endif
J
Jiri Pirko 已提交
1840 1841
	.ndo_fix_features	= igb_fix_features,
	.ndo_set_features	= igb_set_features,
S
Stephen Hemminger 已提交
1842 1843
};

1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860
/**
 * igb_probe - Device Initialization Routine
 * @pdev: PCI device information struct
 * @ent: entry in igb_pci_tbl
 *
 * Returns 0 on success, negative on failure
 *
 * igb_probe initializes an adapter identified by a pci_dev structure.
 * The OS initialization, configuring of the adapter private structure,
 * and a hardware reset occur.
 **/
static int __devinit igb_probe(struct pci_dev *pdev,
			       const struct pci_device_id *ent)
{
	struct net_device *netdev;
	struct igb_adapter *adapter;
	struct e1000_hw *hw;
1861
	u16 eeprom_data = 0;
1862
	s32 ret_val;
1863
	static int global_quad_port_a; /* global quad port a indication */
1864 1865
	const struct e1000_info *ei = igb_info_tbl[ent->driver_data];
	unsigned long mmio_start, mmio_len;
1866
	int err, pci_using_dac;
1867
	u16 eeprom_apme_mask = IGB_EEPROM_APME;
1868
	u8 part_str[E1000_PBANUM_LENGTH];
1869

1870 1871 1872 1873 1874 1875 1876 1877 1878
	/* Catch broken hardware that put the wrong VF device ID in
	 * the PCIe SR-IOV capability.
	 */
	if (pdev->is_virtfn) {
		WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
		     pci_name(pdev), pdev->vendor, pdev->device);
		return -EINVAL;
	}

1879
	err = pci_enable_device_mem(pdev);
1880 1881 1882 1883
	if (err)
		return err;

	pci_using_dac = 0;
1884
	err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
1885
	if (!err) {
1886
		err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
1887 1888 1889
		if (!err)
			pci_using_dac = 1;
	} else {
1890
		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1891
		if (err) {
1892
			err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
1893 1894 1895 1896 1897 1898 1899 1900
			if (err) {
				dev_err(&pdev->dev, "No usable DMA "
					"configuration, aborting\n");
				goto err_dma;
			}
		}
	}

1901 1902 1903
	err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
	                                   IORESOURCE_MEM),
	                                   igb_driver_name);
1904 1905 1906
	if (err)
		goto err_pci_reg;

1907
	pci_enable_pcie_error_reporting(pdev);
1908

1909
	pci_set_master(pdev);
1910
	pci_save_state(pdev);
1911 1912

	err = -ENOMEM;
1913
	netdev = alloc_etherdev_mq(sizeof(struct igb_adapter),
1914
				   IGB_MAX_TX_QUEUES);
1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931
	if (!netdev)
		goto err_alloc_etherdev;

	SET_NETDEV_DEV(netdev, &pdev->dev);

	pci_set_drvdata(pdev, netdev);
	adapter = netdev_priv(netdev);
	adapter->netdev = netdev;
	adapter->pdev = pdev;
	hw = &adapter->hw;
	hw->back = adapter;
	adapter->msg_enable = NETIF_MSG_DRV | NETIF_MSG_PROBE;

	mmio_start = pci_resource_start(pdev, 0);
	mmio_len = pci_resource_len(pdev, 0);

	err = -EIO;
1932 1933
	hw->hw_addr = ioremap(mmio_start, mmio_len);
	if (!hw->hw_addr)
1934 1935
		goto err_ioremap;

S
Stephen Hemminger 已提交
1936
	netdev->netdev_ops = &igb_netdev_ops;
1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958
	igb_set_ethtool_ops(netdev);
	netdev->watchdog_timeo = 5 * HZ;

	strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);

	netdev->mem_start = mmio_start;
	netdev->mem_end = mmio_start + mmio_len;

	/* PCI config space info */
	hw->vendor_id = pdev->vendor;
	hw->device_id = pdev->device;
	hw->revision_id = pdev->revision;
	hw->subsystem_vendor_id = pdev->subsystem_vendor;
	hw->subsystem_device_id = pdev->subsystem_device;

	/* Copy the default MAC, PHY and NVM function pointers */
	memcpy(&hw->mac.ops, ei->mac_ops, sizeof(hw->mac.ops));
	memcpy(&hw->phy.ops, ei->phy_ops, sizeof(hw->phy.ops));
	memcpy(&hw->nvm.ops, ei->nvm_ops, sizeof(hw->nvm.ops));
	/* Initialize skew-specific constants */
	err = ei->get_invariants(hw);
	if (err)
1959
		goto err_sw_init;
1960

1961
	/* setup the private structure */
1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980
	err = igb_sw_init(adapter);
	if (err)
		goto err_sw_init;

	igb_get_bus_info_pcie(hw);

	hw->phy.autoneg_wait_to_complete = false;

	/* Copper options */
	if (hw->phy.media_type == e1000_media_type_copper) {
		hw->phy.mdix = AUTO_ALL_MODES;
		hw->phy.disable_polarity_correction = false;
		hw->phy.ms_type = e1000_ms_hw_default;
	}

	if (igb_check_reset_block(hw))
		dev_info(&pdev->dev,
			"PHY reset is blocked due to SOL/IDER session.\n");

1981
	netdev->hw_features = NETIF_F_SG |
1982
			   NETIF_F_IP_CSUM |
1983 1984 1985
			   NETIF_F_IPV6_CSUM |
			   NETIF_F_TSO |
			   NETIF_F_TSO6 |
J
Jiri Pirko 已提交
1986 1987
			   NETIF_F_RXCSUM |
			   NETIF_F_HW_VLAN_RX;
1988 1989

	netdev->features = netdev->hw_features |
1990 1991 1992
			   NETIF_F_HW_VLAN_TX |
			   NETIF_F_HW_VLAN_FILTER;

1993 1994
	netdev->vlan_features |= NETIF_F_TSO;
	netdev->vlan_features |= NETIF_F_TSO6;
1995
	netdev->vlan_features |= NETIF_F_IP_CSUM;
1996
	netdev->vlan_features |= NETIF_F_IPV6_CSUM;
1997 1998
	netdev->vlan_features |= NETIF_F_SG;

1999
	if (pci_using_dac) {
2000
		netdev->features |= NETIF_F_HIGHDMA;
2001 2002
		netdev->vlan_features |= NETIF_F_HIGHDMA;
	}
2003

2004 2005
	if (hw->mac.type >= e1000_82576) {
		netdev->hw_features |= NETIF_F_SCTP_CSUM;
2006
		netdev->features |= NETIF_F_SCTP_CSUM;
2007
	}
2008

2009 2010
	netdev->priv_flags |= IFF_UNICAST_FLT;

2011
	adapter->en_mng_pt = igb_enable_mng_pass_thru(hw);
2012 2013 2014 2015 2016 2017

	/* before reading the NVM, reset the controller to put the device in a
	 * known good starting state */
	hw->mac.ops.reset_hw(hw);

	/* make sure the NVM is good */
2018
	if (hw->nvm.ops.validate(hw) < 0) {
2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036
		dev_err(&pdev->dev, "The NVM Checksum Is Not Valid\n");
		err = -EIO;
		goto err_eeprom;
	}

	/* copy the MAC address out of the NVM */
	if (hw->mac.ops.read_mac_addr(hw))
		dev_err(&pdev->dev, "NVM Read Error\n");

	memcpy(netdev->dev_addr, hw->mac.addr, netdev->addr_len);
	memcpy(netdev->perm_addr, hw->mac.addr, netdev->addr_len);

	if (!is_valid_ether_addr(netdev->perm_addr)) {
		dev_err(&pdev->dev, "Invalid MAC Address\n");
		err = -EIO;
		goto err_eeprom;
	}

2037
	setup_timer(&adapter->watchdog_timer, igb_watchdog,
2038
	            (unsigned long) adapter);
2039
	setup_timer(&adapter->phy_info_timer, igb_update_phy_info,
2040
	            (unsigned long) adapter);
2041 2042 2043 2044

	INIT_WORK(&adapter->reset_task, igb_reset_task);
	INIT_WORK(&adapter->watchdog_task, igb_watchdog_task);

2045
	/* Initialize link properties that are user-changeable */
2046 2047 2048 2049
	adapter->fc_autoneg = true;
	hw->mac.autoneg = true;
	hw->phy.autoneg_advertised = 0x2f;

2050 2051
	hw->fc.requested_mode = e1000_fc_default;
	hw->fc.current_mode = e1000_fc_default;
2052 2053 2054 2055 2056 2057 2058

	igb_validate_mdi_setting(hw);

	/* Initial Wake on LAN setting If APM wake is enabled in the EEPROM,
	 * enable the ACPI Magic Packet filter
	 */

2059
	if (hw->bus.func == 0)
A
Alexander Duyck 已提交
2060
		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
2061
	else if (hw->mac.type >= e1000_82580)
2062 2063 2064
		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
		                 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
		                 &eeprom_data);
2065 2066
	else if (hw->bus.func == 1)
		hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078

	if (eeprom_data & eeprom_apme_mask)
		adapter->eeprom_wol |= E1000_WUFC_MAG;

	/* now that we have the eeprom settings, apply the special cases where
	 * the eeprom may be wrong or the board simply won't support wake on
	 * lan on a particular port */
	switch (pdev->device) {
	case E1000_DEV_ID_82575GB_QUAD_COPPER:
		adapter->eeprom_wol = 0;
		break;
	case E1000_DEV_ID_82575EB_FIBER_SERDES:
A
Alexander Duyck 已提交
2079 2080
	case E1000_DEV_ID_82576_FIBER:
	case E1000_DEV_ID_82576_SERDES:
2081 2082 2083 2084 2085
		/* Wake events only supported on port A for dual fiber
		 * regardless of eeprom setting */
		if (rd32(E1000_STATUS) & E1000_STATUS_FUNC_1)
			adapter->eeprom_wol = 0;
		break;
2086
	case E1000_DEV_ID_82576_QUAD_COPPER:
2087
	case E1000_DEV_ID_82576_QUAD_COPPER_ET2:
2088 2089 2090 2091 2092 2093 2094 2095 2096
		/* if quad port adapter, disable WoL on all but port A */
		if (global_quad_port_a != 0)
			adapter->eeprom_wol = 0;
		else
			adapter->flags |= IGB_FLAG_QUAD_PORT_A;
		/* Reset for multiple quad port adapters */
		if (++global_quad_port_a == 4)
			global_quad_port_a = 0;
		break;
2097 2098 2099 2100
	}

	/* initialize the wol settings based on the eeprom settings */
	adapter->wol = adapter->eeprom_wol;
2101
	device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114

	/* reset the hardware with the new settings */
	igb_reset(adapter);

	/* let the f/w know that the h/w is now under the control of the
	 * driver. */
	igb_get_hw_control(adapter);

	strcpy(netdev->name, "eth%d");
	err = register_netdev(netdev);
	if (err)
		goto err_register;

2115 2116 2117
	/* carrier off reporting is important to ethtool even BEFORE open */
	netif_carrier_off(netdev);

2118
#ifdef CONFIG_IGB_DCA
2119
	if (dca_add_requester(&pdev->dev) == 0) {
2120
		adapter->flags |= IGB_FLAG_DCA_ENABLED;
J
Jeb Cramer 已提交
2121 2122 2123 2124
		dev_info(&pdev->dev, "DCA enabled\n");
		igb_setup_dca(adapter);
	}

P
Patrick Ohly 已提交
2125
#endif
A
Anders Berggren 已提交
2126 2127 2128
	/* do hw tstamp init after resetting */
	igb_init_hw_timer(adapter);

2129 2130
	dev_info(&pdev->dev, "Intel(R) Gigabit Ethernet Network Connection\n");
	/* print bus type/speed/width info */
J
Johannes Berg 已提交
2131
	dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
2132
		 netdev->name,
2133
		 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
2134
		  (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
2135
		                                            "unknown"),
2136 2137 2138 2139
		 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
		  (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :
		  (hw->bus.width == e1000_bus_width_pcie_x1) ? "Width x1" :
		   "unknown"),
J
Johannes Berg 已提交
2140
		 netdev->dev_addr);
2141

2142 2143 2144 2145
	ret_val = igb_read_part_string(hw, part_str, E1000_PBANUM_LENGTH);
	if (ret_val)
		strcpy(part_str, "Unknown");
	dev_info(&pdev->dev, "%s: PBA No: %s\n", netdev->name, part_str);
2146 2147 2148
	dev_info(&pdev->dev,
		"Using %s interrupts. %d rx queue(s), %d tx queue(s)\n",
		adapter->msix_entries ? "MSI-X" :
2149
		(adapter->flags & IGB_FLAG_HAS_MSI) ? "MSI" : "legacy",
2150
		adapter->num_rx_queues, adapter->num_tx_queues);
2151 2152 2153 2154 2155 2156 2157
	switch (hw->mac.type) {
	case e1000_i350:
		igb_set_eee_i350(hw);
		break;
	default:
		break;
	}
2158 2159 2160 2161 2162 2163
	return 0;

err_register:
	igb_release_hw_control(adapter);
err_eeprom:
	if (!igb_check_reset_block(hw))
2164
		igb_reset_phy(hw);
2165 2166 2167 2168

	if (hw->flash_address)
		iounmap(hw->flash_address);
err_sw_init:
2169
	igb_clear_interrupt_scheme(adapter);
2170 2171 2172 2173
	iounmap(hw->hw_addr);
err_ioremap:
	free_netdev(netdev);
err_alloc_etherdev:
2174 2175
	pci_release_selected_regions(pdev,
	                             pci_select_bars(pdev, IORESOURCE_MEM));
2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194
err_pci_reg:
err_dma:
	pci_disable_device(pdev);
	return err;
}

/**
 * igb_remove - Device Removal Routine
 * @pdev: PCI device information struct
 *
 * igb_remove is called by the PCI subsystem to alert the driver
 * that it should release a PCI device.  The could be caused by a
 * Hot-Plug event, or because the driver is going to be removed from
 * memory.
 **/
static void __devexit igb_remove(struct pci_dev *pdev)
{
	struct net_device *netdev = pci_get_drvdata(pdev);
	struct igb_adapter *adapter = netdev_priv(netdev);
J
Jeb Cramer 已提交
2195
	struct e1000_hw *hw = &adapter->hw;
2196

2197 2198 2199 2200
	/*
	 * The watchdog timer may be rescheduled, so explicitly
	 * disable watchdog from being rescheduled.
	 */
2201 2202 2203 2204
	set_bit(__IGB_DOWN, &adapter->state);
	del_timer_sync(&adapter->watchdog_timer);
	del_timer_sync(&adapter->phy_info_timer);

2205 2206
	cancel_work_sync(&adapter->reset_task);
	cancel_work_sync(&adapter->watchdog_task);
2207

2208
#ifdef CONFIG_IGB_DCA
2209
	if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
J
Jeb Cramer 已提交
2210 2211
		dev_info(&pdev->dev, "DCA disabled\n");
		dca_remove_requester(&pdev->dev);
2212
		adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
A
Alexander Duyck 已提交
2213
		wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
J
Jeb Cramer 已提交
2214 2215 2216
	}
#endif

2217 2218 2219 2220 2221 2222
	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
	 * would have already happened in close and is redundant. */
	igb_release_hw_control(adapter);

	unregister_netdev(netdev);

2223
	igb_clear_interrupt_scheme(adapter);
2224

2225 2226 2227 2228 2229 2230 2231 2232 2233 2234
#ifdef CONFIG_PCI_IOV
	/* reclaim resources allocated to VFs */
	if (adapter->vf_data) {
		/* disable iov and allow time for transactions to clear */
		pci_disable_sriov(pdev);
		msleep(500);

		kfree(adapter->vf_data);
		adapter->vf_data = NULL;
		wr32(E1000_IOVCTL, E1000_IOVCTL_REUSE_VFQ);
2235
		wrfl();
2236 2237 2238 2239
		msleep(100);
		dev_info(&pdev->dev, "IOV Disabled\n");
	}
#endif
2240

2241 2242 2243
	iounmap(hw->hw_addr);
	if (hw->flash_address)
		iounmap(hw->flash_address);
2244 2245
	pci_release_selected_regions(pdev,
	                             pci_select_bars(pdev, IORESOURCE_MEM));
2246 2247 2248

	free_netdev(netdev);

2249
	pci_disable_pcie_error_reporting(pdev);
2250

2251 2252 2253
	pci_disable_device(pdev);
}

2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294
/**
 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
 * @adapter: board private structure to initialize
 *
 * This function initializes the vf specific data storage and then attempts to
 * allocate the VFs.  The reason for ordering it this way is because it is much
 * mor expensive time wise to disable SR-IOV than it is to allocate and free
 * the memory for the VFs.
 **/
static void __devinit igb_probe_vfs(struct igb_adapter * adapter)
{
#ifdef CONFIG_PCI_IOV
	struct pci_dev *pdev = adapter->pdev;

	if (adapter->vfs_allocated_count) {
		adapter->vf_data = kcalloc(adapter->vfs_allocated_count,
		                           sizeof(struct vf_data_storage),
		                           GFP_KERNEL);
		/* if allocation failed then we do not support SR-IOV */
		if (!adapter->vf_data) {
			adapter->vfs_allocated_count = 0;
			dev_err(&pdev->dev, "Unable to allocate memory for VF "
			        "Data Storage\n");
		}
	}

	if (pci_enable_sriov(pdev, adapter->vfs_allocated_count)) {
		kfree(adapter->vf_data);
		adapter->vf_data = NULL;
#endif /* CONFIG_PCI_IOV */
		adapter->vfs_allocated_count = 0;
#ifdef CONFIG_PCI_IOV
	} else {
		unsigned char mac_addr[ETH_ALEN];
		int i;
		dev_info(&pdev->dev, "%d vfs allocated\n",
		         adapter->vfs_allocated_count);
		for (i = 0; i < adapter->vfs_allocated_count; i++) {
			random_ether_addr(mac_addr);
			igb_set_vf_mac(adapter, i, mac_addr);
		}
2295 2296 2297
		/* DMA Coalescing is not supported in IOV mode. */
		if (adapter->flags & IGB_FLAG_DMAC)
			adapter->flags &= ~IGB_FLAG_DMAC;
2298 2299 2300 2301
	}
#endif /* CONFIG_PCI_IOV */
}

2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314

/**
 * igb_init_hw_timer - Initialize hardware timer used with IEEE 1588 timestamp
 * @adapter: board private structure to initialize
 *
 * igb_init_hw_timer initializes the function pointer and values for the hw
 * timer found in hardware.
 **/
static void igb_init_hw_timer(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;

	switch (hw->mac.type) {
2315
	case e1000_i350:
2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357
	case e1000_82580:
		memset(&adapter->cycles, 0, sizeof(adapter->cycles));
		adapter->cycles.read = igb_read_clock;
		adapter->cycles.mask = CLOCKSOURCE_MASK(64);
		adapter->cycles.mult = 1;
		/*
		 * The 82580 timesync updates the system timer every 8ns by 8ns
		 * and the value cannot be shifted.  Instead we need to shift
		 * the registers to generate a 64bit timer value.  As a result
		 * SYSTIMR/L/H, TXSTMPL/H, RXSTMPL/H all have to be shifted by
		 * 24 in order to generate a larger value for synchronization.
		 */
		adapter->cycles.shift = IGB_82580_TSYNC_SHIFT;
		/* disable system timer temporarily by setting bit 31 */
		wr32(E1000_TSAUXC, 0x80000000);
		wrfl();

		/* Set registers so that rollover occurs soon to test this. */
		wr32(E1000_SYSTIMR, 0x00000000);
		wr32(E1000_SYSTIML, 0x80000000);
		wr32(E1000_SYSTIMH, 0x000000FF);
		wrfl();

		/* enable system timer by clearing bit 31 */
		wr32(E1000_TSAUXC, 0x0);
		wrfl();

		timecounter_init(&adapter->clock,
				 &adapter->cycles,
				 ktime_to_ns(ktime_get_real()));
		/*
		 * Synchronize our NIC clock against system wall clock. NIC
		 * time stamp reading requires ~3us per sample, each sample
		 * was pretty stable even under load => only require 10
		 * samples for each offset comparison.
		 */
		memset(&adapter->compare, 0, sizeof(adapter->compare));
		adapter->compare.source = &adapter->clock;
		adapter->compare.target = ktime_get_real;
		adapter->compare.num_samples = 10;
		timecompare_update(&adapter->compare, 0);
		break;
2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369
	case e1000_82576:
		/*
		 * Initialize hardware timer: we keep it running just in case
		 * that some program needs it later on.
		 */
		memset(&adapter->cycles, 0, sizeof(adapter->cycles));
		adapter->cycles.read = igb_read_clock;
		adapter->cycles.mask = CLOCKSOURCE_MASK(64);
		adapter->cycles.mult = 1;
		/**
		 * Scale the NIC clock cycle by a large factor so that
		 * relatively small clock corrections can be added or
L
Lucas De Marchi 已提交
2370
		 * subtracted at each clock tick. The drawbacks of a large
2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408
		 * factor are a) that the clock register overflows more quickly
		 * (not such a big deal) and b) that the increment per tick has
		 * to fit into 24 bits.  As a result we need to use a shift of
		 * 19 so we can fit a value of 16 into the TIMINCA register.
		 */
		adapter->cycles.shift = IGB_82576_TSYNC_SHIFT;
		wr32(E1000_TIMINCA,
		                (1 << E1000_TIMINCA_16NS_SHIFT) |
		                (16 << IGB_82576_TSYNC_SHIFT));

		/* Set registers so that rollover occurs soon to test this. */
		wr32(E1000_SYSTIML, 0x00000000);
		wr32(E1000_SYSTIMH, 0xFF800000);
		wrfl();

		timecounter_init(&adapter->clock,
				 &adapter->cycles,
				 ktime_to_ns(ktime_get_real()));
		/*
		 * Synchronize our NIC clock against system wall clock. NIC
		 * time stamp reading requires ~3us per sample, each sample
		 * was pretty stable even under load => only require 10
		 * samples for each offset comparison.
		 */
		memset(&adapter->compare, 0, sizeof(adapter->compare));
		adapter->compare.source = &adapter->clock;
		adapter->compare.target = ktime_get_real;
		adapter->compare.num_samples = 10;
		timecompare_update(&adapter->compare, 0);
		break;
	case e1000_82575:
		/* 82575 does not support timesync */
	default:
		break;
	}

}

2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424
/**
 * igb_sw_init - Initialize general software structures (struct igb_adapter)
 * @adapter: board private structure to initialize
 *
 * igb_sw_init initializes the Adapter private data structure.
 * Fields are initialized based on PCI device information and
 * OS network device settings (MTU size).
 **/
static int __devinit igb_sw_init(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	struct net_device *netdev = adapter->netdev;
	struct pci_dev *pdev = adapter->pdev;

	pci_read_config_word(pdev, PCI_COMMAND, &hw->bus.pci_cmd_word);

2425
	/* set default ring sizes */
2426 2427
	adapter->tx_ring_count = IGB_DEFAULT_TXD;
	adapter->rx_ring_count = IGB_DEFAULT_RXD;
2428 2429

	/* set default ITR values */
2430 2431 2432
	adapter->rx_itr_setting = IGB_DEFAULT_ITR;
	adapter->tx_itr_setting = IGB_DEFAULT_ITR;

2433 2434 2435
	/* set default work limits */
	adapter->tx_work_limit = IGB_DEFAULT_TX_WORK;

2436 2437
	adapter->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN +
				  VLAN_HLEN;
2438 2439
	adapter->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;

2440 2441
	adapter->node = -1;

E
Eric Dumazet 已提交
2442
	spin_lock_init(&adapter->stats64_lock);
2443
#ifdef CONFIG_PCI_IOV
2444 2445 2446
	switch (hw->mac.type) {
	case e1000_82576:
	case e1000_i350:
2447 2448 2449 2450 2451 2452
		if (max_vfs > 7) {
			dev_warn(&pdev->dev,
				 "Maximum of 7 VFs per PF, using max\n");
			adapter->vfs_allocated_count = 7;
		} else
			adapter->vfs_allocated_count = max_vfs;
2453 2454 2455 2456
		break;
	default:
		break;
	}
2457
#endif /* CONFIG_PCI_IOV */
2458
	adapter->rss_queues = min_t(u32, IGB_MAX_RX_QUEUES, num_online_cpus());
2459 2460 2461
	/* i350 cannot do RSS and SR-IOV at the same time */
	if (hw->mac.type == e1000_i350 && adapter->vfs_allocated_count)
		adapter->rss_queues = 1;
2462 2463 2464 2465 2466 2467 2468 2469 2470 2471

	/*
	 * if rss_queues > 4 or vfs are going to be allocated with rss_queues
	 * then we should combine the queues into a queue pair in order to
	 * conserve interrupts due to limited supply
	 */
	if ((adapter->rss_queues > 4) ||
	    ((adapter->rss_queues > 1) && (adapter->vfs_allocated_count > 6)))
		adapter->flags |= IGB_FLAG_QUEUE_PAIRS;

2472
	/* This call may decrease the number of queues */
2473
	if (igb_init_interrupt_scheme(adapter)) {
2474 2475 2476 2477
		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
		return -ENOMEM;
	}

2478 2479
	igb_probe_vfs(adapter);

2480 2481 2482
	/* Explicitly disable IRQ since the NIC can be in any state. */
	igb_irq_disable(adapter);

2483 2484 2485
	if (hw->mac.type == e1000_i350)
		adapter->flags &= ~IGB_FLAG_DMAC;

2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512
	set_bit(__IGB_DOWN, &adapter->state);
	return 0;
}

/**
 * igb_open - Called when a network interface is made active
 * @netdev: network interface device structure
 *
 * Returns 0 on success, negative value on failure
 *
 * The open entry point is called when a network interface is made
 * active by the system (IFF_UP).  At this point all resources needed
 * for transmit and receive operations are allocated, the interrupt
 * handler is registered with the OS, the watchdog timer is started,
 * and the stack is notified that the interface is ready.
 **/
static int igb_open(struct net_device *netdev)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
	int err;
	int i;

	/* disallow open during test */
	if (test_bit(__IGB_TESTING, &adapter->state))
		return -EBUSY;

2513 2514
	netif_carrier_off(netdev);

2515 2516 2517 2518 2519 2520 2521 2522 2523 2524
	/* allocate transmit descriptors */
	err = igb_setup_all_tx_resources(adapter);
	if (err)
		goto err_setup_tx;

	/* allocate receive descriptors */
	err = igb_setup_all_rx_resources(adapter);
	if (err)
		goto err_setup_rx;

2525
	igb_power_up_link(adapter);
2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539

	/* before we allocate an interrupt, we must be ready to handle it.
	 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
	 * as soon as we call pci_request_irq, so we have to setup our
	 * clean_rx handler before we do so.  */
	igb_configure(adapter);

	err = igb_request_irq(adapter);
	if (err)
		goto err_req_irq;

	/* From here on the code is the same as igb_up() */
	clear_bit(__IGB_DOWN, &adapter->state);

2540 2541 2542 2543
	for (i = 0; i < adapter->num_q_vectors; i++) {
		struct igb_q_vector *q_vector = adapter->q_vector[i];
		napi_enable(&q_vector->napi);
	}
2544 2545 2546

	/* Clear any pending interrupts. */
	rd32(E1000_ICR);
P
PJ Waskiewicz 已提交
2547 2548 2549

	igb_irq_enable(adapter);

2550 2551 2552 2553 2554 2555 2556
	/* notify VFs that reset has been completed */
	if (adapter->vfs_allocated_count) {
		u32 reg_data = rd32(E1000_CTRL_EXT);
		reg_data |= E1000_CTRL_EXT_PFRSTD;
		wr32(E1000_CTRL_EXT, reg_data);
	}

2557 2558
	netif_tx_start_all_queues(netdev);

2559 2560 2561
	/* start the watchdog. */
	hw->mac.get_link_status = 1;
	schedule_work(&adapter->watchdog_task);
2562 2563 2564 2565 2566

	return 0;

err_req_irq:
	igb_release_hw_control(adapter);
2567
	igb_power_down_link(adapter);
2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608
	igb_free_all_rx_resources(adapter);
err_setup_rx:
	igb_free_all_tx_resources(adapter);
err_setup_tx:
	igb_reset(adapter);

	return err;
}

/**
 * igb_close - Disables a network interface
 * @netdev: network interface device structure
 *
 * Returns 0, this is not allowed to fail
 *
 * The close entry point is called when an interface is de-activated
 * by the OS.  The hardware is still under the driver's control, but
 * needs to be disabled.  A global MAC reset is issued to stop the
 * hardware, and all transmit and receive resources are freed.
 **/
static int igb_close(struct net_device *netdev)
{
	struct igb_adapter *adapter = netdev_priv(netdev);

	WARN_ON(test_bit(__IGB_RESETTING, &adapter->state));
	igb_down(adapter);

	igb_free_irq(adapter);

	igb_free_all_tx_resources(adapter);
	igb_free_all_rx_resources(adapter);

	return 0;
}

/**
 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
 * @tx_ring: tx descriptor ring (for a specific queue) to setup
 *
 * Return 0 on success, negative on failure
 **/
2609
int igb_setup_tx_resources(struct igb_ring *tx_ring)
2610
{
2611
	struct device *dev = tx_ring->dev;
2612
	int orig_node = dev_to_node(dev);
2613 2614
	int size;

2615
	size = sizeof(struct igb_tx_buffer) * tx_ring->count;
2616 2617 2618
	tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
	if (!tx_ring->tx_buffer_info)
		tx_ring->tx_buffer_info = vzalloc(size);
2619
	if (!tx_ring->tx_buffer_info)
2620 2621 2622
		goto err;

	/* round up to nearest 4K */
2623
	tx_ring->size = tx_ring->count * sizeof(union e1000_adv_tx_desc);
2624 2625
	tx_ring->size = ALIGN(tx_ring->size, 4096);

2626
	set_dev_node(dev, tx_ring->numa_node);
2627 2628 2629 2630
	tx_ring->desc = dma_alloc_coherent(dev,
					   tx_ring->size,
					   &tx_ring->dma,
					   GFP_KERNEL);
2631 2632 2633 2634 2635 2636
	set_dev_node(dev, orig_node);
	if (!tx_ring->desc)
		tx_ring->desc = dma_alloc_coherent(dev,
						   tx_ring->size,
						   &tx_ring->dma,
						   GFP_KERNEL);
2637 2638 2639 2640 2641 2642

	if (!tx_ring->desc)
		goto err;

	tx_ring->next_to_use = 0;
	tx_ring->next_to_clean = 0;
2643

2644 2645 2646
	return 0;

err:
2647
	vfree(tx_ring->tx_buffer_info);
2648
	dev_err(dev,
2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661
		"Unable to allocate memory for the transmit descriptor ring\n");
	return -ENOMEM;
}

/**
 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
 *				  (Descriptors) for all queues
 * @adapter: board private structure
 *
 * Return 0 on success, negative on failure
 **/
static int igb_setup_all_tx_resources(struct igb_adapter *adapter)
{
2662
	struct pci_dev *pdev = adapter->pdev;
2663 2664 2665
	int i, err = 0;

	for (i = 0; i < adapter->num_tx_queues; i++) {
2666
		err = igb_setup_tx_resources(adapter->tx_ring[i]);
2667
		if (err) {
2668
			dev_err(&pdev->dev,
2669 2670
				"Allocation for Tx Queue %u failed\n", i);
			for (i--; i >= 0; i--)
2671
				igb_free_tx_resources(adapter->tx_ring[i]);
2672 2673 2674 2675 2676 2677 2678 2679
			break;
		}
	}

	return err;
}

/**
2680 2681
 * igb_setup_tctl - configure the transmit control registers
 * @adapter: Board private structure
2682
 **/
2683
void igb_setup_tctl(struct igb_adapter *adapter)
2684 2685 2686 2687
{
	struct e1000_hw *hw = &adapter->hw;
	u32 tctl;

2688 2689
	/* disable queue 0 which is enabled by default on 82575 and 82576 */
	wr32(E1000_TXDCTL(0), 0);
2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704

	/* Program the Transmit Control Register */
	tctl = rd32(E1000_TCTL);
	tctl &= ~E1000_TCTL_CT;
	tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC |
		(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);

	igb_config_collision_dist(hw);

	/* Enable transmits */
	tctl |= E1000_TCTL_EN;

	wr32(E1000_TCTL, tctl);
}

2705 2706 2707 2708 2709 2710 2711
/**
 * igb_configure_tx_ring - Configure transmit ring after Reset
 * @adapter: board private structure
 * @ring: tx ring to configure
 *
 * Configure a transmit ring after a reset.
 **/
2712 2713
void igb_configure_tx_ring(struct igb_adapter *adapter,
                           struct igb_ring *ring)
2714 2715
{
	struct e1000_hw *hw = &adapter->hw;
2716
	u32 txdctl = 0;
2717 2718 2719 2720
	u64 tdba = ring->dma;
	int reg_idx = ring->reg_idx;

	/* disable the queue */
2721
	wr32(E1000_TXDCTL(reg_idx), 0);
2722 2723 2724 2725 2726 2727 2728 2729 2730
	wrfl();
	mdelay(10);

	wr32(E1000_TDLEN(reg_idx),
	                ring->count * sizeof(union e1000_adv_tx_desc));
	wr32(E1000_TDBAL(reg_idx),
	                tdba & 0x00000000ffffffffULL);
	wr32(E1000_TDBAH(reg_idx), tdba >> 32);

2731
	ring->tail = hw->hw_addr + E1000_TDT(reg_idx);
2732
	wr32(E1000_TDH(reg_idx), 0);
2733
	writel(0, ring->tail);
2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750 2751 2752 2753

	txdctl |= IGB_TX_PTHRESH;
	txdctl |= IGB_TX_HTHRESH << 8;
	txdctl |= IGB_TX_WTHRESH << 16;

	txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
	wr32(E1000_TXDCTL(reg_idx), txdctl);
}

/**
 * igb_configure_tx - Configure transmit Unit after Reset
 * @adapter: board private structure
 *
 * Configure the Tx unit of the MAC after a reset.
 **/
static void igb_configure_tx(struct igb_adapter *adapter)
{
	int i;

	for (i = 0; i < adapter->num_tx_queues; i++)
2754
		igb_configure_tx_ring(adapter, adapter->tx_ring[i]);
2755 2756
}

2757 2758 2759 2760 2761 2762
/**
 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
 * @rx_ring:    rx descriptor ring (for a specific queue) to setup
 *
 * Returns 0 on success, negative on failure
 **/
2763
int igb_setup_rx_resources(struct igb_ring *rx_ring)
2764
{
2765
	struct device *dev = rx_ring->dev;
2766
	int orig_node = dev_to_node(dev);
2767 2768
	int size, desc_len;

2769
	size = sizeof(struct igb_rx_buffer) * rx_ring->count;
2770 2771 2772
	rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
	if (!rx_ring->rx_buffer_info)
		rx_ring->rx_buffer_info = vzalloc(size);
2773
	if (!rx_ring->rx_buffer_info)
2774 2775 2776 2777 2778 2779 2780 2781
		goto err;

	desc_len = sizeof(union e1000_adv_rx_desc);

	/* Round up to nearest 4K */
	rx_ring->size = rx_ring->count * desc_len;
	rx_ring->size = ALIGN(rx_ring->size, 4096);

2782
	set_dev_node(dev, rx_ring->numa_node);
2783 2784 2785 2786
	rx_ring->desc = dma_alloc_coherent(dev,
					   rx_ring->size,
					   &rx_ring->dma,
					   GFP_KERNEL);
2787 2788 2789 2790 2791 2792
	set_dev_node(dev, orig_node);
	if (!rx_ring->desc)
		rx_ring->desc = dma_alloc_coherent(dev,
						   rx_ring->size,
						   &rx_ring->dma,
						   GFP_KERNEL);
2793 2794 2795 2796 2797 2798 2799 2800 2801 2802

	if (!rx_ring->desc)
		goto err;

	rx_ring->next_to_clean = 0;
	rx_ring->next_to_use = 0;

	return 0;

err:
2803 2804
	vfree(rx_ring->rx_buffer_info);
	rx_ring->rx_buffer_info = NULL;
2805 2806
	dev_err(dev, "Unable to allocate memory for the receive descriptor"
		" ring\n");
2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818
	return -ENOMEM;
}

/**
 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
 *				  (Descriptors) for all queues
 * @adapter: board private structure
 *
 * Return 0 on success, negative on failure
 **/
static int igb_setup_all_rx_resources(struct igb_adapter *adapter)
{
2819
	struct pci_dev *pdev = adapter->pdev;
2820 2821 2822
	int i, err = 0;

	for (i = 0; i < adapter->num_rx_queues; i++) {
2823
		err = igb_setup_rx_resources(adapter->rx_ring[i]);
2824
		if (err) {
2825
			dev_err(&pdev->dev,
2826 2827
				"Allocation for Rx Queue %u failed\n", i);
			for (i--; i >= 0; i--)
2828
				igb_free_rx_resources(adapter->rx_ring[i]);
2829 2830 2831 2832 2833 2834 2835
			break;
		}
	}

	return err;
}

2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863
/**
 * igb_setup_mrqc - configure the multiple receive queue control registers
 * @adapter: Board private structure
 **/
static void igb_setup_mrqc(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 mrqc, rxcsum;
	u32 j, num_rx_queues, shift = 0, shift2 = 0;
	union e1000_reta {
		u32 dword;
		u8  bytes[4];
	} reta;
	static const u8 rsshash[40] = {
		0x6d, 0x5a, 0x56, 0xda, 0x25, 0x5b, 0x0e, 0xc2, 0x41, 0x67,
		0x25, 0x3d, 0x43, 0xa3, 0x8f, 0xb0, 0xd0, 0xca, 0x2b, 0xcb,
		0xae, 0x7b, 0x30, 0xb4,	0x77, 0xcb, 0x2d, 0xa3, 0x80, 0x30,
		0xf2, 0x0c, 0x6a, 0x42, 0xb7, 0x3b, 0xbe, 0xac, 0x01, 0xfa };

	/* Fill out hash function seeds */
	for (j = 0; j < 10; j++) {
		u32 rsskey = rsshash[(j * 4)];
		rsskey |= rsshash[(j * 4) + 1] << 8;
		rsskey |= rsshash[(j * 4) + 2] << 16;
		rsskey |= rsshash[(j * 4) + 3] << 24;
		array_wr32(E1000_RSSRK(0), j, rsskey);
	}

2864
	num_rx_queues = adapter->rss_queues;
2865 2866 2867 2868

	if (adapter->vfs_allocated_count) {
		/* 82575 and 82576 supports 2 RSS queues for VMDq */
		switch (hw->mac.type) {
2869
		case e1000_i350:
2870 2871 2872 2873
		case e1000_82580:
			num_rx_queues = 1;
			shift = 0;
			break;
2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924
		case e1000_82576:
			shift = 3;
			num_rx_queues = 2;
			break;
		case e1000_82575:
			shift = 2;
			shift2 = 6;
		default:
			break;
		}
	} else {
		if (hw->mac.type == e1000_82575)
			shift = 6;
	}

	for (j = 0; j < (32 * 4); j++) {
		reta.bytes[j & 3] = (j % num_rx_queues) << shift;
		if (shift2)
			reta.bytes[j & 3] |= num_rx_queues << shift2;
		if ((j & 3) == 3)
			wr32(E1000_RETA(j >> 2), reta.dword);
	}

	/*
	 * Disable raw packet checksumming so that RSS hash is placed in
	 * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
	 * offloads as they are enabled by default
	 */
	rxcsum = rd32(E1000_RXCSUM);
	rxcsum |= E1000_RXCSUM_PCSD;

	if (adapter->hw.mac.type >= e1000_82576)
		/* Enable Receive Checksum Offload for SCTP */
		rxcsum |= E1000_RXCSUM_CRCOFL;

	/* Don't need to set TUOFL or IPOFL, they default to 1 */
	wr32(E1000_RXCSUM, rxcsum);

	/* If VMDq is enabled then we set the appropriate mode for that, else
	 * we default to RSS so that an RSS hash is calculated per packet even
	 * if we are only using one queue */
	if (adapter->vfs_allocated_count) {
		if (hw->mac.type > e1000_82575) {
			/* Set the default pool for the PF's first queue */
			u32 vtctl = rd32(E1000_VT_CTL);
			vtctl &= ~(E1000_VT_CTL_DEFAULT_POOL_MASK |
				   E1000_VT_CTL_DISABLE_DEF_POOL);
			vtctl |= adapter->vfs_allocated_count <<
				E1000_VT_CTL_DEFAULT_POOL_SHIFT;
			wr32(E1000_VT_CTL, vtctl);
		}
2925
		if (adapter->rss_queues > 1)
2926 2927 2928 2929 2930 2931 2932 2933
			mrqc = E1000_MRQC_ENABLE_VMDQ_RSS_2Q;
		else
			mrqc = E1000_MRQC_ENABLE_VMDQ;
	} else {
		mrqc = E1000_MRQC_ENABLE_RSS_4Q;
	}
	igb_vmm_control(adapter);

2934 2935 2936 2937 2938 2939 2940 2941 2942 2943
	/*
	 * Generate RSS hash based on TCP port numbers and/or
	 * IPv4/v6 src and dst addresses since UDP cannot be
	 * hashed reliably due to IP fragmentation
	 */
	mrqc |= E1000_MRQC_RSS_FIELD_IPV4 |
		E1000_MRQC_RSS_FIELD_IPV4_TCP |
		E1000_MRQC_RSS_FIELD_IPV6 |
		E1000_MRQC_RSS_FIELD_IPV6_TCP |
		E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
2944 2945 2946 2947

	wr32(E1000_MRQC, mrqc);
}

2948 2949 2950 2951
/**
 * igb_setup_rctl - configure the receive control registers
 * @adapter: Board private structure
 **/
2952
void igb_setup_rctl(struct igb_adapter *adapter)
2953 2954 2955 2956 2957 2958 2959
{
	struct e1000_hw *hw = &adapter->hw;
	u32 rctl;

	rctl = rd32(E1000_RCTL);

	rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2960
	rctl &= ~(E1000_RCTL_LBM_TCVR | E1000_RCTL_LBM_MAC);
2961

2962
	rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_RDMTS_HALF |
2963
		(hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2964

2965 2966 2967 2968
	/*
	 * enable stripping of CRC. It's unlikely this will break BMC
	 * redirection as it did with e1000. Newer features require
	 * that the HW strips the CRC.
2969
	 */
2970
	rctl |= E1000_RCTL_SECRC;
2971

2972
	/* disable store bad packets and clear size bits. */
2973
	rctl &= ~(E1000_RCTL_SBP | E1000_RCTL_SZ_256);
2974

A
Alexander Duyck 已提交
2975 2976
	/* enable LPE to prevent packets larger than max_frame_size */
	rctl |= E1000_RCTL_LPE;
2977

2978 2979
	/* disable queue 0 to prevent tail write w/o re-config */
	wr32(E1000_RXDCTL(0), 0);
2980

2981 2982 2983 2984 2985 2986 2987 2988 2989
	/* Attention!!!  For SR-IOV PF driver operations you must enable
	 * queue drop for all VF and PF queues to prevent head of line blocking
	 * if an un-trusted VF does not provide descriptors to hardware.
	 */
	if (adapter->vfs_allocated_count) {
		/* set all queue drop enable bits */
		wr32(E1000_QDE, ALL_QUEUES);
	}

2990 2991 2992
	wr32(E1000_RCTL, rctl);
}

2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012
static inline int igb_set_vf_rlpml(struct igb_adapter *adapter, int size,
                                   int vfn)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 vmolr;

	/* if it isn't the PF check to see if VFs are enabled and
	 * increase the size to support vlan tags */
	if (vfn < adapter->vfs_allocated_count &&
	    adapter->vf_data[vfn].vlans_enabled)
		size += VLAN_TAG_SIZE;

	vmolr = rd32(E1000_VMOLR(vfn));
	vmolr &= ~E1000_VMOLR_RLPML_MASK;
	vmolr |= size | E1000_VMOLR_LPE;
	wr32(E1000_VMOLR(vfn), vmolr);

	return 0;
}

3013 3014 3015 3016 3017 3018 3019 3020
/**
 * igb_rlpml_set - set maximum receive packet size
 * @adapter: board private structure
 *
 * Configure maximum receivable packet size.
 **/
static void igb_rlpml_set(struct igb_adapter *adapter)
{
3021
	u32 max_frame_size = adapter->max_frame_size;
3022 3023 3024 3025 3026
	struct e1000_hw *hw = &adapter->hw;
	u16 pf_id = adapter->vfs_allocated_count;

	if (pf_id) {
		igb_set_vf_rlpml(adapter, max_frame_size, pf_id);
3027 3028 3029 3030 3031 3032 3033
		/*
		 * If we're in VMDQ or SR-IOV mode, then set global RLPML
		 * to our max jumbo frame size, in case we need to enable
		 * jumbo frames on one of the rings later.
		 * This will not pass over-length frames into the default
		 * queue because it's gated by the VMOLR.RLPML.
		 */
3034
		max_frame_size = MAX_JUMBO_FRAME_SIZE;
3035 3036 3037 3038 3039
	}

	wr32(E1000_RLPML, max_frame_size);
}

3040 3041
static inline void igb_set_vmolr(struct igb_adapter *adapter,
				 int vfn, bool aupe)
3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053
{
	struct e1000_hw *hw = &adapter->hw;
	u32 vmolr;

	/*
	 * This register exists only on 82576 and newer so if we are older then
	 * we should exit and do nothing
	 */
	if (hw->mac.type < e1000_82576)
		return;

	vmolr = rd32(E1000_VMOLR(vfn));
3054 3055 3056 3057 3058
	vmolr |= E1000_VMOLR_STRVLAN;      /* Strip vlan tags */
	if (aupe)
		vmolr |= E1000_VMOLR_AUPE;        /* Accept untagged packets */
	else
		vmolr &= ~(E1000_VMOLR_AUPE); /* Tagged packets ONLY */
3059 3060 3061 3062

	/* clear all bits that might not be set */
	vmolr &= ~(E1000_VMOLR_BAM | E1000_VMOLR_RSSE);

3063
	if (adapter->rss_queues > 1 && vfn == adapter->vfs_allocated_count)
3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074
		vmolr |= E1000_VMOLR_RSSE; /* enable RSS */
	/*
	 * for VMDq only allow the VFs and pool 0 to accept broadcast and
	 * multicast packets
	 */
	if (vfn <= adapter->vfs_allocated_count)
		vmolr |= E1000_VMOLR_BAM;	   /* Accept broadcast */

	wr32(E1000_VMOLR(vfn), vmolr);
}

3075 3076 3077 3078 3079 3080 3081
/**
 * igb_configure_rx_ring - Configure a receive ring after Reset
 * @adapter: board private structure
 * @ring: receive ring to be configured
 *
 * Configure the Rx unit of the MAC after a reset.
 **/
3082 3083
void igb_configure_rx_ring(struct igb_adapter *adapter,
                           struct igb_ring *ring)
3084 3085 3086 3087
{
	struct e1000_hw *hw = &adapter->hw;
	u64 rdba = ring->dma;
	int reg_idx = ring->reg_idx;
3088
	u32 srrctl = 0, rxdctl = 0;
3089 3090

	/* disable the queue */
3091
	wr32(E1000_RXDCTL(reg_idx), 0);
3092 3093 3094 3095 3096 3097 3098 3099 3100

	/* Set DMA base address registers */
	wr32(E1000_RDBAL(reg_idx),
	     rdba & 0x00000000ffffffffULL);
	wr32(E1000_RDBAH(reg_idx), rdba >> 32);
	wr32(E1000_RDLEN(reg_idx),
	               ring->count * sizeof(union e1000_adv_rx_desc));

	/* initialize head and tail */
3101
	ring->tail = hw->hw_addr + E1000_RDT(reg_idx);
3102
	wr32(E1000_RDH(reg_idx), 0);
3103
	writel(0, ring->tail);
3104

3105
	/* set descriptor configuration */
3106
	srrctl = IGB_RX_HDR_LEN << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
3107
#if (PAGE_SIZE / 2) > IGB_RXBUFFER_16384
3108
	srrctl |= IGB_RXBUFFER_16384 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3109
#else
3110
	srrctl |= (PAGE_SIZE / 2) >> E1000_SRRCTL_BSIZEPKT_SHIFT;
3111
#endif
3112
	srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
N
Nick Nunley 已提交
3113 3114
	if (hw->mac.type == e1000_82580)
		srrctl |= E1000_SRRCTL_TIMESTAMP;
3115 3116 3117
	/* Only set Drop Enable if we are supporting multiple queues */
	if (adapter->vfs_allocated_count || adapter->num_rx_queues > 1)
		srrctl |= E1000_SRRCTL_DROP_EN;
3118 3119 3120

	wr32(E1000_SRRCTL(reg_idx), srrctl);

3121
	/* set filtering for VMDQ pools */
3122
	igb_set_vmolr(adapter, reg_idx & 0x7, true);
3123

3124 3125 3126
	rxdctl |= IGB_RX_PTHRESH;
	rxdctl |= IGB_RX_HTHRESH << 8;
	rxdctl |= IGB_RX_WTHRESH << 16;
3127 3128 3129

	/* enable receive descriptor fetching */
	rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
3130 3131 3132
	wr32(E1000_RXDCTL(reg_idx), rxdctl);
}

3133 3134 3135 3136 3137 3138 3139 3140
/**
 * igb_configure_rx - Configure receive Unit after Reset
 * @adapter: board private structure
 *
 * Configure the Rx unit of the MAC after a reset.
 **/
static void igb_configure_rx(struct igb_adapter *adapter)
{
3141
	int i;
3142

3143 3144 3145
	/* set UTA to appropriate mode */
	igb_set_uta(adapter);

3146 3147 3148 3149
	/* set the correct pool for the PF default MAC address in entry 0 */
	igb_rar_set_qsel(adapter, adapter->hw.mac.addr, 0,
	                 adapter->vfs_allocated_count);

3150 3151 3152
	/* Setup the HW Rx Head and Tail Descriptor Pointers and
	 * the Base and Length of the Rx Descriptor Ring */
	for (i = 0; i < adapter->num_rx_queues; i++)
3153
		igb_configure_rx_ring(adapter, adapter->rx_ring[i]);
3154 3155 3156 3157 3158 3159 3160 3161
}

/**
 * igb_free_tx_resources - Free Tx Resources per Queue
 * @tx_ring: Tx descriptor ring for a specific queue
 *
 * Free all transmit software resources
 **/
3162
void igb_free_tx_resources(struct igb_ring *tx_ring)
3163
{
3164
	igb_clean_tx_ring(tx_ring);
3165

3166 3167
	vfree(tx_ring->tx_buffer_info);
	tx_ring->tx_buffer_info = NULL;
3168

3169 3170 3171 3172
	/* if not set, then don't free */
	if (!tx_ring->desc)
		return;

3173 3174
	dma_free_coherent(tx_ring->dev, tx_ring->size,
			  tx_ring->desc, tx_ring->dma);
3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189

	tx_ring->desc = NULL;
}

/**
 * igb_free_all_tx_resources - Free Tx Resources for All Queues
 * @adapter: board private structure
 *
 * Free all transmit software resources
 **/
static void igb_free_all_tx_resources(struct igb_adapter *adapter)
{
	int i;

	for (i = 0; i < adapter->num_tx_queues; i++)
3190
		igb_free_tx_resources(adapter->tx_ring[i]);
3191 3192
}

3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 3210 3211 3212
void igb_unmap_and_free_tx_resource(struct igb_ring *ring,
				    struct igb_tx_buffer *tx_buffer)
{
	if (tx_buffer->skb) {
		dev_kfree_skb_any(tx_buffer->skb);
		if (tx_buffer->dma)
			dma_unmap_single(ring->dev,
					 tx_buffer->dma,
					 tx_buffer->length,
					 DMA_TO_DEVICE);
	} else if (tx_buffer->dma) {
		dma_unmap_page(ring->dev,
			       tx_buffer->dma,
			       tx_buffer->length,
			       DMA_TO_DEVICE);
	}
	tx_buffer->next_to_watch = NULL;
	tx_buffer->skb = NULL;
	tx_buffer->dma = 0;
	/* buffer_info must be completely set up in the transmit path */
3213 3214 3215 3216 3217 3218
}

/**
 * igb_clean_tx_ring - Free Tx Buffers
 * @tx_ring: ring to be cleaned
 **/
3219
static void igb_clean_tx_ring(struct igb_ring *tx_ring)
3220
{
3221
	struct igb_tx_buffer *buffer_info;
3222
	unsigned long size;
3223
	u16 i;
3224

3225
	if (!tx_ring->tx_buffer_info)
3226 3227 3228 3229
		return;
	/* Free all the Tx ring sk_buffs */

	for (i = 0; i < tx_ring->count; i++) {
3230
		buffer_info = &tx_ring->tx_buffer_info[i];
3231
		igb_unmap_and_free_tx_resource(tx_ring, buffer_info);
3232 3233
	}

3234 3235
	size = sizeof(struct igb_tx_buffer) * tx_ring->count;
	memset(tx_ring->tx_buffer_info, 0, size);
3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252

	/* Zero out the descriptor ring */
	memset(tx_ring->desc, 0, tx_ring->size);

	tx_ring->next_to_use = 0;
	tx_ring->next_to_clean = 0;
}

/**
 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
 * @adapter: board private structure
 **/
static void igb_clean_all_tx_rings(struct igb_adapter *adapter)
{
	int i;

	for (i = 0; i < adapter->num_tx_queues; i++)
3253
		igb_clean_tx_ring(adapter->tx_ring[i]);
3254 3255 3256 3257 3258 3259 3260 3261
}

/**
 * igb_free_rx_resources - Free Rx Resources
 * @rx_ring: ring to clean the resources from
 *
 * Free all receive software resources
 **/
3262
void igb_free_rx_resources(struct igb_ring *rx_ring)
3263
{
3264
	igb_clean_rx_ring(rx_ring);
3265

3266 3267
	vfree(rx_ring->rx_buffer_info);
	rx_ring->rx_buffer_info = NULL;
3268

3269 3270 3271 3272
	/* if not set, then don't free */
	if (!rx_ring->desc)
		return;

3273 3274
	dma_free_coherent(rx_ring->dev, rx_ring->size,
			  rx_ring->desc, rx_ring->dma);
3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288 3289

	rx_ring->desc = NULL;
}

/**
 * igb_free_all_rx_resources - Free Rx Resources for All Queues
 * @adapter: board private structure
 *
 * Free all receive software resources
 **/
static void igb_free_all_rx_resources(struct igb_adapter *adapter)
{
	int i;

	for (i = 0; i < adapter->num_rx_queues; i++)
3290
		igb_free_rx_resources(adapter->rx_ring[i]);
3291 3292 3293 3294 3295 3296
}

/**
 * igb_clean_rx_ring - Free Rx Buffers per Queue
 * @rx_ring: ring to free buffers from
 **/
3297
static void igb_clean_rx_ring(struct igb_ring *rx_ring)
3298 3299
{
	unsigned long size;
3300
	u16 i;
3301

3302
	if (!rx_ring->rx_buffer_info)
3303
		return;
3304

3305 3306
	/* Free all the Rx ring sk_buffs */
	for (i = 0; i < rx_ring->count; i++) {
3307
		struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
3308
		if (buffer_info->dma) {
3309
			dma_unmap_single(rx_ring->dev,
3310
			                 buffer_info->dma,
3311
					 IGB_RX_HDR_LEN,
3312
					 DMA_FROM_DEVICE);
3313 3314 3315 3316 3317 3318 3319
			buffer_info->dma = 0;
		}

		if (buffer_info->skb) {
			dev_kfree_skb(buffer_info->skb);
			buffer_info->skb = NULL;
		}
A
Alexander Duyck 已提交
3320
		if (buffer_info->page_dma) {
3321
			dma_unmap_page(rx_ring->dev,
3322
			               buffer_info->page_dma,
A
Alexander Duyck 已提交
3323
				       PAGE_SIZE / 2,
3324
				       DMA_FROM_DEVICE);
A
Alexander Duyck 已提交
3325 3326
			buffer_info->page_dma = 0;
		}
3327 3328 3329
		if (buffer_info->page) {
			put_page(buffer_info->page);
			buffer_info->page = NULL;
3330
			buffer_info->page_offset = 0;
3331 3332 3333
		}
	}

3334 3335
	size = sizeof(struct igb_rx_buffer) * rx_ring->count;
	memset(rx_ring->rx_buffer_info, 0, size);
3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352

	/* Zero out the descriptor ring */
	memset(rx_ring->desc, 0, rx_ring->size);

	rx_ring->next_to_clean = 0;
	rx_ring->next_to_use = 0;
}

/**
 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
 * @adapter: board private structure
 **/
static void igb_clean_all_rx_rings(struct igb_adapter *adapter)
{
	int i;

	for (i = 0; i < adapter->num_rx_queues; i++)
3353
		igb_clean_rx_ring(adapter->rx_ring[i]);
3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365
}

/**
 * igb_set_mac - Change the Ethernet Address of the NIC
 * @netdev: network interface device structure
 * @p: pointer to an address structure
 *
 * Returns 0 on success, negative on failure
 **/
static int igb_set_mac(struct net_device *netdev, void *p)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
3366
	struct e1000_hw *hw = &adapter->hw;
3367 3368 3369 3370 3371 3372
	struct sockaddr *addr = p;

	if (!is_valid_ether_addr(addr->sa_data))
		return -EADDRNOTAVAIL;

	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
3373
	memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
3374

3375 3376 3377
	/* set the correct pool for the new PF MAC address in entry 0 */
	igb_rar_set_qsel(adapter, hw->mac.addr, 0,
	                 adapter->vfs_allocated_count);
3378

3379 3380 3381 3382
	return 0;
}

/**
3383
 * igb_write_mc_addr_list - write multicast addresses to MTA
3384 3385
 * @netdev: network interface device structure
 *
3386 3387 3388 3389
 * Writes multicast address list to the MTA hash table.
 * Returns: -ENOMEM on failure
 *                0 on no addresses written
 *                X on writing X addresses to MTA
3390
 **/
3391
static int igb_write_mc_addr_list(struct net_device *netdev)
3392 3393 3394
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
3395
	struct netdev_hw_addr *ha;
3396
	u8  *mta_list;
3397 3398
	int i;

3399
	if (netdev_mc_empty(netdev)) {
3400 3401 3402 3403 3404
		/* nothing to program, so clear mc list */
		igb_update_mc_addr_list(hw, NULL, 0);
		igb_restore_vf_multicasts(adapter);
		return 0;
	}
3405

3406
	mta_list = kzalloc(netdev_mc_count(netdev) * 6, GFP_ATOMIC);
3407 3408
	if (!mta_list)
		return -ENOMEM;
3409

3410
	/* The shared function expects a packed array of only addresses. */
3411
	i = 0;
3412 3413
	netdev_for_each_mc_addr(ha, netdev)
		memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);
3414 3415 3416 3417

	igb_update_mc_addr_list(hw, mta_list, i);
	kfree(mta_list);

3418
	return netdev_mc_count(netdev);
3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438
}

/**
 * igb_write_uc_addr_list - write unicast addresses to RAR table
 * @netdev: network interface device structure
 *
 * Writes unicast address list to the RAR table.
 * Returns: -ENOMEM on failure/insufficient address space
 *                0 on no addresses written
 *                X on writing X addresses to the RAR table
 **/
static int igb_write_uc_addr_list(struct net_device *netdev)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
	unsigned int vfn = adapter->vfs_allocated_count;
	unsigned int rar_entries = hw->mac.rar_entry_count - (vfn + 1);
	int count = 0;

	/* return ENOMEM indicating insufficient memory for addresses */
3439
	if (netdev_uc_count(netdev) > rar_entries)
3440
		return -ENOMEM;
3441

3442
	if (!netdev_uc_empty(netdev) && rar_entries) {
3443
		struct netdev_hw_addr *ha;
3444 3445

		netdev_for_each_uc_addr(ha, netdev) {
3446 3447
			if (!rar_entries)
				break;
3448 3449
			igb_rar_set_qsel(adapter, ha->addr,
			                 rar_entries--,
3450 3451
			                 vfn);
			count++;
3452 3453 3454 3455 3456 3457 3458 3459 3460
		}
	}
	/* write the addresses in reverse order to avoid write combining */
	for (; rar_entries > 0 ; rar_entries--) {
		wr32(E1000_RAH(rar_entries), 0);
		wr32(E1000_RAL(rar_entries), 0);
	}
	wrfl();

3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496
	return count;
}

/**
 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
 * @netdev: network interface device structure
 *
 * The set_rx_mode entry point is called whenever the unicast or multicast
 * address lists or the network interface flags are updated.  This routine is
 * responsible for configuring the hardware for proper unicast, multicast,
 * promiscuous mode, and all-multi behavior.
 **/
static void igb_set_rx_mode(struct net_device *netdev)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
	unsigned int vfn = adapter->vfs_allocated_count;
	u32 rctl, vmolr = 0;
	int count;

	/* Check for Promiscuous and All Multicast modes */
	rctl = rd32(E1000_RCTL);

	/* clear the effected bits */
	rctl &= ~(E1000_RCTL_UPE | E1000_RCTL_MPE | E1000_RCTL_VFE);

	if (netdev->flags & IFF_PROMISC) {
		rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
		vmolr |= (E1000_VMOLR_ROPE | E1000_VMOLR_MPME);
	} else {
		if (netdev->flags & IFF_ALLMULTI) {
			rctl |= E1000_RCTL_MPE;
			vmolr |= E1000_VMOLR_MPME;
		} else {
			/*
			 * Write addresses to the MTA, if the attempt fails
L
Lucas De Marchi 已提交
3497
			 * then we should just turn on promiscuous mode so
3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510
			 * that we can at least receive multicast traffic
			 */
			count = igb_write_mc_addr_list(netdev);
			if (count < 0) {
				rctl |= E1000_RCTL_MPE;
				vmolr |= E1000_VMOLR_MPME;
			} else if (count) {
				vmolr |= E1000_VMOLR_ROMPE;
			}
		}
		/*
		 * Write addresses to available RAR registers, if there is not
		 * sufficient space to store all the addresses then enable
L
Lucas De Marchi 已提交
3511
		 * unicast promiscuous mode
3512 3513 3514 3515 3516 3517 3518
		 */
		count = igb_write_uc_addr_list(netdev);
		if (count < 0) {
			rctl |= E1000_RCTL_UPE;
			vmolr |= E1000_VMOLR_ROPE;
		}
		rctl |= E1000_RCTL_VFE;
3519
	}
3520
	wr32(E1000_RCTL, rctl);
3521

3522 3523 3524 3525 3526 3527 3528
	/*
	 * In order to support SR-IOV and eventually VMDq it is necessary to set
	 * the VMOLR to enable the appropriate modes.  Without this workaround
	 * we will have issues with VLAN tag stripping not being done for frames
	 * that are only arriving because we are the default pool
	 */
	if (hw->mac.type < e1000_82576)
3529
		return;
3530

3531 3532 3533
	vmolr |= rd32(E1000_VMOLR(vfn)) &
	         ~(E1000_VMOLR_ROPE | E1000_VMOLR_MPME | E1000_VMOLR_ROMPE);
	wr32(E1000_VMOLR(vfn), vmolr);
3534
	igb_restore_vf_multicasts(adapter);
3535 3536
}

G
Greg Rose 已提交
3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575
static void igb_check_wvbr(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 wvbr = 0;

	switch (hw->mac.type) {
	case e1000_82576:
	case e1000_i350:
		if (!(wvbr = rd32(E1000_WVBR)))
			return;
		break;
	default:
		break;
	}

	adapter->wvbr |= wvbr;
}

#define IGB_STAGGERED_QUEUE_OFFSET 8

static void igb_spoof_check(struct igb_adapter *adapter)
{
	int j;

	if (!adapter->wvbr)
		return;

	for(j = 0; j < adapter->vfs_allocated_count; j++) {
		if (adapter->wvbr & (1 << j) ||
		    adapter->wvbr & (1 << (j + IGB_STAGGERED_QUEUE_OFFSET))) {
			dev_warn(&adapter->pdev->dev,
				"Spoof event(s) detected on VF %d\n", j);
			adapter->wvbr &=
				~((1 << j) |
				  (1 << (j + IGB_STAGGERED_QUEUE_OFFSET)));
		}
	}
}

3576 3577 3578 3579 3580
/* Need to wait a few seconds after link up to get diagnostic information from
 * the phy */
static void igb_update_phy_info(unsigned long data)
{
	struct igb_adapter *adapter = (struct igb_adapter *) data;
3581
	igb_get_phy_info(&adapter->hw);
3582 3583
}

A
Alexander Duyck 已提交
3584 3585 3586 3587
/**
 * igb_has_link - check shared code for link and determine up/down
 * @adapter: pointer to driver private info
 **/
3588
bool igb_has_link(struct igb_adapter *adapter)
A
Alexander Duyck 已提交
3589 3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619
{
	struct e1000_hw *hw = &adapter->hw;
	bool link_active = false;
	s32 ret_val = 0;

	/* get_link_status is set on LSC (link status) interrupt or
	 * rx sequence error interrupt.  get_link_status will stay
	 * false until the e1000_check_for_link establishes link
	 * for copper adapters ONLY
	 */
	switch (hw->phy.media_type) {
	case e1000_media_type_copper:
		if (hw->mac.get_link_status) {
			ret_val = hw->mac.ops.check_for_link(hw);
			link_active = !hw->mac.get_link_status;
		} else {
			link_active = true;
		}
		break;
	case e1000_media_type_internal_serdes:
		ret_val = hw->mac.ops.check_for_link(hw);
		link_active = hw->mac.serdes_has_link;
		break;
	default:
	case e1000_media_type_unknown:
		break;
	}

	return link_active;
}

3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638
static bool igb_thermal_sensor_event(struct e1000_hw *hw, u32 event)
{
	bool ret = false;
	u32 ctrl_ext, thstat;

	/* check for thermal sensor event on i350, copper only */
	if (hw->mac.type == e1000_i350) {
		thstat = rd32(E1000_THSTAT);
		ctrl_ext = rd32(E1000_CTRL_EXT);

		if ((hw->phy.media_type == e1000_media_type_copper) &&
		    !(ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII)) {
			ret = !!(thstat & event);
		}
	}

	return ret;
}

3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652
/**
 * igb_watchdog - Timer Call-back
 * @data: pointer to adapter cast into an unsigned long
 **/
static void igb_watchdog(unsigned long data)
{
	struct igb_adapter *adapter = (struct igb_adapter *)data;
	/* Do the rest outside of interrupt context */
	schedule_work(&adapter->watchdog_task);
}

static void igb_watchdog_task(struct work_struct *work)
{
	struct igb_adapter *adapter = container_of(work,
3653 3654
	                                           struct igb_adapter,
                                                   watchdog_task);
3655 3656
	struct e1000_hw *hw = &adapter->hw;
	struct net_device *netdev = adapter->netdev;
3657
	u32 link;
3658
	int i;
3659

A
Alexander Duyck 已提交
3660
	link = igb_has_link(adapter);
3661 3662 3663
	if (link) {
		if (!netif_carrier_ok(netdev)) {
			u32 ctrl;
3664 3665 3666
			hw->mac.ops.get_speed_and_duplex(hw,
			                                 &adapter->link_speed,
			                                 &adapter->link_duplex);
3667 3668

			ctrl = rd32(E1000_CTRL);
3669 3670
			/* Links status message must follow this format */
			printk(KERN_INFO "igb: %s NIC Link is Up %d Mbps %s, "
3671
				 "Flow Control: %s\n",
3672 3673 3674
			       netdev->name,
			       adapter->link_speed,
			       adapter->link_duplex == FULL_DUPLEX ?
3675
				 "Full Duplex" : "Half Duplex",
3676 3677 3678 3679
			       ((ctrl & E1000_CTRL_TFCE) &&
			        (ctrl & E1000_CTRL_RFCE)) ? "RX/TX" :
			       ((ctrl & E1000_CTRL_RFCE) ?  "RX" :
			       ((ctrl & E1000_CTRL_TFCE) ?  "TX" : "None")));
3680

3681 3682 3683 3684 3685 3686
			/* check for thermal sensor event */
			if (igb_thermal_sensor_event(hw, E1000_THSTAT_LINK_THROTTLE)) {
				printk(KERN_INFO "igb: %s The network adapter "
						 "link speed was downshifted "
						 "because it overheated.\n",
						 netdev->name);
3687
			}
3688

3689
			/* adjust timeout factor according to speed/duplex */
3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701
			adapter->tx_timeout_factor = 1;
			switch (adapter->link_speed) {
			case SPEED_10:
				adapter->tx_timeout_factor = 14;
				break;
			case SPEED_100:
				/* maybe add some timeout factor ? */
				break;
			}

			netif_carrier_on(netdev);

3702
			igb_ping_all_vfs(adapter);
3703
			igb_check_vf_rate_limit(adapter);
3704

3705
			/* link state has changed, schedule phy info update */
3706 3707 3708 3709 3710 3711 3712 3713
			if (!test_bit(__IGB_DOWN, &adapter->state))
				mod_timer(&adapter->phy_info_timer,
					  round_jiffies(jiffies + 2 * HZ));
		}
	} else {
		if (netif_carrier_ok(netdev)) {
			adapter->link_speed = 0;
			adapter->link_duplex = 0;
3714 3715 3716 3717 3718 3719

			/* check for thermal sensor event */
			if (igb_thermal_sensor_event(hw, E1000_THSTAT_PWR_DOWN)) {
				printk(KERN_ERR "igb: %s The network adapter "
						"was stopped because it "
						"overheated.\n",
3720 3721
						netdev->name);
			}
3722

3723 3724 3725
			/* Links status message must follow this format */
			printk(KERN_INFO "igb: %s NIC Link is Down\n",
			       netdev->name);
3726
			netif_carrier_off(netdev);
3727

3728 3729
			igb_ping_all_vfs(adapter);

3730
			/* link state has changed, schedule phy info update */
3731 3732 3733 3734 3735 3736
			if (!test_bit(__IGB_DOWN, &adapter->state))
				mod_timer(&adapter->phy_info_timer,
					  round_jiffies(jiffies + 2 * HZ));
		}
	}

E
Eric Dumazet 已提交
3737 3738 3739
	spin_lock(&adapter->stats64_lock);
	igb_update_stats(adapter, &adapter->stats64);
	spin_unlock(&adapter->stats64_lock);
3740

3741
	for (i = 0; i < adapter->num_tx_queues; i++) {
3742
		struct igb_ring *tx_ring = adapter->tx_ring[i];
3743
		if (!netif_carrier_ok(netdev)) {
3744 3745 3746 3747
			/* We've lost link, so the controller stops DMA,
			 * but we've got queued Tx work that's never going
			 * to get done, so reset controller to flush Tx.
			 * (Do the reset outside of interrupt context). */
3748 3749 3750 3751 3752 3753
			if (igb_desc_unused(tx_ring) + 1 < tx_ring->count) {
				adapter->tx_timeout_count++;
				schedule_work(&adapter->reset_task);
				/* return immediately since reset is imminent */
				return;
			}
3754 3755
		}

3756
		/* Force detection of hung controller every watchdog period */
3757
		set_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
3758
	}
3759

3760
	/* Cause software interrupt to ensure rx ring is cleaned */
3761
	if (adapter->msix_entries) {
3762 3763 3764 3765 3766
		u32 eics = 0;
		for (i = 0; i < adapter->num_q_vectors; i++) {
			struct igb_q_vector *q_vector = adapter->q_vector[i];
			eics |= q_vector->eims_value;
		}
3767 3768 3769 3770
		wr32(E1000_EICS, eics);
	} else {
		wr32(E1000_ICS, E1000_ICS_RXDMT0);
	}
3771

G
Greg Rose 已提交
3772 3773
	igb_spoof_check(adapter);

3774 3775 3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786
	/* Reset the timer */
	if (!test_bit(__IGB_DOWN, &adapter->state))
		mod_timer(&adapter->watchdog_timer,
			  round_jiffies(jiffies + 2 * HZ));
}

enum latency_range {
	lowest_latency = 0,
	low_latency = 1,
	bulk_latency = 2,
	latency_invalid = 255
};

3787 3788 3789 3790 3791 3792
/**
 * igb_update_ring_itr - update the dynamic ITR value based on packet size
 *
 *      Stores a new ITR value based on strictly on packet size.  This
 *      algorithm is less sophisticated than that used in igb_update_itr,
 *      due to the difficulty of synchronizing statistics across multiple
3793
 *      receive rings.  The divisors and thresholds used by this function
3794 3795 3796 3797 3798 3799 3800
 *      were determined based on theoretical maximum wire speed and testing
 *      data, in order to minimize response time while increasing bulk
 *      throughput.
 *      This functionality is controlled by the InterruptThrottleRate module
 *      parameter (see igb_param.c)
 *      NOTE:  This function is called only when operating in a multiqueue
 *             receive environment.
3801
 * @q_vector: pointer to q_vector
3802
 **/
3803
static void igb_update_ring_itr(struct igb_q_vector *q_vector)
3804
{
3805
	int new_val = q_vector->itr_val;
3806
	int avg_wire_size = 0;
3807
	struct igb_adapter *adapter = q_vector->adapter;
E
Eric Dumazet 已提交
3808
	unsigned int packets;
3809

3810 3811 3812 3813
	/* For non-gigabit speeds, just fix the interrupt rate at 4000
	 * ints/sec - ITR timer value of 120 ticks.
	 */
	if (adapter->link_speed != SPEED_1000) {
3814
		new_val = IGB_4K_ITR;
3815
		goto set_itr_val;
3816
	}
3817

3818 3819 3820
	packets = q_vector->rx.total_packets;
	if (packets)
		avg_wire_size = q_vector->rx.total_bytes / packets;
3821

3822 3823 3824 3825
	packets = q_vector->tx.total_packets;
	if (packets)
		avg_wire_size = max_t(u32, avg_wire_size,
				      q_vector->tx.total_bytes / packets);
3826 3827 3828 3829

	/* if avg_wire_size isn't set no work was done */
	if (!avg_wire_size)
		goto clear_counts;
3830

3831 3832 3833 3834 3835
	/* Add 24 bytes to size to account for CRC, preamble, and gap */
	avg_wire_size += 24;

	/* Don't starve jumbo frames */
	avg_wire_size = min(avg_wire_size, 3000);
3836

3837 3838 3839 3840 3841
	/* Give a little boost to mid-size frames */
	if ((avg_wire_size > 300) && (avg_wire_size < 1200))
		new_val = avg_wire_size / 3;
	else
		new_val = avg_wire_size / 2;
3842

3843 3844 3845 3846 3847
	/* conservative mode (itr 3) eliminates the lowest_latency setting */
	if (new_val < IGB_20K_ITR &&
	    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
	     (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
		new_val = IGB_20K_ITR;
3848

3849
set_itr_val:
3850 3851 3852
	if (new_val != q_vector->itr_val) {
		q_vector->itr_val = new_val;
		q_vector->set_itr = 1;
3853
	}
3854
clear_counts:
3855 3856 3857 3858
	q_vector->rx.total_bytes = 0;
	q_vector->rx.total_packets = 0;
	q_vector->tx.total_bytes = 0;
	q_vector->tx.total_packets = 0;
3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873
}

/**
 * igb_update_itr - update the dynamic ITR value based on statistics
 *      Stores a new ITR value based on packets and byte
 *      counts during the last interrupt.  The advantage of per interrupt
 *      computation is faster updates and more accurate ITR for the current
 *      traffic pattern.  Constants in this function were computed
 *      based on theoretical maximum wire speed and thresholds were set based
 *      on testing data as well as attempting to minimize response time
 *      while increasing bulk throughput.
 *      this functionality is controlled by the InterruptThrottleRate module
 *      parameter (see igb_param.c)
 *      NOTE:  These calculations are only valid when operating in a single-
 *             queue environment.
3874 3875
 * @q_vector: pointer to q_vector
 * @ring_container: ring info to update the itr for
3876
 **/
3877 3878
static void igb_update_itr(struct igb_q_vector *q_vector,
			   struct igb_ring_container *ring_container)
3879
{
3880 3881 3882
	unsigned int packets = ring_container->total_packets;
	unsigned int bytes = ring_container->total_bytes;
	u8 itrval = ring_container->itr;
3883

3884
	/* no packets, exit with status unchanged */
3885
	if (packets == 0)
3886
		return;
3887

3888
	switch (itrval) {
3889 3890 3891
	case lowest_latency:
		/* handle TSO and jumbo frames */
		if (bytes/packets > 8000)
3892
			itrval = bulk_latency;
3893
		else if ((packets < 5) && (bytes > 512))
3894
			itrval = low_latency;
3895 3896 3897 3898 3899
		break;
	case low_latency:  /* 50 usec aka 20000 ints/s */
		if (bytes > 10000) {
			/* this if handles the TSO accounting */
			if (bytes/packets > 8000) {
3900
				itrval = bulk_latency;
3901
			} else if ((packets < 10) || ((bytes/packets) > 1200)) {
3902
				itrval = bulk_latency;
3903
			} else if ((packets > 35)) {
3904
				itrval = lowest_latency;
3905 3906
			}
		} else if (bytes/packets > 2000) {
3907
			itrval = bulk_latency;
3908
		} else if (packets <= 2 && bytes < 512) {
3909
			itrval = lowest_latency;
3910 3911 3912 3913 3914
		}
		break;
	case bulk_latency: /* 250 usec aka 4000 ints/s */
		if (bytes > 25000) {
			if (packets > 35)
3915
				itrval = low_latency;
3916
		} else if (bytes < 1500) {
3917
			itrval = low_latency;
3918 3919 3920 3921
		}
		break;
	}

3922 3923 3924 3925 3926 3927
	/* clear work counters since we have the values we need */
	ring_container->total_bytes = 0;
	ring_container->total_packets = 0;

	/* write updated itr to ring container */
	ring_container->itr = itrval;
3928 3929
}

3930
static void igb_set_itr(struct igb_q_vector *q_vector)
3931
{
3932
	struct igb_adapter *adapter = q_vector->adapter;
3933
	u32 new_itr = q_vector->itr_val;
3934
	u8 current_itr = 0;
3935 3936 3937 3938

	/* for non-gigabit speeds, just fix the interrupt rate at 4000 */
	if (adapter->link_speed != SPEED_1000) {
		current_itr = 0;
3939
		new_itr = IGB_4K_ITR;
3940 3941 3942
		goto set_itr_now;
	}

3943 3944
	igb_update_itr(q_vector, &q_vector->tx);
	igb_update_itr(q_vector, &q_vector->rx);
3945

3946
	current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
3947

3948
	/* conservative mode (itr 3) eliminates the lowest_latency setting */
3949 3950 3951
	if (current_itr == lowest_latency &&
	    ((q_vector->rx.ring && adapter->rx_itr_setting == 3) ||
	     (!q_vector->rx.ring && adapter->tx_itr_setting == 3)))
3952 3953
		current_itr = low_latency;

3954 3955 3956
	switch (current_itr) {
	/* counts and packets in update_itr are dependent on these numbers */
	case lowest_latency:
3957
		new_itr = IGB_70K_ITR; /* 70,000 ints/sec */
3958 3959
		break;
	case low_latency:
3960
		new_itr = IGB_20K_ITR; /* 20,000 ints/sec */
3961 3962
		break;
	case bulk_latency:
3963
		new_itr = IGB_4K_ITR;  /* 4,000 ints/sec */
3964 3965 3966 3967 3968 3969
		break;
	default:
		break;
	}

set_itr_now:
3970
	if (new_itr != q_vector->itr_val) {
3971 3972 3973
		/* this attempts to bias the interrupt rate towards Bulk
		 * by adding intermediate steps when interrupt rate is
		 * increasing */
3974 3975 3976
		new_itr = new_itr > q_vector->itr_val ?
		             max((new_itr * q_vector->itr_val) /
		                 (new_itr + (q_vector->itr_val >> 2)),
3977
				 new_itr) :
3978 3979 3980 3981 3982 3983 3984
			     new_itr;
		/* Don't write the value here; it resets the adapter's
		 * internal timer, and causes us to delay far longer than
		 * we should between interrupts.  Instead, we write the ITR
		 * value at the beginning of the next interrupt so the timing
		 * ends up being correct.
		 */
3985 3986
		q_vector->itr_val = new_itr;
		q_vector->set_itr = 1;
3987 3988 3989
	}
}

3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002 4003 4004
void igb_tx_ctxtdesc(struct igb_ring *tx_ring, u32 vlan_macip_lens,
		     u32 type_tucmd, u32 mss_l4len_idx)
{
	struct e1000_adv_tx_context_desc *context_desc;
	u16 i = tx_ring->next_to_use;

	context_desc = IGB_TX_CTXTDESC(tx_ring, i);

	i++;
	tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;

	/* set bits to identify this as an advanced context descriptor */
	type_tucmd |= E1000_TXD_CMD_DEXT | E1000_ADVTXD_DTYP_CTXT;

	/* For 82575, context index must be unique per ring. */
4005
	if (test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4006 4007 4008 4009 4010 4011 4012 4013
		mss_l4len_idx |= tx_ring->reg_idx << 4;

	context_desc->vlan_macip_lens	= cpu_to_le32(vlan_macip_lens);
	context_desc->seqnum_seed	= 0;
	context_desc->type_tucmd_mlhl	= cpu_to_le32(type_tucmd);
	context_desc->mss_l4len_idx	= cpu_to_le32(mss_l4len_idx);
}

4014 4015 4016
static int igb_tso(struct igb_ring *tx_ring,
		   struct igb_tx_buffer *first,
		   u8 *hdr_len)
4017
{
4018
	struct sk_buff *skb = first->skb;
4019 4020 4021 4022 4023
	u32 vlan_macip_lens, type_tucmd;
	u32 mss_l4len_idx, l4len;

	if (!skb_is_gso(skb))
		return 0;
4024 4025

	if (skb_header_cloned(skb)) {
4026
		int err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4027 4028 4029 4030
		if (err)
			return err;
	}

4031 4032
	/* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
	type_tucmd = E1000_ADVTXD_TUCMD_L4T_TCP;
4033

4034
	if (first->protocol == __constant_htons(ETH_P_IP)) {
4035 4036 4037 4038 4039 4040 4041
		struct iphdr *iph = ip_hdr(skb);
		iph->tot_len = 0;
		iph->check = 0;
		tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
							 iph->daddr, 0,
							 IPPROTO_TCP,
							 0);
4042
		type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
4043 4044 4045
		first->tx_flags |= IGB_TX_FLAGS_TSO |
				   IGB_TX_FLAGS_CSUM |
				   IGB_TX_FLAGS_IPV4;
4046
	} else if (skb_is_gso_v6(skb)) {
4047 4048 4049 4050
		ipv6_hdr(skb)->payload_len = 0;
		tcp_hdr(skb)->check = ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
						       &ipv6_hdr(skb)->daddr,
						       0, IPPROTO_TCP, 0);
4051 4052
		first->tx_flags |= IGB_TX_FLAGS_TSO |
				   IGB_TX_FLAGS_CSUM;
4053 4054
	}

4055
	/* compute header lengths */
4056 4057
	l4len = tcp_hdrlen(skb);
	*hdr_len = skb_transport_offset(skb) + l4len;
4058

4059 4060 4061 4062
	/* update gso size and bytecount with header size */
	first->gso_segs = skb_shinfo(skb)->gso_segs;
	first->bytecount += (first->gso_segs - 1) * *hdr_len;

4063
	/* MSS L4LEN IDX */
4064 4065
	mss_l4len_idx = l4len << E1000_ADVTXD_L4LEN_SHIFT;
	mss_l4len_idx |= skb_shinfo(skb)->gso_size << E1000_ADVTXD_MSS_SHIFT;
4066

4067 4068 4069
	/* VLAN MACLEN IPLEN */
	vlan_macip_lens = skb_network_header_len(skb);
	vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4070
	vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4071

4072
	igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4073

4074
	return 1;
4075 4076
}

4077
static void igb_tx_csum(struct igb_ring *tx_ring, struct igb_tx_buffer *first)
4078
{
4079
	struct sk_buff *skb = first->skb;
4080 4081 4082
	u32 vlan_macip_lens = 0;
	u32 mss_l4len_idx = 0;
	u32 type_tucmd = 0;
4083

4084
	if (skb->ip_summed != CHECKSUM_PARTIAL) {
4085 4086
		if (!(first->tx_flags & IGB_TX_FLAGS_VLAN))
			return;
4087 4088
	} else {
		u8 l4_hdr = 0;
4089
		switch (first->protocol) {
4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102
		case __constant_htons(ETH_P_IP):
			vlan_macip_lens |= skb_network_header_len(skb);
			type_tucmd |= E1000_ADVTXD_TUCMD_IPV4;
			l4_hdr = ip_hdr(skb)->protocol;
			break;
		case __constant_htons(ETH_P_IPV6):
			vlan_macip_lens |= skb_network_header_len(skb);
			l4_hdr = ipv6_hdr(skb)->nexthdr;
			break;
		default:
			if (unlikely(net_ratelimit())) {
				dev_warn(tx_ring->dev,
				 "partial checksum but proto=%x!\n",
4103
				 first->protocol);
4104
			}
4105 4106
			break;
		}
4107

4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127
		switch (l4_hdr) {
		case IPPROTO_TCP:
			type_tucmd |= E1000_ADVTXD_TUCMD_L4T_TCP;
			mss_l4len_idx = tcp_hdrlen(skb) <<
					E1000_ADVTXD_L4LEN_SHIFT;
			break;
		case IPPROTO_SCTP:
			type_tucmd |= E1000_ADVTXD_TUCMD_L4T_SCTP;
			mss_l4len_idx = sizeof(struct sctphdr) <<
					E1000_ADVTXD_L4LEN_SHIFT;
			break;
		case IPPROTO_UDP:
			mss_l4len_idx = sizeof(struct udphdr) <<
					E1000_ADVTXD_L4LEN_SHIFT;
			break;
		default:
			if (unlikely(net_ratelimit())) {
				dev_warn(tx_ring->dev,
				 "partial checksum but l4 proto=%x!\n",
				 l4_hdr);
4128
			}
4129
			break;
4130
		}
4131 4132 4133

		/* update TX checksum flag */
		first->tx_flags |= IGB_TX_FLAGS_CSUM;
4134
	}
4135

4136
	vlan_macip_lens |= skb_network_offset(skb) << E1000_ADVTXD_MACLEN_SHIFT;
4137
	vlan_macip_lens |= first->tx_flags & IGB_TX_FLAGS_VLAN_MASK;
4138

4139
	igb_tx_ctxtdesc(tx_ring, vlan_macip_lens, type_tucmd, mss_l4len_idx);
4140 4141
}

4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163
static __le32 igb_tx_cmd_type(u32 tx_flags)
{
	/* set type for advanced descriptor with frame checksum insertion */
	__le32 cmd_type = cpu_to_le32(E1000_ADVTXD_DTYP_DATA |
				      E1000_ADVTXD_DCMD_IFCS |
				      E1000_ADVTXD_DCMD_DEXT);

	/* set HW vlan bit if vlan is present */
	if (tx_flags & IGB_TX_FLAGS_VLAN)
		cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_VLE);

	/* set timestamp bit if present */
	if (tx_flags & IGB_TX_FLAGS_TSTAMP)
		cmd_type |= cpu_to_le32(E1000_ADVTXD_MAC_TSTAMP);

	/* set segmentation bits for TSO */
	if (tx_flags & IGB_TX_FLAGS_TSO)
		cmd_type |= cpu_to_le32(E1000_ADVTXD_DCMD_TSE);

	return cmd_type;
}

4164 4165 4166
static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
				 union e1000_adv_tx_desc *tx_desc,
				 u32 tx_flags, unsigned int paylen)
4167 4168 4169 4170 4171
{
	u32 olinfo_status = paylen << E1000_ADVTXD_PAYLEN_SHIFT;

	/* 82575 requires a unique index per ring if any offload is enabled */
	if ((tx_flags & (IGB_TX_FLAGS_CSUM | IGB_TX_FLAGS_VLAN)) &&
4172
	    test_bit(IGB_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183
		olinfo_status |= tx_ring->reg_idx << 4;

	/* insert L4 checksum */
	if (tx_flags & IGB_TX_FLAGS_CSUM) {
		olinfo_status |= E1000_TXD_POPTS_TXSM << 8;

		/* insert IPv4 checksum */
		if (tx_flags & IGB_TX_FLAGS_IPV4)
			olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
	}

4184
	tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
4185 4186
}

4187 4188 4189 4190 4191
/*
 * The largest size we can write to the descriptor is 65535.  In order to
 * maintain a power of two alignment we have to limit ourselves to 32K.
 */
#define IGB_MAX_TXD_PWR	15
4192
#define IGB_MAX_DATA_PER_TXD	(1<<IGB_MAX_TXD_PWR)
4193

4194 4195
static void igb_tx_map(struct igb_ring *tx_ring,
		       struct igb_tx_buffer *first,
4196
		       const u8 hdr_len)
4197
{
4198
	struct sk_buff *skb = first->skb;
4199 4200 4201 4202 4203 4204 4205 4206
	struct igb_tx_buffer *tx_buffer_info;
	union e1000_adv_tx_desc *tx_desc;
	dma_addr_t dma;
	struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
	unsigned int data_len = skb->data_len;
	unsigned int size = skb_headlen(skb);
	unsigned int paylen = skb->len - hdr_len;
	__le32 cmd_type;
4207
	u32 tx_flags = first->tx_flags;
4208 4209 4210 4211
	u16 i = tx_ring->next_to_use;

	tx_desc = IGB_TX_DESC(tx_ring, i);

4212
	igb_tx_olinfo_status(tx_ring, tx_desc, tx_flags, paylen);
4213 4214 4215 4216
	cmd_type = igb_tx_cmd_type(tx_flags);

	dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
	if (dma_mapping_error(tx_ring->dev, dma))
4217
		goto dma_error;
4218

4219 4220 4221 4222 4223 4224 4225 4226 4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242 4243 4244
	/* record length, and DMA address */
	first->length = size;
	first->dma = dma;
	tx_desc->read.buffer_addr = cpu_to_le64(dma);

	for (;;) {
		while (unlikely(size > IGB_MAX_DATA_PER_TXD)) {
			tx_desc->read.cmd_type_len =
				cmd_type | cpu_to_le32(IGB_MAX_DATA_PER_TXD);

			i++;
			tx_desc++;
			if (i == tx_ring->count) {
				tx_desc = IGB_TX_DESC(tx_ring, 0);
				i = 0;
			}

			dma += IGB_MAX_DATA_PER_TXD;
			size -= IGB_MAX_DATA_PER_TXD;

			tx_desc->read.olinfo_status = 0;
			tx_desc->read.buffer_addr = cpu_to_le64(dma);
		}

		if (likely(!data_len))
			break;
4245

4246
		tx_desc->read.cmd_type_len = cmd_type | cpu_to_le32(size);
4247

4248
		i++;
4249 4250 4251
		tx_desc++;
		if (i == tx_ring->count) {
			tx_desc = IGB_TX_DESC(tx_ring, 0);
4252
			i = 0;
4253
		}
4254

4255 4256 4257 4258 4259 4260
		size = frag->size;
		data_len -= size;

		dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
				   size, DMA_TO_DEVICE);
		if (dma_mapping_error(tx_ring->dev, dma))
4261 4262
			goto dma_error;

4263 4264 4265 4266 4267 4268 4269 4270
		tx_buffer_info = &tx_ring->tx_buffer_info[i];
		tx_buffer_info->length = size;
		tx_buffer_info->dma = dma;

		tx_desc->read.olinfo_status = 0;
		tx_desc->read.buffer_addr = cpu_to_le64(dma);

		frag++;
4271 4272
	}

4273 4274 4275
	/* write last descriptor with RS and EOP bits */
	cmd_type |= cpu_to_le32(size) | cpu_to_le32(IGB_TXD_DCMD);
	tx_desc->read.cmd_type_len = cmd_type;
4276 4277 4278 4279

	/* set the timestamp */
	first->time_stamp = jiffies;

4280 4281 4282 4283 4284 4285 4286 4287 4288 4289
	/*
	 * Force memory writes to complete before letting h/w know there
	 * are new descriptors to fetch.  (Only applicable for weak-ordered
	 * memory model archs, such as IA-64).
	 *
	 * We also need this memory barrier to make certain all of the
	 * status bits have been updated before next_to_watch is written.
	 */
	wmb();

4290
	/* set next_to_watch value indicating a packet is present */
4291
	first->next_to_watch = tx_desc;
4292

4293 4294 4295
	i++;
	if (i == tx_ring->count)
		i = 0;
4296

4297
	tx_ring->next_to_use = i;
4298

4299
	writel(i, tx_ring->tail);
4300

4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314 4315
	/* we need this if more than one processor can write to our tail
	 * at a time, it syncronizes IO on IA64/Altix systems */
	mmiowb();

	return;

dma_error:
	dev_err(tx_ring->dev, "TX DMA map failed\n");

	/* clear dma mappings for failed tx_buffer_info map */
	for (;;) {
		tx_buffer_info = &tx_ring->tx_buffer_info[i];
		igb_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
		if (tx_buffer_info == first)
			break;
4316 4317
		if (i == 0)
			i = tx_ring->count;
4318 4319 4320
		i--;
	}

4321 4322 4323
	tx_ring->next_to_use = i;
}

4324
static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4325
{
4326 4327
	struct net_device *netdev = tx_ring->netdev;

4328 4329
	netif_stop_subqueue(netdev, tx_ring->queue_index);

4330 4331 4332 4333 4334 4335 4336
	/* Herbert's original patch had:
	 *  smp_mb__after_netif_stop_queue();
	 * but since that doesn't exist yet, just open code it. */
	smp_mb();

	/* We need to check again in a case another CPU has just
	 * made room available. */
4337
	if (igb_desc_unused(tx_ring) < size)
4338 4339 4340
		return -EBUSY;

	/* A reprieve! */
4341
	netif_wake_subqueue(netdev, tx_ring->queue_index);
E
Eric Dumazet 已提交
4342 4343 4344 4345 4346

	u64_stats_update_begin(&tx_ring->tx_syncp2);
	tx_ring->tx_stats.restart_queue2++;
	u64_stats_update_end(&tx_ring->tx_syncp2);

4347 4348 4349
	return 0;
}

4350
static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
4351
{
4352
	if (igb_desc_unused(tx_ring) >= size)
4353
		return 0;
4354
	return __igb_maybe_stop_tx(tx_ring, size);
4355 4356
}

4357 4358
netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
				struct igb_ring *tx_ring)
4359
{
4360
	struct igb_tx_buffer *first;
4361
	int tso;
N
Nick Nunley 已提交
4362
	u32 tx_flags = 0;
4363
	__be16 protocol = vlan_get_protocol(skb);
N
Nick Nunley 已提交
4364
	u8 hdr_len = 0;
4365 4366 4367 4368 4369 4370

	/* need: 1 descriptor per page,
	 *       + 2 desc gap to keep tail from touching head,
	 *       + 1 desc for skb->data,
	 *       + 1 desc for context descriptor,
	 * otherwise try next time */
4371
	if (igb_maybe_stop_tx(tx_ring, skb_shinfo(skb)->nr_frags + 4)) {
4372 4373 4374
		/* this is a hard error */
		return NETDEV_TX_BUSY;
	}
4375

4376 4377 4378 4379 4380 4381
	/* record the location of the first descriptor for this packet */
	first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
	first->skb = skb;
	first->bytecount = skb->len;
	first->gso_segs = 1;

4382 4383
	if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
		skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
4384 4385
		tx_flags |= IGB_TX_FLAGS_TSTAMP;
	}
4386

4387
	if (vlan_tx_tag_present(skb)) {
4388 4389 4390 4391
		tx_flags |= IGB_TX_FLAGS_VLAN;
		tx_flags |= (vlan_tx_tag_get(skb) << IGB_TX_FLAGS_VLAN_SHIFT);
	}

4392 4393 4394
	/* record initial flags and protocol */
	first->tx_flags = tx_flags;
	first->protocol = protocol;
A
Alexander Duyck 已提交
4395

4396 4397
	tso = igb_tso(tx_ring, first, &hdr_len);
	if (tso < 0)
4398
		goto out_drop;
4399 4400
	else if (!tso)
		igb_tx_csum(tx_ring, first);
4401

4402
	igb_tx_map(tx_ring, first, hdr_len);
4403 4404

	/* Make sure there is space in the ring for the next send. */
4405
	igb_maybe_stop_tx(tx_ring, MAX_SKB_FRAGS + 4);
4406

4407
	return NETDEV_TX_OK;
4408 4409

out_drop:
4410 4411
	igb_unmap_and_free_tx_resource(tx_ring, first);

4412
	return NETDEV_TX_OK;
4413 4414
}

4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425
static inline struct igb_ring *igb_tx_queue_mapping(struct igb_adapter *adapter,
						    struct sk_buff *skb)
{
	unsigned int r_idx = skb->queue_mapping;

	if (r_idx >= adapter->num_tx_queues)
		r_idx = r_idx % adapter->num_tx_queues;

	return adapter->tx_ring[r_idx];
}

4426 4427
static netdev_tx_t igb_xmit_frame(struct sk_buff *skb,
				  struct net_device *netdev)
4428 4429
{
	struct igb_adapter *adapter = netdev_priv(netdev);
4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440

	if (test_bit(__IGB_DOWN, &adapter->state)) {
		dev_kfree_skb_any(skb);
		return NETDEV_TX_OK;
	}

	if (skb->len <= 0) {
		dev_kfree_skb_any(skb);
		return NETDEV_TX_OK;
	}

4441 4442 4443 4444 4445 4446 4447 4448 4449
	/*
	 * The minimum packet size with TCTL.PSP set is 17 so pad the skb
	 * in order to meet this minimum size requirement.
	 */
	if (skb->len < 17) {
		if (skb_padto(skb, 17))
			return NETDEV_TX_OK;
		skb->len = 17;
	}
4450

4451
	return igb_xmit_frame_ring(skb, igb_tx_queue_mapping(adapter, skb));
4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464
}

/**
 * igb_tx_timeout - Respond to a Tx Hang
 * @netdev: network interface device structure
 **/
static void igb_tx_timeout(struct net_device *netdev)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;

	/* Do the reset outside of interrupt context */
	adapter->tx_timeout_count++;
4465

4466 4467 4468
	if (hw->mac.type == e1000_82580)
		hw->dev_spec._82575.global_device_reset = true;

4469
	schedule_work(&adapter->reset_task);
4470 4471
	wr32(E1000_EICS,
	     (adapter->eims_enable_mask & ~adapter->eims_other));
4472 4473 4474 4475 4476 4477 4478
}

static void igb_reset_task(struct work_struct *work)
{
	struct igb_adapter *adapter;
	adapter = container_of(work, struct igb_adapter, reset_task);

4479 4480
	igb_dump(adapter);
	netdev_err(adapter->netdev, "Reset adapter\n");
4481 4482 4483 4484
	igb_reinit_locked(adapter);
}

/**
E
Eric Dumazet 已提交
4485
 * igb_get_stats64 - Get System Network Statistics
4486
 * @netdev: network interface device structure
E
Eric Dumazet 已提交
4487
 * @stats: rtnl_link_stats64 pointer
4488 4489
 *
 **/
E
Eric Dumazet 已提交
4490 4491
static struct rtnl_link_stats64 *igb_get_stats64(struct net_device *netdev,
						 struct rtnl_link_stats64 *stats)
4492
{
E
Eric Dumazet 已提交
4493 4494 4495 4496 4497 4498 4499 4500
	struct igb_adapter *adapter = netdev_priv(netdev);

	spin_lock(&adapter->stats64_lock);
	igb_update_stats(adapter, &adapter->stats64);
	memcpy(stats, &adapter->stats64, sizeof(*stats));
	spin_unlock(&adapter->stats64_lock);

	return stats;
4501 4502 4503 4504 4505 4506 4507 4508 4509 4510 4511 4512
}

/**
 * igb_change_mtu - Change the Maximum Transfer Unit
 * @netdev: network interface device structure
 * @new_mtu: new value for maximum frame size
 *
 * Returns 0 on success, negative on failure
 **/
static int igb_change_mtu(struct net_device *netdev, int new_mtu)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
4513
	struct pci_dev *pdev = adapter->pdev;
4514
	int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
4515

4516
	if ((new_mtu < 68) || (max_frame > MAX_JUMBO_FRAME_SIZE)) {
4517
		dev_err(&pdev->dev, "Invalid MTU setting\n");
4518 4519 4520
		return -EINVAL;
	}

4521
#define MAX_STD_JUMBO_FRAME_SIZE 9238
4522
	if (max_frame > MAX_STD_JUMBO_FRAME_SIZE) {
4523
		dev_err(&pdev->dev, "MTU > 9216 not supported.\n");
4524 4525 4526 4527 4528
		return -EINVAL;
	}

	while (test_and_set_bit(__IGB_RESETTING, &adapter->state))
		msleep(1);
4529

4530 4531
	/* igb_down has a dependency on max_frame_size */
	adapter->max_frame_size = max_frame;
4532

4533 4534
	if (netif_running(netdev))
		igb_down(adapter);
4535

4536
	dev_info(&pdev->dev, "changing MTU from %d to %d\n",
4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554
		 netdev->mtu, new_mtu);
	netdev->mtu = new_mtu;

	if (netif_running(netdev))
		igb_up(adapter);
	else
		igb_reset(adapter);

	clear_bit(__IGB_RESETTING, &adapter->state);

	return 0;
}

/**
 * igb_update_stats - Update the board statistics counters
 * @adapter: board private structure
 **/

E
Eric Dumazet 已提交
4555 4556
void igb_update_stats(struct igb_adapter *adapter,
		      struct rtnl_link_stats64 *net_stats)
4557 4558 4559
{
	struct e1000_hw *hw = &adapter->hw;
	struct pci_dev *pdev = adapter->pdev;
4560
	u32 reg, mpc;
4561
	u16 phy_tmp;
4562 4563
	int i;
	u64 bytes, packets;
E
Eric Dumazet 已提交
4564 4565
	unsigned int start;
	u64 _bytes, _packets;
4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576 4577

#define PHY_IDLE_ERROR_COUNT_MASK 0x00FF

	/*
	 * Prevent stats update while adapter is being reset, or if the pci
	 * connection is down.
	 */
	if (adapter->link_speed == 0)
		return;
	if (pci_channel_offline(pdev))
		return;

4578 4579 4580 4581
	bytes = 0;
	packets = 0;
	for (i = 0; i < adapter->num_rx_queues; i++) {
		u32 rqdpc_tmp = rd32(E1000_RQDPC(i)) & 0x0FFF;
4582
		struct igb_ring *ring = adapter->rx_ring[i];
E
Eric Dumazet 已提交
4583

4584
		ring->rx_stats.drops += rqdpc_tmp;
4585
		net_stats->rx_fifo_errors += rqdpc_tmp;
E
Eric Dumazet 已提交
4586 4587 4588 4589 4590 4591 4592 4593

		do {
			start = u64_stats_fetch_begin_bh(&ring->rx_syncp);
			_bytes = ring->rx_stats.bytes;
			_packets = ring->rx_stats.packets;
		} while (u64_stats_fetch_retry_bh(&ring->rx_syncp, start));
		bytes += _bytes;
		packets += _packets;
4594 4595
	}

4596 4597
	net_stats->rx_bytes = bytes;
	net_stats->rx_packets = packets;
4598 4599 4600 4601

	bytes = 0;
	packets = 0;
	for (i = 0; i < adapter->num_tx_queues; i++) {
4602
		struct igb_ring *ring = adapter->tx_ring[i];
E
Eric Dumazet 已提交
4603 4604 4605 4606 4607 4608 4609
		do {
			start = u64_stats_fetch_begin_bh(&ring->tx_syncp);
			_bytes = ring->tx_stats.bytes;
			_packets = ring->tx_stats.packets;
		} while (u64_stats_fetch_retry_bh(&ring->tx_syncp, start));
		bytes += _bytes;
		packets += _packets;
4610
	}
4611 4612
	net_stats->tx_bytes = bytes;
	net_stats->tx_packets = packets;
4613 4614

	/* read stats registers */
4615 4616 4617 4618 4619 4620 4621 4622 4623 4624 4625 4626 4627 4628 4629 4630 4631
	adapter->stats.crcerrs += rd32(E1000_CRCERRS);
	adapter->stats.gprc += rd32(E1000_GPRC);
	adapter->stats.gorc += rd32(E1000_GORCL);
	rd32(E1000_GORCH); /* clear GORCL */
	adapter->stats.bprc += rd32(E1000_BPRC);
	adapter->stats.mprc += rd32(E1000_MPRC);
	adapter->stats.roc += rd32(E1000_ROC);

	adapter->stats.prc64 += rd32(E1000_PRC64);
	adapter->stats.prc127 += rd32(E1000_PRC127);
	adapter->stats.prc255 += rd32(E1000_PRC255);
	adapter->stats.prc511 += rd32(E1000_PRC511);
	adapter->stats.prc1023 += rd32(E1000_PRC1023);
	adapter->stats.prc1522 += rd32(E1000_PRC1522);
	adapter->stats.symerrs += rd32(E1000_SYMERRS);
	adapter->stats.sec += rd32(E1000_SEC);

4632 4633 4634
	mpc = rd32(E1000_MPC);
	adapter->stats.mpc += mpc;
	net_stats->rx_fifo_errors += mpc;
4635 4636 4637 4638 4639 4640 4641 4642 4643 4644 4645 4646 4647 4648
	adapter->stats.scc += rd32(E1000_SCC);
	adapter->stats.ecol += rd32(E1000_ECOL);
	adapter->stats.mcc += rd32(E1000_MCC);
	adapter->stats.latecol += rd32(E1000_LATECOL);
	adapter->stats.dc += rd32(E1000_DC);
	adapter->stats.rlec += rd32(E1000_RLEC);
	adapter->stats.xonrxc += rd32(E1000_XONRXC);
	adapter->stats.xontxc += rd32(E1000_XONTXC);
	adapter->stats.xoffrxc += rd32(E1000_XOFFRXC);
	adapter->stats.xofftxc += rd32(E1000_XOFFTXC);
	adapter->stats.fcruc += rd32(E1000_FCRUC);
	adapter->stats.gptc += rd32(E1000_GPTC);
	adapter->stats.gotc += rd32(E1000_GOTCL);
	rd32(E1000_GOTCH); /* clear GOTCL */
4649
	adapter->stats.rnbc += rd32(E1000_RNBC);
4650 4651 4652 4653 4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666
	adapter->stats.ruc += rd32(E1000_RUC);
	adapter->stats.rfc += rd32(E1000_RFC);
	adapter->stats.rjc += rd32(E1000_RJC);
	adapter->stats.tor += rd32(E1000_TORH);
	adapter->stats.tot += rd32(E1000_TOTH);
	adapter->stats.tpr += rd32(E1000_TPR);

	adapter->stats.ptc64 += rd32(E1000_PTC64);
	adapter->stats.ptc127 += rd32(E1000_PTC127);
	adapter->stats.ptc255 += rd32(E1000_PTC255);
	adapter->stats.ptc511 += rd32(E1000_PTC511);
	adapter->stats.ptc1023 += rd32(E1000_PTC1023);
	adapter->stats.ptc1522 += rd32(E1000_PTC1522);

	adapter->stats.mptc += rd32(E1000_MPTC);
	adapter->stats.bptc += rd32(E1000_BPTC);

4667 4668
	adapter->stats.tpt += rd32(E1000_TPT);
	adapter->stats.colc += rd32(E1000_COLC);
4669 4670

	adapter->stats.algnerrc += rd32(E1000_ALGNERRC);
4671 4672 4673 4674 4675 4676 4677
	/* read internal phy specific stats */
	reg = rd32(E1000_CTRL_EXT);
	if (!(reg & E1000_CTRL_EXT_LINK_MODE_MASK)) {
		adapter->stats.rxerrc += rd32(E1000_RXERRC);
		adapter->stats.tncrs += rd32(E1000_TNCRS);
	}

4678 4679 4680 4681 4682 4683 4684 4685 4686 4687 4688 4689 4690 4691
	adapter->stats.tsctc += rd32(E1000_TSCTC);
	adapter->stats.tsctfc += rd32(E1000_TSCTFC);

	adapter->stats.iac += rd32(E1000_IAC);
	adapter->stats.icrxoc += rd32(E1000_ICRXOC);
	adapter->stats.icrxptc += rd32(E1000_ICRXPTC);
	adapter->stats.icrxatc += rd32(E1000_ICRXATC);
	adapter->stats.ictxptc += rd32(E1000_ICTXPTC);
	adapter->stats.ictxatc += rd32(E1000_ICTXATC);
	adapter->stats.ictxqec += rd32(E1000_ICTXQEC);
	adapter->stats.ictxqmtc += rd32(E1000_ICTXQMTC);
	adapter->stats.icrxdmtc += rd32(E1000_ICRXDMTC);

	/* Fill out the OS statistics structure */
4692 4693
	net_stats->multicast = adapter->stats.mprc;
	net_stats->collisions = adapter->stats.colc;
4694 4695 4696 4697

	/* Rx Errors */

	/* RLEC on some newer hardware can be incorrect so build
4698
	 * our own version based on RUC and ROC */
4699
	net_stats->rx_errors = adapter->stats.rxerrc +
4700 4701 4702
		adapter->stats.crcerrs + adapter->stats.algnerrc +
		adapter->stats.ruc + adapter->stats.roc +
		adapter->stats.cexterr;
4703 4704 4705 4706 4707
	net_stats->rx_length_errors = adapter->stats.ruc +
				      adapter->stats.roc;
	net_stats->rx_crc_errors = adapter->stats.crcerrs;
	net_stats->rx_frame_errors = adapter->stats.algnerrc;
	net_stats->rx_missed_errors = adapter->stats.mpc;
4708 4709

	/* Tx Errors */
4710 4711 4712 4713 4714
	net_stats->tx_errors = adapter->stats.ecol +
			       adapter->stats.latecol;
	net_stats->tx_aborted_errors = adapter->stats.ecol;
	net_stats->tx_window_errors = adapter->stats.latecol;
	net_stats->tx_carrier_errors = adapter->stats.tncrs;
4715 4716 4717 4718 4719 4720

	/* Tx Dropped needs to be maintained elsewhere */

	/* Phy Stats */
	if (hw->phy.media_type == e1000_media_type_copper) {
		if ((adapter->link_speed == SPEED_1000) &&
4721
		   (!igb_read_phy_reg(hw, PHY_1000T_STATUS, &phy_tmp))) {
4722 4723 4724 4725 4726 4727 4728 4729 4730
			phy_tmp &= PHY_IDLE_ERROR_COUNT_MASK;
			adapter->phy_stats.idle_errors += phy_tmp;
		}
	}

	/* Management Stats */
	adapter->stats.mgptc += rd32(E1000_MGTPTC);
	adapter->stats.mgprc += rd32(E1000_MGTPRC);
	adapter->stats.mgpdc += rd32(E1000_MGTPDC);
4731 4732 4733 4734 4735 4736 4737 4738 4739

	/* OS2BMC Stats */
	reg = rd32(E1000_MANC);
	if (reg & E1000_MANC_EN_BMC2OS) {
		adapter->stats.o2bgptc += rd32(E1000_O2BGPTC);
		adapter->stats.o2bspc += rd32(E1000_O2BSPC);
		adapter->stats.b2ospc += rd32(E1000_B2OSPC);
		adapter->stats.b2ogprc += rd32(E1000_B2OGPRC);
	}
4740 4741 4742 4743
}

static irqreturn_t igb_msix_other(int irq, void *data)
{
4744
	struct igb_adapter *adapter = data;
4745
	struct e1000_hw *hw = &adapter->hw;
P
PJ Waskiewicz 已提交
4746 4747
	u32 icr = rd32(E1000_ICR);
	/* reading ICR causes bit 31 of EICR to be cleared */
4748

4749 4750 4751
	if (icr & E1000_ICR_DRSTA)
		schedule_work(&adapter->reset_task);

4752
	if (icr & E1000_ICR_DOUTSYNC) {
4753 4754
		/* HW is reporting DMA is out of sync */
		adapter->stats.doosync++;
G
Greg Rose 已提交
4755 4756 4757 4758
		/* The DMA Out of Sync is also indication of a spoof event
		 * in IOV mode. Check the Wrong VM Behavior register to
		 * see if it is really a spoof event. */
		igb_check_wvbr(adapter);
4759
	}
4760

4761 4762 4763 4764 4765 4766 4767 4768 4769 4770 4771
	/* Check for a mailbox event */
	if (icr & E1000_ICR_VMMB)
		igb_msg_task(adapter);

	if (icr & E1000_ICR_LSC) {
		hw->mac.get_link_status = 1;
		/* guard against interrupt when we're going down */
		if (!test_bit(__IGB_DOWN, &adapter->state))
			mod_timer(&adapter->watchdog_timer, jiffies + 1);
	}

4772 4773 4774 4775 4776 4777
	if (adapter->vfs_allocated_count)
		wr32(E1000_IMS, E1000_IMS_LSC |
				E1000_IMS_VMMB |
				E1000_IMS_DOUTSYNC);
	else
		wr32(E1000_IMS, E1000_IMS_LSC | E1000_IMS_DOUTSYNC);
P
PJ Waskiewicz 已提交
4778
	wr32(E1000_EIMS, adapter->eims_other);
4779 4780 4781 4782

	return IRQ_HANDLED;
}

4783
static void igb_write_itr(struct igb_q_vector *q_vector)
4784
{
4785
	struct igb_adapter *adapter = q_vector->adapter;
4786
	u32 itr_val = q_vector->itr_val & 0x7FFC;
4787

4788 4789
	if (!q_vector->set_itr)
		return;
4790

4791 4792
	if (!itr_val)
		itr_val = 0x4;
4793

4794 4795
	if (adapter->hw.mac.type == e1000_82575)
		itr_val |= itr_val << 16;
4796
	else
4797
		itr_val |= E1000_EITR_CNT_IGNR;
4798

4799 4800
	writel(itr_val, q_vector->itr_register);
	q_vector->set_itr = 0;
4801 4802
}

4803
static irqreturn_t igb_msix_ring(int irq, void *data)
4804
{
4805
	struct igb_q_vector *q_vector = data;
4806

4807 4808
	/* Write the ITR value calculated from the previous interrupt. */
	igb_write_itr(q_vector);
4809

4810
	napi_schedule(&q_vector->napi);
P
PJ Waskiewicz 已提交
4811

4812
	return IRQ_HANDLED;
J
Jeb Cramer 已提交
4813 4814
}

4815
#ifdef CONFIG_IGB_DCA
4816
static void igb_update_dca(struct igb_q_vector *q_vector)
J
Jeb Cramer 已提交
4817
{
4818
	struct igb_adapter *adapter = q_vector->adapter;
J
Jeb Cramer 已提交
4819 4820 4821
	struct e1000_hw *hw = &adapter->hw;
	int cpu = get_cpu();

4822 4823 4824
	if (q_vector->cpu == cpu)
		goto out_no_update;

4825 4826
	if (q_vector->tx.ring) {
		int q = q_vector->tx.ring->reg_idx;
4827 4828 4829 4830
		u32 dca_txctrl = rd32(E1000_DCA_TXCTRL(q));
		if (hw->mac.type == e1000_82575) {
			dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK;
			dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
A
Alexander Duyck 已提交
4831
		} else {
4832 4833 4834 4835 4836 4837 4838
			dca_txctrl &= ~E1000_DCA_TXCTRL_CPUID_MASK_82576;
			dca_txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
			              E1000_DCA_TXCTRL_CPUID_SHIFT;
		}
		dca_txctrl |= E1000_DCA_TXCTRL_DESC_DCA_EN;
		wr32(E1000_DCA_TXCTRL(q), dca_txctrl);
	}
4839 4840
	if (q_vector->rx.ring) {
		int q = q_vector->rx.ring->reg_idx;
4841 4842
		u32 dca_rxctrl = rd32(E1000_DCA_RXCTRL(q));
		if (hw->mac.type == e1000_82575) {
A
Alexander Duyck 已提交
4843
			dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK;
M
Maciej Sosnowski 已提交
4844
			dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
4845 4846 4847 4848
		} else {
			dca_rxctrl &= ~E1000_DCA_RXCTRL_CPUID_MASK_82576;
			dca_rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu) <<
			              E1000_DCA_RXCTRL_CPUID_SHIFT;
A
Alexander Duyck 已提交
4849
		}
J
Jeb Cramer 已提交
4850 4851 4852 4853 4854
		dca_rxctrl |= E1000_DCA_RXCTRL_DESC_DCA_EN;
		dca_rxctrl |= E1000_DCA_RXCTRL_HEAD_DCA_EN;
		dca_rxctrl |= E1000_DCA_RXCTRL_DATA_DCA_EN;
		wr32(E1000_DCA_RXCTRL(q), dca_rxctrl);
	}
4855 4856
	q_vector->cpu = cpu;
out_no_update:
J
Jeb Cramer 已提交
4857 4858 4859 4860 4861
	put_cpu();
}

static void igb_setup_dca(struct igb_adapter *adapter)
{
4862
	struct e1000_hw *hw = &adapter->hw;
J
Jeb Cramer 已提交
4863 4864
	int i;

4865
	if (!(adapter->flags & IGB_FLAG_DCA_ENABLED))
J
Jeb Cramer 已提交
4866 4867
		return;

4868 4869 4870
	/* Always use CB2 mode, difference is masked in the CB driver. */
	wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_CB2);

4871
	for (i = 0; i < adapter->num_q_vectors; i++) {
4872 4873
		adapter->q_vector[i]->cpu = -1;
		igb_update_dca(adapter->q_vector[i]);
J
Jeb Cramer 已提交
4874 4875 4876 4877 4878 4879 4880
	}
}

static int __igb_notify_dca(struct device *dev, void *data)
{
	struct net_device *netdev = dev_get_drvdata(dev);
	struct igb_adapter *adapter = netdev_priv(netdev);
4881
	struct pci_dev *pdev = adapter->pdev;
J
Jeb Cramer 已提交
4882 4883 4884 4885 4886 4887
	struct e1000_hw *hw = &adapter->hw;
	unsigned long event = *(unsigned long *)data;

	switch (event) {
	case DCA_PROVIDER_ADD:
		/* if already enabled, don't do it again */
4888
		if (adapter->flags & IGB_FLAG_DCA_ENABLED)
J
Jeb Cramer 已提交
4889 4890
			break;
		if (dca_add_requester(dev) == 0) {
4891
			adapter->flags |= IGB_FLAG_DCA_ENABLED;
4892
			dev_info(&pdev->dev, "DCA enabled\n");
J
Jeb Cramer 已提交
4893 4894 4895 4896 4897
			igb_setup_dca(adapter);
			break;
		}
		/* Fall Through since DCA is disabled. */
	case DCA_PROVIDER_REMOVE:
4898
		if (adapter->flags & IGB_FLAG_DCA_ENABLED) {
J
Jeb Cramer 已提交
4899
			/* without this a class_device is left
4900
			 * hanging around in the sysfs model */
J
Jeb Cramer 已提交
4901
			dca_remove_requester(dev);
4902
			dev_info(&pdev->dev, "DCA disabled\n");
4903
			adapter->flags &= ~IGB_FLAG_DCA_ENABLED;
A
Alexander Duyck 已提交
4904
			wr32(E1000_DCA_CTRL, E1000_DCA_CTRL_DCA_MODE_DISABLE);
J
Jeb Cramer 已提交
4905 4906 4907
		}
		break;
	}
4908

J
Jeb Cramer 已提交
4909
	return 0;
4910 4911
}

J
Jeb Cramer 已提交
4912 4913 4914 4915 4916 4917 4918 4919 4920 4921
static int igb_notify_dca(struct notifier_block *nb, unsigned long event,
                          void *p)
{
	int ret_val;

	ret_val = driver_for_each_device(&igb_driver.driver, NULL, &event,
	                                 __igb_notify_dca);

	return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
}
4922
#endif /* CONFIG_IGB_DCA */
4923

4924 4925 4926 4927 4928 4929 4930 4931
static void igb_ping_all_vfs(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 ping;
	int i;

	for (i = 0 ; i < adapter->vfs_allocated_count; i++) {
		ping = E1000_PF_CONTROL_MSG;
4932
		if (adapter->vf_data[i].flags & IGB_VF_FLAG_CTS)
4933 4934 4935 4936 4937
			ping |= E1000_VT_MSGTYPE_CTS;
		igb_write_mbx(hw, &ping, 1, i);
	}
}

4938 4939 4940 4941 4942 4943
static int igb_set_vf_promisc(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 vmolr = rd32(E1000_VMOLR(vf));
	struct vf_data_storage *vf_data = &adapter->vf_data[vf];

4944
	vf_data->flags &= ~(IGB_VF_FLAG_UNI_PROMISC |
4945 4946 4947 4948 4949
	                    IGB_VF_FLAG_MULTI_PROMISC);
	vmolr &= ~(E1000_VMOLR_ROPE | E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);

	if (*msgbuf & E1000_VF_SET_PROMISC_MULTICAST) {
		vmolr |= E1000_VMOLR_MPME;
4950
		vf_data->flags |= IGB_VF_FLAG_MULTI_PROMISC;
4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969 4970 4971 4972 4973 4974 4975 4976 4977
		*msgbuf &= ~E1000_VF_SET_PROMISC_MULTICAST;
	} else {
		/*
		 * if we have hashes and we are clearing a multicast promisc
		 * flag we need to write the hashes to the MTA as this step
		 * was previously skipped
		 */
		if (vf_data->num_vf_mc_hashes > 30) {
			vmolr |= E1000_VMOLR_MPME;
		} else if (vf_data->num_vf_mc_hashes) {
			int j;
			vmolr |= E1000_VMOLR_ROMPE;
			for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
				igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
		}
	}

	wr32(E1000_VMOLR(vf), vmolr);

	/* there are flags left unprocessed, likely not supported */
	if (*msgbuf & E1000_VT_MSGINFO_MASK)
		return -EINVAL;

	return 0;

}

4978 4979 4980 4981 4982 4983 4984 4985
static int igb_set_vf_multicasts(struct igb_adapter *adapter,
				  u32 *msgbuf, u32 vf)
{
	int n = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
	u16 *hash_list = (u16 *)&msgbuf[1];
	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
	int i;

4986
	/* salt away the number of multicast addresses assigned
4987 4988 4989 4990 4991
	 * to this VF for later use to restore when the PF multi cast
	 * list changes
	 */
	vf_data->num_vf_mc_hashes = n;

4992 4993 4994 4995 4996
	/* only up to 30 hash values supported */
	if (n > 30)
		n = 30;

	/* store the hashes for later use */
4997
	for (i = 0; i < n; i++)
4998
		vf_data->vf_mc_hashes[i] = hash_list[i];
4999 5000

	/* Flush and reset the mta with the new values */
5001
	igb_set_rx_mode(adapter->netdev);
5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012

	return 0;
}

static void igb_restore_vf_multicasts(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	struct vf_data_storage *vf_data;
	int i, j;

	for (i = 0; i < adapter->vfs_allocated_count; i++) {
5013 5014 5015
		u32 vmolr = rd32(E1000_VMOLR(i));
		vmolr &= ~(E1000_VMOLR_ROMPE | E1000_VMOLR_MPME);

5016
		vf_data = &adapter->vf_data[i];
5017 5018 5019 5020 5021 5022 5023 5024 5025 5026

		if ((vf_data->num_vf_mc_hashes > 30) ||
		    (vf_data->flags & IGB_VF_FLAG_MULTI_PROMISC)) {
			vmolr |= E1000_VMOLR_MPME;
		} else if (vf_data->num_vf_mc_hashes) {
			vmolr |= E1000_VMOLR_ROMPE;
			for (j = 0; j < vf_data->num_vf_mc_hashes; j++)
				igb_mta_set(hw, vf_data->vf_mc_hashes[j]);
		}
		wr32(E1000_VMOLR(i), vmolr);
5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054
	}
}

static void igb_clear_vf_vfta(struct igb_adapter *adapter, u32 vf)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 pool_mask, reg, vid;
	int i;

	pool_mask = 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);

	/* Find the vlan filter for this id */
	for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
		reg = rd32(E1000_VLVF(i));

		/* remove the vf from the pool */
		reg &= ~pool_mask;

		/* if pool is empty then remove entry from vfta */
		if (!(reg & E1000_VLVF_POOLSEL_MASK) &&
		    (reg & E1000_VLVF_VLANID_ENABLE)) {
			reg = 0;
			vid = reg & E1000_VLVF_VLANID_MASK;
			igb_vfta_set(hw, vid, false);
		}

		wr32(E1000_VLVF(i), reg);
	}
5055 5056

	adapter->vf_data[vf].vlans_enabled = 0;
5057 5058 5059 5060 5061 5062 5063
}

static s32 igb_vlvf_set(struct igb_adapter *adapter, u32 vid, bool add, u32 vf)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 reg, i;

5064 5065 5066 5067 5068
	/* The vlvf table only exists on 82576 hardware and newer */
	if (hw->mac.type < e1000_82576)
		return -1;

	/* we only need to do this if VMDq is enabled */
5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086 5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097
	if (!adapter->vfs_allocated_count)
		return -1;

	/* Find the vlan filter for this id */
	for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
		reg = rd32(E1000_VLVF(i));
		if ((reg & E1000_VLVF_VLANID_ENABLE) &&
		    vid == (reg & E1000_VLVF_VLANID_MASK))
			break;
	}

	if (add) {
		if (i == E1000_VLVF_ARRAY_SIZE) {
			/* Did not find a matching VLAN ID entry that was
			 * enabled.  Search for a free filter entry, i.e.
			 * one without the enable bit set
			 */
			for (i = 0; i < E1000_VLVF_ARRAY_SIZE; i++) {
				reg = rd32(E1000_VLVF(i));
				if (!(reg & E1000_VLVF_VLANID_ENABLE))
					break;
			}
		}
		if (i < E1000_VLVF_ARRAY_SIZE) {
			/* Found an enabled/available entry */
			reg |= 1 << (E1000_VLVF_POOLSEL_SHIFT + vf);

			/* if !enabled we need to set this up in vfta */
			if (!(reg & E1000_VLVF_VLANID_ENABLE)) {
5098 5099
				/* add VID to filter table */
				igb_vfta_set(hw, vid, true);
5100 5101
				reg |= E1000_VLVF_VLANID_ENABLE;
			}
A
Alexander Duyck 已提交
5102 5103
			reg &= ~E1000_VLVF_VLANID_MASK;
			reg |= vid;
5104
			wr32(E1000_VLVF(i), reg);
5105 5106 5107 5108 5109 5110 5111 5112 5113 5114 5115 5116 5117 5118 5119

			/* do not modify RLPML for PF devices */
			if (vf >= adapter->vfs_allocated_count)
				return 0;

			if (!adapter->vf_data[vf].vlans_enabled) {
				u32 size;
				reg = rd32(E1000_VMOLR(vf));
				size = reg & E1000_VMOLR_RLPML_MASK;
				size += 4;
				reg &= ~E1000_VMOLR_RLPML_MASK;
				reg |= size;
				wr32(E1000_VMOLR(vf), reg);
			}

5120
			adapter->vf_data[vf].vlans_enabled++;
5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131
		}
	} else {
		if (i < E1000_VLVF_ARRAY_SIZE) {
			/* remove vf from the pool */
			reg &= ~(1 << (E1000_VLVF_POOLSEL_SHIFT + vf));
			/* if pool is empty then remove entry from vfta */
			if (!(reg & E1000_VLVF_POOLSEL_MASK)) {
				reg = 0;
				igb_vfta_set(hw, vid, false);
			}
			wr32(E1000_VLVF(i), reg);
5132 5133 5134 5135 5136 5137 5138 5139 5140 5141 5142 5143 5144 5145 5146

			/* do not modify RLPML for PF devices */
			if (vf >= adapter->vfs_allocated_count)
				return 0;

			adapter->vf_data[vf].vlans_enabled--;
			if (!adapter->vf_data[vf].vlans_enabled) {
				u32 size;
				reg = rd32(E1000_VMOLR(vf));
				size = reg & E1000_VMOLR_RLPML_MASK;
				size -= 4;
				reg &= ~E1000_VMOLR_RLPML_MASK;
				reg |= size;
				wr32(E1000_VMOLR(vf), reg);
			}
5147 5148
		}
	}
5149 5150 5151 5152 5153 5154 5155 5156 5157 5158 5159 5160 5161 5162 5163 5164 5165 5166 5167 5168 5169 5170 5171 5172 5173 5174 5175 5176 5177 5178 5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193 5194 5195 5196 5197
	return 0;
}

static void igb_set_vmvir(struct igb_adapter *adapter, u32 vid, u32 vf)
{
	struct e1000_hw *hw = &adapter->hw;

	if (vid)
		wr32(E1000_VMVIR(vf), (vid | E1000_VMVIR_VLANA_DEFAULT));
	else
		wr32(E1000_VMVIR(vf), 0);
}

static int igb_ndo_set_vf_vlan(struct net_device *netdev,
			       int vf, u16 vlan, u8 qos)
{
	int err = 0;
	struct igb_adapter *adapter = netdev_priv(netdev);

	if ((vf >= adapter->vfs_allocated_count) || (vlan > 4095) || (qos > 7))
		return -EINVAL;
	if (vlan || qos) {
		err = igb_vlvf_set(adapter, vlan, !!vlan, vf);
		if (err)
			goto out;
		igb_set_vmvir(adapter, vlan | (qos << VLAN_PRIO_SHIFT), vf);
		igb_set_vmolr(adapter, vf, !vlan);
		adapter->vf_data[vf].pf_vlan = vlan;
		adapter->vf_data[vf].pf_qos = qos;
		dev_info(&adapter->pdev->dev,
			 "Setting VLAN %d, QOS 0x%x on VF %d\n", vlan, qos, vf);
		if (test_bit(__IGB_DOWN, &adapter->state)) {
			dev_warn(&adapter->pdev->dev,
				 "The VF VLAN has been set,"
				 " but the PF device is not up.\n");
			dev_warn(&adapter->pdev->dev,
				 "Bring the PF device up before"
				 " attempting to use the VF device.\n");
		}
	} else {
		igb_vlvf_set(adapter, adapter->vf_data[vf].pf_vlan,
				   false, vf);
		igb_set_vmvir(adapter, vlan, vf);
		igb_set_vmolr(adapter, vf, true);
		adapter->vf_data[vf].pf_vlan = 0;
		adapter->vf_data[vf].pf_qos = 0;
       }
out:
       return err;
5198 5199 5200 5201 5202 5203 5204 5205 5206 5207
}

static int igb_set_vf_vlan(struct igb_adapter *adapter, u32 *msgbuf, u32 vf)
{
	int add = (msgbuf[0] & E1000_VT_MSGINFO_MASK) >> E1000_VT_MSGINFO_SHIFT;
	int vid = (msgbuf[1] & E1000_VLVF_VLANID_MASK);

	return igb_vlvf_set(adapter, vid, add, vf);
}

5208
static inline void igb_vf_reset(struct igb_adapter *adapter, u32 vf)
5209
{
G
Greg Rose 已提交
5210 5211
	/* clear flags - except flag that indicates PF has set the MAC */
	adapter->vf_data[vf].flags &= IGB_VF_FLAG_PF_SET_MAC;
5212
	adapter->vf_data[vf].last_nack = jiffies;
5213 5214

	/* reset offloads to defaults */
5215
	igb_set_vmolr(adapter, vf, true);
5216 5217 5218

	/* reset vlans for device */
	igb_clear_vf_vfta(adapter, vf);
5219 5220 5221 5222 5223 5224
	if (adapter->vf_data[vf].pf_vlan)
		igb_ndo_set_vf_vlan(adapter->netdev, vf,
				    adapter->vf_data[vf].pf_vlan,
				    adapter->vf_data[vf].pf_qos);
	else
		igb_clear_vf_vfta(adapter, vf);
5225 5226 5227 5228 5229

	/* reset multicast table array for vf */
	adapter->vf_data[vf].num_vf_mc_hashes = 0;

	/* Flush and reset the mta with the new values */
5230
	igb_set_rx_mode(adapter->netdev);
5231 5232
}

5233 5234 5235 5236 5237
static void igb_vf_reset_event(struct igb_adapter *adapter, u32 vf)
{
	unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;

	/* generate a new mac address as we were hotplug removed/added */
5238 5239
	if (!(adapter->vf_data[vf].flags & IGB_VF_FLAG_PF_SET_MAC))
		random_ether_addr(vf_mac);
5240 5241 5242 5243 5244 5245

	/* process remaining reset events */
	igb_vf_reset(adapter, vf);
}

static void igb_vf_reset_msg(struct igb_adapter *adapter, u32 vf)
5246 5247 5248
{
	struct e1000_hw *hw = &adapter->hw;
	unsigned char *vf_mac = adapter->vf_data[vf].vf_mac_addresses;
5249
	int rar_entry = hw->mac.rar_entry_count - (vf + 1);
5250 5251 5252 5253
	u32 reg, msgbuf[3];
	u8 *addr = (u8 *)(&msgbuf[1]);

	/* process all the same items cleared in a function level reset */
5254
	igb_vf_reset(adapter, vf);
5255 5256

	/* set vf mac address */
5257
	igb_rar_set_qsel(adapter, vf_mac, rar_entry, vf);
5258 5259 5260 5261 5262 5263 5264

	/* enable transmit and receive for vf */
	reg = rd32(E1000_VFTE);
	wr32(E1000_VFTE, reg | (1 << vf));
	reg = rd32(E1000_VFRE);
	wr32(E1000_VFRE, reg | (1 << vf));

G
Greg Rose 已提交
5265
	adapter->vf_data[vf].flags |= IGB_VF_FLAG_CTS;
5266 5267 5268 5269 5270 5271 5272 5273 5274

	/* reply to reset with ack and vf mac address */
	msgbuf[0] = E1000_VF_RESET | E1000_VT_MSGTYPE_ACK;
	memcpy(addr, vf_mac, 6);
	igb_write_mbx(hw, msgbuf, 3, vf);
}

static int igb_set_vf_mac_addr(struct igb_adapter *adapter, u32 *msg, int vf)
{
G
Greg Rose 已提交
5275 5276 5277 5278
	/*
	 * The VF MAC Address is stored in a packed array of bytes
	 * starting at the second 32 bit word of the msg array
	 */
5279 5280
	unsigned char *addr = (char *)&msg[1];
	int err = -1;
5281

5282 5283
	if (is_valid_ether_addr(addr))
		err = igb_set_vf_mac(adapter, vf, addr);
5284

5285
	return err;
5286 5287 5288 5289 5290
}

static void igb_rcv_ack_from_vf(struct igb_adapter *adapter, u32 vf)
{
	struct e1000_hw *hw = &adapter->hw;
5291
	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5292 5293 5294
	u32 msg = E1000_VT_MSGTYPE_NACK;

	/* if device isn't clear to send it shouldn't be reading either */
5295 5296
	if (!(vf_data->flags & IGB_VF_FLAG_CTS) &&
	    time_after(jiffies, vf_data->last_nack + (2 * HZ))) {
5297
		igb_write_mbx(hw, &msg, 1, vf);
5298
		vf_data->last_nack = jiffies;
5299 5300 5301
	}
}

5302
static void igb_rcv_msg_from_vf(struct igb_adapter *adapter, u32 vf)
5303
{
5304 5305
	struct pci_dev *pdev = adapter->pdev;
	u32 msgbuf[E1000_VFMAILBOX_SIZE];
5306
	struct e1000_hw *hw = &adapter->hw;
5307
	struct vf_data_storage *vf_data = &adapter->vf_data[vf];
5308 5309
	s32 retval;

5310
	retval = igb_read_mbx(hw, msgbuf, E1000_VFMAILBOX_SIZE, vf);
5311

5312 5313
	if (retval) {
		/* if receive failed revoke VF CTS stats and restart init */
5314
		dev_err(&pdev->dev, "Error receiving message from VF\n");
5315 5316 5317 5318 5319
		vf_data->flags &= ~IGB_VF_FLAG_CTS;
		if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
			return;
		goto out;
	}
5320 5321 5322

	/* this is a message we already processed, do nothing */
	if (msgbuf[0] & (E1000_VT_MSGTYPE_ACK | E1000_VT_MSGTYPE_NACK))
5323
		return;
5324 5325 5326 5327 5328 5329 5330 5331

	/*
	 * until the vf completes a reset it should not be
	 * allowed to start any configuration.
	 */

	if (msgbuf[0] == E1000_VF_RESET) {
		igb_vf_reset_msg(adapter, vf);
5332
		return;
5333 5334
	}

5335
	if (!(vf_data->flags & IGB_VF_FLAG_CTS)) {
5336 5337 5338 5339
		if (!time_after(jiffies, vf_data->last_nack + (2 * HZ)))
			return;
		retval = -1;
		goto out;
5340 5341 5342 5343
	}

	switch ((msgbuf[0] & 0xFFFF)) {
	case E1000_VF_SET_MAC_ADDR:
5344 5345 5346 5347 5348 5349 5350 5351
		retval = -EINVAL;
		if (!(vf_data->flags & IGB_VF_FLAG_PF_SET_MAC))
			retval = igb_set_vf_mac_addr(adapter, msgbuf, vf);
		else
			dev_warn(&pdev->dev,
				 "VF %d attempted to override administratively "
				 "set MAC address\nReload the VF driver to "
				 "resume operations\n", vf);
5352
		break;
5353 5354 5355
	case E1000_VF_SET_PROMISC:
		retval = igb_set_vf_promisc(adapter, msgbuf, vf);
		break;
5356 5357 5358 5359 5360 5361 5362
	case E1000_VF_SET_MULTICAST:
		retval = igb_set_vf_multicasts(adapter, msgbuf, vf);
		break;
	case E1000_VF_SET_LPE:
		retval = igb_set_vf_rlpml(adapter, msgbuf[1], vf);
		break;
	case E1000_VF_SET_VLAN:
5363 5364 5365 5366 5367 5368
		retval = -1;
		if (vf_data->pf_vlan)
			dev_warn(&pdev->dev,
				 "VF %d attempted to override administratively "
				 "set VLAN tag\nReload the VF driver to "
				 "resume operations\n", vf);
5369 5370
		else
			retval = igb_set_vf_vlan(adapter, msgbuf, vf);
5371 5372
		break;
	default:
5373
		dev_err(&pdev->dev, "Unhandled Msg %08x\n", msgbuf[0]);
5374 5375 5376 5377
		retval = -1;
		break;
	}

5378 5379
	msgbuf[0] |= E1000_VT_MSGTYPE_CTS;
out:
5380 5381 5382 5383 5384 5385 5386
	/* notify the VF of the results of what it sent us */
	if (retval)
		msgbuf[0] |= E1000_VT_MSGTYPE_NACK;
	else
		msgbuf[0] |= E1000_VT_MSGTYPE_ACK;

	igb_write_mbx(hw, msgbuf, 1, vf);
5387
}
5388

5389 5390 5391 5392 5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406
static void igb_msg_task(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	u32 vf;

	for (vf = 0; vf < adapter->vfs_allocated_count; vf++) {
		/* process any reset requests */
		if (!igb_check_for_rst(hw, vf))
			igb_vf_reset_event(adapter, vf);

		/* process any messages pending */
		if (!igb_check_for_msg(hw, vf))
			igb_rcv_msg_from_vf(adapter, vf);

		/* process any acks */
		if (!igb_check_for_ack(hw, vf))
			igb_rcv_ack_from_vf(adapter, vf);
	}
5407 5408
}

5409 5410 5411 5412 5413 5414 5415
/**
 *  igb_set_uta - Set unicast filter table address
 *  @adapter: board private structure
 *
 *  The unicast table address is a register array of 32-bit registers.
 *  The table is meant to be used in a way similar to how the MTA is used
 *  however due to certain limitations in the hardware it is necessary to
L
Lucas De Marchi 已提交
5416 5417
 *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
 *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
5418 5419 5420 5421 5422 5423 5424 5425 5426 5427 5428 5429 5430 5431 5432 5433 5434 5435
 **/
static void igb_set_uta(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
	int i;

	/* The UTA table only exists on 82576 hardware and newer */
	if (hw->mac.type < e1000_82576)
		return;

	/* we only need to do this if VMDq is enabled */
	if (!adapter->vfs_allocated_count)
		return;

	for (i = 0; i < hw->mac.uta_reg_count; i++)
		array_wr32(E1000_UTA, i, ~0);
}

5436 5437 5438 5439 5440 5441 5442
/**
 * igb_intr_msi - Interrupt Handler
 * @irq: interrupt number
 * @data: pointer to a network interface device structure
 **/
static irqreturn_t igb_intr_msi(int irq, void *data)
{
5443 5444
	struct igb_adapter *adapter = data;
	struct igb_q_vector *q_vector = adapter->q_vector[0];
5445 5446 5447 5448
	struct e1000_hw *hw = &adapter->hw;
	/* read ICR disables interrupts using IAM */
	u32 icr = rd32(E1000_ICR);

5449
	igb_write_itr(q_vector);
5450

5451 5452 5453
	if (icr & E1000_ICR_DRSTA)
		schedule_work(&adapter->reset_task);

5454
	if (icr & E1000_ICR_DOUTSYNC) {
5455 5456 5457 5458
		/* HW is reporting DMA is out of sync */
		adapter->stats.doosync++;
	}

5459 5460 5461 5462 5463 5464
	if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
		hw->mac.get_link_status = 1;
		if (!test_bit(__IGB_DOWN, &adapter->state))
			mod_timer(&adapter->watchdog_timer, jiffies + 1);
	}

5465
	napi_schedule(&q_vector->napi);
5466 5467 5468 5469 5470

	return IRQ_HANDLED;
}

/**
5471
 * igb_intr - Legacy Interrupt Handler
5472 5473 5474 5475 5476
 * @irq: interrupt number
 * @data: pointer to a network interface device structure
 **/
static irqreturn_t igb_intr(int irq, void *data)
{
5477 5478
	struct igb_adapter *adapter = data;
	struct igb_q_vector *q_vector = adapter->q_vector[0];
5479 5480 5481 5482 5483 5484 5485 5486 5487 5488
	struct e1000_hw *hw = &adapter->hw;
	/* Interrupt Auto-Mask...upon reading ICR, interrupts are masked.  No
	 * need for the IMC write */
	u32 icr = rd32(E1000_ICR);

	/* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
	 * not set, then the adapter didn't send an interrupt */
	if (!(icr & E1000_ICR_INT_ASSERTED))
		return IRQ_NONE;

5489 5490
	igb_write_itr(q_vector);

5491 5492 5493
	if (icr & E1000_ICR_DRSTA)
		schedule_work(&adapter->reset_task);

5494
	if (icr & E1000_ICR_DOUTSYNC) {
5495 5496 5497 5498
		/* HW is reporting DMA is out of sync */
		adapter->stats.doosync++;
	}

5499 5500 5501 5502 5503 5504 5505
	if (icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
		hw->mac.get_link_status = 1;
		/* guard against interrupt when we're going down */
		if (!test_bit(__IGB_DOWN, &adapter->state))
			mod_timer(&adapter->watchdog_timer, jiffies + 1);
	}

5506
	napi_schedule(&q_vector->napi);
5507 5508 5509 5510

	return IRQ_HANDLED;
}

5511
void igb_ring_irq_enable(struct igb_q_vector *q_vector)
5512
{
5513
	struct igb_adapter *adapter = q_vector->adapter;
5514
	struct e1000_hw *hw = &adapter->hw;
5515

5516 5517 5518 5519
	if ((q_vector->rx.ring && (adapter->rx_itr_setting & 3)) ||
	    (!q_vector->rx.ring && (adapter->tx_itr_setting & 3))) {
		if ((adapter->num_q_vectors == 1) && !adapter->vf_data)
			igb_set_itr(q_vector);
5520
		else
5521
			igb_update_ring_itr(q_vector);
5522 5523
	}

5524 5525
	if (!test_bit(__IGB_DOWN, &adapter->state)) {
		if (adapter->msix_entries)
5526
			wr32(E1000_EIMS, q_vector->eims_value);
5527 5528 5529
		else
			igb_irq_enable(adapter);
	}
5530 5531
}

5532 5533 5534 5535 5536 5537
/**
 * igb_poll - NAPI Rx polling callback
 * @napi: napi polling structure
 * @budget: count of how many packets we should handle
 **/
static int igb_poll(struct napi_struct *napi, int budget)
5538
{
5539 5540 5541
	struct igb_q_vector *q_vector = container_of(napi,
	                                             struct igb_q_vector,
	                                             napi);
5542
	bool clean_complete = true;
5543

5544
#ifdef CONFIG_IGB_DCA
5545 5546
	if (q_vector->adapter->flags & IGB_FLAG_DCA_ENABLED)
		igb_update_dca(q_vector);
J
Jeb Cramer 已提交
5547
#endif
5548
	if (q_vector->tx.ring)
5549
		clean_complete = igb_clean_tx_irq(q_vector);
5550

5551
	if (q_vector->rx.ring)
5552
		clean_complete &= igb_clean_rx_irq(q_vector, budget);
5553

5554 5555 5556
	/* If all work not completed, return budget and keep polling */
	if (!clean_complete)
		return budget;
5557

5558
	/* If not enough Rx work done, exit the polling mode */
5559 5560
	napi_complete(napi);
	igb_ring_irq_enable(q_vector);
5561

5562
	return 0;
5563
}
A
Al Viro 已提交
5564

5565
/**
5566
 * igb_systim_to_hwtstamp - convert system time value to hw timestamp
5567
 * @adapter: board private structure
5568 5569 5570 5571 5572 5573 5574 5575 5576 5577 5578 5579
 * @shhwtstamps: timestamp structure to update
 * @regval: unsigned 64bit system time value.
 *
 * We need to convert the system time value stored in the RX/TXSTMP registers
 * into a hwtstamp which can be used by the upper level timestamping functions
 */
static void igb_systim_to_hwtstamp(struct igb_adapter *adapter,
                                   struct skb_shared_hwtstamps *shhwtstamps,
                                   u64 regval)
{
	u64 ns;

5580 5581 5582 5583 5584 5585 5586
	/*
	 * The 82580 starts with 1ns at bit 0 in RX/TXSTMPL, shift this up to
	 * 24 to match clock shift we setup earlier.
	 */
	if (adapter->hw.mac.type == e1000_82580)
		regval <<= IGB_82580_TSYNC_SHIFT;

5587 5588 5589 5590 5591 5592 5593 5594 5595 5596
	ns = timecounter_cyc2time(&adapter->clock, regval);
	timecompare_update(&adapter->compare, ns);
	memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
	shhwtstamps->hwtstamp = ns_to_ktime(ns);
	shhwtstamps->syststamp = timecompare_transform(&adapter->compare, ns);
}

/**
 * igb_tx_hwtstamp - utility function which checks for TX time stamp
 * @q_vector: pointer to q_vector containing needed info
5597
 * @buffer: pointer to igb_tx_buffer structure
5598 5599 5600 5601 5602
 *
 * If we were asked to do hardware stamping and such a time stamp is
 * available, then it must have been for this skb here because we only
 * allow only one such packet into the queue.
 */
5603 5604
static void igb_tx_hwtstamp(struct igb_q_vector *q_vector,
			    struct igb_tx_buffer *buffer_info)
5605
{
5606
	struct igb_adapter *adapter = q_vector->adapter;
5607
	struct e1000_hw *hw = &adapter->hw;
5608 5609
	struct skb_shared_hwtstamps shhwtstamps;
	u64 regval;
5610

5611
	/* if skb does not support hw timestamp or TX stamp not valid exit */
5612
	if (likely(!(buffer_info->tx_flags & IGB_TX_FLAGS_TSTAMP)) ||
5613 5614 5615 5616 5617 5618 5619
	    !(rd32(E1000_TSYNCTXCTL) & E1000_TSYNCTXCTL_VALID))
		return;

	regval = rd32(E1000_TXSTMPL);
	regval |= (u64)rd32(E1000_TXSTMPH) << 32;

	igb_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
5620
	skb_tstamp_tx(buffer_info->skb, &shhwtstamps);
5621 5622
}

5623 5624
/**
 * igb_clean_tx_irq - Reclaim resources after transmit completes
5625
 * @q_vector: pointer to q_vector containing needed info
5626 5627
 * returns true if ring is completely cleaned
 **/
5628
static bool igb_clean_tx_irq(struct igb_q_vector *q_vector)
5629
{
5630
	struct igb_adapter *adapter = q_vector->adapter;
5631
	struct igb_ring *tx_ring = q_vector->tx.ring;
5632
	struct igb_tx_buffer *tx_buffer;
5633
	union e1000_adv_tx_desc *tx_desc, *eop_desc;
5634
	unsigned int total_bytes = 0, total_packets = 0;
5635
	unsigned int budget = q_vector->tx.work_limit;
5636
	unsigned int i = tx_ring->next_to_clean;
5637

5638 5639
	if (test_bit(__IGB_DOWN, &adapter->state))
		return true;
A
Alexander Duyck 已提交
5640

5641
	tx_buffer = &tx_ring->tx_buffer_info[i];
5642
	tx_desc = IGB_TX_DESC(tx_ring, i);
5643
	i -= tx_ring->count;
5644

5645
	for (; budget; budget--) {
5646
		eop_desc = tx_buffer->next_to_watch;
5647

5648 5649 5650 5651 5652 5653
		/* prevent any other reads prior to eop_desc */
		rmb();

		/* if next_to_watch is not set then there is no work pending */
		if (!eop_desc)
			break;
5654 5655 5656 5657 5658

		/* if DD is not set pending work has not been completed */
		if (!(eop_desc->wb.status & cpu_to_le32(E1000_TXD_STAT_DD)))
			break;

5659 5660
		/* clear next_to_watch to prevent false hangs */
		tx_buffer->next_to_watch = NULL;
5661

5662 5663 5664
		/* update the statistics for this packet */
		total_bytes += tx_buffer->bytecount;
		total_packets += tx_buffer->gso_segs;
5665

5666 5667 5668 5669 5670 5671
		/* retrieve hardware timestamp */
		igb_tx_hwtstamp(q_vector, tx_buffer);

		/* free the skb */
		dev_kfree_skb_any(tx_buffer->skb);
		tx_buffer->skb = NULL;
5672

5673 5674 5675 5676 5677 5678 5679 5680 5681
		/* unmap skb header data */
		dma_unmap_single(tx_ring->dev,
				 tx_buffer->dma,
				 tx_buffer->length,
				 DMA_TO_DEVICE);

		/* clear last DMA location and unmap remaining buffers */
		while (tx_desc != eop_desc) {
			tx_buffer->dma = 0;
5682

5683 5684
			tx_buffer++;
			tx_desc++;
5685
			i++;
5686 5687
			if (unlikely(!i)) {
				i -= tx_ring->count;
5688
				tx_buffer = tx_ring->tx_buffer_info;
5689 5690
				tx_desc = IGB_TX_DESC(tx_ring, 0);
			}
5691 5692 5693 5694 5695 5696 5697 5698 5699 5700 5701 5702 5703 5704 5705 5706 5707 5708 5709 5710 5711 5712

			/* unmap any remaining paged data */
			if (tx_buffer->dma) {
				dma_unmap_page(tx_ring->dev,
					       tx_buffer->dma,
					       tx_buffer->length,
					       DMA_TO_DEVICE);
			}
		}

		/* clear last DMA location */
		tx_buffer->dma = 0;

		/* move us one more past the eop_desc for start of next pkt */
		tx_buffer++;
		tx_desc++;
		i++;
		if (unlikely(!i)) {
			i -= tx_ring->count;
			tx_buffer = tx_ring->tx_buffer_info;
			tx_desc = IGB_TX_DESC(tx_ring, 0);
		}
A
Alexander Duyck 已提交
5713 5714
	}

5715
	i += tx_ring->count;
5716
	tx_ring->next_to_clean = i;
5717 5718 5719 5720
	u64_stats_update_begin(&tx_ring->tx_syncp);
	tx_ring->tx_stats.bytes += total_bytes;
	tx_ring->tx_stats.packets += total_packets;
	u64_stats_update_end(&tx_ring->tx_syncp);
5721 5722
	q_vector->tx.total_bytes += total_bytes;
	q_vector->tx.total_packets += total_packets;
5723

5724
	if (test_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags)) {
5725
		struct e1000_hw *hw = &adapter->hw;
E
Eric Dumazet 已提交
5726

5727
		eop_desc = tx_buffer->next_to_watch;
5728 5729 5730

		/* Detect a transmit hang in hardware, this serializes the
		 * check with the clearing of time_stamp and movement of i */
5731
		clear_bit(IGB_RING_FLAG_TX_DETECT_HANG, &tx_ring->flags);
5732 5733
		if (eop_desc &&
		    time_after(jiffies, tx_buffer->time_stamp +
5734 5735
			       (adapter->tx_timeout_factor * HZ)) &&
		    !(rd32(E1000_STATUS) & E1000_STATUS_TXOFF)) {
5736 5737

			/* detected Tx unit hang */
5738
			dev_err(tx_ring->dev,
5739
				"Detected Tx Unit Hang\n"
A
Alexander Duyck 已提交
5740
				"  Tx Queue             <%d>\n"
5741 5742 5743 5744 5745 5746
				"  TDH                  <%x>\n"
				"  TDT                  <%x>\n"
				"  next_to_use          <%x>\n"
				"  next_to_clean        <%x>\n"
				"buffer_info[next_to_clean]\n"
				"  time_stamp           <%lx>\n"
5747
				"  next_to_watch        <%p>\n"
5748 5749
				"  jiffies              <%lx>\n"
				"  desc.status          <%x>\n",
A
Alexander Duyck 已提交
5750
				tx_ring->queue_index,
5751
				rd32(E1000_TDH(tx_ring->reg_idx)),
5752
				readl(tx_ring->tail),
5753 5754
				tx_ring->next_to_use,
				tx_ring->next_to_clean,
5755 5756
				tx_buffer->time_stamp,
				eop_desc,
5757
				jiffies,
A
Alexander Duyck 已提交
5758
				eop_desc->wb.status);
5759 5760 5761 5762 5763
			netif_stop_subqueue(tx_ring->netdev,
					    tx_ring->queue_index);

			/* we are about to reset, no point in enabling stuff */
			return true;
5764 5765
		}
	}
5766 5767 5768 5769 5770 5771 5772 5773 5774 5775 5776 5777 5778 5779 5780 5781 5782 5783 5784 5785 5786

	if (unlikely(total_packets &&
		     netif_carrier_ok(tx_ring->netdev) &&
		     igb_desc_unused(tx_ring) >= IGB_TX_QUEUE_WAKE)) {
		/* Make sure that anybody stopping the queue after this
		 * sees the new next_to_clean.
		 */
		smp_mb();
		if (__netif_subqueue_stopped(tx_ring->netdev,
					     tx_ring->queue_index) &&
		    !(test_bit(__IGB_DOWN, &adapter->state))) {
			netif_wake_subqueue(tx_ring->netdev,
					    tx_ring->queue_index);

			u64_stats_update_begin(&tx_ring->tx_syncp);
			tx_ring->tx_stats.restart_queue++;
			u64_stats_update_end(&tx_ring->tx_syncp);
		}
	}

	return !!budget;
5787 5788
}

5789
static inline void igb_rx_checksum(struct igb_ring *ring,
5790 5791
				   union e1000_adv_rx_desc *rx_desc,
				   struct sk_buff *skb)
5792
{
5793
	skb_checksum_none_assert(skb);
5794

5795
	/* Ignore Checksum bit is set */
5796
	if (igb_test_staterr(rx_desc, E1000_RXD_STAT_IXSM))
5797 5798 5799 5800
		return;

	/* Rx checksum disabled via ethtool */
	if (!(ring->netdev->features & NETIF_F_RXCSUM))
5801
		return;
5802

5803
	/* TCP/UDP checksum error bit is set */
5804 5805 5806
	if (igb_test_staterr(rx_desc,
			     E1000_RXDEXT_STATERR_TCPE |
			     E1000_RXDEXT_STATERR_IPE)) {
5807 5808 5809 5810 5811
		/*
		 * work around errata with sctp packets where the TCPE aka
		 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
		 * packets, (aka let the stack check the crc32c)
		 */
5812 5813
		if (!((skb->len == 60) &&
		      test_bit(IGB_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
E
Eric Dumazet 已提交
5814
			u64_stats_update_begin(&ring->rx_syncp);
5815
			ring->rx_stats.csum_err++;
E
Eric Dumazet 已提交
5816 5817
			u64_stats_update_end(&ring->rx_syncp);
		}
5818 5819 5820 5821
		/* let the stack verify checksum errors */
		return;
	}
	/* It must be a TCP or UDP packet with a valid checksum */
5822 5823
	if (igb_test_staterr(rx_desc, E1000_RXD_STAT_TCPCS |
				      E1000_RXD_STAT_UDPCS))
5824 5825
		skb->ip_summed = CHECKSUM_UNNECESSARY;

5826 5827
	dev_dbg(ring->dev, "cksum success: bits %08X\n",
		le32_to_cpu(rx_desc->wb.upper.status_error));
5828 5829
}

5830 5831 5832
static void igb_rx_hwtstamp(struct igb_q_vector *q_vector,
			    union e1000_adv_rx_desc *rx_desc,
			    struct sk_buff *skb)
5833 5834 5835 5836 5837
{
	struct igb_adapter *adapter = q_vector->adapter;
	struct e1000_hw *hw = &adapter->hw;
	u64 regval;

5838 5839 5840 5841
	if (!igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP |
				       E1000_RXDADV_STAT_TS))
		return;

5842 5843 5844 5845 5846 5847 5848 5849
	/*
	 * If this bit is set, then the RX registers contain the time stamp. No
	 * other packet will be time stamped until we read these registers, so
	 * read the registers to make them available again. Because only one
	 * packet can be time stamped at a time, we know that the register
	 * values must belong to this one here and therefore we don't need to
	 * compare any of the additional attributes stored for it.
	 *
5850
	 * If nothing went wrong, then it should have a shared tx_flags that we
5851 5852
	 * can turn into a skb_shared_hwtstamps.
	 */
5853
	if (igb_test_staterr(rx_desc, E1000_RXDADV_STAT_TSIP)) {
N
Nick Nunley 已提交
5854 5855 5856 5857 5858 5859 5860
		u32 *stamp = (u32 *)skb->data;
		regval = le32_to_cpu(*(stamp + 2));
		regval |= (u64)le32_to_cpu(*(stamp + 3)) << 32;
		skb_pull(skb, IGB_TS_HDR_LEN);
	} else {
		if(!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
			return;
5861

N
Nick Nunley 已提交
5862 5863 5864
		regval = rd32(E1000_RXSTMPL);
		regval |= (u64)rd32(E1000_RXSTMPH) << 32;
	}
5865 5866 5867

	igb_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
}
5868
static inline u16 igb_get_hlen(union e1000_adv_rx_desc *rx_desc)
5869 5870 5871 5872 5873 5874 5875
{
	/* HW will not DMA in data larger than the given buffer, even if it
	 * parses the (NFS, of course) header to be larger.  In that case, it
	 * fills the header buffer and spills the rest into the page.
	 */
	u16 hlen = (le16_to_cpu(rx_desc->wb.lower.lo_dword.hdr_info) &
	           E1000_RXDADV_HDRBUFLEN_MASK) >> E1000_RXDADV_HDRBUFLEN_SHIFT;
5876 5877
	if (hlen > IGB_RX_HDR_LEN)
		hlen = IGB_RX_HDR_LEN;
5878 5879 5880
	return hlen;
}

5881
static bool igb_clean_rx_irq(struct igb_q_vector *q_vector, int budget)
5882
{
5883
	struct igb_ring *rx_ring = q_vector->rx.ring;
5884 5885
	union e1000_adv_rx_desc *rx_desc;
	const int current_node = numa_node_id();
5886
	unsigned int total_bytes = 0, total_packets = 0;
5887 5888
	u16 cleaned_count = igb_desc_unused(rx_ring);
	u16 i = rx_ring->next_to_clean;
5889

5890
	rx_desc = IGB_RX_DESC(rx_ring, i);
5891

5892
	while (igb_test_staterr(rx_desc, E1000_RXD_STAT_DD)) {
5893
		struct igb_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];
5894 5895
		struct sk_buff *skb = buffer_info->skb;
		union e1000_adv_rx_desc *next_rxd;
5896

5897
		buffer_info->skb = NULL;
5898
		prefetch(skb->data);
5899 5900 5901 5902

		i++;
		if (i == rx_ring->count)
			i = 0;
5903

5904
		next_rxd = IGB_RX_DESC(rx_ring, i);
5905
		prefetch(next_rxd);
5906

5907 5908 5909 5910 5911 5912
		/*
		 * This memory barrier is needed to keep us from reading
		 * any other fields out of the rx_desc until we know the
		 * RXD_STAT_DD bit is set
		 */
		rmb();
5913

5914 5915 5916
		if (!skb_is_nonlinear(skb)) {
			__skb_put(skb, igb_get_hlen(rx_desc));
			dma_unmap_single(rx_ring->dev, buffer_info->dma,
5917
					 IGB_RX_HDR_LEN,
5918
					 DMA_FROM_DEVICE);
J
Jesse Brandeburg 已提交
5919
			buffer_info->dma = 0;
5920 5921
		}

5922 5923
		if (rx_desc->wb.upper.length) {
			u16 length = le16_to_cpu(rx_desc->wb.upper.length);
5924

K
Koki Sanagi 已提交
5925
			skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
5926 5927 5928 5929
						buffer_info->page,
						buffer_info->page_offset,
						length);

5930 5931 5932 5933
			skb->len += length;
			skb->data_len += length;
			skb->truesize += length;

5934 5935
			if ((page_count(buffer_info->page) != 1) ||
			    (page_to_nid(buffer_info->page) != current_node))
5936 5937 5938
				buffer_info->page = NULL;
			else
				get_page(buffer_info->page);
5939

5940 5941 5942
			dma_unmap_page(rx_ring->dev, buffer_info->page_dma,
				       PAGE_SIZE / 2, DMA_FROM_DEVICE);
			buffer_info->page_dma = 0;
5943 5944
		}

5945
		if (!igb_test_staterr(rx_desc, E1000_RXD_STAT_EOP)) {
5946 5947
			struct igb_rx_buffer *next_buffer;
			next_buffer = &rx_ring->rx_buffer_info[i];
5948 5949 5950 5951
			buffer_info->skb = next_buffer->skb;
			buffer_info->dma = next_buffer->dma;
			next_buffer->skb = skb;
			next_buffer->dma = 0;
5952 5953
			goto next_desc;
		}
5954

5955 5956
		if (igb_test_staterr(rx_desc,
				     E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
5957
			dev_kfree_skb_any(skb);
5958 5959 5960
			goto next_desc;
		}

5961 5962
		igb_rx_hwtstamp(q_vector, rx_desc, skb);
		igb_rx_checksum(rx_ring, rx_desc, skb);
5963

5964
		if (igb_test_staterr(rx_desc, E1000_RXD_STAT_VP)) {
J
Jiri Pirko 已提交
5965
			u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
5966

J
Jiri Pirko 已提交
5967 5968
			__vlan_hwaccel_put_tag(skb, vid);
		}
5969 5970 5971 5972 5973 5974

		total_bytes += skb->len;
		total_packets++;

		skb->protocol = eth_type_trans(skb, rx_ring->netdev);

J
Jiri Pirko 已提交
5975
		napi_gro_receive(&q_vector->napi, skb);
5976

5977
		budget--;
5978
next_desc:
5979 5980 5981 5982
		if (!budget)
			break;

		cleaned_count++;
5983 5984
		/* return some buffers to hardware, one at a time is too slow */
		if (cleaned_count >= IGB_RX_BUFFER_WRITE) {
5985
			igb_alloc_rx_buffers(rx_ring, cleaned_count);
5986 5987 5988 5989 5990 5991
			cleaned_count = 0;
		}

		/* use prefetched values */
		rx_desc = next_rxd;
	}
5992

5993
	rx_ring->next_to_clean = i;
E
Eric Dumazet 已提交
5994
	u64_stats_update_begin(&rx_ring->rx_syncp);
5995 5996
	rx_ring->rx_stats.packets += total_packets;
	rx_ring->rx_stats.bytes += total_bytes;
E
Eric Dumazet 已提交
5997
	u64_stats_update_end(&rx_ring->rx_syncp);
5998 5999
	q_vector->rx.total_packets += total_packets;
	q_vector->rx.total_bytes += total_bytes;
6000 6001

	if (cleaned_count)
6002
		igb_alloc_rx_buffers(rx_ring, cleaned_count);
6003

6004
	return !!budget;
6005 6006
}

6007
static bool igb_alloc_mapped_skb(struct igb_ring *rx_ring,
6008
				 struct igb_rx_buffer *bi)
6009 6010 6011 6012 6013 6014 6015 6016 6017 6018 6019 6020 6021 6022 6023 6024 6025 6026 6027 6028 6029 6030 6031 6032 6033 6034 6035 6036 6037 6038 6039 6040 6041
{
	struct sk_buff *skb = bi->skb;
	dma_addr_t dma = bi->dma;

	if (dma)
		return true;

	if (likely(!skb)) {
		skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
						IGB_RX_HDR_LEN);
		bi->skb = skb;
		if (!skb) {
			rx_ring->rx_stats.alloc_failed++;
			return false;
		}

		/* initialize skb for ring */
		skb_record_rx_queue(skb, rx_ring->queue_index);
	}

	dma = dma_map_single(rx_ring->dev, skb->data,
			     IGB_RX_HDR_LEN, DMA_FROM_DEVICE);

	if (dma_mapping_error(rx_ring->dev, dma)) {
		rx_ring->rx_stats.alloc_failed++;
		return false;
	}

	bi->dma = dma;
	return true;
}

static bool igb_alloc_mapped_page(struct igb_ring *rx_ring,
6042
				  struct igb_rx_buffer *bi)
6043 6044 6045 6046 6047 6048 6049 6050 6051 6052 6053 6054 6055 6056 6057 6058 6059 6060 6061 6062 6063 6064 6065 6066 6067 6068 6069 6070 6071 6072 6073
{
	struct page *page = bi->page;
	dma_addr_t page_dma = bi->page_dma;
	unsigned int page_offset = bi->page_offset ^ (PAGE_SIZE / 2);

	if (page_dma)
		return true;

	if (!page) {
		page = netdev_alloc_page(rx_ring->netdev);
		bi->page = page;
		if (unlikely(!page)) {
			rx_ring->rx_stats.alloc_failed++;
			return false;
		}
	}

	page_dma = dma_map_page(rx_ring->dev, page,
				page_offset, PAGE_SIZE / 2,
				DMA_FROM_DEVICE);

	if (dma_mapping_error(rx_ring->dev, page_dma)) {
		rx_ring->rx_stats.alloc_failed++;
		return false;
	}

	bi->page_dma = page_dma;
	bi->page_offset = page_offset;
	return true;
}

6074
/**
6075
 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
6076 6077
 * @adapter: address of board private structure
 **/
6078
void igb_alloc_rx_buffers(struct igb_ring *rx_ring, u16 cleaned_count)
6079 6080
{
	union e1000_adv_rx_desc *rx_desc;
6081
	struct igb_rx_buffer *bi;
6082
	u16 i = rx_ring->next_to_use;
6083

6084
	rx_desc = IGB_RX_DESC(rx_ring, i);
6085
	bi = &rx_ring->rx_buffer_info[i];
6086
	i -= rx_ring->count;
6087 6088

	while (cleaned_count--) {
6089 6090
		if (!igb_alloc_mapped_skb(rx_ring, bi))
			break;
6091

6092 6093 6094
		/* Refresh the desc even if buffer_addrs didn't change
		 * because each write-back erases this info. */
		rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
6095

6096 6097 6098 6099
		if (!igb_alloc_mapped_page(rx_ring, bi))
			break;

		rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
6100

6101 6102
		rx_desc++;
		bi++;
6103
		i++;
6104
		if (unlikely(!i)) {
6105
			rx_desc = IGB_RX_DESC(rx_ring, 0);
6106
			bi = rx_ring->rx_buffer_info;
6107 6108 6109 6110 6111
			i -= rx_ring->count;
		}

		/* clear the hdr_addr for the next_to_use descriptor */
		rx_desc->read.hdr_addr = 0;
6112 6113
	}

6114 6115
	i += rx_ring->count;

6116 6117 6118 6119 6120 6121 6122 6123
	if (rx_ring->next_to_use != i) {
		rx_ring->next_to_use = i;

		/* Force memory writes to complete before letting h/w
		 * know there are new descriptors to fetch.  (Only
		 * applicable for weak-ordered memory model archs,
		 * such as IA-64). */
		wmb();
6124
		writel(i, rx_ring->tail);
6125 6126 6127 6128 6129 6130 6131 6132 6133 6134 6135 6136 6137 6138 6139 6140 6141 6142 6143 6144 6145 6146
	}
}

/**
 * igb_mii_ioctl -
 * @netdev:
 * @ifreq:
 * @cmd:
 **/
static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct mii_ioctl_data *data = if_mii(ifr);

	if (adapter->hw.phy.media_type != e1000_media_type_copper)
		return -EOPNOTSUPP;

	switch (cmd) {
	case SIOCGMIIPHY:
		data->phy_id = adapter->hw.phy.addr;
		break;
	case SIOCGMIIREG:
6147 6148
		if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F,
		                     &data->val_out))
6149 6150 6151 6152 6153 6154 6155 6156 6157
			return -EIO;
		break;
	case SIOCSMIIREG:
	default:
		return -EOPNOTSUPP;
	}
	return 0;
}

6158 6159 6160 6161 6162 6163
/**
 * igb_hwtstamp_ioctl - control hardware time stamping
 * @netdev:
 * @ifreq:
 * @cmd:
 *
6164 6165 6166 6167 6168 6169 6170 6171 6172 6173 6174 6175
 * Outgoing time stamping can be enabled and disabled. Play nice and
 * disable it when requested, although it shouldn't case any overhead
 * when no packet needs it. At most one packet in the queue may be
 * marked for time stamping, otherwise it would be impossible to tell
 * for sure to which packet the hardware time stamp belongs.
 *
 * Incoming time stamping has to be configured via the hardware
 * filters. Not all combinations are supported, in particular event
 * type has to be specified. Matching the kind of event packet is
 * not supported, with the exception of "all V2 events regardless of
 * level 2 or 4".
 *
6176 6177 6178 6179
 **/
static int igb_hwtstamp_ioctl(struct net_device *netdev,
			      struct ifreq *ifr, int cmd)
{
6180 6181
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
6182
	struct hwtstamp_config config;
6183 6184
	u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
	u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
6185
	u32 tsync_rx_cfg = 0;
6186 6187
	bool is_l4 = false;
	bool is_l2 = false;
6188
	u32 regval;
6189 6190 6191 6192 6193 6194 6195 6196

	if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
		return -EFAULT;

	/* reserved for future extensions */
	if (config.flags)
		return -EINVAL;

6197 6198
	switch (config.tx_type) {
	case HWTSTAMP_TX_OFF:
6199
		tsync_tx_ctl = 0;
6200 6201 6202 6203 6204 6205 6206 6207
	case HWTSTAMP_TX_ON:
		break;
	default:
		return -ERANGE;
	}

	switch (config.rx_filter) {
	case HWTSTAMP_FILTER_NONE:
6208
		tsync_rx_ctl = 0;
6209 6210 6211 6212 6213 6214 6215 6216 6217 6218
		break;
	case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
	case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
	case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
	case HWTSTAMP_FILTER_ALL:
		/*
		 * register TSYNCRXCFG must be set, therefore it is not
		 * possible to time stamp both Sync and Delay_Req messages
		 * => fall back to time stamping all packets
		 */
6219
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
6220 6221 6222
		config.rx_filter = HWTSTAMP_FILTER_ALL;
		break;
	case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
6223
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
6224
		tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
6225
		is_l4 = true;
6226 6227
		break;
	case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
6228
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
6229
		tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
6230
		is_l4 = true;
6231 6232 6233
		break;
	case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
	case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
6234
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
6235
		tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_SYNC_MESSAGE;
6236 6237
		is_l2 = true;
		is_l4 = true;
6238 6239 6240 6241
		config.rx_filter = HWTSTAMP_FILTER_SOME;
		break;
	case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
	case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
6242
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L2_L4_V2;
6243
		tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V2_DELAY_REQ_MESSAGE;
6244 6245
		is_l2 = true;
		is_l4 = true;
6246 6247 6248 6249 6250
		config.rx_filter = HWTSTAMP_FILTER_SOME;
		break;
	case HWTSTAMP_FILTER_PTP_V2_EVENT:
	case HWTSTAMP_FILTER_PTP_V2_SYNC:
	case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
6251
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
6252
		config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
6253
		is_l2 = true;
6254 6255 6256 6257 6258
		break;
	default:
		return -ERANGE;
	}

6259 6260 6261 6262 6263 6264
	if (hw->mac.type == e1000_82575) {
		if (tsync_rx_ctl | tsync_tx_ctl)
			return -EINVAL;
		return 0;
	}

N
Nick Nunley 已提交
6265 6266 6267 6268 6269 6270 6271 6272 6273 6274
	/*
	 * Per-packet timestamping only works if all packets are
	 * timestamped, so enable timestamping in all packets as
	 * long as one rx filter was configured.
	 */
	if ((hw->mac.type == e1000_82580) && tsync_rx_ctl) {
		tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
		tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
	}

6275 6276
	/* enable/disable TX */
	regval = rd32(E1000_TSYNCTXCTL);
6277 6278
	regval &= ~E1000_TSYNCTXCTL_ENABLED;
	regval |= tsync_tx_ctl;
6279 6280
	wr32(E1000_TSYNCTXCTL, regval);

6281
	/* enable/disable RX */
6282
	regval = rd32(E1000_TSYNCRXCTL);
6283 6284
	regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
	regval |= tsync_rx_ctl;
6285 6286
	wr32(E1000_TSYNCRXCTL, regval);

6287 6288
	/* define which PTP packets are time stamped */
	wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
6289

6290 6291 6292 6293 6294 6295 6296 6297 6298 6299 6300 6301 6302 6303 6304 6305 6306 6307 6308 6309 6310 6311 6312 6313 6314 6315 6316 6317 6318 6319
	/* define ethertype filter for timestamped packets */
	if (is_l2)
		wr32(E1000_ETQF(3),
		                (E1000_ETQF_FILTER_ENABLE | /* enable filter */
		                 E1000_ETQF_1588 | /* enable timestamping */
		                 ETH_P_1588));     /* 1588 eth protocol type */
	else
		wr32(E1000_ETQF(3), 0);

#define PTP_PORT 319
	/* L4 Queue Filter[3]: filter by destination port and protocol */
	if (is_l4) {
		u32 ftqf = (IPPROTO_UDP /* UDP */
			| E1000_FTQF_VF_BP /* VF not compared */
			| E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
			| E1000_FTQF_MASK); /* mask all inputs */
		ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */

		wr32(E1000_IMIR(3), htons(PTP_PORT));
		wr32(E1000_IMIREXT(3),
		     (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
		if (hw->mac.type == e1000_82576) {
			/* enable source port check */
			wr32(E1000_SPQF(3), htons(PTP_PORT));
			ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
		}
		wr32(E1000_FTQF(3), ftqf);
	} else {
		wr32(E1000_FTQF(3), E1000_FTQF_MASK);
	}
6320 6321 6322 6323 6324 6325 6326
	wrfl();

	adapter->hwtstamp_config = config;

	/* clear TX/RX time stamp registers, just to be sure */
	regval = rd32(E1000_TXSTMPH);
	regval = rd32(E1000_RXSTMPH);
6327

6328 6329
	return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
		-EFAULT : 0;
6330 6331
}

6332 6333 6334 6335 6336 6337 6338 6339 6340 6341 6342 6343 6344
/**
 * igb_ioctl -
 * @netdev:
 * @ifreq:
 * @cmd:
 **/
static int igb_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
{
	switch (cmd) {
	case SIOCGMIIPHY:
	case SIOCGMIIREG:
	case SIOCSMIIREG:
		return igb_mii_ioctl(netdev, ifr, cmd);
6345 6346
	case SIOCSHWTSTAMP:
		return igb_hwtstamp_ioctl(netdev, ifr, cmd);
6347 6348 6349 6350 6351
	default:
		return -EOPNOTSUPP;
	}
}

6352 6353 6354 6355 6356
s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
{
	struct igb_adapter *adapter = hw->back;
	u16 cap_offset;

6357
	cap_offset = adapter->pdev->pcie_cap;
6358 6359 6360 6361 6362 6363 6364 6365 6366 6367 6368 6369 6370
	if (!cap_offset)
		return -E1000_ERR_CONFIG;

	pci_read_config_word(adapter->pdev, cap_offset + reg, value);

	return 0;
}

s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value)
{
	struct igb_adapter *adapter = hw->back;
	u16 cap_offset;

6371
	cap_offset = adapter->pdev->pcie_cap;
6372 6373 6374 6375 6376 6377 6378 6379
	if (!cap_offset)
		return -E1000_ERR_CONFIG;

	pci_write_config_word(adapter->pdev, cap_offset + reg, *value);

	return 0;
}

J
Jiri Pirko 已提交
6380
static void igb_vlan_mode(struct net_device *netdev, u32 features)
6381 6382 6383 6384
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
	u32 ctrl, rctl;
6385
	bool enable = !!(features & NETIF_F_HW_VLAN_RX);
6386

6387
	if (enable) {
6388 6389 6390 6391 6392
		/* enable VLAN tag insert/strip */
		ctrl = rd32(E1000_CTRL);
		ctrl |= E1000_CTRL_VME;
		wr32(E1000_CTRL, ctrl);

6393
		/* Disable CFI check */
6394 6395 6396 6397 6398 6399 6400 6401 6402 6403
		rctl = rd32(E1000_RCTL);
		rctl &= ~E1000_RCTL_CFIEN;
		wr32(E1000_RCTL, rctl);
	} else {
		/* disable VLAN tag insert/strip */
		ctrl = rd32(E1000_CTRL);
		ctrl &= ~E1000_CTRL_VME;
		wr32(E1000_CTRL, ctrl);
	}

6404
	igb_rlpml_set(adapter);
6405 6406 6407 6408 6409 6410
}

static void igb_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
6411
	int pf_id = adapter->vfs_allocated_count;
6412

6413 6414
	/* attempt to add filter to vlvf array */
	igb_vlvf_set(adapter, vid, true, pf_id);
6415

6416 6417
	/* add the filter since PF can receive vlans w/o entry in vlvf */
	igb_vfta_set(hw, vid, true);
J
Jiri Pirko 已提交
6418 6419

	set_bit(vid, adapter->active_vlans);
6420 6421 6422 6423 6424 6425
}

static void igb_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
6426
	int pf_id = adapter->vfs_allocated_count;
6427
	s32 err;
6428

6429 6430
	/* remove vlan from VLVF table array */
	err = igb_vlvf_set(adapter, vid, false, pf_id);
6431

6432 6433
	/* if vid was not present in VLVF just remove it from table */
	if (err)
6434
		igb_vfta_set(hw, vid, false);
J
Jiri Pirko 已提交
6435 6436

	clear_bit(vid, adapter->active_vlans);
6437 6438 6439 6440
}

static void igb_restore_vlan(struct igb_adapter *adapter)
{
J
Jiri Pirko 已提交
6441
	u16 vid;
6442

6443 6444
	igb_vlan_mode(adapter->netdev, adapter->netdev->features);

J
Jiri Pirko 已提交
6445 6446
	for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
		igb_vlan_rx_add_vid(adapter->netdev, vid);
6447 6448
}

6449
int igb_set_spd_dplx(struct igb_adapter *adapter, u32 spd, u8 dplx)
6450
{
6451
	struct pci_dev *pdev = adapter->pdev;
6452 6453 6454 6455
	struct e1000_mac_info *mac = &adapter->hw.mac;

	mac->autoneg = 0;

6456 6457 6458 6459 6460
	/* Make sure dplx is at most 1 bit and lsb of speed is not set
	 * for the switch() below to work */
	if ((spd & 1) || (dplx & ~1))
		goto err_inval;

6461 6462
	/* Fiber NIC's only allow 1000 Gbps Full duplex */
	if ((adapter->hw.phy.media_type == e1000_media_type_internal_serdes) &&
6463 6464 6465
	    spd != SPEED_1000 &&
	    dplx != DUPLEX_FULL)
		goto err_inval;
6466

6467
	switch (spd + dplx) {
6468 6469 6470 6471 6472 6473 6474 6475 6476 6477 6478 6479 6480 6481 6482 6483 6484 6485
	case SPEED_10 + DUPLEX_HALF:
		mac->forced_speed_duplex = ADVERTISE_10_HALF;
		break;
	case SPEED_10 + DUPLEX_FULL:
		mac->forced_speed_duplex = ADVERTISE_10_FULL;
		break;
	case SPEED_100 + DUPLEX_HALF:
		mac->forced_speed_duplex = ADVERTISE_100_HALF;
		break;
	case SPEED_100 + DUPLEX_FULL:
		mac->forced_speed_duplex = ADVERTISE_100_FULL;
		break;
	case SPEED_1000 + DUPLEX_FULL:
		mac->autoneg = 1;
		adapter->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
		break;
	case SPEED_1000 + DUPLEX_HALF: /* not supported */
	default:
6486
		goto err_inval;
6487 6488
	}
	return 0;
6489 6490 6491 6492

err_inval:
	dev_err(&pdev->dev, "Unsupported Speed/Duplex configuration\n");
	return -EINVAL;
6493 6494
}

6495
static int __igb_shutdown(struct pci_dev *pdev, bool *enable_wake)
6496 6497 6498 6499
{
	struct net_device *netdev = pci_get_drvdata(pdev);
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
A
Alexander Duyck 已提交
6500
	u32 ctrl, rctl, status;
6501 6502 6503 6504 6505 6506 6507
	u32 wufc = adapter->wol;
#ifdef CONFIG_PM
	int retval = 0;
#endif

	netif_device_detach(netdev);

A
Alexander Duyck 已提交
6508 6509 6510
	if (netif_running(netdev))
		igb_close(netdev);

6511
	igb_clear_interrupt_scheme(adapter);
6512 6513 6514 6515 6516 6517 6518 6519 6520 6521 6522 6523 6524

#ifdef CONFIG_PM
	retval = pci_save_state(pdev);
	if (retval)
		return retval;
#endif

	status = rd32(E1000_STATUS);
	if (status & E1000_STATUS_LU)
		wufc &= ~E1000_WUFC_LNKC;

	if (wufc) {
		igb_setup_rctl(adapter);
6525
		igb_set_rx_mode(netdev);
6526 6527 6528 6529 6530 6531 6532 6533 6534 6535 6536 6537 6538 6539 6540 6541 6542

		/* turn on all-multi mode if wake on multicast is enabled */
		if (wufc & E1000_WUFC_MC) {
			rctl = rd32(E1000_RCTL);
			rctl |= E1000_RCTL_MPE;
			wr32(E1000_RCTL, rctl);
		}

		ctrl = rd32(E1000_CTRL);
		/* advertise wake from D3Cold */
		#define E1000_CTRL_ADVD3WUC 0x00100000
		/* phy power management enable */
		#define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
		ctrl |= E1000_CTRL_ADVD3WUC;
		wr32(E1000_CTRL, ctrl);

		/* Allow time for pending master requests to run */
6543
		igb_disable_pcie_master(hw);
6544 6545 6546 6547 6548 6549 6550 6551

		wr32(E1000_WUC, E1000_WUC_PME_EN);
		wr32(E1000_WUFC, wufc);
	} else {
		wr32(E1000_WUC, 0);
		wr32(E1000_WUFC, 0);
	}

6552 6553
	*enable_wake = wufc || adapter->en_mng_pt;
	if (!*enable_wake)
6554 6555 6556
		igb_power_down_link(adapter);
	else
		igb_power_up_link(adapter);
6557 6558 6559 6560 6561 6562 6563 6564 6565 6566 6567

	/* Release control of h/w to f/w.  If f/w is AMT enabled, this
	 * would have already happened in close and is redundant. */
	igb_release_hw_control(adapter);

	pci_disable_device(pdev);

	return 0;
}

#ifdef CONFIG_PM
6568 6569 6570 6571 6572 6573 6574 6575 6576 6577 6578 6579 6580 6581 6582 6583 6584 6585 6586
static int igb_suspend(struct pci_dev *pdev, pm_message_t state)
{
	int retval;
	bool wake;

	retval = __igb_shutdown(pdev, &wake);
	if (retval)
		return retval;

	if (wake) {
		pci_prepare_to_sleep(pdev);
	} else {
		pci_wake_from_d3(pdev, false);
		pci_set_power_state(pdev, PCI_D3hot);
	}

	return 0;
}

6587 6588 6589 6590 6591 6592 6593 6594 6595
static int igb_resume(struct pci_dev *pdev)
{
	struct net_device *netdev = pci_get_drvdata(pdev);
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
	u32 err;

	pci_set_power_state(pdev, PCI_D0);
	pci_restore_state(pdev);
6596
	pci_save_state(pdev);
T
Taku Izumi 已提交
6597

6598
	err = pci_enable_device_mem(pdev);
6599 6600 6601 6602 6603 6604 6605 6606 6607 6608
	if (err) {
		dev_err(&pdev->dev,
			"igb: Cannot enable PCI device from suspend\n");
		return err;
	}
	pci_set_master(pdev);

	pci_enable_wake(pdev, PCI_D3hot, 0);
	pci_enable_wake(pdev, PCI_D3cold, 0);

6609
	if (igb_init_interrupt_scheme(adapter)) {
A
Alexander Duyck 已提交
6610 6611
		dev_err(&pdev->dev, "Unable to allocate memory for queues\n");
		return -ENOMEM;
6612 6613 6614
	}

	igb_reset(adapter);
6615 6616 6617 6618 6619

	/* let the f/w know that the h/w is now under the control of the
	 * driver. */
	igb_get_hw_control(adapter);

6620 6621
	wr32(E1000_WUS, ~0);

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Alexander Duyck 已提交
6622 6623 6624 6625 6626
	if (netif_running(netdev)) {
		err = igb_open(netdev);
		if (err)
			return err;
	}
6627 6628 6629 6630 6631 6632 6633 6634 6635

	netif_device_attach(netdev);

	return 0;
}
#endif

static void igb_shutdown(struct pci_dev *pdev)
{
6636 6637 6638 6639 6640 6641 6642 6643
	bool wake;

	__igb_shutdown(pdev, &wake);

	if (system_state == SYSTEM_POWER_OFF) {
		pci_wake_from_d3(pdev, wake);
		pci_set_power_state(pdev, PCI_D3hot);
	}
6644 6645 6646 6647 6648 6649 6650 6651 6652 6653 6654
}

#ifdef CONFIG_NET_POLL_CONTROLLER
/*
 * Polling 'interrupt' - used by things like netconsole to send skbs
 * without having to re-enable interrupts. It's not called while
 * the interrupt routine is executing.
 */
static void igb_netpoll(struct net_device *netdev)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
6655
	struct e1000_hw *hw = &adapter->hw;
6656 6657
	int i;

6658
	if (!adapter->msix_entries) {
6659
		struct igb_q_vector *q_vector = adapter->q_vector[0];
6660
		igb_irq_disable(adapter);
6661
		napi_schedule(&q_vector->napi);
6662 6663
		return;
	}
6664

6665 6666 6667 6668
	for (i = 0; i < adapter->num_q_vectors; i++) {
		struct igb_q_vector *q_vector = adapter->q_vector[i];
		wr32(E1000_EIMC, q_vector->eims_value);
		napi_schedule(&q_vector->napi);
6669
	}
6670 6671 6672 6673 6674 6675 6676 6677 6678 6679 6680 6681 6682 6683 6684 6685 6686 6687 6688
}
#endif /* CONFIG_NET_POLL_CONTROLLER */

/**
 * igb_io_error_detected - called when PCI error is detected
 * @pdev: Pointer to PCI device
 * @state: The current pci connection state
 *
 * This function is called after a PCI bus error affecting
 * this device has been detected.
 */
static pci_ers_result_t igb_io_error_detected(struct pci_dev *pdev,
					      pci_channel_state_t state)
{
	struct net_device *netdev = pci_get_drvdata(pdev);
	struct igb_adapter *adapter = netdev_priv(netdev);

	netif_device_detach(netdev);

6689 6690 6691
	if (state == pci_channel_io_perm_failure)
		return PCI_ERS_RESULT_DISCONNECT;

6692 6693 6694 6695 6696 6697 6698 6699 6700 6701 6702 6703 6704 6705 6706 6707 6708 6709 6710 6711
	if (netif_running(netdev))
		igb_down(adapter);
	pci_disable_device(pdev);

	/* Request a slot slot reset. */
	return PCI_ERS_RESULT_NEED_RESET;
}

/**
 * igb_io_slot_reset - called after the pci bus has been reset.
 * @pdev: Pointer to PCI device
 *
 * Restart the card from scratch, as if from a cold-boot. Implementation
 * resembles the first-half of the igb_resume routine.
 */
static pci_ers_result_t igb_io_slot_reset(struct pci_dev *pdev)
{
	struct net_device *netdev = pci_get_drvdata(pdev);
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
6712
	pci_ers_result_t result;
T
Taku Izumi 已提交
6713
	int err;
6714

6715
	if (pci_enable_device_mem(pdev)) {
6716 6717
		dev_err(&pdev->dev,
			"Cannot re-enable PCI device after reset.\n");
6718 6719 6720 6721
		result = PCI_ERS_RESULT_DISCONNECT;
	} else {
		pci_set_master(pdev);
		pci_restore_state(pdev);
6722
		pci_save_state(pdev);
6723

6724 6725
		pci_enable_wake(pdev, PCI_D3hot, 0);
		pci_enable_wake(pdev, PCI_D3cold, 0);
6726

6727 6728 6729 6730
		igb_reset(adapter);
		wr32(E1000_WUS, ~0);
		result = PCI_ERS_RESULT_RECOVERED;
	}
6731

6732 6733 6734 6735 6736 6737
	err = pci_cleanup_aer_uncorrect_error_status(pdev);
	if (err) {
		dev_err(&pdev->dev, "pci_cleanup_aer_uncorrect_error_status "
		        "failed 0x%0x\n", err);
		/* non-fatal, continue */
	}
6738 6739

	return result;
6740 6741 6742 6743 6744 6745 6746 6747 6748 6749 6750 6751 6752 6753 6754 6755 6756 6757 6758 6759 6760 6761 6762 6763 6764 6765 6766 6767 6768
}

/**
 * igb_io_resume - called when traffic can start flowing again.
 * @pdev: Pointer to PCI device
 *
 * This callback is called when the error recovery driver tells us that
 * its OK to resume normal operation. Implementation resembles the
 * second-half of the igb_resume routine.
 */
static void igb_io_resume(struct pci_dev *pdev)
{
	struct net_device *netdev = pci_get_drvdata(pdev);
	struct igb_adapter *adapter = netdev_priv(netdev);

	if (netif_running(netdev)) {
		if (igb_up(adapter)) {
			dev_err(&pdev->dev, "igb_up failed after reset\n");
			return;
		}
	}

	netif_device_attach(netdev);

	/* let the f/w know that the h/w is now under the control of the
	 * driver. */
	igb_get_hw_control(adapter);
}

6769 6770 6771 6772 6773 6774 6775 6776 6777 6778 6779 6780 6781 6782 6783 6784 6785 6786 6787 6788 6789 6790 6791 6792 6793 6794 6795
static void igb_rar_set_qsel(struct igb_adapter *adapter, u8 *addr, u32 index,
                             u8 qsel)
{
	u32 rar_low, rar_high;
	struct e1000_hw *hw = &adapter->hw;

	/* HW expects these in little endian so we reverse the byte order
	 * from network order (big endian) to little endian
	 */
	rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
	          ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
	rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));

	/* Indicate to hardware the Address is Valid. */
	rar_high |= E1000_RAH_AV;

	if (hw->mac.type == e1000_82575)
		rar_high |= E1000_RAH_POOL_1 * qsel;
	else
		rar_high |= E1000_RAH_POOL_1 << qsel;

	wr32(E1000_RAL(index), rar_low);
	wrfl();
	wr32(E1000_RAH(index), rar_high);
	wrfl();
}

6796 6797 6798 6799
static int igb_set_vf_mac(struct igb_adapter *adapter,
                          int vf, unsigned char *mac_addr)
{
	struct e1000_hw *hw = &adapter->hw;
6800 6801 6802
	/* VF MAC addresses start at end of receive addresses and moves
	 * torwards the first, as a result a collision should not be possible */
	int rar_entry = hw->mac.rar_entry_count - (vf + 1);
6803

6804
	memcpy(adapter->vf_data[vf].vf_mac_addresses, mac_addr, ETH_ALEN);
6805

6806
	igb_rar_set_qsel(adapter, mac_addr, rar_entry, vf);
6807 6808 6809 6810

	return 0;
}

6811 6812 6813 6814 6815 6816 6817 6818 6819 6820 6821 6822 6823 6824 6825 6826 6827 6828
static int igb_ndo_set_vf_mac(struct net_device *netdev, int vf, u8 *mac)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	if (!is_valid_ether_addr(mac) || (vf >= adapter->vfs_allocated_count))
		return -EINVAL;
	adapter->vf_data[vf].flags |= IGB_VF_FLAG_PF_SET_MAC;
	dev_info(&adapter->pdev->dev, "setting MAC %pM on VF %d\n", mac, vf);
	dev_info(&adapter->pdev->dev, "Reload the VF driver to make this"
				      " change effective.");
	if (test_bit(__IGB_DOWN, &adapter->state)) {
		dev_warn(&adapter->pdev->dev, "The VF MAC address has been set,"
			 " but the PF device is not up.\n");
		dev_warn(&adapter->pdev->dev, "Bring the PF device up before"
			 " attempting to use the VF device.\n");
	}
	return igb_set_vf_mac(adapter, vf, mac);
}

6829 6830 6831 6832 6833 6834 6835 6836 6837 6838 6839 6840 6841 6842 6843 6844 6845 6846 6847 6848 6849 6850 6851 6852 6853 6854 6855 6856 6857 6858 6859 6860 6861 6862 6863 6864 6865 6866 6867 6868 6869 6870 6871 6872 6873 6874 6875 6876 6877 6878 6879 6880 6881 6882 6883 6884 6885 6886 6887 6888 6889 6890 6891 6892 6893
static int igb_link_mbps(int internal_link_speed)
{
	switch (internal_link_speed) {
	case SPEED_100:
		return 100;
	case SPEED_1000:
		return 1000;
	default:
		return 0;
	}
}

static void igb_set_vf_rate_limit(struct e1000_hw *hw, int vf, int tx_rate,
				  int link_speed)
{
	int rf_dec, rf_int;
	u32 bcnrc_val;

	if (tx_rate != 0) {
		/* Calculate the rate factor values to set */
		rf_int = link_speed / tx_rate;
		rf_dec = (link_speed - (rf_int * tx_rate));
		rf_dec = (rf_dec * (1<<E1000_RTTBCNRC_RF_INT_SHIFT)) / tx_rate;

		bcnrc_val = E1000_RTTBCNRC_RS_ENA;
		bcnrc_val |= ((rf_int<<E1000_RTTBCNRC_RF_INT_SHIFT) &
		               E1000_RTTBCNRC_RF_INT_MASK);
		bcnrc_val |= (rf_dec & E1000_RTTBCNRC_RF_DEC_MASK);
	} else {
		bcnrc_val = 0;
	}

	wr32(E1000_RTTDQSEL, vf); /* vf X uses queue X */
	wr32(E1000_RTTBCNRC, bcnrc_val);
}

static void igb_check_vf_rate_limit(struct igb_adapter *adapter)
{
	int actual_link_speed, i;
	bool reset_rate = false;

	/* VF TX rate limit was not set or not supported */
	if ((adapter->vf_rate_link_speed == 0) ||
	    (adapter->hw.mac.type != e1000_82576))
		return;

	actual_link_speed = igb_link_mbps(adapter->link_speed);
	if (actual_link_speed != adapter->vf_rate_link_speed) {
		reset_rate = true;
		adapter->vf_rate_link_speed = 0;
		dev_info(&adapter->pdev->dev,
		         "Link speed has been changed. VF Transmit "
		         "rate is disabled\n");
	}

	for (i = 0; i < adapter->vfs_allocated_count; i++) {
		if (reset_rate)
			adapter->vf_data[i].tx_rate = 0;

		igb_set_vf_rate_limit(&adapter->hw, i,
		                      adapter->vf_data[i].tx_rate,
		                      actual_link_speed);
	}
}

6894 6895
static int igb_ndo_set_vf_bw(struct net_device *netdev, int vf, int tx_rate)
{
6896 6897 6898 6899 6900 6901 6902 6903 6904 6905 6906 6907 6908 6909 6910 6911 6912 6913
	struct igb_adapter *adapter = netdev_priv(netdev);
	struct e1000_hw *hw = &adapter->hw;
	int actual_link_speed;

	if (hw->mac.type != e1000_82576)
		return -EOPNOTSUPP;

	actual_link_speed = igb_link_mbps(adapter->link_speed);
	if ((vf >= adapter->vfs_allocated_count) ||
	    (!(rd32(E1000_STATUS) & E1000_STATUS_LU)) ||
	    (tx_rate < 0) || (tx_rate > actual_link_speed))
		return -EINVAL;

	adapter->vf_rate_link_speed = actual_link_speed;
	adapter->vf_data[vf].tx_rate = (u16)tx_rate;
	igb_set_vf_rate_limit(hw, vf, tx_rate, actual_link_speed);

	return 0;
6914 6915 6916 6917 6918 6919 6920 6921 6922 6923
}

static int igb_ndo_get_vf_config(struct net_device *netdev,
				 int vf, struct ifla_vf_info *ivi)
{
	struct igb_adapter *adapter = netdev_priv(netdev);
	if (vf >= adapter->vfs_allocated_count)
		return -EINVAL;
	ivi->vf = vf;
	memcpy(&ivi->mac, adapter->vf_data[vf].vf_mac_addresses, ETH_ALEN);
6924
	ivi->tx_rate = adapter->vf_data[vf].tx_rate;
6925 6926 6927 6928 6929
	ivi->vlan = adapter->vf_data[vf].pf_vlan;
	ivi->qos = adapter->vf_data[vf].pf_qos;
	return 0;
}

6930 6931 6932
static void igb_vmm_control(struct igb_adapter *adapter)
{
	struct e1000_hw *hw = &adapter->hw;
6933
	u32 reg;
6934

6935 6936 6937 6938
	switch (hw->mac.type) {
	case e1000_82575:
	default:
		/* replication is not supported for 82575 */
6939
		return;
6940 6941 6942 6943 6944 6945 6946 6947 6948 6949
	case e1000_82576:
		/* notify HW that the MAC is adding vlan tags */
		reg = rd32(E1000_DTXCTL);
		reg |= E1000_DTXCTL_VLAN_ADDED;
		wr32(E1000_DTXCTL, reg);
	case e1000_82580:
		/* enable replication vlan tag stripping */
		reg = rd32(E1000_RPLOLR);
		reg |= E1000_RPLOLR_STRVLAN;
		wr32(E1000_RPLOLR, reg);
6950 6951
	case e1000_i350:
		/* none of the above registers are supported by i350 */
6952 6953
		break;
	}
6954

6955 6956 6957
	if (adapter->vfs_allocated_count) {
		igb_vmdq_set_loopback_pf(hw, true);
		igb_vmdq_set_replication_pf(hw, true);
G
Greg Rose 已提交
6958 6959
		igb_vmdq_set_anti_spoofing_pf(hw, true,
						adapter->vfs_allocated_count);
6960 6961 6962 6963
	} else {
		igb_vmdq_set_loopback_pf(hw, false);
		igb_vmdq_set_replication_pf(hw, false);
	}
6964 6965
}

6966
/* igb_main.c */