meson-gxbb.dtsi 13.1 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
/*
 * Copyright (c) 2016 Andreas Färber
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

43
#include "meson-gx.dtsi"
44
#include <dt-bindings/gpio/meson-gxbb-gpio.h>
45
#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
46
#include <dt-bindings/clock/gxbb-clkc.h>
47 48
#include <dt-bindings/clock/gxbb-aoclkc.h>
#include <dt-bindings/reset/gxbb-aoclkc.h>
49 50 51 52 53

/ {
	compatible = "amlogic,meson-gxbb";

	soc {
54 55 56 57 58 59 60 61 62 63 64 65 66 67
		usb0_phy: phy@c0000000 {
			compatible = "amlogic,meson-gxbb-usb2-phy";
			#phy-cells = <0>;
			reg = <0x0 0xc0000000 0x0 0x20>;
			resets = <&reset RESET_USB_OTG>;
			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
			clock-names = "usb_general", "usb";
			status = "disabled";
		};

		usb1_phy: phy@c0000020 {
			compatible = "amlogic,meson-gxbb-usb2-phy";
			#phy-cells = <0>;
			reg = <0x0 0xc0000020 0x0 0x20>;
68
			resets = <&reset RESET_USB_OTG>;
69 70 71 72 73
			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
			clock-names = "usb_general", "usb";
			status = "disabled";
		};

74 75 76 77 78 79 80 81 82 83 84
		usb0: usb@c9000000 {
			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
			reg = <0x0 0xc9000000 0x0 0x40000>;
			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
			clock-names = "otg";
			phys = <&usb0_phy>;
			phy-names = "usb2-phy";
			dr_mode = "host";
			status = "disabled";
		};
85

86 87 88 89 90 91 92 93 94 95 96 97 98 99
		usb1: usb@c9100000 {
			compatible = "amlogic,meson-gxbb-usb", "snps,dwc2";
			reg = <0x0 0xc9100000 0x0 0x40000>;
			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
			clock-names = "otg";
			phys = <&usb1_phy>;
			phy-names = "usb2-phy";
			dr_mode = "host";
			status = "disabled";
		};
	};
};

100 101 102 103 104
&ethmac {
	clocks = <&clkc CLKID_ETH>,
		 <&clkc CLKID_FCLK_DIV2>,
		 <&clkc CLKID_MPLL2>;
	clock-names = "stmmaceth", "clkin0", "clkin1";
105 106 107 108 109 110 111 112
};

&aobus {
	pinctrl_aobus: pinctrl@14 {
		compatible = "amlogic,meson-gxbb-aobus-pinctrl";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
113

114 115 116 117 118 119 120
		gpio_ao: bank@14 {
			reg = <0x0 0x00014 0x0 0x8>,
			      <0x0 0x0002c 0x0 0x4>,
			      <0x0 0x00024 0x0 0x8>;
			reg-names = "mux", "pull", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
121
			gpio-ranges = <&pinctrl_aobus 0 0 14>;
122 123 124 125 126 127
		};

		uart_ao_a_pins: uart_ao_a {
			mux {
				groups = "uart_tx_ao_a", "uart_rx_ao_a";
				function = "uart_ao";
128
			};
129
		};
130

131 132 133 134 135 136 137 138
		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
			mux {
				groups = "uart_cts_ao_a",
				       "uart_rts_ao_a";
				function = "uart_ao";
			};
		};

139 140 141 142 143 144 145
		uart_ao_b_pins: uart_ao_b {
			mux {
				groups = "uart_tx_ao_b", "uart_rx_ao_b";
				function = "uart_ao_b";
			};
		};

146 147 148 149 150 151 152 153
		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
			mux {
				groups = "uart_cts_ao_b",
				       "uart_rts_ao_b";
				function = "uart_ao_b";
			};
		};

154 155 156 157
		remote_input_ao_pins: remote_input_ao {
			mux {
				groups = "remote_input_ao";
				function = "remote_input_ao";
158
			};
159
		};
160

161 162 163 164 165
		i2c_ao_pins: i2c_ao {
			mux {
				groups = "i2c_sck_ao",
				       "i2c_sda_ao";
				function = "i2c_ao";
166
			};
167
		};
168

169 170 171 172
		pwm_ao_a_3_pins: pwm_ao_a_3 {
			mux {
				groups = "pwm_ao_a_3";
				function = "pwm_ao_a_3";
173
			};
174
		};
175

176 177 178 179
		pwm_ao_a_6_pins: pwm_ao_a_6 {
			mux {
				groups = "pwm_ao_a_6";
				function = "pwm_ao_a_6";
180
			};
181
		};
182

183 184 185 186
		pwm_ao_a_12_pins: pwm_ao_a_12 {
			mux {
				groups = "pwm_ao_a_12";
				function = "pwm_ao_a_12";
187
			};
188
		};
189

190 191 192 193
		pwm_ao_b_pins: pwm_ao_b {
			mux {
				groups = "pwm_ao_b";
				function = "pwm_ao_b";
194
			};
195
		};
196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237

		i2s_am_clk_pins: i2s_am_clk {
			mux {
				groups = "i2s_am_clk";
				function = "i2s_out_ao";
			};
		};

		i2s_out_ao_clk_pins: i2s_out_ao_clk {
			mux {
				groups = "i2s_out_ao_clk";
				function = "i2s_out_ao";
			};
		};

		i2s_out_lr_clk_pins: i2s_out_lr_clk {
			mux {
				groups = "i2s_out_lr_clk";
				function = "i2s_out_ao";
			};
		};

		i2s_out_ch01_ao_pins: i2s_out_ch01_ao {
			mux {
				groups = "i2s_out_ch01_ao";
				function = "i2s_out_ao";
			};
		};

		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
			mux {
				groups = "i2s_out_ch23_ao";
				function = "i2s_out_ao";
			};
		};

		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
			mux {
				groups = "i2s_out_ch45_ao";
				function = "i2s_out_ao";
			};
		};
238 239 240 241 242 243 244 245 246 247 248 249 250 251

		spdif_out_ao_6_pins: spdif_out_ao_6 {
			mux {
				groups = "spdif_out_ao_6";
				function = "spdif_out_ao";
			};
		};

		spdif_out_ao_13_pins: spdif_out_ao_13 {
			mux {
				groups = "spdif_out_ao_13";
				function = "spdif_out_ao";
			};
		};
252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269
	};
};

&periphs {
	pinctrl_periphs: pinctrl@4b0 {
		compatible = "amlogic,meson-gxbb-periphs-pinctrl";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		gpio: bank@4b0 {
			reg = <0x0 0x004b0 0x0 0x28>,
			      <0x0 0x004e8 0x0 0x14>,
			      <0x0 0x00120 0x0 0x14>,
			      <0x0 0x00430 0x0 0x40>;
			reg-names = "mux", "pull", "pull-enable", "gpio";
			gpio-controller;
			#gpio-cells = <2>;
270
			gpio-ranges = <&pinctrl_periphs 0 14 120>;
271
		};
272

273 274 275 276
		emmc_pins: emmc {
			mux {
				groups = "emmc_nand_d07",
				       "emmc_cmd",
277 278
				       "emmc_clk",
				       "emmc_ds";
279
				function = "emmc";
280
			};
281
		};
282

283 284 285 286 287 288 289
		nor_pins: nor {
			mux {
				groups = "nor_d",
				       "nor_q",
				       "nor_c",
				       "nor_cs";
				function = "nor";
290
			};
291
		};
292

293 294 295 296 297 298 299 300 301
		sdcard_pins: sdcard {
			mux {
				groups = "sdcard_d0",
				       "sdcard_d1",
				       "sdcard_d2",
				       "sdcard_d3",
				       "sdcard_cmd",
				       "sdcard_clk";
				function = "sdcard";
302
			};
303 304
		};

305 306 307 308 309 310 311 312 313
		sdio_pins: sdio {
			mux {
				groups = "sdio_d0",
				       "sdio_d1",
				       "sdio_d2",
				       "sdio_d3",
				       "sdio_cmd",
				       "sdio_clk";
				function = "sdio";
314
			};
315
		};
316

317 318 319 320
		sdio_irq_pins: sdio_irq {
			mux {
				groups = "sdio_irq";
				function = "sdio";
321
			};
322
		};
323

324 325 326 327 328
		uart_a_pins: uart_a {
			mux {
				groups = "uart_tx_a",
				       "uart_rx_a";
				function = "uart_a";
329
			};
330
		};
331

332 333 334 335 336 337 338 339
		uart_a_cts_rts_pins: uart_a_cts_rts {
			mux {
				groups = "uart_cts_a",
				       "uart_rts_a";
				function = "uart_a";
			};
		};

340 341 342 343 344
		uart_b_pins: uart_b {
			mux {
				groups = "uart_tx_b",
				       "uart_rx_b";
				function = "uart_b";
345
			};
346
		};
347

348 349 350 351 352 353 354 355
		uart_b_cts_rts_pins: uart_b_cts_rts {
			mux {
				groups = "uart_cts_b",
				       "uart_rts_b";
				function = "uart_b";
			};
		};

356 357 358 359 360
		uart_c_pins: uart_c {
			mux {
				groups = "uart_tx_c",
				       "uart_rx_c";
				function = "uart_c";
361
			};
362
		};
363

364 365 366 367 368 369 370 371
		uart_c_cts_rts_pins: uart_c_cts_rts {
			mux {
				groups = "uart_cts_c",
				       "uart_rts_c";
				function = "uart_c";
			};
		};

372 373 374 375 376
		i2c_a_pins: i2c_a {
			mux {
				groups = "i2c_sck_a",
				       "i2c_sda_a";
				function = "i2c_a";
377
			};
378 379
		};

380 381 382 383 384 385 386
		i2c_b_pins: i2c_b {
			mux {
				groups = "i2c_sck_b",
				       "i2c_sda_b";
				function = "i2c_b";
			};
		};
387

388 389 390 391 392
		i2c_c_pins: i2c_c {
			mux {
				groups = "i2c_sck_c",
				       "i2c_sda_c";
				function = "i2c_c";
393
			};
394
		};
395

396
		eth_rgmii_pins: eth-rgmii {
397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412
			mux {
				groups = "eth_mdio",
				       "eth_mdc",
				       "eth_clk_rx_clk",
				       "eth_rx_dv",
				       "eth_rxd0",
				       "eth_rxd1",
				       "eth_rxd2",
				       "eth_rxd3",
				       "eth_rgmii_tx_clk",
				       "eth_tx_en",
				       "eth_txd0",
				       "eth_txd1",
				       "eth_txd2",
				       "eth_txd3";
				function = "eth";
413
			};
414 415
		};

416 417 418 419 420 421 422 423 424 425 426 427 428 429 430
		eth_rmii_pins: eth-rmii {
			mux {
				groups = "eth_mdio",
				       "eth_mdc",
				       "eth_clk_rx_clk",
				       "eth_rx_dv",
				       "eth_rxd0",
				       "eth_rxd1",
				       "eth_tx_en",
				       "eth_txd0",
				       "eth_txd1";
				function = "eth";
			};
		};

431 432 433 434 435 436
		pwm_a_x_pins: pwm_a_x {
			mux {
				groups = "pwm_a_x";
				function = "pwm_a_x";
			};
		};
437

438 439 440 441
		pwm_a_y_pins: pwm_a_y {
			mux {
				groups = "pwm_a_y";
				function = "pwm_a_y";
442
			};
443
		};
444

445 446 447 448
		pwm_b_pins: pwm_b {
			mux {
				groups = "pwm_b";
				function = "pwm_b";
449
			};
450 451
		};

452 453 454 455 456
		pwm_d_pins: pwm_d {
			mux {
				groups = "pwm_d";
				function = "pwm_d";
			};
457
		};
458

459 460 461 462 463
		pwm_e_pins: pwm_e {
			mux {
				groups = "pwm_e";
				function = "pwm_e";
			};
464 465
		};

466 467 468 469 470
		pwm_f_x_pins: pwm_f_x {
			mux {
				groups = "pwm_f_x";
				function = "pwm_f_x";
			};
471 472
		};

473 474 475 476 477
		pwm_f_y_pins: pwm_f_y {
			mux {
				groups = "pwm_f_y";
				function = "pwm_f_y";
			};
478
		};
479 480 481 482 483 484 485 486 487 488 489 490 491 492

		hdmi_hpd_pins: hdmi_hpd {
			mux {
				groups = "hdmi_hpd";
				function = "hdmi_hpd";
			};
		};

		hdmi_i2c_pins: hdmi_i2c {
			mux {
				groups = "hdmi_sda", "hdmi_scl";
				function = "hdmi_i2c";
			};
		};
493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513

		i2sout_ch23_y_pins: i2sout_ch23_y {
			mux {
				groups = "i2sout_ch23_y";
				function = "i2s_out";
			};
		};

		i2sout_ch45_y_pins: i2sout_ch45_y {
			mux {
				groups = "i2sout_ch45_y";
				function = "i2s_out";
			};
		};

		i2sout_ch67_y_pins: i2sout_ch67_y {
			mux {
				groups = "i2sout_ch67_y";
				function = "i2s_out";
			};
		};
514 515 516 517 518 519 520

		spdif_out_y_pins: spdif_out_y {
			mux {
				groups = "spdif_out_y";
				function = "spdif_out";
			};
		};
521 522
	};
};
523 524 525 526 527 528 529

&hiubus {
	clkc: clock-controller@0 {
		compatible = "amlogic,gxbb-clkc";
		#clock-cells = <1>;
		reg = <0x0 0x0 0x0 0x3db>;
	};
530
};
531

532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568
&apb {
	mali: gpu@c0000 {
		compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
		reg = <0x0 0xc0000 0x0 0x40000>;
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "gp", "gpmmu", "pp", "pmu",
			"pp0", "ppmmu0", "pp1", "ppmmu1",
			"pp2", "ppmmu2";
		clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
		clock-names = "bus", "core";

		/*
		 * Mali clocking is provided by two identical clock paths
		 * MALI_0 and MALI_1 muxed to a single clock by a glitch
		 * free mux to safely change frequency while running.
		 */
		assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
				  <&clkc CLKID_MALI_0>,
				  <&clkc CLKID_MALI>; /* Glitch free mux */
		assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
					 <0>, /* Do Nothing */
					 <&clkc CLKID_MALI_0>;
		assigned-clock-rates = <0>, /* Do Nothing */
				       <666666666>,
				       <0>; /* Do Nothing */
	};
};

569 570 571 572
&i2c_A {
	clocks = <&clkc CLKID_I2C>;
};

573 574 575 576
&i2c_AO {
	clocks = <&clkc CLKID_AO_I2C>;
};

577 578 579 580 581 582
&i2c_B {
	clocks = <&clkc CLKID_I2C>;
};

&i2c_C {
	clocks = <&clkc CLKID_I2C>;
583
};
584

585 586 587 588 589 590 591 592 593 594
&saradc {
	compatible = "amlogic,meson-gxbb-saradc", "amlogic,meson-saradc";
	clocks = <&xtal>,
		 <&clkc CLKID_SAR_ADC>,
		 <&clkc CLKID_SANA>,
		 <&clkc CLKID_SAR_ADC_CLK>,
		 <&clkc CLKID_SAR_ADC_SEL>;
	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
};

595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614
&sd_emmc_a {
	clocks = <&clkc CLKID_SD_EMMC_A>,
		 <&xtal>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
};

&sd_emmc_b {
	clocks = <&clkc CLKID_SD_EMMC_B>,
		 <&xtal>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
};

&sd_emmc_c {
	clocks = <&clkc CLKID_SD_EMMC_C>,
		 <&xtal>,
		 <&clkc CLKID_FCLK_DIV2>;
	clock-names = "core", "clkin0", "clkin1";
};
615

616 617 618 619
&spifc {
	clocks = <&clkc CLKID_SPI>;
};

620 621 622
&vpu {
	compatible = "amlogic,meson-gxbb-vpu", "amlogic,meson-gx-vpu";
};
623 624 625 626 627 628 629 630 631 632 633 634

&hdmi_tx {
	compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
	resets = <&reset RESET_HDMITX_CAPB3>,
		 <&reset RESET_HDMI_SYSTEM_RESET>,
		 <&reset RESET_HDMI_TX>;
	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
	clocks = <&clkc CLKID_HDMI_PCLK>,
		 <&clkc CLKID_CLK81>,
		 <&clkc CLKID_GCLK_VENCI_INT0>;
	clock-names = "isfr", "iahb", "venci";
};