i915_dma.c 62.2 KB
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/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
 */
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/*
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#include "drmP.h"
#include "drm.h"
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#include "drm_crtc_helper.h"
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#include "drm_fb_helper.h"
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#include "intel_drv.h"
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#include "i915_drm.h"
#include "i915_drv.h"
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#include "i915_trace.h"
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#include <linux/pci.h>
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#include <linux/vgaarb.h>
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#include <linux/acpi.h>
#include <linux/pnp.h>
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#include <linux/vga_switcheroo.h>
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#include <linux/slab.h>
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extern int intel_max_stolen; /* from AGP driver */

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/**
 * Sets up the hardware status page for devices that need a physical address
 * in the register.
 */
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static int i915_init_phys_hws(struct drm_device *dev)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
	/* Program Hardware Status Page */
	dev_priv->status_page_dmah =
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		drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
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	if (!dev_priv->status_page_dmah) {
		DRM_ERROR("Can not allocate hardware status page\n");
		return -ENOMEM;
	}
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	dev_priv->render_ring.status_page.page_addr
		= dev_priv->status_page_dmah->vaddr;
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	dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;

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	memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
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	if (IS_I965G(dev))
		dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
					     0xf0;

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	I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
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	DRM_DEBUG_DRIVER("Enabled hardware status page\n");
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	return 0;
}

/**
 * Frees the hardware status page, whether it's a physical address or a virtual
 * address set up by the X Server.
 */
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static void i915_free_hws(struct drm_device *dev)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
	if (dev_priv->status_page_dmah) {
		drm_pci_free(dev, dev_priv->status_page_dmah);
		dev_priv->status_page_dmah = NULL;
	}

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	if (dev_priv->render_ring.status_page.gfx_addr) {
		dev_priv->render_ring.status_page.gfx_addr = 0;
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		drm_core_ioremapfree(&dev_priv->hws_map, dev);
	}

	/* Need to rewrite hardware status page */
	I915_WRITE(HWS_PGA, 0x1ffff000);
}

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void i915_kernel_lost_context(struct drm_device * dev)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct drm_i915_master_private *master_priv;
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	struct intel_ring_buffer *ring = &dev_priv->render_ring;
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	/*
	 * We should never lose context on the ring with modesetting
	 * as we don't expose it to userspace
	 */
	if (drm_core_check_feature(dev, DRIVER_MODESET))
		return;

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	ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
	ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
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	ring->space = ring->head - (ring->tail + 8);
	if (ring->space < 0)
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		ring->space += ring->size;
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	if (!dev->primary->master)
		return;

	master_priv = dev->primary->master->driver_priv;
	if (ring->head == ring->tail && master_priv->sarea_priv)
		master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
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}

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static int i915_dma_cleanup(struct drm_device * dev)
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{
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	drm_i915_private_t *dev_priv = dev->dev_private;
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	/* Make sure interrupts are disabled here because the uninstall ioctl
	 * may not have been called from userspace and after dev_private
	 * is freed, it's too late.
	 */
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	if (dev->irq_enabled)
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		drm_irq_uninstall(dev);
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	mutex_lock(&dev->struct_mutex);
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	intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
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	if (HAS_BSD(dev))
		intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
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	mutex_unlock(&dev->struct_mutex);
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	/* Clear the HWS virtual address at teardown */
	if (I915_NEED_GFX_HWS(dev))
		i915_free_hws(dev);
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	return 0;
}

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static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
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{
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	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
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	master_priv->sarea = drm_getsarea(dev);
	if (master_priv->sarea) {
		master_priv->sarea_priv = (drm_i915_sarea_t *)
			((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
	} else {
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		DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
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	}

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	if (init->ring_size != 0) {
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		if (dev_priv->render_ring.gem_object != NULL) {
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			i915_dma_cleanup(dev);
			DRM_ERROR("Client tried to initialize ringbuffer in "
				  "GEM mode\n");
			return -EINVAL;
		}
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		dev_priv->render_ring.size = init->ring_size;
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		dev_priv->render_ring.map.offset = init->ring_start;
		dev_priv->render_ring.map.size = init->ring_size;
		dev_priv->render_ring.map.type = 0;
		dev_priv->render_ring.map.flags = 0;
		dev_priv->render_ring.map.mtrr = 0;
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		drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
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		if (dev_priv->render_ring.map.handle == NULL) {
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			i915_dma_cleanup(dev);
			DRM_ERROR("can not ioremap virtual address for"
				  " ring buffer\n");
			return -ENOMEM;
		}
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	}

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	dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
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	dev_priv->cpp = init->cpp;
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	dev_priv->back_offset = init->back_offset;
	dev_priv->front_offset = init->front_offset;
	dev_priv->current_page = 0;
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	if (master_priv->sarea_priv)
		master_priv->sarea_priv->pf_current_page = 0;
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	/* Allow hardware batchbuffers unless told otherwise.
	 */
	dev_priv->allow_batchbuffer = 1;

	return 0;
}

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static int i915_dma_resume(struct drm_device * dev)
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{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;

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	struct intel_ring_buffer *ring;
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	DRM_DEBUG_DRIVER("%s\n", __func__);
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	ring = &dev_priv->render_ring;

	if (ring->map.handle == NULL) {
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		DRM_ERROR("can not ioremap virtual address for"
			  " ring buffer\n");
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		return -ENOMEM;
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	}

	/* Program Hardware Status Page */
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	if (!ring->status_page.page_addr) {
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		DRM_ERROR("Can not find hardware status page\n");
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		return -EINVAL;
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	}
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	DRM_DEBUG_DRIVER("hw status page @ %p\n",
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				ring->status_page.page_addr);
	if (ring->status_page.gfx_addr != 0)
		ring->setup_status_page(dev, ring);
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	else
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		I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
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	DRM_DEBUG_DRIVER("Enabled hardware status page\n");
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	return 0;
}

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static int i915_dma_init(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
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{
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	drm_i915_init_t *init = data;
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	int retcode = 0;

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	switch (init->func) {
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	case I915_INIT_DMA:
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		retcode = i915_initialize(dev, init);
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		break;
	case I915_CLEANUP_DMA:
		retcode = i915_dma_cleanup(dev);
		break;
	case I915_RESUME_DMA:
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		retcode = i915_dma_resume(dev);
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		break;
	default:
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		retcode = -EINVAL;
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		break;
	}

	return retcode;
}

/* Implement basically the same security restrictions as hardware does
 * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 *
 * Most of the calculations below involve calculating the size of a
 * particular instruction.  It's important to get the size right as
 * that tells us where the next instruction to check is.  Any illegal
 * instruction detected will be given a size of zero, which is a
 * signal to abort the rest of the buffer.
 */
static int do_validate_cmd(int cmd)
{
	switch (((cmd >> 29) & 0x7)) {
	case 0x0:
		switch ((cmd >> 23) & 0x3f) {
		case 0x0:
			return 1;	/* MI_NOOP */
		case 0x4:
			return 1;	/* MI_FLUSH */
		default:
			return 0;	/* disallow everything else */
		}
		break;
	case 0x1:
		return 0;	/* reserved */
	case 0x2:
		return (cmd & 0xff) + 2;	/* 2d commands */
	case 0x3:
		if (((cmd >> 24) & 0x1f) <= 0x18)
			return 1;

		switch ((cmd >> 24) & 0x1f) {
		case 0x1c:
			return 1;
		case 0x1d:
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			switch ((cmd >> 16) & 0xff) {
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			case 0x3:
				return (cmd & 0x1f) + 2;
			case 0x4:
				return (cmd & 0xf) + 2;
			default:
				return (cmd & 0xffff) + 2;
			}
		case 0x1e:
			if (cmd & (1 << 23))
				return (cmd & 0xffff) + 1;
			else
				return 1;
		case 0x1f:
			if ((cmd & (1 << 23)) == 0)	/* inline vertices */
				return (cmd & 0x1ffff) + 2;
			else if (cmd & (1 << 17))	/* indirect random */
				if ((cmd & 0xffff) == 0)
					return 0;	/* unknown length, too hard */
				else
					return (((cmd & 0xffff) + 1) / 2) + 1;
			else
				return 2;	/* indirect sequential */
		default:
			return 0;
		}
	default:
		return 0;
	}

	return 0;
}

static int validate_cmd(int cmd)
{
	int ret = do_validate_cmd(cmd);

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/*	printk("validate_cmd( %x ): %d\n", cmd, ret); */
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	return ret;
}

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static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int i;

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	if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
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		return -EINVAL;
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	BEGIN_LP_RING((dwords+1)&~1);
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	for (i = 0; i < dwords;) {
		int cmd, sz;

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		cmd = buffer[i];
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		if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
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			return -EINVAL;
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		OUT_RING(cmd);

		while (++i, --sz) {
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			OUT_RING(buffer[i]);
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		}
	}

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	if (dwords & 1)
		OUT_RING(0);

	ADVANCE_LP_RING();

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	return 0;
}

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int
i915_emit_box(struct drm_device *dev,
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	      struct drm_clip_rect *boxes,
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	      int i, int DR1, int DR4)
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{
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	struct drm_clip_rect box = boxes[i];
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	if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
		DRM_ERROR("Bad box %d,%d..%d,%d\n",
			  box.x1, box.y1, box.x2, box.y2);
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		return -EINVAL;
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	}

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	if (IS_I965G(dev)) {
		BEGIN_LP_RING(4);
		OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
		OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
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		OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
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		OUT_RING(DR4);
		ADVANCE_LP_RING();
	} else {
		BEGIN_LP_RING(6);
		OUT_RING(GFX_OP_DRAWRECT_INFO);
		OUT_RING(DR1);
		OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
		OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
		OUT_RING(DR4);
		OUT_RING(0);
		ADVANCE_LP_RING();
	}
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	return 0;
}

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/* XXX: Emitting the counter should really be moved to part of the IRQ
 * emit. For now, do it in both places:
 */

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static void i915_emit_breadcrumb(struct drm_device *dev)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
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	dev_priv->counter++;
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	if (dev_priv->counter > 0x7FFFFFFFUL)
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		dev_priv->counter = 0;
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	if (master_priv->sarea_priv)
		master_priv->sarea_priv->last_enqueue = dev_priv->counter;
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	BEGIN_LP_RING(4);
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	OUT_RING(MI_STORE_DWORD_INDEX);
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	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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	OUT_RING(dev_priv->counter);
	OUT_RING(0);
	ADVANCE_LP_RING();
}

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static int i915_dispatch_cmdbuffer(struct drm_device * dev,
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				   drm_i915_cmdbuffer_t *cmd,
				   struct drm_clip_rect *cliprects,
				   void *cmdbuf)
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{
	int nbox = cmd->num_cliprects;
	int i = 0, count, ret;

	if (cmd->sz & 0x3) {
		DRM_ERROR("alignment");
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		return -EINVAL;
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	}

	i915_kernel_lost_context(dev);

	count = nbox ? nbox : 1;

	for (i = 0; i < count; i++) {
		if (i < nbox) {
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			ret = i915_emit_box(dev, cliprects, i,
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					    cmd->DR1, cmd->DR4);
			if (ret)
				return ret;
		}

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		ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
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		if (ret)
			return ret;
	}

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	i915_emit_breadcrumb(dev);
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	return 0;
}

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static int i915_dispatch_batchbuffer(struct drm_device * dev,
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				     drm_i915_batchbuffer_t * batch,
				     struct drm_clip_rect *cliprects)
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{
	int nbox = batch->num_cliprects;
	int i = 0, count;

	if ((batch->start | batch->used) & 0x7) {
		DRM_ERROR("alignment");
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		return -EINVAL;
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	}

	i915_kernel_lost_context(dev);

	count = nbox ? nbox : 1;

	for (i = 0; i < count; i++) {
		if (i < nbox) {
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			int ret = i915_emit_box(dev, cliprects, i,
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						batch->DR1, batch->DR4);
			if (ret)
				return ret;
		}

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		if (!IS_I830(dev) && !IS_845G(dev)) {
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			BEGIN_LP_RING(2);
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			if (IS_I965G(dev)) {
				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
				OUT_RING(batch->start);
			} else {
				OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
				OUT_RING(batch->start | MI_BATCH_NON_SECURE);
			}
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			ADVANCE_LP_RING();
		} else {
			BEGIN_LP_RING(4);
			OUT_RING(MI_BATCH_BUFFER);
			OUT_RING(batch->start | MI_BATCH_NON_SECURE);
			OUT_RING(batch->start + batch->used - 4);
			OUT_RING(0);
			ADVANCE_LP_RING();
		}
	}

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	if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
		BEGIN_LP_RING(2);
		OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
		OUT_RING(MI_NOOP);
		ADVANCE_LP_RING();
	}
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	i915_emit_breadcrumb(dev);
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	return 0;
}

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static int i915_dispatch_flip(struct drm_device * dev)
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{
	drm_i915_private_t *dev_priv = dev->dev_private;
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	struct drm_i915_master_private *master_priv =
		dev->primary->master->driver_priv;
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	if (!master_priv->sarea_priv)
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		return -EINVAL;

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	DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
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			  __func__,
			 dev_priv->current_page,
			 master_priv->sarea_priv->pf_current_page);
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	i915_kernel_lost_context(dev);

	BEGIN_LP_RING(2);
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	OUT_RING(MI_FLUSH | MI_READ_FLUSH);
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	OUT_RING(0);
	ADVANCE_LP_RING();
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	BEGIN_LP_RING(6);
	OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
	OUT_RING(0);
	if (dev_priv->current_page == 0) {
		OUT_RING(dev_priv->back_offset);
		dev_priv->current_page = 1;
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	} else {
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		OUT_RING(dev_priv->front_offset);
		dev_priv->current_page = 0;
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	}
545 546
	OUT_RING(0);
	ADVANCE_LP_RING();
L
Linus Torvalds 已提交
547

548 549 550 551
	BEGIN_LP_RING(2);
	OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
	OUT_RING(0);
	ADVANCE_LP_RING();
L
Linus Torvalds 已提交
552

553
	master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
L
Linus Torvalds 已提交
554 555

	BEGIN_LP_RING(4);
556
	OUT_RING(MI_STORE_DWORD_INDEX);
557
	OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
558 559
	OUT_RING(dev_priv->counter);
	OUT_RING(0);
L
Linus Torvalds 已提交
560 561
	ADVANCE_LP_RING();

562
	master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
563
	return 0;
L
Linus Torvalds 已提交
564 565
}

566
static int i915_quiescent(struct drm_device * dev)
L
Linus Torvalds 已提交
567 568 569 570
{
	drm_i915_private_t *dev_priv = dev->dev_private;

	i915_kernel_lost_context(dev);
571 572
	return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
				      dev_priv->render_ring.size - 8);
L
Linus Torvalds 已提交
573 574
}

575 576
static int i915_flush_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv)
L
Linus Torvalds 已提交
577
{
578 579 580
	int ret;

	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
L
Linus Torvalds 已提交
581

582 583 584 585 586
	mutex_lock(&dev->struct_mutex);
	ret = i915_quiescent(dev);
	mutex_unlock(&dev->struct_mutex);

	return ret;
L
Linus Torvalds 已提交
587 588
}

589 590
static int i915_batchbuffer(struct drm_device *dev, void *data,
			    struct drm_file *file_priv)
L
Linus Torvalds 已提交
591 592
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
593
	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
L
Linus Torvalds 已提交
594
	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
595
	    master_priv->sarea_priv;
596
	drm_i915_batchbuffer_t *batch = data;
L
Linus Torvalds 已提交
597
	int ret;
598
	struct drm_clip_rect *cliprects = NULL;
L
Linus Torvalds 已提交
599 600 601

	if (!dev_priv->allow_batchbuffer) {
		DRM_ERROR("Batchbuffer ioctl disabled\n");
E
Eric Anholt 已提交
602
		return -EINVAL;
L
Linus Torvalds 已提交
603 604
	}

605
	DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
606
			batch->start, batch->used, batch->num_cliprects);
L
Linus Torvalds 已提交
607

608
	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
L
Linus Torvalds 已提交
609

610 611 612 613
	if (batch->num_cliprects < 0)
		return -EINVAL;

	if (batch->num_cliprects) {
614 615 616
		cliprects = kcalloc(batch->num_cliprects,
				    sizeof(struct drm_clip_rect),
				    GFP_KERNEL);
617 618 619 620 621 622
		if (cliprects == NULL)
			return -ENOMEM;

		ret = copy_from_user(cliprects, batch->cliprects,
				     batch->num_cliprects *
				     sizeof(struct drm_clip_rect));
623 624
		if (ret != 0) {
			ret = -EFAULT;
625
			goto fail_free;
626
		}
627
	}
L
Linus Torvalds 已提交
628

629
	mutex_lock(&dev->struct_mutex);
630
	ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
631
	mutex_unlock(&dev->struct_mutex);
L
Linus Torvalds 已提交
632

633
	if (sarea_priv)
634
		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
635 636

fail_free:
637
	kfree(cliprects);
638

L
Linus Torvalds 已提交
639 640 641
	return ret;
}

642 643
static int i915_cmdbuffer(struct drm_device *dev, void *data,
			  struct drm_file *file_priv)
L
Linus Torvalds 已提交
644 645
{
	drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
646
	struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
L
Linus Torvalds 已提交
647
	drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
648
	    master_priv->sarea_priv;
649
	drm_i915_cmdbuffer_t *cmdbuf = data;
650 651
	struct drm_clip_rect *cliprects = NULL;
	void *batch_data;
L
Linus Torvalds 已提交
652 653
	int ret;

654
	DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
655
			cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
L
Linus Torvalds 已提交
656

657
	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
L
Linus Torvalds 已提交
658

659 660 661
	if (cmdbuf->num_cliprects < 0)
		return -EINVAL;

662
	batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
663 664 665 666
	if (batch_data == NULL)
		return -ENOMEM;

	ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
667 668
	if (ret != 0) {
		ret = -EFAULT;
669
		goto fail_batch_free;
670
	}
671 672

	if (cmdbuf->num_cliprects) {
673 674
		cliprects = kcalloc(cmdbuf->num_cliprects,
				    sizeof(struct drm_clip_rect), GFP_KERNEL);
675 676
		if (cliprects == NULL) {
			ret = -ENOMEM;
677
			goto fail_batch_free;
678
		}
679 680 681 682

		ret = copy_from_user(cliprects, cmdbuf->cliprects,
				     cmdbuf->num_cliprects *
				     sizeof(struct drm_clip_rect));
683 684
		if (ret != 0) {
			ret = -EFAULT;
685
			goto fail_clip_free;
686
		}
L
Linus Torvalds 已提交
687 688
	}

689
	mutex_lock(&dev->struct_mutex);
690
	ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
691
	mutex_unlock(&dev->struct_mutex);
L
Linus Torvalds 已提交
692 693
	if (ret) {
		DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
694
		goto fail_clip_free;
L
Linus Torvalds 已提交
695 696
	}

697
	if (sarea_priv)
698
		sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
699 700

fail_clip_free:
701
	kfree(cliprects);
702
fail_batch_free:
703
	kfree(batch_data);
704 705

	return ret;
L
Linus Torvalds 已提交
706 707
}

708 709
static int i915_flip_bufs(struct drm_device *dev, void *data,
			  struct drm_file *file_priv)
L
Linus Torvalds 已提交
710
{
711 712
	int ret;

713
	DRM_DEBUG_DRIVER("%s\n", __func__);
L
Linus Torvalds 已提交
714

715
	RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
L
Linus Torvalds 已提交
716

717 718 719 720 721
	mutex_lock(&dev->struct_mutex);
	ret = i915_dispatch_flip(dev);
	mutex_unlock(&dev->struct_mutex);

	return ret;
L
Linus Torvalds 已提交
722 723
}

724 725
static int i915_getparam(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
L
Linus Torvalds 已提交
726 727
{
	drm_i915_private_t *dev_priv = dev->dev_private;
728
	drm_i915_getparam_t *param = data;
L
Linus Torvalds 已提交
729 730 731
	int value;

	if (!dev_priv) {
732
		DRM_ERROR("called with no initialization\n");
E
Eric Anholt 已提交
733
		return -EINVAL;
L
Linus Torvalds 已提交
734 735
	}

736
	switch (param->param) {
L
Linus Torvalds 已提交
737
	case I915_PARAM_IRQ_ACTIVE:
738
		value = dev->pdev->irq ? 1 : 0;
L
Linus Torvalds 已提交
739 740 741 742
		break;
	case I915_PARAM_ALLOW_BATCHBUFFER:
		value = dev_priv->allow_batchbuffer ? 1 : 0;
		break;
D
Dave Airlie 已提交
743 744 745
	case I915_PARAM_LAST_DISPATCH:
		value = READ_BREADCRUMB(dev_priv);
		break;
K
Kristian Høgsberg 已提交
746 747 748
	case I915_PARAM_CHIPSET_ID:
		value = dev->pci_device;
		break;
749
	case I915_PARAM_HAS_GEM:
750
		value = dev_priv->has_gem;
751
		break;
752 753 754
	case I915_PARAM_NUM_FENCES_AVAIL:
		value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
		break;
755 756 757
	case I915_PARAM_HAS_OVERLAY:
		value = dev_priv->overlay ? 1 : 0;
		break;
758 759 760
	case I915_PARAM_HAS_PAGEFLIPPING:
		value = 1;
		break;
J
Jesse Barnes 已提交
761 762 763 764
	case I915_PARAM_HAS_EXECBUF2:
		/* depends on GEM */
		value = dev_priv->has_gem;
		break;
765 766 767
	case I915_PARAM_HAS_BSD:
		value = HAS_BSD(dev);
		break;
L
Linus Torvalds 已提交
768
	default:
769
		DRM_DEBUG_DRIVER("Unknown parameter %d\n",
J
Jesse Barnes 已提交
770
				 param->param);
E
Eric Anholt 已提交
771
		return -EINVAL;
L
Linus Torvalds 已提交
772 773
	}

774
	if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
L
Linus Torvalds 已提交
775
		DRM_ERROR("DRM_COPY_TO_USER failed\n");
E
Eric Anholt 已提交
776
		return -EFAULT;
L
Linus Torvalds 已提交
777 778 779 780 781
	}

	return 0;
}

782 783
static int i915_setparam(struct drm_device *dev, void *data,
			 struct drm_file *file_priv)
L
Linus Torvalds 已提交
784 785
{
	drm_i915_private_t *dev_priv = dev->dev_private;
786
	drm_i915_setparam_t *param = data;
L
Linus Torvalds 已提交
787 788

	if (!dev_priv) {
789
		DRM_ERROR("called with no initialization\n");
E
Eric Anholt 已提交
790
		return -EINVAL;
L
Linus Torvalds 已提交
791 792
	}

793
	switch (param->param) {
L
Linus Torvalds 已提交
794 795 796
	case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
		break;
	case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
797
		dev_priv->tex_lru_log_granularity = param->value;
L
Linus Torvalds 已提交
798 799
		break;
	case I915_SETPARAM_ALLOW_BATCHBUFFER:
800
		dev_priv->allow_batchbuffer = param->value;
L
Linus Torvalds 已提交
801
		break;
802 803 804 805 806 807 808
	case I915_SETPARAM_NUM_USED_FENCES:
		if (param->value > dev_priv->num_fence_regs ||
		    param->value < 0)
			return -EINVAL;
		/* Userspace can use first N regs */
		dev_priv->fence_reg_start = param->value;
		break;
L
Linus Torvalds 已提交
809
	default:
810
		DRM_DEBUG_DRIVER("unknown parameter %d\n",
811
					param->param);
E
Eric Anholt 已提交
812
		return -EINVAL;
L
Linus Torvalds 已提交
813 814 815 816 817
	}

	return 0;
}

818 819
static int i915_set_status_page(struct drm_device *dev, void *data,
				struct drm_file *file_priv)
820 821
{
	drm_i915_private_t *dev_priv = dev->dev_private;
822
	drm_i915_hws_addr_t *hws = data;
823
	struct intel_ring_buffer *ring = &dev_priv->render_ring;
824 825 826

	if (!I915_NEED_GFX_HWS(dev))
		return -EINVAL;
827 828

	if (!dev_priv) {
829
		DRM_ERROR("called with no initialization\n");
E
Eric Anholt 已提交
830
		return -EINVAL;
831 832
	}

J
Jesse Barnes 已提交
833 834 835 836 837
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
		WARN(1, "tried to set status page when mode setting active\n");
		return 0;
	}

838
	DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
839

840
	ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
841

842
	dev_priv->hws_map.offset = dev->agp->base + hws->addr;
843 844 845 846 847
	dev_priv->hws_map.size = 4*1024;
	dev_priv->hws_map.type = 0;
	dev_priv->hws_map.flags = 0;
	dev_priv->hws_map.mtrr = 0;

848
	drm_core_ioremap_wc(&dev_priv->hws_map, dev);
849 850
	if (dev_priv->hws_map.handle == NULL) {
		i915_dma_cleanup(dev);
851
		ring->status_page.gfx_addr = 0;
852 853
		DRM_ERROR("can not ioremap virtual address for"
				" G33 hw status page\n");
E
Eric Anholt 已提交
854
		return -ENOMEM;
855
	}
856 857 858
	ring->status_page.page_addr = dev_priv->hws_map.handle;
	memset(ring->status_page.page_addr, 0, PAGE_SIZE);
	I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
859

860
	DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
861
			 ring->status_page.gfx_addr);
862
	DRM_DEBUG_DRIVER("load hws at %p\n",
863
			 ring->status_page.page_addr);
864 865 866
	return 0;
}

867 868 869 870 871 872 873 874 875 876 877 878
static int i915_get_bridge_dev(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
	if (!dev_priv->bridge_dev) {
		DRM_ERROR("bridge device not found\n");
		return -1;
	}
	return 0;
}

879 880 881 882 883 884 885 886 887 888 889 890 891 892 893
#define MCHBAR_I915 0x44
#define MCHBAR_I965 0x48
#define MCHBAR_SIZE (4*4096)

#define DEVEN_REG 0x54
#define   DEVEN_MCHBAR_EN (1 << 28)

/* Allocate space for the MCH regs if needed, return nonzero on error */
static int
intel_alloc_mchbar_resource(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
	u32 temp_lo, temp_hi = 0;
	u64 mchbar_addr;
894
	int ret;
895 896 897 898 899 900 901 902 903

	if (IS_I965G(dev))
		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
	pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
	mchbar_addr = ((u64)temp_hi << 32) | temp_lo;

	/* If ACPI doesn't have it, assume we need to allocate it ourselves */
#ifdef CONFIG_PNP
	if (mchbar_addr &&
904 905
	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
		return 0;
906 907 908
#endif

	/* Get some space for it */
909 910 911 912
	dev_priv->mch_res.name = "i915 MCHBAR";
	dev_priv->mch_res.flags = IORESOURCE_MEM;
	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
				     &dev_priv->mch_res,
913 914
				     MCHBAR_SIZE, MCHBAR_SIZE,
				     PCIBIOS_MIN_MEM,
915
				     0, pcibios_align_resource,
916 917 918 919
				     dev_priv->bridge_dev);
	if (ret) {
		DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
		dev_priv->mch_res.start = 0;
920
		return ret;
921 922 923 924 925 926 927 928
	}

	if (IS_I965G(dev))
		pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
				       upper_32_bits(dev_priv->mch_res.start));

	pci_write_config_dword(dev_priv->bridge_dev, reg,
			       lower_32_bits(dev_priv->mch_res.start));
929
	return 0;
930 931 932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992
}

/* Setup MCHBAR if possible, return true if we should disable it again */
static void
intel_setup_mchbar(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
	u32 temp;
	bool enabled;

	dev_priv->mchbar_need_disable = false;

	if (IS_I915G(dev) || IS_I915GM(dev)) {
		pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
		enabled = !!(temp & DEVEN_MCHBAR_EN);
	} else {
		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
		enabled = temp & 1;
	}

	/* If it's already enabled, don't have to do anything */
	if (enabled)
		return;

	if (intel_alloc_mchbar_resource(dev))
		return;

	dev_priv->mchbar_need_disable = true;

	/* Space is allocated or reserved, so enable it. */
	if (IS_I915G(dev) || IS_I915GM(dev)) {
		pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
				       temp | DEVEN_MCHBAR_EN);
	} else {
		pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
		pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
	}
}

static void
intel_teardown_mchbar(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
	u32 temp;

	if (dev_priv->mchbar_need_disable) {
		if (IS_I915G(dev) || IS_I915GM(dev)) {
			pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
			temp &= ~DEVEN_MCHBAR_EN;
			pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
		} else {
			pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
			temp &= ~1;
			pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
		}
	}

	if (dev_priv->mch_res.start)
		release_resource(&dev_priv->mch_res);
}

J
Jesse Barnes 已提交
993 994 995 996 997 998 999 1000 1001 1002
/**
 * i915_probe_agp - get AGP bootup configuration
 * @pdev: PCI device
 * @aperture_size: returns AGP aperture configured size
 * @preallocated_size: returns size of BIOS preallocated AGP space
 *
 * Since Intel integrated graphics are UMA, the BIOS has to set aside
 * some RAM for the framebuffer at early boot.  This code figures out
 * how much was set aside so we can use it for our own purposes.
 */
1003
static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
1004 1005
			  uint32_t *preallocated_size,
			  uint32_t *start)
J
Jesse Barnes 已提交
1006
{
1007
	struct drm_i915_private *dev_priv = dev->dev_private;
J
Jesse Barnes 已提交
1008 1009
	u16 tmp = 0;
	unsigned long overhead;
1010
	unsigned long stolen;
J
Jesse Barnes 已提交
1011 1012

	/* Get the fb aperture size and "stolen" memory amount. */
1013
	pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
J
Jesse Barnes 已提交
1014 1015 1016 1017

	*aperture_size = 1024 * 1024;
	*preallocated_size = 1024 * 1024;

1018
	switch (dev->pdev->device) {
J
Jesse Barnes 已提交
1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029
	case PCI_DEVICE_ID_INTEL_82830_CGC:
	case PCI_DEVICE_ID_INTEL_82845G_IG:
	case PCI_DEVICE_ID_INTEL_82855GM_IG:
	case PCI_DEVICE_ID_INTEL_82865_IG:
		if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
			*aperture_size *= 64;
		else
			*aperture_size *= 128;
		break;
	default:
		/* 9xx supports large sizes, just look at the length */
1030
		*aperture_size = pci_resource_len(dev->pdev, 2);
J
Jesse Barnes 已提交
1031 1032 1033 1034 1035 1036 1037
		break;
	}

	/*
	 * Some of the preallocated space is taken by the GTT
	 * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
	 */
1038
	if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1039 1040 1041 1042
		overhead = 4096;
	else
		overhead = (*aperture_size / 1024) + 4096;

1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054
	if (IS_GEN6(dev)) {
		/* SNB has memory control reg at 0x50.w */
		pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);

		switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
		case INTEL_855_GMCH_GMS_DISABLED:
			DRM_ERROR("video memory is disabled\n");
			return -1;
		case SNB_GMCH_GMS_STOLEN_32M:
			stolen = 32 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_64M:
1055
			stolen = 64 * 1024 * 1024;
1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106
			break;
		case SNB_GMCH_GMS_STOLEN_96M:
			stolen = 96 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_128M:
			stolen = 128 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_160M:
			stolen = 160 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_192M:
			stolen = 192 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_224M:
			stolen = 224 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_256M:
			stolen = 256 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_288M:
			stolen = 288 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_320M:
			stolen = 320 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_352M:
			stolen = 352 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_384M:
			stolen = 384 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_416M:
			stolen = 416 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_448M:
			stolen = 448 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_480M:
			stolen = 480 * 1024 * 1024;
			break;
		case SNB_GMCH_GMS_STOLEN_512M:
			stolen = 512 * 1024 * 1024;
			break;
		default:
			DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
				  tmp & SNB_GMCH_GMS_STOLEN_MASK);
			return -1;
		}
	} else {
		switch (tmp & INTEL_GMCH_GMS_MASK) {
		case INTEL_855_GMCH_GMS_DISABLED:
1107 1108
			DRM_ERROR("video memory is disabled\n");
			return -1;
1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151
		case INTEL_855_GMCH_GMS_STOLEN_1M:
			stolen = 1 * 1024 * 1024;
			break;
		case INTEL_855_GMCH_GMS_STOLEN_4M:
			stolen = 4 * 1024 * 1024;
			break;
		case INTEL_855_GMCH_GMS_STOLEN_8M:
			stolen = 8 * 1024 * 1024;
			break;
		case INTEL_855_GMCH_GMS_STOLEN_16M:
			stolen = 16 * 1024 * 1024;
			break;
		case INTEL_855_GMCH_GMS_STOLEN_32M:
			stolen = 32 * 1024 * 1024;
			break;
		case INTEL_915G_GMCH_GMS_STOLEN_48M:
			stolen = 48 * 1024 * 1024;
			break;
		case INTEL_915G_GMCH_GMS_STOLEN_64M:
			stolen = 64 * 1024 * 1024;
			break;
		case INTEL_GMCH_GMS_STOLEN_128M:
			stolen = 128 * 1024 * 1024;
			break;
		case INTEL_GMCH_GMS_STOLEN_256M:
			stolen = 256 * 1024 * 1024;
			break;
		case INTEL_GMCH_GMS_STOLEN_96M:
			stolen = 96 * 1024 * 1024;
			break;
		case INTEL_GMCH_GMS_STOLEN_160M:
			stolen = 160 * 1024 * 1024;
			break;
		case INTEL_GMCH_GMS_STOLEN_224M:
			stolen = 224 * 1024 * 1024;
			break;
		case INTEL_GMCH_GMS_STOLEN_352M:
			stolen = 352 * 1024 * 1024;
			break;
		default:
			DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
				  tmp & INTEL_GMCH_GMS_MASK);
			return -1;
1152
		}
J
Jesse Barnes 已提交
1153
	}
1154

1155
	*preallocated_size = stolen - overhead;
1156
	*start = overhead;
J
Jesse Barnes 已提交
1157 1158 1159 1160

	return 0;
}

1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187
#define PTE_ADDRESS_MASK		0xfffff000
#define PTE_ADDRESS_MASK_HIGH		0x000000f0 /* i915+ */
#define PTE_MAPPING_TYPE_UNCACHED	(0 << 1)
#define PTE_MAPPING_TYPE_DCACHE		(1 << 1) /* i830 only */
#define PTE_MAPPING_TYPE_CACHED		(3 << 1)
#define PTE_MAPPING_TYPE_MASK		(3 << 1)
#define PTE_VALID			(1 << 0)

/**
 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
 * @dev: drm device
 * @gtt_addr: address to translate
 *
 * Some chip functions require allocations from stolen space but need the
 * physical address of the memory in question.  We use this routine
 * to get a physical address suitable for register programming from a given
 * GTT address.
 */
static unsigned long i915_gtt_to_phys(struct drm_device *dev,
				      unsigned long gtt_addr)
{
	unsigned long *gtt;
	unsigned long entry, phys;
	int gtt_bar = IS_I9XX(dev) ? 0 : 1;
	int gtt_offset, gtt_size;

	if (IS_I965G(dev)) {
1188
		if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209
			gtt_offset = 2*1024*1024;
			gtt_size = 2*1024*1024;
		} else {
			gtt_offset = 512*1024;
			gtt_size = 512*1024;
		}
	} else {
		gtt_bar = 3;
		gtt_offset = 0;
		gtt_size = pci_resource_len(dev->pdev, gtt_bar);
	}

	gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
			 gtt_size);
	if (!gtt) {
		DRM_ERROR("ioremap of GTT failed\n");
		return 0;
	}

	entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));

1210
	DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235

	/* Mask out these reserved bits on this hardware. */
	if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
	    IS_I945G(dev) || IS_I945GM(dev)) {
		entry &= ~PTE_ADDRESS_MASK_HIGH;
	}

	/* If it's not a mapping type we know, then bail. */
	if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
	    (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED)	{
		iounmap(gtt);
		return 0;
	}

	if (!(entry & PTE_VALID)) {
		DRM_ERROR("bad GTT entry in stolen space\n");
		iounmap(gtt);
		return 0;
	}

	iounmap(gtt);

	phys =(entry & PTE_ADDRESS_MASK) |
		((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));

1236
	DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249

	return phys;
}

static void i915_warn_stolen(struct drm_device *dev)
{
	DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
	DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
}

static void i915_setup_compression(struct drm_device *dev, int size)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
1250
	struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
A
Andrew Morton 已提交
1251 1252
	unsigned long cfb_base;
	unsigned long ll_base = 0;
1253 1254 1255 1256

	/* Leave 1M for line length buffer & misc. */
	compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
	if (!compressed_fb) {
1257
		dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1258 1259 1260 1261 1262 1263 1264
		i915_warn_stolen(dev);
		return;
	}

	compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
	if (!compressed_fb) {
		i915_warn_stolen(dev);
1265
		dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1266 1267 1268
		return;
	}

1269 1270 1271 1272
	cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
	if (!cfb_base) {
		DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
		drm_mm_put_block(compressed_fb);
1273 1274
	}

1275
	if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294
		compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
						    4096, 0);
		if (!compressed_llb) {
			i915_warn_stolen(dev);
			return;
		}

		compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
		if (!compressed_llb) {
			i915_warn_stolen(dev);
			return;
		}

		ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
		if (!ll_base) {
			DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
			drm_mm_put_block(compressed_fb);
			drm_mm_put_block(compressed_llb);
		}
1295 1296 1297 1298
	}

	dev_priv->cfb_size = size;

1299
	intel_disable_fbc(dev);
1300
	dev_priv->compressed_fb = compressed_fb;
1301 1302 1303
	if (IS_IRONLAKE_M(dev))
		I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
	else if (IS_GM45(dev)) {
1304 1305 1306 1307
		I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
	} else {
		I915_WRITE(FBC_CFB_BASE, cfb_base);
		I915_WRITE(FBC_LL_BASE, ll_base);
1308
		dev_priv->compressed_llb = compressed_llb;
1309 1310
	}

1311
	DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1312 1313 1314
		  ll_base, size >> 20);
}

1315 1316 1317 1318 1319
static void i915_cleanup_compression(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	drm_mm_put_block(dev_priv->compressed_fb);
1320
	if (dev_priv->compressed_llb)
1321 1322 1323
		drm_mm_put_block(dev_priv->compressed_llb);
}

1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336
/* true = enable decode, false = disable decoder */
static unsigned int i915_vga_set_decode(void *cookie, bool state)
{
	struct drm_device *dev = cookie;

	intel_modeset_vga_set_state(dev, state);
	if (state)
		return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
		       VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
	else
		return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
}

1337 1338 1339 1340 1341
static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
	if (state == VGA_SWITCHEROO_ON) {
1342
		printk(KERN_INFO "i915: switched on\n");
1343 1344 1345
		/* i915 resume handler doesn't set to D0 */
		pci_set_power_state(dev->pdev, PCI_D0);
		i915_resume(dev);
1346
		drm_kms_helper_poll_enable(dev);
1347 1348
	} else {
		printk(KERN_ERR "i915: switched off\n");
1349
		drm_kms_helper_poll_disable(dev);
1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364
		i915_suspend(dev, pmm);
	}
}

static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
{
	struct drm_device *dev = pci_get_drvdata(pdev);
	bool can_switch;

	spin_lock(&dev->count_lock);
	can_switch = (dev->open_count == 0);
	spin_unlock(&dev->count_lock);
	return can_switch;
}

1365
static int i915_load_modeset_init(struct drm_device *dev,
1366
				  unsigned long prealloc_start,
1367 1368
				  unsigned long prealloc_size,
				  unsigned long agp_size)
J
Jesse Barnes 已提交
1369 1370 1371 1372 1373
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int fb_bar = IS_I9XX(dev) ? 2 : 0;
	int ret = 0;

1374
	dev->mode_config.fb_base = pci_resource_start(dev->pdev, fb_bar) &
J
Jesse Barnes 已提交
1375 1376 1377 1378
		0xff000000;

	/* Basic memrange allocator for stolen space (aka vram) */
	drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1379
	DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
J
Jesse Barnes 已提交
1380

1381 1382
	/* We're off and running w/KMS */
	dev_priv->mm.suspended = 0;
J
Jesse Barnes 已提交
1383

1384 1385 1386 1387 1388 1389 1390 1391 1392 1393
	/* Let GEM Manage from end of prealloc space to end of aperture.
	 *
	 * However, leave one page at the end still bound to the scratch page.
	 * There are a number of places where the hardware apparently
	 * prefetches past the end of the object, and we've seen multiple
	 * hangs with the GPU head pointer stuck in a batchbuffer bound
	 * at the last page of the aperture.  One page should be enough to
	 * keep any prefetching inside of the aperture.
	 */
	i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
J
Jesse Barnes 已提交
1394

1395
	mutex_lock(&dev->struct_mutex);
J
Jesse Barnes 已提交
1396
	ret = i915_gem_init_ringbuffer(dev);
1397
	mutex_unlock(&dev->struct_mutex);
J
Jesse Barnes 已提交
1398
	if (ret)
1399
		goto out;
J
Jesse Barnes 已提交
1400

1401
	/* Try to set up FBC with a reasonable compressed buffer size */
1402
	if (I915_HAS_FBC(dev) && i915_powersave) {
1403 1404 1405 1406 1407 1408 1409 1410 1411 1412
		int cfb_size;

		/* Try to get an 8M buffer... */
		if (prealloc_size > (9*1024*1024))
			cfb_size = 8*1024*1024;
		else /* fall back to 7/8 of the stolen space */
			cfb_size = prealloc_size * 7 / 8;
		i915_setup_compression(dev, cfb_size);
	}

J
Jesse Barnes 已提交
1413 1414 1415 1416 1417 1418 1419 1420
	/* Allow hardware batchbuffers unless told otherwise.
	 */
	dev_priv->allow_batchbuffer = 1;

	ret = intel_init_bios(dev);
	if (ret)
		DRM_INFO("failed to find VBIOS tables\n");

1421 1422 1423
	/* if we have > 1 VGA cards, then disable the radeon VGA resources */
	ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
	if (ret)
1424
		goto cleanup_ringbuffer;
1425

1426 1427 1428 1429
	ret = vga_switcheroo_register_client(dev->pdev,
					     i915_switcheroo_set_state,
					     i915_switcheroo_can_switch);
	if (ret)
1430
		goto cleanup_vga_client;
1431

1432 1433 1434 1435
	/* IIR "flip pending" bit means done if this bit is set */
	if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
		dev_priv->flip_pending_is_done = true;

1436 1437
	intel_modeset_init(dev);

J
Jesse Barnes 已提交
1438 1439
	ret = drm_irq_install(dev);
	if (ret)
1440
		goto cleanup_vga_switcheroo;
J
Jesse Barnes 已提交
1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451

	/* Always safe in the mode setting case. */
	/* FIXME: do pre/post-mode set stuff in core KMS code */
	dev->vblank_disable_allowed = 1;

	/*
	 * Initialize the hardware status page IRQ location.
	 */

	I915_WRITE(INSTPM, (1 << 5) | (1 << 21));

1452 1453 1454 1455
	ret = intel_fbdev_init(dev);
	if (ret)
		goto cleanup_irq;

1456
	drm_kms_helper_poll_init(dev);
J
Jesse Barnes 已提交
1457 1458
	return 0;

1459 1460 1461 1462 1463 1464 1465
cleanup_irq:
	drm_irq_uninstall(dev);
cleanup_vga_switcheroo:
	vga_switcheroo_unregister_client(dev->pdev);
cleanup_vga_client:
	vga_client_register(dev->pdev, NULL, NULL, NULL);
cleanup_ringbuffer:
1466
	mutex_lock(&dev->struct_mutex);
J
Jesse Barnes 已提交
1467
	i915_gem_cleanup_ringbuffer(dev);
1468
	mutex_unlock(&dev->struct_mutex);
J
Jesse Barnes 已提交
1469 1470 1471 1472
out:
	return ret;
}

1473 1474 1475 1476
int i915_master_create(struct drm_device *dev, struct drm_master *master)
{
	struct drm_i915_master_private *master_priv;

1477
	master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491
	if (!master_priv)
		return -ENOMEM;

	master->driver_priv = master_priv;
	return 0;
}

void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
{
	struct drm_i915_master_private *master_priv = master->driver_priv;

	if (!master_priv)
		return;

1492
	kfree(master_priv);
1493 1494 1495 1496

	master->driver_priv = NULL;
}

1497
static void i915_pineview_get_mem_freq(struct drm_device *dev)
1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u32 tmp;

	tmp = I915_READ(CLKCFG);

	switch (tmp & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_533:
		dev_priv->fsb_freq = 533; /* 133*4 */
		break;
	case CLKCFG_FSB_800:
		dev_priv->fsb_freq = 800; /* 200*4 */
		break;
	case CLKCFG_FSB_667:
		dev_priv->fsb_freq =  667; /* 167*4 */
		break;
	case CLKCFG_FSB_400:
		dev_priv->fsb_freq = 400; /* 100*4 */
		break;
	}

	switch (tmp & CLKCFG_MEM_MASK) {
	case CLKCFG_MEM_533:
		dev_priv->mem_freq = 533;
		break;
	case CLKCFG_MEM_667:
		dev_priv->mem_freq = 667;
		break;
	case CLKCFG_MEM_800:
		dev_priv->mem_freq = 800;
		break;
	}
1530 1531 1532 1533

	/* detect pineview DDR3 setting */
	tmp = I915_READ(CSHRDDR3CTL);
	dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1534 1535
}

1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884 1885 1886 1887 1888 1889 1890 1891 1892 1893 1894 1895 1896 1897 1898 1899 1900 1901 1902 1903 1904 1905 1906 1907 1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921 1922 1923 1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048
static void i915_ironlake_get_mem_freq(struct drm_device *dev)
{
	drm_i915_private_t *dev_priv = dev->dev_private;
	u16 ddrpll, csipll;

	ddrpll = I915_READ16(DDRMPLL1);
	csipll = I915_READ16(CSIPLL0);

	switch (ddrpll & 0xff) {
	case 0xc:
		dev_priv->mem_freq = 800;
		break;
	case 0x10:
		dev_priv->mem_freq = 1066;
		break;
	case 0x14:
		dev_priv->mem_freq = 1333;
		break;
	case 0x18:
		dev_priv->mem_freq = 1600;
		break;
	default:
		DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
				 ddrpll & 0xff);
		dev_priv->mem_freq = 0;
		break;
	}

	dev_priv->r_t = dev_priv->mem_freq;

	switch (csipll & 0x3ff) {
	case 0x00c:
		dev_priv->fsb_freq = 3200;
		break;
	case 0x00e:
		dev_priv->fsb_freq = 3733;
		break;
	case 0x010:
		dev_priv->fsb_freq = 4266;
		break;
	case 0x012:
		dev_priv->fsb_freq = 4800;
		break;
	case 0x014:
		dev_priv->fsb_freq = 5333;
		break;
	case 0x016:
		dev_priv->fsb_freq = 5866;
		break;
	case 0x018:
		dev_priv->fsb_freq = 6400;
		break;
	default:
		DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
				 csipll & 0x3ff);
		dev_priv->fsb_freq = 0;
		break;
	}

	if (dev_priv->fsb_freq == 3200) {
		dev_priv->c_m = 0;
	} else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
		dev_priv->c_m = 1;
	} else {
		dev_priv->c_m = 2;
	}
}

struct v_table {
	u8 vid;
	unsigned long vd; /* in .1 mil */
	unsigned long vm; /* in .1 mil */
	u8 pvid;
};

static struct v_table v_table[] = {
	{ 0, 16125, 15000, 0x7f, },
	{ 1, 16000, 14875, 0x7e, },
	{ 2, 15875, 14750, 0x7d, },
	{ 3, 15750, 14625, 0x7c, },
	{ 4, 15625, 14500, 0x7b, },
	{ 5, 15500, 14375, 0x7a, },
	{ 6, 15375, 14250, 0x79, },
	{ 7, 15250, 14125, 0x78, },
	{ 8, 15125, 14000, 0x77, },
	{ 9, 15000, 13875, 0x76, },
	{ 10, 14875, 13750, 0x75, },
	{ 11, 14750, 13625, 0x74, },
	{ 12, 14625, 13500, 0x73, },
	{ 13, 14500, 13375, 0x72, },
	{ 14, 14375, 13250, 0x71, },
	{ 15, 14250, 13125, 0x70, },
	{ 16, 14125, 13000, 0x6f, },
	{ 17, 14000, 12875, 0x6e, },
	{ 18, 13875, 12750, 0x6d, },
	{ 19, 13750, 12625, 0x6c, },
	{ 20, 13625, 12500, 0x6b, },
	{ 21, 13500, 12375, 0x6a, },
	{ 22, 13375, 12250, 0x69, },
	{ 23, 13250, 12125, 0x68, },
	{ 24, 13125, 12000, 0x67, },
	{ 25, 13000, 11875, 0x66, },
	{ 26, 12875, 11750, 0x65, },
	{ 27, 12750, 11625, 0x64, },
	{ 28, 12625, 11500, 0x63, },
	{ 29, 12500, 11375, 0x62, },
	{ 30, 12375, 11250, 0x61, },
	{ 31, 12250, 11125, 0x60, },
	{ 32, 12125, 11000, 0x5f, },
	{ 33, 12000, 10875, 0x5e, },
	{ 34, 11875, 10750, 0x5d, },
	{ 35, 11750, 10625, 0x5c, },
	{ 36, 11625, 10500, 0x5b, },
	{ 37, 11500, 10375, 0x5a, },
	{ 38, 11375, 10250, 0x59, },
	{ 39, 11250, 10125, 0x58, },
	{ 40, 11125, 10000, 0x57, },
	{ 41, 11000, 9875, 0x56, },
	{ 42, 10875, 9750, 0x55, },
	{ 43, 10750, 9625, 0x54, },
	{ 44, 10625, 9500, 0x53, },
	{ 45, 10500, 9375, 0x52, },
	{ 46, 10375, 9250, 0x51, },
	{ 47, 10250, 9125, 0x50, },
	{ 48, 10125, 9000, 0x4f, },
	{ 49, 10000, 8875, 0x4e, },
	{ 50, 9875, 8750, 0x4d, },
	{ 51, 9750, 8625, 0x4c, },
	{ 52, 9625, 8500, 0x4b, },
	{ 53, 9500, 8375, 0x4a, },
	{ 54, 9375, 8250, 0x49, },
	{ 55, 9250, 8125, 0x48, },
	{ 56, 9125, 8000, 0x47, },
	{ 57, 9000, 7875, 0x46, },
	{ 58, 8875, 7750, 0x45, },
	{ 59, 8750, 7625, 0x44, },
	{ 60, 8625, 7500, 0x43, },
	{ 61, 8500, 7375, 0x42, },
	{ 62, 8375, 7250, 0x41, },
	{ 63, 8250, 7125, 0x40, },
	{ 64, 8125, 7000, 0x3f, },
	{ 65, 8000, 6875, 0x3e, },
	{ 66, 7875, 6750, 0x3d, },
	{ 67, 7750, 6625, 0x3c, },
	{ 68, 7625, 6500, 0x3b, },
	{ 69, 7500, 6375, 0x3a, },
	{ 70, 7375, 6250, 0x39, },
	{ 71, 7250, 6125, 0x38, },
	{ 72, 7125, 6000, 0x37, },
	{ 73, 7000, 5875, 0x36, },
	{ 74, 6875, 5750, 0x35, },
	{ 75, 6750, 5625, 0x34, },
	{ 76, 6625, 5500, 0x33, },
	{ 77, 6500, 5375, 0x32, },
	{ 78, 6375, 5250, 0x31, },
	{ 79, 6250, 5125, 0x30, },
	{ 80, 6125, 5000, 0x2f, },
	{ 81, 6000, 4875, 0x2e, },
	{ 82, 5875, 4750, 0x2d, },
	{ 83, 5750, 4625, 0x2c, },
	{ 84, 5625, 4500, 0x2b, },
	{ 85, 5500, 4375, 0x2a, },
	{ 86, 5375, 4250, 0x29, },
	{ 87, 5250, 4125, 0x28, },
	{ 88, 5125, 4000, 0x27, },
	{ 89, 5000, 3875, 0x26, },
	{ 90, 4875, 3750, 0x25, },
	{ 91, 4750, 3625, 0x24, },
	{ 92, 4625, 3500, 0x23, },
	{ 93, 4500, 3375, 0x22, },
	{ 94, 4375, 3250, 0x21, },
	{ 95, 4250, 3125, 0x20, },
	{ 96, 4125, 3000, 0x1f, },
	{ 97, 4125, 3000, 0x1e, },
	{ 98, 4125, 3000, 0x1d, },
	{ 99, 4125, 3000, 0x1c, },
	{ 100, 4125, 3000, 0x1b, },
	{ 101, 4125, 3000, 0x1a, },
	{ 102, 4125, 3000, 0x19, },
	{ 103, 4125, 3000, 0x18, },
	{ 104, 4125, 3000, 0x17, },
	{ 105, 4125, 3000, 0x16, },
	{ 106, 4125, 3000, 0x15, },
	{ 107, 4125, 3000, 0x14, },
	{ 108, 4125, 3000, 0x13, },
	{ 109, 4125, 3000, 0x12, },
	{ 110, 4125, 3000, 0x11, },
	{ 111, 4125, 3000, 0x10, },
	{ 112, 4125, 3000, 0x0f, },
	{ 113, 4125, 3000, 0x0e, },
	{ 114, 4125, 3000, 0x0d, },
	{ 115, 4125, 3000, 0x0c, },
	{ 116, 4125, 3000, 0x0b, },
	{ 117, 4125, 3000, 0x0a, },
	{ 118, 4125, 3000, 0x09, },
	{ 119, 4125, 3000, 0x08, },
	{ 120, 1125, 0, 0x07, },
	{ 121, 1000, 0, 0x06, },
	{ 122, 875, 0, 0x05, },
	{ 123, 750, 0, 0x04, },
	{ 124, 625, 0, 0x03, },
	{ 125, 500, 0, 0x02, },
	{ 126, 375, 0, 0x01, },
	{ 127, 0, 0, 0x00, },
};

struct cparams {
	int i;
	int t;
	int m;
	int c;
};

static struct cparams cparams[] = {
	{ 1, 1333, 301, 28664 },
	{ 1, 1066, 294, 24460 },
	{ 1, 800, 294, 25192 },
	{ 0, 1333, 276, 27605 },
	{ 0, 1066, 276, 27605 },
	{ 0, 800, 231, 23784 },
};

unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
{
	u64 total_count, diff, ret;
	u32 count1, count2, count3, m = 0, c = 0;
	unsigned long now = jiffies_to_msecs(jiffies), diff1;
	int i;

	diff1 = now - dev_priv->last_time1;

	count1 = I915_READ(DMIEC);
	count2 = I915_READ(DDREC);
	count3 = I915_READ(CSIEC);

	total_count = count1 + count2 + count3;

	/* FIXME: handle per-counter overflow */
	if (total_count < dev_priv->last_count1) {
		diff = ~0UL - dev_priv->last_count1;
		diff += total_count;
	} else {
		diff = total_count - dev_priv->last_count1;
	}

	for (i = 0; i < ARRAY_SIZE(cparams); i++) {
		if (cparams[i].i == dev_priv->c_m &&
		    cparams[i].t == dev_priv->r_t) {
			m = cparams[i].m;
			c = cparams[i].c;
			break;
		}
	}

	div_u64(diff, diff1);
	ret = ((m * diff) + c);
	div_u64(ret, 10);

	dev_priv->last_count1 = total_count;
	dev_priv->last_time1 = now;

	return ret;
}

unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
{
	unsigned long m, x, b;
	u32 tsfs;

	tsfs = I915_READ(TSFS);

	m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
	x = I915_READ8(TR1);

	b = tsfs & TSFS_INTR_MASK;

	return ((m * x) / 127) - b;
}

static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
{
	unsigned long val = 0;
	int i;

	for (i = 0; i < ARRAY_SIZE(v_table); i++) {
		if (v_table[i].pvid == pxvid) {
			if (IS_MOBILE(dev_priv->dev))
				val = v_table[i].vm;
			else
				val = v_table[i].vd;
		}
	}

	return val;
}

void i915_update_gfx_val(struct drm_i915_private *dev_priv)
{
	struct timespec now, diff1;
	u64 diff;
	unsigned long diffms;
	u32 count;

	getrawmonotonic(&now);
	diff1 = timespec_sub(now, dev_priv->last_time2);

	/* Don't divide by 0 */
	diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
	if (!diffms)
		return;

	count = I915_READ(GFXEC);

	if (count < dev_priv->last_count2) {
		diff = ~0UL - dev_priv->last_count2;
		diff += count;
	} else {
		diff = count - dev_priv->last_count2;
	}

	dev_priv->last_count2 = count;
	dev_priv->last_time2 = now;

	/* More magic constants... */
	diff = diff * 1181;
	div_u64(diff, diffms * 10);
	dev_priv->gfx_power = diff;
}

unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
{
	unsigned long t, corr, state1, corr2, state2;
	u32 pxvid, ext_v;

	pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
	pxvid = (pxvid >> 24) & 0x7f;
	ext_v = pvid_to_extvid(dev_priv, pxvid);

	state1 = ext_v;

	t = i915_mch_val(dev_priv);

	/* Revel in the empirically derived constants */

	/* Correction factor in 1/100000 units */
	if (t > 80)
		corr = ((t * 2349) + 135940);
	else if (t >= 50)
		corr = ((t * 964) + 29317);
	else /* < 50 */
		corr = ((t * 301) + 1004);

	corr = corr * ((150142 * state1) / 10000 - 78642);
	corr /= 100000;
	corr2 = (corr * dev_priv->corr);

	state2 = (corr2 * state1) / 10000;
	state2 /= 100; /* convert to mW */

	i915_update_gfx_val(dev_priv);

	return dev_priv->gfx_power + state2;
}

/* Global for IPS driver to get at the current i915 device */
static struct drm_i915_private *i915_mch_dev;
/*
 * Lock protecting IPS related data structures
 *   - i915_mch_dev
 *   - dev_priv->max_delay
 *   - dev_priv->min_delay
 *   - dev_priv->fmax
 *   - dev_priv->gpu_busy
 */
DEFINE_SPINLOCK(mchdev_lock);

/**
 * i915_read_mch_val - return value for IPS use
 *
 * Calculate and return a value for the IPS driver to use when deciding whether
 * we have thermal and power headroom to increase CPU or GPU power budget.
 */
unsigned long i915_read_mch_val(void)
{
  	struct drm_i915_private *dev_priv;
	unsigned long chipset_val, graphics_val, ret = 0;

  	spin_lock(&mchdev_lock);
	if (!i915_mch_dev)
		goto out_unlock;
	dev_priv = i915_mch_dev;

	chipset_val = i915_chipset_val(dev_priv);
	graphics_val = i915_gfx_val(dev_priv);

	ret = chipset_val + graphics_val;

out_unlock:
  	spin_unlock(&mchdev_lock);

  	return ret;
}
EXPORT_SYMBOL_GPL(i915_read_mch_val);

/**
 * i915_gpu_raise - raise GPU frequency limit
 *
 * Raise the limit; IPS indicates we have thermal headroom.
 */
bool i915_gpu_raise(void)
{
  	struct drm_i915_private *dev_priv;
	bool ret = true;

  	spin_lock(&mchdev_lock);
	if (!i915_mch_dev) {
		ret = false;
		goto out_unlock;
	}
	dev_priv = i915_mch_dev;

	if (dev_priv->max_delay > dev_priv->fmax)
		dev_priv->max_delay--;

out_unlock:
  	spin_unlock(&mchdev_lock);

  	return ret;
}
EXPORT_SYMBOL_GPL(i915_gpu_raise);

/**
 * i915_gpu_lower - lower GPU frequency limit
 *
 * IPS indicates we're close to a thermal limit, so throttle back the GPU
 * frequency maximum.
 */
bool i915_gpu_lower(void)
{
  	struct drm_i915_private *dev_priv;
	bool ret = true;

  	spin_lock(&mchdev_lock);
	if (!i915_mch_dev) {
		ret = false;
		goto out_unlock;
	}
	dev_priv = i915_mch_dev;

	if (dev_priv->max_delay < dev_priv->min_delay)
		dev_priv->max_delay++;

out_unlock:
  	spin_unlock(&mchdev_lock);

  	return ret;
}
EXPORT_SYMBOL_GPL(i915_gpu_lower);

/**
 * i915_gpu_busy - indicate GPU business to IPS
 *
 * Tell the IPS driver whether or not the GPU is busy.
 */
bool i915_gpu_busy(void)
{
  	struct drm_i915_private *dev_priv;
	bool ret = false;

  	spin_lock(&mchdev_lock);
	if (!i915_mch_dev)
		goto out_unlock;
	dev_priv = i915_mch_dev;

	ret = dev_priv->busy;

out_unlock:
  	spin_unlock(&mchdev_lock);

  	return ret;
}
EXPORT_SYMBOL_GPL(i915_gpu_busy);

/**
 * i915_gpu_turbo_disable - disable graphics turbo
 *
 * Disable graphics turbo by resetting the max frequency and setting the
 * current frequency to the default.
 */
bool i915_gpu_turbo_disable(void)
{
  	struct drm_i915_private *dev_priv;
	bool ret = true;

  	spin_lock(&mchdev_lock);
	if (!i915_mch_dev) {
		ret = false;
		goto out_unlock;
	}
	dev_priv = i915_mch_dev;

	dev_priv->max_delay = dev_priv->fstart;

	if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
		ret = false;

out_unlock:
  	spin_unlock(&mchdev_lock);

  	return ret;
}
EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);

J
Jesse Barnes 已提交
2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059
/**
 * i915_driver_load - setup chip and create an initial config
 * @dev: DRM device
 * @flags: startup flags
 *
 * The driver load routine has to do several things:
 *   - drive output discovery via intel_modeset_init()
 *   - initialize the memory manager
 *   - allocate initial config memory
 *   - setup the DRM framebuffer with the allocated memory
 */
2060
int i915_driver_load(struct drm_device *dev, unsigned long flags)
2061
{
2062
	struct drm_i915_private *dev_priv;
2063
	resource_size_t base, size;
2064
	int ret = 0, mmio_bar;
2065
	uint32_t agp_size, prealloc_size, prealloc_start;
2066 2067 2068 2069 2070 2071 2072
	/* i915 has 4 more counters */
	dev->counters += 4;
	dev->types[6] = _DRM_STAT_IRQ;
	dev->types[7] = _DRM_STAT_PRIMARY;
	dev->types[8] = _DRM_STAT_SECONDARY;
	dev->types[9] = _DRM_STAT_DMA;

2073
	dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
J
Jesse Barnes 已提交
2074 2075 2076 2077
	if (dev_priv == NULL)
		return -ENOMEM;

	dev->dev_private = (void *)dev_priv;
2078
	dev_priv->dev = dev;
2079
	dev_priv->info = (struct intel_device_info *) flags;
J
Jesse Barnes 已提交
2080 2081

	/* Add register map (needed for suspend/resume) */
2082
	mmio_bar = IS_I9XX(dev) ? 0 : 1;
2083 2084
	base = pci_resource_start(dev->pdev, mmio_bar);
	size = pci_resource_len(dev->pdev, mmio_bar);
J
Jesse Barnes 已提交
2085

2086 2087 2088 2089 2090
	if (i915_get_bridge_dev(dev)) {
		ret = -EIO;
		goto free_priv;
	}

2091 2092 2093 2094
	/* overlay on gen2 is broken and can't address above 1G */
	if (IS_GEN2(dev))
		dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));

2095
	dev_priv->regs = ioremap(base, size);
J
Jesse Barnes 已提交
2096 2097 2098
	if (!dev_priv->regs) {
		DRM_ERROR("failed to map registers\n");
		ret = -EIO;
2099
		goto put_bridge;
J
Jesse Barnes 已提交
2100
	}
2101

2102 2103 2104
        dev_priv->mm.gtt_mapping =
		io_mapping_create_wc(dev->agp->base,
				     dev->agp->agp_info.aper_size * 1024*1024);
2105 2106 2107 2108 2109
	if (dev_priv->mm.gtt_mapping == NULL) {
		ret = -EIO;
		goto out_rmmap;
	}

2110 2111 2112 2113 2114 2115 2116 2117 2118 2119
	/* Set up a WC MTRR for non-PAT systems.  This is more common than
	 * one would think, because the kernel disables PAT on first
	 * generation Core chips because WC PAT gets overridden by a UC
	 * MTRR if present.  Even if a UC MTRR isn't present.
	 */
	dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
					 dev->agp->agp_info.aper_size *
					 1024 * 1024,
					 MTRR_TYPE_WRCOMB, 1);
	if (dev_priv->mm.gtt_mtrr < 0) {
2120
		DRM_INFO("MTRR allocation failed.  Graphics "
2121 2122 2123
			 "performance may suffer.\n");
	}

2124
	ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
2125 2126 2127
	if (ret)
		goto out_iomapfree;

2128 2129 2130 2131 2132 2133
	if (prealloc_size > intel_max_stolen) {
		DRM_INFO("detected %dM stolen memory, trimming to %dM\n",
			 prealloc_size >> 20, intel_max_stolen >> 20);
		prealloc_size = intel_max_stolen;
	}

2134
	dev_priv->wq = create_singlethread_workqueue("i915");
2135 2136 2137 2138 2139 2140
	if (dev_priv->wq == NULL) {
		DRM_ERROR("Failed to create our workqueue.\n");
		ret = -ENOMEM;
		goto out_iomapfree;
	}

2141 2142 2143
	/* enable GEM by default */
	dev_priv->has_gem = 1;

2144 2145 2146 2147 2148 2149 2150 2151 2152
	if (prealloc_size > agp_size * 3 / 4) {
		DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
			  "memory stolen.\n",
			  prealloc_size / 1024, agp_size / 1024);
		DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
			  "updating the BIOS to fix).\n");
		dev_priv->has_gem = 0;
	}

2153 2154 2155 2156 2157 2158 2159
	if (dev_priv->has_gem == 0 &&
	    drm_core_check_feature(dev, DRIVER_MODESET)) {
		DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
		ret = -ENODEV;
		goto out_iomapfree;
	}

2160
	dev->driver->get_vblank_counter = i915_get_vblank_counter;
2161
	dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2162
	if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
2163
		dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2164
		dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2165
	}
2166

2167 2168 2169
	/* Try to make sure MCHBAR is enabled before poking at it */
	intel_setup_mchbar(dev);

2170 2171
	i915_gem_load(dev);

2172 2173 2174 2175
	/* Init HWS */
	if (!I915_NEED_GFX_HWS(dev)) {
		ret = i915_init_phys_hws(dev);
		if (ret != 0)
2176
			goto out_workqueue_free;
2177
	}
2178

2179 2180 2181 2182
	if (IS_PINEVIEW(dev))
		i915_pineview_get_mem_freq(dev);
	else if (IS_IRONLAKE(dev))
		i915_ironlake_get_mem_freq(dev);
2183

2184 2185 2186 2187 2188 2189
	/* On the 945G/GM, the chipset reports the MSI capability on the
	 * integrated graphics even though the support isn't actually there
	 * according to the published specs.  It doesn't appear to function
	 * correctly in testing on 945G.
	 * This may be a side effect of MSI having been made available for PEG
	 * and the registers being closely associated.
2190 2191
	 *
	 * According to chipset errata, on the 965GM, MSI interrupts may
2192 2193
	 * be lost or delayed, but we use them anyways to avoid
	 * stuck interrupts on some machines.
2194
	 */
2195
	if (!IS_I945G(dev) && !IS_I945GM(dev))
2196
		pci_enable_msi(dev->pdev);
2197 2198

	spin_lock_init(&dev_priv->user_irq_lock);
2199
	spin_lock_init(&dev_priv->error_lock);
2200
	dev_priv->trace_irq_seqno = 0;
2201

2202 2203 2204 2205 2206 2207 2208
	ret = drm_vblank_init(dev, I915_NUM_PIPE);

	if (ret) {
		(void) i915_driver_unload(dev);
		return ret;
	}

2209 2210 2211
	/* Start out suspended */
	dev_priv->mm.suspended = 1;

2212 2213
	intel_detect_pch(dev);

J
Jesse Barnes 已提交
2214
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2215 2216
		ret = i915_load_modeset_init(dev, prealloc_start,
					     prealloc_size, agp_size);
J
Jesse Barnes 已提交
2217 2218
		if (ret < 0) {
			DRM_ERROR("failed to init modeset\n");
2219
			goto out_workqueue_free;
J
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2220 2221 2222
		}
	}

2223
	/* Must be done after probing outputs */
2224
	intel_opregion_init(dev, 0);
2225

B
Ben Gamari 已提交
2226 2227
	setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
		    (unsigned long) dev);
2228 2229 2230 2231 2232 2233

	spin_lock(&mchdev_lock);
	i915_mch_dev = dev_priv;
	dev_priv->mchdev_lock = &mchdev_lock;
	spin_unlock(&mchdev_lock);

J
Jesse Barnes 已提交
2234 2235
	return 0;

2236 2237
out_workqueue_free:
	destroy_workqueue(dev_priv->wq);
2238 2239
out_iomapfree:
	io_mapping_free(dev_priv->mm.gtt_mapping);
J
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2240 2241
out_rmmap:
	iounmap(dev_priv->regs);
2242 2243
put_bridge:
	pci_dev_put(dev_priv->bridge_dev);
J
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2244
free_priv:
2245
	kfree(dev_priv);
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2246 2247 2248 2249 2250 2251 2252
	return ret;
}

int i915_driver_unload(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

2253 2254 2255 2256
	spin_lock(&mchdev_lock);
	i915_mch_dev = NULL;
	spin_unlock(&mchdev_lock);

2257 2258 2259 2260 2261 2262 2263
	io_mapping_free(dev_priv->mm.gtt_mapping);
	if (dev_priv->mm.gtt_mtrr >= 0) {
		mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
			 dev->agp->agp_info.aper_size * 1024 * 1024);
		dev_priv->mm.gtt_mtrr = -1;
	}

J
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2264
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2265 2266
		intel_modeset_cleanup(dev);

Z
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2267 2268 2269 2270 2271 2272 2273 2274 2275
		/*
		 * free the memory space allocated for the child device
		 * config parsed from VBT
		 */
		if (dev_priv->child_dev && dev_priv->child_dev_num) {
			kfree(dev_priv->child_dev);
			dev_priv->child_dev = NULL;
			dev_priv->child_dev_num = 0;
		}
2276

2277
		vga_switcheroo_unregister_client(dev->pdev);
2278
		vga_client_register(dev->pdev, NULL, NULL, NULL);
J
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2279 2280
	}

2281
	/* Free error state after interrupts are fully disabled. */
2282 2283
	del_timer_sync(&dev_priv->hangcheck_timer);
	cancel_work_sync(&dev_priv->error_work);
2284
	i915_destroy_error_state(dev);
2285

2286 2287 2288
	if (dev->pdev->msi_enabled)
		pci_disable_msi(dev->pdev);

2289 2290
	if (dev_priv->regs != NULL)
		iounmap(dev_priv->regs);
J
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2291

2292
	intel_opregion_free(dev, 0);
2293

J
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2294
	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2295 2296 2297
		/* Flush any outstanding unpin_work. */
		flush_workqueue(dev_priv->wq);

2298 2299
		i915_gem_free_all_phys_object(dev);

J
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2300 2301 2302
		mutex_lock(&dev->struct_mutex);
		i915_gem_cleanup_ringbuffer(dev);
		mutex_unlock(&dev->struct_mutex);
2303 2304
		if (I915_HAS_FBC(dev) && i915_powersave)
			i915_cleanup_compression(dev);
J
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2305 2306
		drm_mm_takedown(&dev_priv->vram);
		i915_gem_lastclose(dev);
2307 2308

		intel_cleanup_overlay(dev);
J
Jesse Barnes 已提交
2309 2310
	}

2311 2312
	intel_teardown_mchbar(dev);

2313 2314
	destroy_workqueue(dev_priv->wq);

2315
	pci_dev_put(dev_priv->bridge_dev);
2316
	kfree(dev->dev_private);
J
Jesse Barnes 已提交
2317

2318 2319 2320
	return 0;
}

2321 2322 2323 2324
int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
{
	struct drm_i915_file_private *i915_file_priv;

2325
	DRM_DEBUG_DRIVER("\n");
2326
	i915_file_priv = (struct drm_i915_file_private *)
2327
	    kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
2328 2329 2330 2331 2332 2333

	if (!i915_file_priv)
		return -ENOMEM;

	file_priv->driver_priv = i915_file_priv;

2334
	INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
2335 2336 2337 2338

	return 0;
}

J
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2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350
/**
 * i915_driver_lastclose - clean up after all DRM clients have exited
 * @dev: DRM device
 *
 * Take care of cleaning up after all DRM clients have exited.  In the
 * mode setting case, we want to restore the kernel's initial mode (just
 * in case the last client left us in a bad state).
 *
 * Additionally, in the non-mode setting case, we'll tear down the AGP
 * and DMA structures, since the kernel won't be using them, and clea
 * up any GEM state.
 */
2351
void i915_driver_lastclose(struct drm_device * dev)
L
Linus Torvalds 已提交
2352
{
J
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2353 2354
	drm_i915_private_t *dev_priv = dev->dev_private;

J
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2355
	if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2356
		drm_fb_helper_restore();
2357
		vga_switcheroo_process_delayed_switch();
D
Dave Airlie 已提交
2358
		return;
J
Jesse Barnes 已提交
2359
	}
D
Dave Airlie 已提交
2360

2361 2362
	i915_gem_lastclose(dev);

J
Jesse Barnes 已提交
2363
	if (dev_priv->agp_heap)
D
Dave Airlie 已提交
2364
		i915_mem_takedown(&(dev_priv->agp_heap));
J
Jesse Barnes 已提交
2365

D
Dave Airlie 已提交
2366
	i915_dma_cleanup(dev);
L
Linus Torvalds 已提交
2367 2368
}

2369
void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
L
Linus Torvalds 已提交
2370
{
J
Jesse Barnes 已提交
2371
	drm_i915_private_t *dev_priv = dev->dev_private;
2372
	i915_gem_release(dev, file_priv);
J
Jesse Barnes 已提交
2373 2374
	if (!drm_core_check_feature(dev, DRIVER_MODESET))
		i915_mem_release(dev, file_priv, dev_priv->agp_heap);
L
Linus Torvalds 已提交
2375 2376
}

2377 2378 2379 2380
void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
{
	struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;

2381
	kfree(i915_file_priv);
2382 2383
}

2384
struct drm_ioctl_desc i915_ioctls[] = {
2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424
	DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
	DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
	DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
	DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
D
Dave Airlie 已提交
2425 2426 2427
};

int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439

/**
 * Determine if the device really is AGP or not.
 *
 * All Intel graphics chipsets are treated as AGP, even if they are really
 * PCI-e.
 *
 * \param dev   The device to be tested.
 *
 * \returns
 * A value of 1 is always retured to indictate every i9x5 is AGP.
 */
2440
int i915_driver_device_is_agp(struct drm_device * dev)
2441 2442 2443
{
	return 1;
}