dmaengine.h 36.9 KB
Newer Older
C
Chris Leech 已提交
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
/*
 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc., 59
 * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called COPYING.
 */
21 22
#ifndef LINUX_DMAENGINE_H
#define LINUX_DMAENGINE_H
23

C
Chris Leech 已提交
24
#include <linux/device.h>
25
#include <linux/err.h>
C
Chris Leech 已提交
26
#include <linux/uio.h>
27
#include <linux/bug.h>
28
#include <linux/scatterlist.h>
29
#include <linux/bitmap.h>
30
#include <linux/types.h>
31
#include <asm/page.h>
32

C
Chris Leech 已提交
33
/**
34
 * typedef dma_cookie_t - an opaque DMA cookie
C
Chris Leech 已提交
35 36 37 38
 *
 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
 */
typedef s32 dma_cookie_t;
S
Steven J. Magnani 已提交
39 40
#define DMA_MIN_COOKIE	1
#define DMA_MAX_COOKIE	INT_MAX
C
Chris Leech 已提交
41

42 43 44 45
static inline int dma_submit_error(dma_cookie_t cookie)
{
	return cookie < 0 ? cookie : 0;
}
C
Chris Leech 已提交
46 47 48

/**
 * enum dma_status - DMA transaction status
49
 * @DMA_COMPLETE: transaction completed
C
Chris Leech 已提交
50
 * @DMA_IN_PROGRESS: transaction not yet processed
51
 * @DMA_PAUSED: transaction is paused
C
Chris Leech 已提交
52 53 54
 * @DMA_ERROR: transaction failed
 */
enum dma_status {
V
Vinod Koul 已提交
55
	DMA_COMPLETE,
C
Chris Leech 已提交
56
	DMA_IN_PROGRESS,
57
	DMA_PAUSED,
C
Chris Leech 已提交
58 59 60
	DMA_ERROR,
};

61 62
/**
 * enum dma_transaction_type - DMA transaction types/indexes
63 64 65
 *
 * Note: The DMA_ASYNC_TX capability is not to be set by drivers.  It is
 * automatically set as dma devices are registered.
66 67 68 69
 */
enum dma_transaction_type {
	DMA_MEMCPY,
	DMA_XOR,
70
	DMA_PQ,
D
Dan Williams 已提交
71 72
	DMA_XOR_VAL,
	DMA_PQ_VAL,
73
	DMA_INTERRUPT,
74
	DMA_SG,
75
	DMA_PRIVATE,
76
	DMA_ASYNC_TX,
77
	DMA_SLAVE,
78
	DMA_CYCLIC,
79
	DMA_INTERLEAVE,
80
/* last transaction type for creation of the capabilities mask */
81 82
	DMA_TX_TYPE_END,
};
83

84 85 86 87 88 89 90 91 92 93 94 95
/**
 * enum dma_transfer_direction - dma transfer mode and direction indicator
 * @DMA_MEM_TO_MEM: Async/Memcpy mode
 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
 */
enum dma_transfer_direction {
	DMA_MEM_TO_MEM,
	DMA_MEM_TO_DEV,
	DMA_DEV_TO_MEM,
	DMA_DEV_TO_DEV,
96
	DMA_TRANS_NONE,
97
};
98

99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166
/**
 * Interleaved Transfer Request
 * ----------------------------
 * A chunk is collection of contiguous bytes to be transfered.
 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
 * ICGs may or maynot change between chunks.
 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
 *  that when repeated an integral number of times, specifies the transfer.
 * A transfer template is specification of a Frame, the number of times
 *  it is to be repeated and other per-transfer attributes.
 *
 * Practically, a client driver would have ready a template for each
 *  type of transfer it is going to need during its lifetime and
 *  set only 'src_start' and 'dst_start' before submitting the requests.
 *
 *
 *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
 *  |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
 *
 *    ==  Chunk size
 *    ... ICG
 */

/**
 * struct data_chunk - Element of scatter-gather list that makes a frame.
 * @size: Number of bytes to read from source.
 *	  size_dst := fn(op, size_src), so doesn't mean much for destination.
 * @icg: Number of bytes to jump after last src/dst address of this
 *	 chunk and before first src/dst address for next chunk.
 *	 Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
 *	 Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
 */
struct data_chunk {
	size_t size;
	size_t icg;
};

/**
 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
 *	 and attributes.
 * @src_start: Bus address of source for the first chunk.
 * @dst_start: Bus address of destination for the first chunk.
 * @dir: Specifies the type of Source and Destination.
 * @src_inc: If the source address increments after reading from it.
 * @dst_inc: If the destination address increments after writing to it.
 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
 *		Otherwise, source is read contiguously (icg ignored).
 *		Ignored if src_inc is false.
 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
 *		Otherwise, destination is filled contiguously (icg ignored).
 *		Ignored if dst_inc is false.
 * @numf: Number of frames in this template.
 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
 * @sgl: Array of {chunk,icg} pairs that make up a frame.
 */
struct dma_interleaved_template {
	dma_addr_t src_start;
	dma_addr_t dst_start;
	enum dma_transfer_direction dir;
	bool src_inc;
	bool dst_inc;
	bool src_sgl;
	bool dst_sgl;
	size_t numf;
	size_t frame_size;
	struct data_chunk sgl[0];
};

167
/**
168
 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
169
 *  control completion, and communicate status.
170
 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
171
 *  this transaction
172
 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
173 174 175 176 177 178 179
 *  acknowledges receipt, i.e. has has a chance to establish any dependency
 *  chains
 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
 *  sources that were the result of a previous operation, in the case of a PQ
 *  operation it continues the calculation with new sources
D
Dan Williams 已提交
180 181
 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
 *  on the result of this operation
182
 */
183
enum dma_ctrl_flags {
184
	DMA_PREP_INTERRUPT = (1 << 0),
185
	DMA_CTRL_ACK = (1 << 1),
186 187 188 189
	DMA_PREP_PQ_DISABLE_P = (1 << 2),
	DMA_PREP_PQ_DISABLE_Q = (1 << 3),
	DMA_PREP_CONTINUE = (1 << 4),
	DMA_PREP_FENCE = (1 << 5),
190 191
};

192 193 194 195 196 197
/**
 * enum dma_ctrl_cmd - DMA operations that can optionally be exercised
 * on a running channel.
 * @DMA_TERMINATE_ALL: terminate all ongoing transfers
 * @DMA_PAUSE: pause ongoing transfers
 * @DMA_RESUME: resume paused transfer
198 199 200 201 202
 * @DMA_SLAVE_CONFIG: this command is only implemented by DMA controllers
 * that need to runtime reconfigure the slave channels (as opposed to passing
 * configuration data in statically from the platform). An additional
 * argument of struct dma_slave_config must be passed in with this
 * command.
I
Ira Snyder 已提交
203 204
 * @FSLDMA_EXTERNAL_START: this command will put the Freescale DMA controller
 * into external start mode.
205 206 207 208 209
 */
enum dma_ctrl_cmd {
	DMA_TERMINATE_ALL,
	DMA_PAUSE,
	DMA_RESUME,
210
	DMA_SLAVE_CONFIG,
I
Ira Snyder 已提交
211
	FSLDMA_EXTERNAL_START,
212 213
};

D
Dan Williams 已提交
214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232
/**
 * enum sum_check_bits - bit position of pq_check_flags
 */
enum sum_check_bits {
	SUM_CHECK_P = 0,
	SUM_CHECK_Q = 1,
};

/**
 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
 */
enum sum_check_flags {
	SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
	SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
};


233 234 235 236 237 238
/**
 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
 * See linux/cpumask.h
 */
typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;

C
Chris Leech 已提交
239 240 241 242 243 244 245 246 247 248 249 250 251 252
/**
 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
 * @memcpy_count: transaction counter
 * @bytes_transferred: byte counter
 */

struct dma_chan_percpu {
	/* stats */
	unsigned long memcpy_count;
	unsigned long bytes_transferred;
};

/**
 * struct dma_chan - devices supply DMA channels, clients use them
253
 * @device: ptr to the dma device who supplies this channel, always !%NULL
C
Chris Leech 已提交
254
 * @cookie: last cookie value returned to client
255
 * @completed_cookie: last completed cookie for this channel
256
 * @chan_id: channel ID for sysfs
257
 * @dev: class device for sysfs
C
Chris Leech 已提交
258 259
 * @device_node: used to add this to the device chan list
 * @local: per-cpu pointer to a struct dma_chan_percpu
260
 * @client_count: how many clients are using this channel
261
 * @table_count: number of appearances in the mem-to-mem allocation table
262
 * @private: private data for certain client-channel associations
C
Chris Leech 已提交
263 264 265 266
 */
struct dma_chan {
	struct dma_device *device;
	dma_cookie_t cookie;
267
	dma_cookie_t completed_cookie;
C
Chris Leech 已提交
268 269 270

	/* sysfs */
	int chan_id;
271
	struct dma_chan_dev *dev;
C
Chris Leech 已提交
272 273

	struct list_head device_node;
274
	struct dma_chan_percpu __percpu *local;
275
	int client_count;
276
	int table_count;
277
	void *private;
C
Chris Leech 已提交
278 279
};

280 281
/**
 * struct dma_chan_dev - relate sysfs device node to backing channel device
282 283 284 285
 * @chan: driver channel device
 * @device: sysfs device
 * @dev_id: parent dma_device dev_id
 * @idr_ref: reference count to gate release of dma_device dev_id
286 287 288 289
 */
struct dma_chan_dev {
	struct dma_chan *chan;
	struct device device;
290 291
	int dev_id;
	atomic_t *idr_ref;
292 293
};

294 295 296 297 298 299 300 301 302 303 304 305 306 307 308
/**
 * enum dma_slave_buswidth - defines bus with of the DMA slave
 * device, source or target buses
 */
enum dma_slave_buswidth {
	DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
	DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
	DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
	DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
	DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
};

/**
 * struct dma_slave_config - dma slave channel runtime config
 * @direction: whether the data shall go in or out on this slave
309 310
 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
 * legal values.
311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329
 * @src_addr: this is the physical address where DMA slave data
 * should be read (RX), if the source is memory this argument is
 * ignored.
 * @dst_addr: this is the physical address where DMA slave data
 * should be written (TX), if the source is memory this argument
 * is ignored.
 * @src_addr_width: this is the width in bytes of the source (RX)
 * register where DMA data shall be read. If the source
 * is memory this may be ignored depending on architecture.
 * Legal values: 1, 2, 4, 8.
 * @dst_addr_width: same as src_addr_width but for destination
 * target (TX) mutatis mutandis.
 * @src_maxburst: the maximum number of words (note: words, as in
 * units of the src_addr_width member, not bytes) that can be sent
 * in one burst to the device. Typically something like half the
 * FIFO depth on I/O peripherals so you don't overflow it. This
 * may or may not be applicable on memory sources.
 * @dst_maxburst: same as src_maxburst but for destination target
 * mutatis mutandis.
330 331 332
 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
 * with 'true' if peripheral should be flow controller. Direction will be
 * selected at Runtime.
333 334 335
 * @slave_id: Slave requester id. Only valid for slave channels. The dma
 * slave peripheral will have unique id as dma requester which need to be
 * pass as slave config.
336 337 338 339 340 341 342 343
 *
 * This struct is passed in as configuration data to a DMA engine
 * in order to set up a certain channel for DMA transport at runtime.
 * The DMA device/engine has to provide support for an additional
 * command in the channel config interface, DMA_SLAVE_CONFIG
 * and this struct will then be passed in as an argument to the
 * DMA engine device_control() function.
 *
344 345 346 347 348
 * The rationale for adding configuration information to this struct is as
 * follows: if it is likely that more than one DMA slave controllers in
 * the world will support the configuration option, then make it generic.
 * If not: if it is fixed so that it be sent in static from the platform
 * data, then prefer to do that.
349 350
 */
struct dma_slave_config {
351
	enum dma_transfer_direction direction;
352 353 354 355 356 357
	dma_addr_t src_addr;
	dma_addr_t dst_addr;
	enum dma_slave_buswidth src_addr_width;
	enum dma_slave_buswidth dst_addr_width;
	u32 src_maxburst;
	u32 dst_maxburst;
358
	bool device_fc;
359
	unsigned int slave_id;
360 361
};

362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387
/**
 * enum dma_residue_granularity - Granularity of the reported transfer residue
 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
 *  DMA channel is only able to tell whether a descriptor has been completed or
 *  not, which means residue reporting is not supported by this channel. The
 *  residue field of the dma_tx_state field will always be 0.
 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
 *  completed segment of the transfer (For cyclic transfers this is after each
 *  period). This is typically implemented by having the hardware generate an
 *  interrupt after each transferred segment and then the drivers updates the
 *  outstanding residue by the size of the segment. Another possibility is if
 *  the hardware supports scatter-gather and the segment descriptor has a field
 *  which gets set after the segment has been completed. The driver then counts
 *  the number of segments without the flag set to compute the residue.
 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
 *  burst. This is typically only supported if the hardware has a progress
 *  register of some sort (E.g. a register with the current read/write address
 *  or a register with the amount of bursts/beats/bytes that have been
 *  transferred or still need to be transferred).
 */
enum dma_residue_granularity {
	DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
	DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
	DMA_RESIDUE_GRANULARITY_BURST = 2,
};

388 389 390 391 392 393 394 395 396 397
/* struct dma_slave_caps - expose capabilities of a slave channel only
 *
 * @src_addr_widths: bit mask of src addr widths the channel supports
 * @dstn_addr_widths: bit mask of dstn addr widths the channel supports
 * @directions: bit mask of slave direction the channel supported
 * 	since the enum dma_transfer_direction is not defined as bits for each
 * 	type of direction, the dma controller should fill (1 << <TYPE>) and same
 * 	should be checked by controller as well
 * @cmd_pause: true, if pause and thereby resume is supported
 * @cmd_terminate: true, if terminate cmd is supported
398
 * @residue_granularity: granularity of the reported transfer residue
399 400 401 402 403 404 405
 */
struct dma_slave_caps {
	u32 src_addr_widths;
	u32 dstn_addr_widths;
	u32 directions;
	bool cmd_pause;
	bool cmd_terminate;
406
	enum dma_residue_granularity residue_granularity;
407 408
};

409 410 411 412
static inline const char *dma_chan_name(struct dma_chan *chan)
{
	return dev_name(&chan->dev->device);
}
413

C
Chris Leech 已提交
414 415
void dma_chan_cleanup(struct kref *kref);

416 417 418 419 420 421 422 423
/**
 * typedef dma_filter_fn - callback filter for dma_request_channel
 * @chan: channel to be reviewed
 * @filter_param: opaque parameter passed through dma_request_channel
 *
 * When this optional parameter is specified in a call to dma_request_channel a
 * suitable channel is passed to this routine for further dispositioning before
 * being returned.  Where 'suitable' indicates a non-busy channel that
424 425
 * satisfies the given capability mask.  It returns 'true' to indicate that the
 * channel is suitable.
426
 */
427
typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
428

429
typedef void (*dma_async_tx_callback)(void *dma_async_param);
430 431 432 433 434 435 436 437 438 439 440

struct dmaengine_unmap_data {
	u8 to_cnt;
	u8 from_cnt;
	u8 bidi_cnt;
	struct device *dev;
	struct kref kref;
	size_t len;
	dma_addr_t addr[0];
};

441 442 443 444 445
/**
 * struct dma_async_tx_descriptor - async transaction descriptor
 * ---dma generic offload fields---
 * @cookie: tracking cookie for this transaction, set to -EBUSY if
 *	this tx is sitting on a dependency list
446 447
 * @flags: flags to augment operation preparation, control completion, and
 * 	communicate status
448 449 450 451 452 453
 * @phys: physical address of the descriptor
 * @chan: target channel for this operation
 * @tx_submit: set the prepared descriptor(s) to be executed by the engine
 * @callback: routine to call after this operation is complete
 * @callback_param: general parameter to pass to the callback routine
 * ---async_tx api specific fields---
454
 * @next: at completion submit this descriptor
455
 * @parent: pointer to the next level up in the dependency chain
456
 * @lock: protect the parent and next pointers
457 458 459
 */
struct dma_async_tx_descriptor {
	dma_cookie_t cookie;
460
	enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
461 462 463 464 465
	dma_addr_t phys;
	struct dma_chan *chan;
	dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
	dma_async_tx_callback callback;
	void *callback_param;
466
	struct dmaengine_unmap_data *unmap;
467
#ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
468
	struct dma_async_tx_descriptor *next;
469 470
	struct dma_async_tx_descriptor *parent;
	spinlock_t lock;
471
#endif
472 473
};

474
#ifdef CONFIG_DMA_ENGINE
475 476 477 478 479 480 481
static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
				 struct dmaengine_unmap_data *unmap)
{
	kref_get(&unmap->kref);
	tx->unmap = unmap;
}

482 483
struct dmaengine_unmap_data *
dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
484
void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
485 486 487 488 489 490 491 492 493 494 495 496 497 498
#else
static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
				 struct dmaengine_unmap_data *unmap)
{
}
static inline struct dmaengine_unmap_data *
dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
{
	return NULL;
}
static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
{
}
#endif
499

500 501 502
static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
{
	if (tx->unmap) {
503
		dmaengine_unmap_put(tx->unmap);
504 505 506 507
		tx->unmap = NULL;
	}
}

508
#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565
static inline void txd_lock(struct dma_async_tx_descriptor *txd)
{
}
static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
{
}
static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
{
	BUG();
}
static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
{
}
static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
{
}
static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
{
	return NULL;
}
static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
{
	return NULL;
}

#else
static inline void txd_lock(struct dma_async_tx_descriptor *txd)
{
	spin_lock_bh(&txd->lock);
}
static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
{
	spin_unlock_bh(&txd->lock);
}
static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
{
	txd->next = next;
	next->parent = txd;
}
static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
{
	txd->parent = NULL;
}
static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
{
	txd->next = NULL;
}
static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
{
	return txd->parent;
}
static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
{
	return txd->next;
}
#endif

566 567 568 569 570 571 572 573 574 575 576 577 578 579 580
/**
 * struct dma_tx_state - filled in to report the status of
 * a transfer.
 * @last: last completed DMA cookie
 * @used: last issued DMA cookie (i.e. the one in progress)
 * @residue: the remaining number of bytes left to transmit
 *	on the selected transfer for states DMA_IN_PROGRESS and
 *	DMA_PAUSED if this is implemented in the driver, else 0
 */
struct dma_tx_state {
	dma_cookie_t last;
	dma_cookie_t used;
	u32 residue;
};

C
Chris Leech 已提交
581 582 583
/**
 * struct dma_device - info on the entity supplying DMA services
 * @chancnt: how many DMA channels are supported
584
 * @privatecnt: how many DMA channels are requested by dma_request_channel
C
Chris Leech 已提交
585 586
 * @channels: the list of struct dma_chan
 * @global_node: list_head for global dma_device_list
587 588
 * @cap_mask: one or more dma_capability flags
 * @max_xor: maximum number of xor sources, 0 if no capability
589
 * @max_pq: maximum number of PQ sources and PQ-continue capability
590 591 592 593
 * @copy_align: alignment shift for memcpy operations
 * @xor_align: alignment shift for xor operations
 * @pq_align: alignment shift for pq operations
 * @fill_align: alignment shift for memset operations
594
 * @dev_id: unique device ID
595
 * @dev: struct device reference for dma mapping api
596 597 598
 * @device_alloc_chan_resources: allocate resources and return the
 *	number of allocated descriptors
 * @device_free_chan_resources: release DMA channel's resources
599 600
 * @device_prep_dma_memcpy: prepares a memcpy operation
 * @device_prep_dma_xor: prepares a xor operation
D
Dan Williams 已提交
601
 * @device_prep_dma_xor_val: prepares a xor validation operation
602 603
 * @device_prep_dma_pq: prepares a pq operation
 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
604
 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
605
 * @device_prep_slave_sg: prepares a slave dma operation
606 607 608
 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
 *	The function takes a buffer of size buf_len. The callback function will
 *	be called after period_len bytes have been transferred.
609
 * @device_prep_interleaved_dma: Transfer expression in a generic way.
610 611
 * @device_control: manipulate all pending operations on a channel, returns
 *	zero or error code
612 613
 * @device_tx_status: poll for transaction completion, the optional
 *	txstate parameter can be supplied with a pointer to get a
L
Lucas De Marchi 已提交
614
 *	struct with auxiliary transfer status information, otherwise the call
615
 *	will just return a simple status code
616
 * @device_issue_pending: push pending transactions to hardware
617
 * @device_slave_caps: return the slave channel capabilities
C
Chris Leech 已提交
618 619 620 621
 */
struct dma_device {

	unsigned int chancnt;
622
	unsigned int privatecnt;
C
Chris Leech 已提交
623 624
	struct list_head channels;
	struct list_head global_node;
625
	dma_cap_mask_t  cap_mask;
626 627
	unsigned short max_xor;
	unsigned short max_pq;
628 629 630 631
	u8 copy_align;
	u8 xor_align;
	u8 pq_align;
	u8 fill_align;
632
	#define DMA_HAS_PQ_CONTINUE (1 << 15)
C
Chris Leech 已提交
633 634

	int dev_id;
635
	struct device *dev;
C
Chris Leech 已提交
636

637
	int (*device_alloc_chan_resources)(struct dma_chan *chan);
C
Chris Leech 已提交
638
	void (*device_free_chan_resources)(struct dma_chan *chan);
639 640

	struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
641
		struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
642
		size_t len, unsigned long flags);
643
	struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
644
		struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
645
		unsigned int src_cnt, size_t len, unsigned long flags);
D
Dan Williams 已提交
646
	struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
647
		struct dma_chan *chan, dma_addr_t *src,	unsigned int src_cnt,
D
Dan Williams 已提交
648
		size_t len, enum sum_check_flags *result, unsigned long flags);
649 650 651 652 653 654 655 656
	struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
		struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
		unsigned int src_cnt, const unsigned char *scf,
		size_t len, unsigned long flags);
	struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
		struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
		unsigned int src_cnt, const unsigned char *scf, size_t len,
		enum sum_check_flags *pqres, unsigned long flags);
657
	struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
658
		struct dma_chan *chan, unsigned long flags);
659 660 661 662 663
	struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
		struct dma_chan *chan,
		struct scatterlist *dst_sg, unsigned int dst_nents,
		struct scatterlist *src_sg, unsigned int src_nents,
		unsigned long flags);
664

665 666
	struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
		struct dma_chan *chan, struct scatterlist *sgl,
667
		unsigned int sg_len, enum dma_transfer_direction direction,
668
		unsigned long flags, void *context);
669 670
	struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
671
		size_t period_len, enum dma_transfer_direction direction,
672
		unsigned long flags, void *context);
673 674 675
	struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
		struct dma_chan *chan, struct dma_interleaved_template *xt,
		unsigned long flags);
676 677
	int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
		unsigned long arg);
678

679 680 681
	enum dma_status (*device_tx_status)(struct dma_chan *chan,
					    dma_cookie_t cookie,
					    struct dma_tx_state *txstate);
682
	void (*device_issue_pending)(struct dma_chan *chan);
683
	int (*device_slave_caps)(struct dma_chan *chan, struct dma_slave_caps *caps);
C
Chris Leech 已提交
684 685
};

686 687 688 689
static inline int dmaengine_device_control(struct dma_chan *chan,
					   enum dma_ctrl_cmd cmd,
					   unsigned long arg)
{
690 691
	if (chan->device->device_control)
		return chan->device->device_control(chan, cmd, arg);
692 693

	return -ENOSYS;
694 695 696 697 698 699 700 701 702
}

static inline int dmaengine_slave_config(struct dma_chan *chan,
					  struct dma_slave_config *config)
{
	return dmaengine_device_control(chan, DMA_SLAVE_CONFIG,
			(unsigned long)config);
}

703 704 705 706 707
static inline bool is_slave_direction(enum dma_transfer_direction direction)
{
	return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
}

708
static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
709
	struct dma_chan *chan, dma_addr_t buf, size_t len,
710
	enum dma_transfer_direction dir, unsigned long flags)
711 712
{
	struct scatterlist sg;
713 714 715
	sg_init_table(&sg, 1);
	sg_dma_address(&sg) = buf;
	sg_dma_len(&sg) = len;
716

717 718
	return chan->device->device_prep_slave_sg(chan, &sg, 1,
						  dir, flags, NULL);
719 720
}

721 722 723 724 725
static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
	struct dma_chan *chan, struct scatterlist *sgl,	unsigned int sg_len,
	enum dma_transfer_direction dir, unsigned long flags)
{
	return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
726
						  dir, flags, NULL);
727 728
}

729 730 731 732 733 734 735 736 737 738 739 740
#ifdef CONFIG_RAPIDIO_DMA_ENGINE
struct rio_dma_ext;
static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
	struct dma_chan *chan, struct scatterlist *sgl,	unsigned int sg_len,
	enum dma_transfer_direction dir, unsigned long flags,
	struct rio_dma_ext *rio_ext)
{
	return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
						  dir, flags, rio_ext);
}
#endif

741 742
static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
743 744
		size_t period_len, enum dma_transfer_direction dir,
		unsigned long flags)
745 746
{
	return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
747
						period_len, dir, flags, NULL);
748 749 750 751 752 753 754
}

static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
		struct dma_chan *chan, struct dma_interleaved_template *xt,
		unsigned long flags)
{
	return chan->device->device_prep_interleaved_dma(chan, xt, flags);
755 756
}

757 758 759 760 761 762 763 764 765 766 767 768 769 770 771
static inline int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps)
{
	if (!chan || !caps)
		return -EINVAL;

	/* check if the channel supports slave transactions */
	if (!test_bit(DMA_SLAVE, chan->device->cap_mask.bits))
		return -ENXIO;

	if (chan->device->device_slave_caps)
		return chan->device->device_slave_caps(chan, caps);

	return -ENXIO;
}

772 773 774 775 776 777 778 779 780 781 782 783 784 785 786
static inline int dmaengine_terminate_all(struct dma_chan *chan)
{
	return dmaengine_device_control(chan, DMA_TERMINATE_ALL, 0);
}

static inline int dmaengine_pause(struct dma_chan *chan)
{
	return dmaengine_device_control(chan, DMA_PAUSE, 0);
}

static inline int dmaengine_resume(struct dma_chan *chan)
{
	return dmaengine_device_control(chan, DMA_RESUME, 0);
}

787 788 789 790 791 792
static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
	dma_cookie_t cookie, struct dma_tx_state *state)
{
	return chan->device->device_tx_status(chan, cookie, state);
}

793
static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
794 795 796 797
{
	return desc->tx_submit(desc);
}

798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833
static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
{
	size_t mask;

	if (!align)
		return true;
	mask = (1 << align) - 1;
	if (mask & (off1 | off2 | len))
		return false;
	return true;
}

static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
				       size_t off2, size_t len)
{
	return dmaengine_check_align(dev->copy_align, off1, off2, len);
}

static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
				      size_t off2, size_t len)
{
	return dmaengine_check_align(dev->xor_align, off1, off2, len);
}

static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
				     size_t off2, size_t len)
{
	return dmaengine_check_align(dev->pq_align, off1, off2, len);
}

static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
				       size_t off2, size_t len)
{
	return dmaengine_check_align(dev->fill_align, off1, off2, len);
}

834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858
static inline void
dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
{
	dma->max_pq = maxpq;
	if (has_pq_continue)
		dma->max_pq |= DMA_HAS_PQ_CONTINUE;
}

static inline bool dmaf_continue(enum dma_ctrl_flags flags)
{
	return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
}

static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
{
	enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;

	return (flags & mask) == mask;
}

static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
{
	return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
}

859
static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887
{
	return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
}

/* dma_maxpq - reduce maxpq in the face of continued operations
 * @dma - dma device with PQ capability
 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
 *
 * When an engine does not support native continuation we need 3 extra
 * source slots to reuse P and Q with the following coefficients:
 * 1/ {00} * P : remove P from Q', but use it as a source for P'
 * 2/ {01} * Q : use Q to continue Q' calculation
 * 3/ {00} * Q : subtract Q from P' to cancel (2)
 *
 * In the case where P is disabled we only need 1 extra source:
 * 1/ {01} * Q : use Q to continue Q' calculation
 */
static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
{
	if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
		return dma_dev_to_maxpq(dma);
	else if (dmaf_p_disabled_continue(flags))
		return dma_dev_to_maxpq(dma) - 1;
	else if (dmaf_continue(flags))
		return dma_dev_to_maxpq(dma) - 3;
	BUG();
}

C
Chris Leech 已提交
888 889
/* --- public DMA engine API --- */

890
#ifdef CONFIG_DMA_ENGINE
891 892
void dmaengine_get(void);
void dmaengine_put(void);
893 894 895 896 897 898 899 900 901
#else
static inline void dmaengine_get(void)
{
}
static inline void dmaengine_put(void)
{
}
#endif

902 903 904 905 906 907 908 909 910 911 912 913
#ifdef CONFIG_NET_DMA
#define net_dmaengine_get()	dmaengine_get()
#define net_dmaengine_put()	dmaengine_put()
#else
static inline void net_dmaengine_get(void)
{
}
static inline void net_dmaengine_put(void)
{
}
#endif

914 915 916
#ifdef CONFIG_ASYNC_TX_DMA
#define async_dmaengine_get()	dmaengine_get()
#define async_dmaengine_put()	dmaengine_put()
917
#ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
918 919
#define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
#else
920
#define async_dma_find_channel(type) dma_find_channel(type)
921
#endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
922 923 924 925 926 927 928 929 930 931 932 933
#else
static inline void async_dmaengine_get(void)
{
}
static inline void async_dmaengine_put(void)
{
}
static inline struct dma_chan *
async_dma_find_channel(enum dma_transaction_type type)
{
	return NULL;
}
934
#endif /* CONFIG_ASYNC_TX_DMA */
935

936 937 938 939 940 941 942 943 944
dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
	void *dest, void *src, size_t len);
dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
	struct page *page, unsigned int offset, void *kdata, size_t len);
dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
	struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
	unsigned int src_off, size_t len);
void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
	struct dma_chan *chan);
C
Chris Leech 已提交
945

946
static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
947
{
948 949 950
	tx->flags |= DMA_CTRL_ACK;
}

951 952 953 954 955
static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
{
	tx->flags &= ~DMA_CTRL_ACK;
}

956
static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
957
{
958
	return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
C
Chris Leech 已提交
959 960
}

961 962 963
#define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
static inline void
__dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
C
Chris Leech 已提交
964
{
965 966
	set_bit(tx_type, dstp->bits);
}
C
Chris Leech 已提交
967

968 969 970 971 972 973 974
#define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
static inline void
__dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
{
	clear_bit(tx_type, dstp->bits);
}

975 976 977 978 979 980
#define dma_cap_zero(mask) __dma_cap_zero(&(mask))
static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
{
	bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
}

981 982 983 984 985
#define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
static inline int
__dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
{
	return test_bit(tx_type, srcp->bits);
C
Chris Leech 已提交
986 987
}

988
#define for_each_dma_cap_mask(cap, mask) \
A
Akinobu Mita 已提交
989
	for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
990

C
Chris Leech 已提交
991
/**
992
 * dma_async_issue_pending - flush pending transactions to HW
993
 * @chan: target DMA channel
C
Chris Leech 已提交
994 995 996 997
 *
 * This allows drivers to push copies to HW in batches,
 * reducing MMIO writes where possible.
 */
998
static inline void dma_async_issue_pending(struct dma_chan *chan)
C
Chris Leech 已提交
999
{
D
Dan Williams 已提交
1000
	chan->device->device_issue_pending(chan);
C
Chris Leech 已提交
1001 1002 1003
}

/**
1004
 * dma_async_is_tx_complete - poll for transaction completion
C
Chris Leech 已提交
1005 1006 1007 1008 1009 1010 1011 1012 1013
 * @chan: DMA channel
 * @cookie: transaction identifier to check status of
 * @last: returns last completed cookie, can be NULL
 * @used: returns last issued cookie, can be NULL
 *
 * If @last and @used are passed in, upon return they reflect the driver
 * internal state and can be used with dma_async_is_complete() to check
 * the status of multiple cookies without re-checking hardware state.
 */
1014
static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
C
Chris Leech 已提交
1015 1016
	dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
{
1017 1018 1019 1020 1021 1022 1023 1024 1025
	struct dma_tx_state state;
	enum dma_status status;

	status = chan->device->device_tx_status(chan, cookie, &state);
	if (last)
		*last = state.last;
	if (used)
		*used = state.used;
	return status;
C
Chris Leech 已提交
1026 1027 1028 1029 1030 1031 1032 1033
}

/**
 * dma_async_is_complete - test a cookie against chan state
 * @cookie: transaction identifier to test status of
 * @last_complete: last know completed transaction
 * @last_used: last cookie value handed out
 *
1034
 * dma_async_is_complete() is used in dma_async_is_tx_complete()
S
Sebastian Siewior 已提交
1035
 * the test logic is separated for lightweight testing of multiple cookies
C
Chris Leech 已提交
1036 1037 1038 1039 1040 1041
 */
static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
			dma_cookie_t last_complete, dma_cookie_t last_used)
{
	if (last_complete <= last_used) {
		if ((cookie <= last_complete) || (cookie > last_used))
1042
			return DMA_COMPLETE;
C
Chris Leech 已提交
1043 1044
	} else {
		if ((cookie <= last_complete) && (cookie > last_used))
1045
			return DMA_COMPLETE;
C
Chris Leech 已提交
1046 1047 1048 1049
	}
	return DMA_IN_PROGRESS;
}

1050 1051 1052 1053 1054 1055 1056 1057 1058 1059
static inline void
dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
{
	if (st) {
		st->last = last;
		st->used = used;
		st->residue = residue;
	}
}

1060
#ifdef CONFIG_DMA_ENGINE
1061 1062
struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1063
enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1064
void dma_issue_pending_all(void);
1065 1066
struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
					dma_filter_fn fn, void *fn_param);
1067 1068
struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
						  const char *name);
M
Markus Pargmann 已提交
1069
struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
1070
void dma_release_channel(struct dma_chan *chan);
1071
#else
1072 1073 1074 1075 1076 1077
static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
{
	return NULL;
}
static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
{
1078
	return DMA_COMPLETE;
1079
}
1080 1081
static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
{
1082
	return DMA_COMPLETE;
1083
}
1084 1085
static inline void dma_issue_pending_all(void)
{
1086
}
1087
static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1088 1089 1090 1091
					      dma_filter_fn fn, void *fn_param)
{
	return NULL;
}
1092 1093 1094 1095 1096
static inline struct dma_chan *dma_request_slave_channel_reason(
					struct device *dev, const char *name)
{
	return ERR_PTR(-ENODEV);
}
1097
static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
M
Markus Pargmann 已提交
1098
							 const char *name)
1099
{
1100
	return NULL;
1101
}
1102 1103
static inline void dma_release_channel(struct dma_chan *chan)
{
1104
}
1105
#endif
C
Chris Leech 已提交
1106 1107 1108 1109 1110

/* --- DMA device --- */

int dma_async_device_register(struct dma_device *device);
void dma_async_device_unregister(struct dma_device *device);
1111
void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1112
struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
1113
struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
1114
struct dma_chan *net_dma_find_channel(void);
1115
#define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1116 1117 1118 1119
#define dma_request_slave_channel_compat(mask, x, y, dev, name) \
	__dma_request_slave_channel_compat(&(mask), x, y, dev, name)

static inline struct dma_chan
1120 1121 1122
*__dma_request_slave_channel_compat(const dma_cap_mask_t *mask,
				  dma_filter_fn fn, void *fn_param,
				  struct device *dev, char *name)
1123 1124 1125 1126 1127 1128 1129 1130 1131
{
	struct dma_chan *chan;

	chan = dma_request_slave_channel(dev, name);
	if (chan)
		return chan;

	return __dma_request_channel(mask, fn, fn_param);
}
C
Chris Leech 已提交
1132

1133 1134 1135
/* --- Helper iov-locking functions --- */

struct dma_page_list {
1136
	char __user *base_address;
1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154
	int nr_pages;
	struct page **pages;
};

struct dma_pinned_list {
	int nr_iovecs;
	struct dma_page_list page_list[0];
};

struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);

dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
	struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
	struct dma_pinned_list *pinned_list, struct page *page,
	unsigned int offset, size_t len);

C
Chris Leech 已提交
1155
#endif /* DMAENGINE_H */