io.c 11.0 KB
Newer Older
1 2 3 4 5 6
/*
 * linux/arch/arm/mach-omap2/io.c
 *
 * OMAP2 I/O mapping code
 *
 * Copyright (C) 2005 Nokia Corporation
7
 * Copyright (C) 2007-2009 Texas Instruments
8 9 10 11
 *
 * Author:
 *	Juha Yrjola <juha.yrjola@nokia.com>
 *	Syed Khasim <x0khasim@ti.com>
12
 *
13 14
 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
 *
15 16 17 18 19 20 21
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/init.h>
22
#include <linux/io.h>
23
#include <linux/clk.h>
24

25 26 27
#include <asm/tlb.h>
#include <asm/mach/map.h>

28 29 30 31
#include <plat/sram.h>
#include <plat/sdrc.h>
#include <plat/serial.h>
#include <plat/omap-pm.h>
32 33
#include <plat/omap_hwmod.h>
#include <plat/multi.h>
34
#include <plat/dma.h>
35 36

#include "iomap.h"
37
#include "voltage.h"
38
#include "powerdomain.h"
39
#include "clockdomain.h"
40
#include "common.h"
41 42 43
#include "clock2xxx.h"
#include "clock3xxx.h"
#include "clock44xx.h"
44

45 46 47 48
/*
 * The machine specific code may provide the extra mapping besides the
 * default mapping provided here.
 */
49

50
#if defined(CONFIG_SOC_OMAP2420) || defined(CONFIG_SOC_OMAP2430)
51
static struct map_desc omap24xx_io_desc[] __initdata = {
52 53 54 55 56 57
	{
		.virtual	= L3_24XX_VIRT,
		.pfn		= __phys_to_pfn(L3_24XX_PHYS),
		.length		= L3_24XX_SIZE,
		.type		= MT_DEVICE
	},
58
	{
59 60 61 62
		.virtual	= L4_24XX_VIRT,
		.pfn		= __phys_to_pfn(L4_24XX_PHYS),
		.length		= L4_24XX_SIZE,
		.type		= MT_DEVICE
63
	},
64 65
};

66
#ifdef CONFIG_SOC_OMAP2420
67 68
static struct map_desc omap242x_io_desc[] __initdata = {
	{
69 70 71
		.virtual	= DSP_MEM_2420_VIRT,
		.pfn		= __phys_to_pfn(DSP_MEM_2420_PHYS),
		.length		= DSP_MEM_2420_SIZE,
72 73 74
		.type		= MT_DEVICE
	},
	{
75 76 77
		.virtual	= DSP_IPI_2420_VIRT,
		.pfn		= __phys_to_pfn(DSP_IPI_2420_PHYS),
		.length		= DSP_IPI_2420_SIZE,
78
		.type		= MT_DEVICE
79
	},
80
	{
81 82 83
		.virtual	= DSP_MMU_2420_VIRT,
		.pfn		= __phys_to_pfn(DSP_MMU_2420_PHYS),
		.length		= DSP_MMU_2420_SIZE,
84 85 86 87 88 89
		.type		= MT_DEVICE
	},
};

#endif

90
#ifdef CONFIG_SOC_OMAP2430
91
static struct map_desc omap243x_io_desc[] __initdata = {
92 93 94 95 96 97 98 99 100 101 102 103
	{
		.virtual	= L4_WK_243X_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_243X_PHYS),
		.length		= L4_WK_243X_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_GPMC_PHYS),
		.length		= OMAP243X_GPMC_SIZE,
		.type		= MT_DEVICE
	},
104 105 106 107 108 109 110 111 112 113 114 115 116
	{
		.virtual	= OMAP243X_SDRC_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_SDRC_PHYS),
		.length		= OMAP243X_SDRC_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP243X_SMS_VIRT,
		.pfn		= __phys_to_pfn(OMAP243X_SMS_PHYS),
		.length		= OMAP243X_SMS_SIZE,
		.type		= MT_DEVICE
	},
};
117 118
#endif
#endif
119

120
#ifdef	CONFIG_ARCH_OMAP3
121
static struct map_desc omap34xx_io_desc[] __initdata = {
122
	{
123 124 125
		.virtual	= L3_34XX_VIRT,
		.pfn		= __phys_to_pfn(L3_34XX_PHYS),
		.length		= L3_34XX_SIZE,
126 127 128
		.type		= MT_DEVICE
	},
	{
129 130 131
		.virtual	= L4_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
		.length		= L4_34XX_SIZE,
132 133
		.type		= MT_DEVICE
	},
134 135 136 137
	{
		.virtual	= OMAP34XX_GPMC_VIRT,
		.pfn		= __phys_to_pfn(OMAP34XX_GPMC_PHYS),
		.length		= OMAP34XX_GPMC_SIZE,
138
		.type		= MT_DEVICE
139 140 141 142 143 144 145 146 147 148 149
	},
	{
		.virtual	= OMAP343X_SMS_VIRT,
		.pfn		= __phys_to_pfn(OMAP343X_SMS_PHYS),
		.length		= OMAP343X_SMS_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= OMAP343X_SDRC_VIRT,
		.pfn		= __phys_to_pfn(OMAP343X_SDRC_PHYS),
		.length		= OMAP343X_SDRC_SIZE,
150
		.type		= MT_DEVICE
151 152 153 154 155 156 157 158 159 160 161 162 163
	},
	{
		.virtual	= L4_PER_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_34XX_PHYS),
		.length		= L4_PER_34XX_SIZE,
		.type		= MT_DEVICE
	},
	{
		.virtual	= L4_EMU_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_EMU_34XX_PHYS),
		.length		= L4_EMU_34XX_SIZE,
		.type		= MT_DEVICE
	},
164 165 166 167 168 169 170 171 172
#if defined(CONFIG_DEBUG_LL) &&							\
	(defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
	{
		.virtual	= ZOOM_UART_VIRT,
		.pfn		= __phys_to_pfn(ZOOM_UART_BASE),
		.length		= SZ_1M,
		.type		= MT_DEVICE
	},
#endif
173
};
174
#endif
175

176
#ifdef CONFIG_SOC_TI81XX
177
static struct map_desc omapti81xx_io_desc[] __initdata = {
178 179 180 181 182 183 184 185 186
	{
		.virtual	= L4_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
		.length		= L4_34XX_SIZE,
		.type		= MT_DEVICE
	}
};
#endif

187
#ifdef CONFIG_SOC_AM33XX
188
static struct map_desc omapam33xx_io_desc[] __initdata = {
189 190 191 192 193 194
	{
		.virtual	= L4_34XX_VIRT,
		.pfn		= __phys_to_pfn(L4_34XX_PHYS),
		.length		= L4_34XX_SIZE,
		.type		= MT_DEVICE
	},
195 196 197 198 199 200
	{
		.virtual	= L4_WK_AM33XX_VIRT,
		.pfn		= __phys_to_pfn(L4_WK_AM33XX_PHYS),
		.length		= L4_WK_AM33XX_SIZE,
		.type		= MT_DEVICE
	}
201 202 203
};
#endif

204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223
#ifdef	CONFIG_ARCH_OMAP4
static struct map_desc omap44xx_io_desc[] __initdata = {
	{
		.virtual	= L3_44XX_VIRT,
		.pfn		= __phys_to_pfn(L3_44XX_PHYS),
		.length		= L3_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_44XX_PHYS),
		.length		= L4_44XX_SIZE,
		.type		= MT_DEVICE,
	},
	{
		.virtual	= L4_PER_44XX_VIRT,
		.pfn		= __phys_to_pfn(L4_PER_44XX_PHYS),
		.length		= L4_PER_44XX_SIZE,
		.type		= MT_DEVICE,
	},
224 225 226 227 228 229 230 231 232
#ifdef CONFIG_OMAP4_ERRATA_I688
	{
		.virtual	= OMAP4_SRAM_VA,
		.pfn		= __phys_to_pfn(OMAP4_SRAM_PA),
		.length		= PAGE_SIZE,
		.type		= MT_MEMORY_SO,
	},
#endif

233 234
};
#endif
235

236
#ifdef CONFIG_SOC_OMAP2420
237
void __init omap242x_map_common_io(void)
238
{
239 240
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
241
}
242 243
#endif

244
#ifdef CONFIG_SOC_OMAP2430
245
void __init omap243x_map_common_io(void)
246
{
247 248
	iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
	iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
249
}
250 251
#endif

252
#ifdef CONFIG_ARCH_OMAP3
253
void __init omap34xx_map_common_io(void)
254
{
255
	iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
256
}
257
#endif
258

259
#ifdef CONFIG_SOC_TI81XX
260
void __init omapti81xx_map_common_io(void)
261
{
262
	iotable_init(omapti81xx_io_desc, ARRAY_SIZE(omapti81xx_io_desc));
263 264 265
}
#endif

266
#ifdef CONFIG_SOC_AM33XX
267
void __init omapam33xx_map_common_io(void)
268
{
269
	iotable_init(omapam33xx_io_desc, ARRAY_SIZE(omapam33xx_io_desc));
270 271 272
}
#endif

273
#ifdef CONFIG_ARCH_OMAP4
274
void __init omap44xx_map_common_io(void)
275
{
276
	iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
277
	omap_barriers_init();
278
}
279
#endif
280

281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
/*
 * omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
 *
 * Sets the CORE DPLL3 M2 divider to the same value that it's at
 * currently.  This has the effect of setting the SDRC SDRAM AC timing
 * registers to the values currently defined by the kernel.  Currently
 * only defined for OMAP3; will return 0 if called on OMAP2.  Returns
 * -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
 * or passes along the return value of clk_set_rate().
 */
static int __init _omap2_init_reprogram_sdrc(void)
{
	struct clk *dpll3_m2_ck;
	int v = -EINVAL;
	long rate;

	if (!cpu_is_omap34xx())
		return 0;

	dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
301
	if (IS_ERR(dpll3_m2_ck))
302 303 304 305 306 307 308 309 310 311 312 313 314
		return -EINVAL;

	rate = clk_get_rate(dpll3_m2_ck);
	pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
	v = clk_set_rate(dpll3_m2_ck, rate);
	if (v)
		pr_err("dpll3_m2_clk rate change failed: %d\n", v);

	clk_put(dpll3_m2_ck);

	return v;
}

P
Paul Walmsley 已提交
315 316 317 318 319
static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
{
	return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
}

320
static void __init omap_common_init_early(void)
321
{
322
	omap_init_consistent_dma_size();
323
}
P
Paul Walmsley 已提交
324

325 326 327
static void __init omap_hwmod_init_postsetup(void)
{
	u8 postsetup_state;
P
Paul Walmsley 已提交
328 329 330 331 332 333 334 335

	/* Set the default postsetup state for all hwmods */
#ifdef CONFIG_PM_RUNTIME
	postsetup_state = _HWMOD_STATE_IDLE;
#else
	postsetup_state = _HWMOD_STATE_ENABLED;
#endif
	omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
336

337
	omap_pm_if_early_init();
338 339
}

340
#ifdef CONFIG_SOC_OMAP2420
341 342
void __init omap2420_init_early(void)
{
343
	omap2_set_globals_242x();
344
	omap2xxx_check_revision();
345 346 347 348 349 350 351
	omap_common_init_early();
	omap2xxx_voltagedomains_init();
	omap242x_powerdomains_init();
	omap242x_clockdomains_init();
	omap2420_hwmod_init();
	omap_hwmod_init_postsetup();
	omap2420_clk_init();
352
}
353 354 355 356 357 358 359

void __init omap2420_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap2_pm_init();
}
360
#endif
361

362
#ifdef CONFIG_SOC_OMAP2430
363 364
void __init omap2430_init_early(void)
{
365
	omap2_set_globals_243x();
366
	omap2xxx_check_revision();
367 368 369 370 371 372 373 374
	omap_common_init_early();
	omap2xxx_voltagedomains_init();
	omap243x_powerdomains_init();
	omap243x_clockdomains_init();
	omap2430_hwmod_init();
	omap_hwmod_init_postsetup();
	omap2430_clk_init();
}
375 376 377 378 379 380 381

void __init omap2430_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap2_pm_init();
}
382
#endif
383 384 385 386 387

/*
 * Currently only board-omap3beagle.c should call this because of the
 * same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
 */
388
#ifdef CONFIG_ARCH_OMAP3
389 390
void __init omap3_init_early(void)
{
391
	omap2_set_globals_3xxx();
392 393
	omap3xxx_check_revision();
	omap3xxx_check_features();
394 395 396 397 398 399 400
	omap_common_init_early();
	omap3xxx_voltagedomains_init();
	omap3xxx_powerdomains_init();
	omap3xxx_clockdomains_init();
	omap3xxx_hwmod_init();
	omap_hwmod_init_postsetup();
	omap3xxx_clk_init();
401 402 403 404
}

void __init omap3430_init_early(void)
{
405
	omap3_init_early();
406 407 408 409
}

void __init omap35xx_init_early(void)
{
410
	omap3_init_early();
411 412 413 414
}

void __init omap3630_init_early(void)
{
415
	omap3_init_early();
416 417 418 419
}

void __init am35xx_init_early(void)
{
420
	omap3_init_early();
421 422
}

423
void __init ti81xx_init_early(void)
424
{
425
	omap2_set_globals_ti81xx();
426 427
	omap3xxx_check_revision();
	ti81xx_check_features();
428 429 430 431 432 433 434
	omap_common_init_early();
	omap3xxx_voltagedomains_init();
	omap3xxx_powerdomains_init();
	omap3xxx_clockdomains_init();
	omap3xxx_hwmod_init();
	omap_hwmod_init_postsetup();
	omap3xxx_clk_init();
435
}
436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477

void __init omap3_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap3_pm_init();
}

void __init omap3430_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap3_pm_init();
}

void __init omap35xx_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap3_pm_init();
}

void __init omap3630_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap3_pm_init();
}

void __init am35xx_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap3_pm_init();
}

void __init ti81xx_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap3_pm_init();
}
478
#endif
479

480 481 482 483 484 485 486
#ifdef CONFIG_SOC_AM33XX
void __init am33xx_init_early(void)
{
	omap2_set_globals_am33xx();
	omap3xxx_check_revision();
	ti81xx_check_features();
	omap_common_init_early();
487
	am33xx_voltagedomains_init();
488
	am33xx_powerdomains_init();
489
	am33xx_clockdomains_init();
490 491 492
}
#endif

493
#ifdef CONFIG_ARCH_OMAP4
494 495
void __init omap4430_init_early(void)
{
496
	omap2_set_globals_443x();
497 498
	omap4xxx_check_revision();
	omap4xxx_check_features();
499 500 501 502 503 504 505
	omap_common_init_early();
	omap44xx_voltagedomains_init();
	omap44xx_powerdomains_init();
	omap44xx_clockdomains_init();
	omap44xx_hwmod_init();
	omap_hwmod_init_postsetup();
	omap4xxx_clk_init();
506
}
507 508 509 510 511 512 513

void __init omap4430_init_late(void)
{
	omap_mux_late_init();
	omap2_common_pm_late_init();
	omap4_pm_init();
}
514
#endif
515

516
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
517 518
				      struct omap_sdrc_params *sdrc_cs1)
{
519 520
	omap_sram_init();

521
	if (cpu_is_omap24xx() || omap3_has_sdrc()) {
522 523 524
		omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
		_omap2_init_reprogram_sdrc();
	}
525
}