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acx.h 32.5 KB
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/*
 * This file is part of wl1271
 *
 * Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
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 * Copyright (C) 2008-2010 Nokia Corporation
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 *
 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

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#ifndef __ACX_H__
#define __ACX_H__
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#include "wl12xx.h"
#include "cmd.h"
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/*************************************************************************

    Host Interrupt Register (WiLink -> Host)

**************************************************************************/
/* HW Initiated interrupt Watchdog timer expiration */
#define WL1271_ACX_INTR_WATCHDOG           BIT(0)
/* Init sequence is done (masked interrupt, detection through polling only ) */
#define WL1271_ACX_INTR_INIT_COMPLETE      BIT(1)
/* Event was entered to Event MBOX #A*/
#define WL1271_ACX_INTR_EVENT_A            BIT(2)
/* Event was entered to Event MBOX #B*/
#define WL1271_ACX_INTR_EVENT_B            BIT(3)
/* Command processing completion*/
#define WL1271_ACX_INTR_CMD_COMPLETE       BIT(4)
/* Signaling the host on HW wakeup */
#define WL1271_ACX_INTR_HW_AVAILABLE       BIT(5)
/* The MISC bit is used for aggregation of RX, TxComplete and TX rate update */
#define WL1271_ACX_INTR_DATA               BIT(6)
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/* Trace message on MBOX #A */
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#define WL1271_ACX_INTR_TRACE_A            BIT(7)
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/* Trace message on MBOX #B */
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#define WL1271_ACX_INTR_TRACE_B            BIT(8)

#define WL1271_ACX_INTR_ALL		   0xFFFFFFFF
#define WL1271_ACX_ALL_EVENTS_VECTOR       (WL1271_ACX_INTR_WATCHDOG      | \
					    WL1271_ACX_INTR_INIT_COMPLETE | \
					    WL1271_ACX_INTR_EVENT_A       | \
					    WL1271_ACX_INTR_EVENT_B       | \
					    WL1271_ACX_INTR_CMD_COMPLETE  | \
					    WL1271_ACX_INTR_HW_AVAILABLE  | \
					    WL1271_ACX_INTR_DATA)

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#define WL1271_INTR_MASK                   (WL1271_ACX_INTR_WATCHDOG     | \
					    WL1271_ACX_INTR_EVENT_A      | \
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					    WL1271_ACX_INTR_EVENT_B      | \
					    WL1271_ACX_INTR_HW_AVAILABLE | \
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					    WL1271_ACX_INTR_DATA)

/* Target's information element */
struct acx_header {
	struct wl1271_cmd_header cmd;

	/* acx (or information element) header */
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	__le16 id;
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	/* payload length (not including headers */
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	__le16 len;
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} __packed;
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struct acx_error_counter {
	struct acx_header header;

	/* The number of PLCP errors since the last time this */
	/* information element was interrogated. This field is */
	/* automatically cleared when it is interrogated.*/
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	__le32 PLCP_error;
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	/* The number of FCS errors since the last time this */
	/* information element was interrogated. This field is */
	/* automatically cleared when it is interrogated.*/
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	__le32 FCS_error;
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	/* The number of MPDUs without PLCP header errors received*/
	/* since the last time this information element was interrogated. */
	/* This field is automatically cleared when it is interrogated.*/
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	__le32 valid_frame;
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	/* the number of missed sequence numbers in the squentially */
	/* values of frames seq numbers */
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	__le32 seq_num_miss;
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} __packed;
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enum wl12xx_role {
	WL1271_ROLE_STA = 0,
	WL1271_ROLE_IBSS,
	WL1271_ROLE_AP,
	WL1271_ROLE_DEVICE,
	WL1271_ROLE_P2P_CL,
	WL1271_ROLE_P2P_GO,

	WL12XX_INVALID_ROLE_TYPE = 0xff
};

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enum wl1271_psm_mode {
	/* Active mode */
	WL1271_PSM_CAM = 0,

	/* Power save mode */
	WL1271_PSM_PS = 1,

	/* Extreme low power */
	WL1271_PSM_ELP = 2,
};

struct acx_sleep_auth {
	struct acx_header header;

	/* The sleep level authorization of the device. */
	/* 0 - Always active*/
	/* 1 - Power down mode: light / fast sleep*/
	/* 2 - ELP mode: Deep / Max sleep*/
	u8  sleep_auth;
	u8  padding[3];
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} __packed;
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enum {
	HOSTIF_PCI_MASTER_HOST_INDIRECT,
	HOSTIF_PCI_MASTER_HOST_DIRECT,
	HOSTIF_SLAVE,
	HOSTIF_PKT_RING,
	HOSTIF_DONTCARE = 0xFF
};

#define DEFAULT_UCAST_PRIORITY          0
#define DEFAULT_RX_Q_PRIORITY           0
#define DEFAULT_RXQ_PRIORITY            0 /* low 0 .. 15 high  */
#define DEFAULT_RXQ_TYPE                0x07    /* All frames, Data/Ctrl/Mgmt */
#define TRACE_BUFFER_MAX_SIZE           256

#define  DP_RX_PACKET_RING_CHUNK_SIZE 1600
#define  DP_TX_PACKET_RING_CHUNK_SIZE 1600
#define  DP_RX_PACKET_RING_CHUNK_NUM 2
#define  DP_TX_PACKET_RING_CHUNK_NUM 2
#define  DP_TX_COMPLETE_TIME_OUT 20

#define TX_MSDU_LIFETIME_MIN       0
#define TX_MSDU_LIFETIME_MAX       3000
#define TX_MSDU_LIFETIME_DEF       512
#define RX_MSDU_LIFETIME_MIN       0
#define RX_MSDU_LIFETIME_MAX       0xFFFFFFFF
#define RX_MSDU_LIFETIME_DEF       512000

struct acx_rx_msdu_lifetime {
	struct acx_header header;

	/*
	 * The maximum amount of time, in TU, before the
	 * firmware discards the MSDU.
	 */
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	__le32 lifetime;
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} __packed;
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struct acx_packet_detection {
	struct acx_header header;

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	__le32 threshold;
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} __packed;
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enum acx_slot_type {
	SLOT_TIME_LONG = 0,
	SLOT_TIME_SHORT = 1,
	DEFAULT_SLOT_TIME = SLOT_TIME_SHORT,
	MAX_SLOT_TIMES = 0xFF
};

#define STATION_WONE_INDEX 0

struct acx_slot {
	struct acx_header header;

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	u8 role_id;
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	u8 wone_index; /* Reserved */
	u8 slot_time;
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	u8 reserved[5];
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} __packed;
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#define ACX_MC_ADDRESS_GROUP_MAX	(8)
#define ADDRESS_GROUP_MAX_LEN	        (ETH_ALEN * ACX_MC_ADDRESS_GROUP_MAX)
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struct acx_dot11_grp_addr_tbl {
	struct acx_header header;

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	u8 role_id;
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	u8 enabled;
	u8 num_groups;
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	u8 pad[1];
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	u8 mac_table[ADDRESS_GROUP_MAX_LEN];
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} __packed;
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struct acx_rx_timeout {
	struct acx_header header;

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	u8 role_id;
	u8 reserved;
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	__le16 ps_poll_timeout;
	__le16 upsd_timeout;
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	u8 padding[2];
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} __packed;
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struct acx_rts_threshold {
	struct acx_header header;

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	u8 role_id;
	u8 reserved;
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	__le16 threshold;
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} __packed;
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struct acx_beacon_filter_option {
	struct acx_header header;

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	u8 role_id;
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	u8 enable;
	/*
	 * The number of beacons without the unicast TIM
	 * bit set that the firmware buffers before
	 * signaling the host about ready frames.
	 * When set to 0 and the filter is enabled, beacons
	 * without the unicast TIM bit set are dropped.
	 */
	u8 max_num_beacons;
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	u8 pad[1];
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} __packed;
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/*
 * ACXBeaconFilterEntry (not 221)
 * Byte Offset     Size (Bytes)    Definition
 * ===========     ============    ==========
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 * 0               1               IE identifier
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 * 1               1               Treatment bit mask
 *
 * ACXBeaconFilterEntry (221)
 * Byte Offset     Size (Bytes)    Definition
 * ===========     ============    ==========
 * 0               1               IE identifier
 * 1               1               Treatment bit mask
 * 2               3               OUI
 * 5               1               Type
 * 6               2               Version
 *
 *
 * Treatment bit mask - The information element handling:
 * bit 0 - The information element is compared and transferred
 * in case of change.
 * bit 1 - The information element is transferred to the host
 * with each appearance or disappearance.
 * Note that both bits can be set at the same time.
 */
#define	BEACON_FILTER_TABLE_MAX_IE_NUM		       (32)
#define BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM (6)
#define BEACON_FILTER_TABLE_IE_ENTRY_SIZE	       (2)
#define BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE (6)
#define BEACON_FILTER_TABLE_MAX_SIZE ((BEACON_FILTER_TABLE_MAX_IE_NUM * \
			    BEACON_FILTER_TABLE_IE_ENTRY_SIZE) + \
			   (BEACON_FILTER_TABLE_MAX_VENDOR_SPECIFIC_IE_NUM * \
			    BEACON_FILTER_TABLE_EXTRA_VENDOR_SPECIFIC_IE_SIZE))

struct acx_beacon_filter_ie_table {
	struct acx_header header;

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	u8 role_id;
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	u8 num_ie;
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	u8 pad[2];
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	u8 table[BEACON_FILTER_TABLE_MAX_SIZE];
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} __packed;
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struct acx_conn_monit_params {
       struct acx_header header;

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	   u8 role_id;
	   u8 padding[3];
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       __le32 synch_fail_thold; /* number of beacons missed */
       __le32 bss_lose_timeout; /* number of TU's from synch fail */
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} __packed;
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struct acx_bt_wlan_coex {
	struct acx_header header;

	u8 enable;
	u8 pad[3];
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} __packed;
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struct acx_bt_wlan_coex_param {
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	struct acx_header header;

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	__le32 params[CONF_SG_PARAMS_MAX];
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	u8 param_idx;
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	u8 padding[3];
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} __packed;
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struct acx_dco_itrim_params {
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	struct acx_header header;

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	u8 enable;
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	u8 padding[3];
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	__le32 timeout;
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} __packed;
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struct acx_energy_detection {
	struct acx_header header;

	/* The RX Clear Channel Assessment threshold in the PHY */
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	__le16 rx_cca_threshold;
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	u8 tx_energy_detection;
	u8 pad;
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} __packed;
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struct acx_beacon_broadcast {
	struct acx_header header;

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	u8 role_id;
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	/* Enables receiving of broadcast packets in PS mode */
	u8 rx_broadcast_in_ps;

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	__le16 beacon_rx_timeout;
	__le16 broadcast_timeout;

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	/* Consecutive PS Poll failures before updating the host */
	u8 ps_poll_threshold;
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	u8 pad[1];
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} __packed;
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struct acx_event_mask {
	struct acx_header header;

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	__le32 event_mask;
	__le32 high_event_mask; /* Unused */
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} __packed;
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#define SCAN_PASSIVE		BIT(0)
#define SCAN_5GHZ_BAND		BIT(1)
#define SCAN_TRIGGERED		BIT(2)
#define SCAN_PRIORITY_HIGH	BIT(3)

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/* When set, disable HW encryption */
#define DF_ENCRYPTION_DISABLE      0x01
#define DF_SNIFF_MODE_ENABLE       0x80

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struct acx_feature_config {
	struct acx_header header;

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	u8 role_id;
	u8 padding[3];
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	__le32 options;
	__le32 data_flow_options;
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} __packed;
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struct acx_current_tx_power {
	struct acx_header header;

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	u8  role_id;
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	u8  current_tx_power;
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	u8  padding[2];
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} __packed;
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struct acx_wake_up_condition {
	struct acx_header header;

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	u8 role_id;
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	u8 wake_up_event; /* Only one bit can be set */
	u8 listen_interval;
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	u8 pad[1];
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} __packed;
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struct acx_aid {
	struct acx_header header;

	/*
	 * To be set when associated with an AP.
	 */
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	u8 role_id;
	u8 reserved;
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	__le16 aid;
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} __packed;
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enum acx_preamble_type {
	ACX_PREAMBLE_LONG = 0,
	ACX_PREAMBLE_SHORT = 1
};

struct acx_preamble {
	struct acx_header header;

	/*
	 * When set, the WiLink transmits the frames with a short preamble and
	 * when cleared, the WiLink transmits the frames with a long preamble.
	 */
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	u8 role_id;
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	u8 preamble;
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	u8 padding[2];
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} __packed;
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enum acx_ctsprotect_type {
	CTSPROTECT_DISABLE = 0,
	CTSPROTECT_ENABLE = 1
};

struct acx_ctsprotect {
	struct acx_header header;
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	u8 role_id;
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	u8 ctsprotect;
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	u8 padding[2];
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} __packed;
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struct acx_tx_statistics {
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	__le32 internal_desc_overflow;
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}  __packed;
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struct acx_rx_statistics {
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	__le32 out_of_mem;
	__le32 hdr_overflow;
	__le32 hw_stuck;
	__le32 dropped;
	__le32 fcs_err;
	__le32 xfr_hint_trig;
	__le32 path_reset;
	__le32 reset_counter;
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} __packed;
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struct acx_dma_statistics {
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	__le32 rx_requested;
	__le32 rx_errors;
	__le32 tx_requested;
	__le32 tx_errors;
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}  __packed;
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struct acx_isr_statistics {
	/* host command complete */
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	__le32 cmd_cmplt;
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	/* fiqisr() */
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	__le32 fiqs;
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	/* (INT_STS_ND & INT_TRIG_RX_HEADER) */
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	__le32 rx_headers;
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	/* (INT_STS_ND & INT_TRIG_RX_CMPLT) */
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	__le32 rx_completes;
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	/* (INT_STS_ND & INT_TRIG_NO_RX_BUF) */
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	__le32 rx_mem_overflow;
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	/* (INT_STS_ND & INT_TRIG_S_RX_RDY) */
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	__le32 rx_rdys;
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	/* irqisr() */
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	__le32 irqs;
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	/* (INT_STS_ND & INT_TRIG_TX_PROC) */
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	__le32 tx_procs;
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	/* (INT_STS_ND & INT_TRIG_DECRYPT_DONE) */
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	__le32 decrypt_done;
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	/* (INT_STS_ND & INT_TRIG_DMA0) */
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	__le32 dma0_done;
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	/* (INT_STS_ND & INT_TRIG_DMA1) */
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	__le32 dma1_done;
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	/* (INT_STS_ND & INT_TRIG_TX_EXC_CMPLT) */
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	__le32 tx_exch_complete;
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	/* (INT_STS_ND & INT_TRIG_COMMAND) */
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	__le32 commands;
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	/* (INT_STS_ND & INT_TRIG_RX_PROC) */
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	__le32 rx_procs;
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	/* (INT_STS_ND & INT_TRIG_PM_802) */
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	__le32 hw_pm_mode_changes;
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	/* (INT_STS_ND & INT_TRIG_ACKNOWLEDGE) */
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	__le32 host_acknowledges;
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	/* (INT_STS_ND & INT_TRIG_PM_PCI) */
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	__le32 pci_pm;
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	/* (INT_STS_ND & INT_TRIG_ACM_WAKEUP) */
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	__le32 wakeups;
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	/* (INT_STS_ND & INT_TRIG_LOW_RSSI) */
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	__le32 low_rssi;
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} __packed;
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struct acx_wep_statistics {
	/* WEP address keys configured */
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	__le32 addr_key_count;
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	/* default keys configured */
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	__le32 default_key_count;
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	__le32 reserved;
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	/* number of times that WEP key not found on lookup */
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	__le32 key_not_found;
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	/* number of times that WEP key decryption failed */
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	__le32 decrypt_fail;
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	/* WEP packets decrypted */
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	__le32 packets;
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	/* WEP decrypt interrupts */
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	__le32 interrupt;
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} __packed;
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#define ACX_MISSED_BEACONS_SPREAD 10

struct acx_pwr_statistics {
	/* the amount of enters into power save mode (both PD & ELP) */
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	__le32 ps_enter;
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	/* the amount of enters into ELP mode */
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	__le32 elp_enter;
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	/* the amount of missing beacon interrupts to the host */
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	__le32 missing_bcns;
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	/* the amount of wake on host-access times */
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	__le32 wake_on_host;
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	/* the amount of wake on timer-expire */
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	__le32 wake_on_timer_exp;
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	/* the number of packets that were transmitted with PS bit set */
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	__le32 tx_with_ps;
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	/* the number of packets that were transmitted with PS bit clear */
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	__le32 tx_without_ps;
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	/* the number of received beacons */
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	__le32 rcvd_beacons;
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	/* the number of entering into PowerOn (power save off) */
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	__le32 power_save_off;
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	/* the number of entries into power save mode */
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	__le16 enable_ps;
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	/*
	 * the number of exits from power save, not including failed PS
	 * transitions
	 */
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	__le16 disable_ps;
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	/*
	 * the number of times the TSF counter was adjusted because
	 * of drift
	 */
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	__le32 fix_tsf_ps;
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	/* Gives statistics about the spread continuous missed beacons.
	 * The 16 LSB are dedicated for the PS mode.
	 * The 16 MSB are dedicated for the PS mode.
	 * cont_miss_bcns_spread[0] - single missed beacon.
	 * cont_miss_bcns_spread[1] - two continuous missed beacons.
	 * cont_miss_bcns_spread[2] - three continuous missed beacons.
	 * ...
	 * cont_miss_bcns_spread[9] - ten and more continuous missed beacons.
	*/
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	__le32 cont_miss_bcns_spread[ACX_MISSED_BEACONS_SPREAD];
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	/* the number of beacons in awake mode */
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	__le32 rcvd_awake_beacons;
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} __packed;
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struct acx_mic_statistics {
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	__le32 rx_pkts;
	__le32 calc_failure;
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} __packed;
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struct acx_aes_statistics {
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	__le32 encrypt_fail;
	__le32 decrypt_fail;
	__le32 encrypt_packets;
	__le32 decrypt_packets;
	__le32 encrypt_interrupt;
	__le32 decrypt_interrupt;
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} __packed;
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struct acx_event_statistics {
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	__le32 heart_beat;
	__le32 calibration;
	__le32 rx_mismatch;
	__le32 rx_mem_empty;
	__le32 rx_pool;
	__le32 oom_late;
	__le32 phy_transmit_error;
	__le32 tx_stuck;
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} __packed;
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struct acx_ps_statistics {
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	__le32 pspoll_timeouts;
	__le32 upsd_timeouts;
	__le32 upsd_max_sptime;
	__le32 upsd_max_apturn;
	__le32 pspoll_max_apturn;
	__le32 pspoll_utilization;
	__le32 upsd_utilization;
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} __packed;
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struct acx_rxpipe_statistics {
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	__le32 rx_prep_beacon_drop;
	__le32 descr_host_int_trig_rx_data;
	__le32 beacon_buffer_thres_host_int_trig_rx_data;
	__le32 missed_beacon_host_int_trig_rx_data;
	__le32 tx_xfr_host_int_trig_rx_data;
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} __packed;
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struct acx_statistics {
	struct acx_header header;

	struct acx_tx_statistics tx;
	struct acx_rx_statistics rx;
	struct acx_dma_statistics dma;
	struct acx_isr_statistics isr;
	struct acx_wep_statistics wep;
	struct acx_pwr_statistics pwr;
	struct acx_aes_statistics aes;
	struct acx_mic_statistics mic;
	struct acx_event_statistics event;
	struct acx_ps_statistics ps;
	struct acx_rxpipe_statistics rxpipe;
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} __packed;
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struct acx_rate_class {
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	__le32 enabled_rates;
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	u8 short_retry_limit;
	u8 long_retry_limit;
	u8 aflags;
	u8 reserved;
};

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#define ACX_TX_BASIC_RATE      0
#define ACX_TX_AP_FULL_RATE    1
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#define ACX_TX_BASIC_RATE_P2P  2
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#define ACX_TX_AP_MODE_MGMT_RATE 4
#define ACX_TX_AP_MODE_BCST_RATE 5
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struct acx_rate_policy {
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	struct acx_header header;

	__le32 rate_policy_idx;
	struct acx_rate_class rate_policy;
} __packed;

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struct acx_ac_cfg {
	struct acx_header header;
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	u8 role_id;
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	u8 ac;
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	u8 aifsn;
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	u8 cw_min;
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	__le16 cw_max;
	__le16 tx_op_limit;
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} __packed;
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struct acx_tid_config {
	struct acx_header header;
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	u8 role_id;
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	u8 queue_id;
	u8 channel_type;
	u8 tsid;
	u8 ps_scheme;
	u8 ack_policy;
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	u8 padding[2];
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	__le32 apsd_conf[2];
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} __packed;
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struct acx_frag_threshold {
	struct acx_header header;
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	__le16 frag_threshold;
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	u8 padding[2];
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} __packed;
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struct acx_tx_config_options {
	struct acx_header header;
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	__le16 tx_compl_timeout;     /* msec */
	__le16 tx_compl_threshold;   /* number of packets */
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} __packed;
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703
struct wl12xx_acx_config_memory {
704 705 706 707 708 709 710 711 712 713 714
	struct acx_header header;

	u8 rx_mem_block_num;
	u8 tx_min_mem_block_num;
	u8 num_stations;
	u8 num_ssid_profiles;
	__le32 total_tx_descriptors;
	u8 dyn_mem_enable;
	u8 tx_free_req;
	u8 rx_free_req;
	u8 tx_min;
715 716
	u8 fwlog_blocks;
	u8 padding[3];
717 718
} __packed;

719 720 721
struct wl1271_acx_mem_map {
	struct acx_header header;

722 723
	__le32 code_start;
	__le32 code_end;
724

725 726
	__le32 wep_defkey_start;
	__le32 wep_defkey_end;
727

728 729
	__le32 sta_table_start;
	__le32 sta_table_end;
730

731 732
	__le32 packet_template_start;
	__le32 packet_template_end;
733 734

	/* Address of the TX result interface (control block) */
735 736
	__le32 tx_result;
	__le32 tx_result_queue_start;
737

738 739
	__le32 queue_memory_start;
	__le32 queue_memory_end;
740

741 742
	__le32 packet_memory_pool_start;
	__le32 packet_memory_pool_end;
743

744 745
	__le32 debug_buffer1_start;
	__le32 debug_buffer1_end;
746

747 748
	__le32 debug_buffer2_start;
	__le32 debug_buffer2_end;
749 750

	/* Number of blocks FW allocated for TX packets */
751
	__le32 num_tx_mem_blocks;
752 753

	/* Number of blocks FW allocated for RX packets */
754
	__le32 num_rx_mem_blocks;
755 756 757 758

	/* the following 4 fields are valid in SLAVE mode only */
	u8 *tx_cbuf;
	u8 *rx_cbuf;
759 760
	__le32 rx_ctrl;
	__le32 tx_ctrl;
761
} __packed;
762 763 764 765

struct wl1271_acx_rx_config_opt {
	struct acx_header header;

766 767 768
	__le16 mblk_threshold;
	__le16 threshold;
	__le16 timeout;
769 770
	u8 queue_type;
	u8 reserved;
771
} __packed;
772

773 774 775 776

struct wl1271_acx_bet_enable {
	struct acx_header header;

777
	u8 role_id;
778 779
	u8 enable;
	u8 max_consecutive;
780
	u8 padding[1];
781
} __packed;
782

783 784 785
#define ACX_IPV4_VERSION 4
#define ACX_IPV6_VERSION 6
#define ACX_IPV4_ADDR_SIZE 4
786 787 788 789 790

/* bitmap of enabled arp_filter features */
#define ACX_ARP_FILTER_ARP_FILTERING	BIT(0)
#define ACX_ARP_FILTER_AUTO_ARP		BIT(1)

791 792
struct wl1271_acx_arp_filter {
	struct acx_header header;
793
	u8 role_id;
794
	u8 version;         /* ACX_IPV4_VERSION, ACX_IPV6_VERSION */
795
	u8 enable;          /* bitmap of enabled ARP filtering features */
796
	u8 padding[1];
797 798 799 800
	u8 address[16];     /* The configured device IP address - all ARP
			       requests directed to this IP address will pass
			       through. For IPv4, the first four bytes are
			       used. */
801
} __packed;
802

803 804 805 806 807 808
struct wl1271_acx_pm_config {
	struct acx_header header;

	__le32 host_clk_settling_time;
	u8 host_fast_wakeup_support;
	u8 padding[3];
809
} __packed;
810

811 812 813
struct wl1271_acx_keep_alive_mode {
	struct acx_header header;

814
	u8 role_id;
815
	u8 enabled;
816
	u8 padding[2];
817
} __packed;
818 819 820 821 822 823 824 825 826 827 828 829 830 831

enum {
	ACX_KEEP_ALIVE_NO_TX = 0,
	ACX_KEEP_ALIVE_PERIOD_ONLY
};

enum {
	ACX_KEEP_ALIVE_TPL_INVALID = 0,
	ACX_KEEP_ALIVE_TPL_VALID
};

struct wl1271_acx_keep_alive_config {
	struct acx_header header;

832
	u8 role_id;
833 834 835
	u8 index;
	u8 tpl_validation;
	u8 trigger;
836
	__le32 period;
837
} __packed;
838

839 840 841 842 843 844 845 846 847 848
#define HOST_IF_CFG_RX_FIFO_ENABLE     BIT(0)
#define HOST_IF_CFG_TX_EXTRA_BLKS_SWAP BIT(1)
#define HOST_IF_CFG_TX_PAD_TO_SDIO_BLK BIT(3)

struct wl1271_acx_host_config_bitmap {
	struct acx_header header;

	__le32 host_cfg_bitmap;
} __packed;

849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879
enum {
	WL1271_ACX_TRIG_TYPE_LEVEL = 0,
	WL1271_ACX_TRIG_TYPE_EDGE,
};

enum {
	WL1271_ACX_TRIG_DIR_LOW = 0,
	WL1271_ACX_TRIG_DIR_HIGH,
	WL1271_ACX_TRIG_DIR_BIDIR,
};

enum {
	WL1271_ACX_TRIG_ENABLE = 1,
	WL1271_ACX_TRIG_DISABLE,
};

enum {
	WL1271_ACX_TRIG_METRIC_RSSI_BEACON = 0,
	WL1271_ACX_TRIG_METRIC_RSSI_DATA,
	WL1271_ACX_TRIG_METRIC_SNR_BEACON,
	WL1271_ACX_TRIG_METRIC_SNR_DATA,
};

enum {
	WL1271_ACX_TRIG_IDX_RSSI = 0,
	WL1271_ACX_TRIG_COUNT = 8,
};

struct wl1271_acx_rssi_snr_trigger {
	struct acx_header header;

880
	u8 role_id;
881 882 883
	u8 metric;
	u8 type;
	u8 dir;
884 885
	__le16 threshold;
	__le16 pacing; /* 0 - 60000 ms */
886 887 888
	u8 hysteresis;
	u8 index;
	u8 enable;
889
	u8 padding[1];
890 891 892 893 894
};

struct wl1271_acx_rssi_snr_avg_weights {
	struct acx_header header;

895 896
	u8 role_id;
	u8 padding[3];
897 898 899 900 901 902
	u8 rssi_beacon;
	u8 rssi_data;
	u8 snr_beacon;
	u8 snr_data;
};

903 904 905 906

/* special capability bit (not employed by the 802.11n spec) */
#define WL12XX_HT_CAP_HT_OPERATION BIT(16)

907 908 909 910 911 912 913 914
/*
 * ACX_PEER_HT_CAP
 * Configure HT capabilities - declare the capabilities of the peer
 * we are connected to.
 */
struct wl1271_acx_ht_capabilities {
	struct acx_header header;

915
	/* bitmask of capability bits supported by the peer */
916 917
	__le32 ht_capabilites;

918 919
	/* Indicates to which link these capabilities apply. */
	u8 hlid;
920 921 922 923 924 925 926 927 928

	/*
	 * This the maximum A-MPDU length supported by the AP. The FW may not
	 * exceed this length when sending A-MPDUs
	 */
	u8 ampdu_max_length;

	/* This is the minimal spacing required when sending A-MPDUs to the AP*/
	u8 ampdu_min_spacing;
929 930

	u8 padding;
931 932 933 934 935 936 937 938 939
} __packed;

/*
 * ACX_HT_BSS_OPERATION
 * Configure HT capabilities - AP rules for behavior in the BSS.
 */
struct wl1271_acx_ht_information {
	struct acx_header header;

940 941
	u8 role_id;

942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962
	/* Values: 0 - RIFS not allowed, 1 - RIFS allowed */
	u8 rifs_mode;

	/* Values: 0 - 3 like in spec */
	u8 ht_protection;

	/* Values: 0 - GF protection not required, 1 - GF protection required */
	u8 gf_protection;

	/*Values: 0 - TX Burst limit not required, 1 - TX Burst Limit required*/
	u8 ht_tx_burst_limit;

	/*
	 * Values: 0 - Dual CTS protection not required,
	 *         1 - Dual CTS Protection required
	 * Note: When this value is set to 1 FW will protect all TXOP with RTS
	 * frame and will not use CTS-to-self regardless of the value of the
	 * ACX_CTS_PROTECTION information element
	 */
	u8 dual_cts_protection;

963
	u8 padding[2];
964 965
} __packed;

966
#define RX_BA_MAX_SESSIONS 2
967

968
struct wl1271_acx_ba_initiator_policy {
969
	struct acx_header header;
970 971

	/* Specifies role Id, Range 0-7, 0xFF means ANY role. */
972
	u8 role_id;
973

974
	/*
975 976
	 * Per TID setting for allowing TX BA. Set a bit to 1 to allow
	 * TX BA sessions for the corresponding TID.
977
	 */
978
	u8 tid_bitmap;
979 980

	/* Windows size in number of packets */
981
	u8 win_size;
982

983
	u8 padding1[1];
984

985 986
	/* As initiator inactivity timeout in time units(TU) of 1024us */
	u16 inactivity_timeout;
987

988
	u8 padding[2];
989 990
} __packed;

991 992 993
struct wl1271_acx_ba_receiver_setup {
	struct acx_header header;

994 995
	/* Specifies link id, range 0-31 */
	u8 hlid;
996 997 998 999 1000 1001

	u8 tid;

	u8 enable;

	/* Windows size in number of packets */
1002
	u8 win_size;
1003 1004 1005

	/* BA session starting sequence number.  RANGE 0-FFF */
	u16 ssn;
1006 1007

	u8 padding[2];
1008 1009
} __packed;

1010 1011 1012 1013 1014 1015 1016 1017 1018
struct wl1271_acx_fw_tsf_information {
	struct acx_header header;

	__le32 current_tsf_high;
	__le32 current_tsf_low;
	__le32 last_bttt_high;
	__le32 last_tbtt_low;
	u8 last_dtim_count;
	u8 padding[3];
1019
} __packed;
1020

1021 1022 1023
struct wl1271_acx_ps_rx_streaming {
	struct acx_header header;

1024
	u8 role_id;
1025 1026 1027 1028 1029 1030 1031 1032
	u8 tid;
	u8 enable;

	/* interval between triggers (10-100 msec) */
	u8 period;

	/* timeout before first trigger (0-200 msec) */
	u8 timeout;
1033
	u8 padding[3];
1034 1035
} __packed;

1036
struct wl1271_acx_ap_max_tx_retry {
1037 1038
	struct acx_header header;

1039 1040 1041
	u8 role_id;
	u8 padding_1;

1042 1043 1044 1045 1046 1047 1048
	/*
	 * the number of frames transmission failures before
	 * issuing the aging event.
	 */
	__le16 max_tx_retry;
} __packed;

1049 1050 1051 1052 1053 1054 1055 1056 1057
struct wl1271_acx_config_ps {
	struct acx_header header;

	u8 exit_retries;
	u8 enter_retries;
	u8 padding[2];
	__le32 null_data_rate;
} __packed;

1058 1059 1060 1061 1062 1063 1064
struct wl1271_acx_inconnection_sta {
	struct acx_header header;

	u8 addr[ETH_ALEN];
	u8 padding1[2];
} __packed;

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1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123
/*
 * ACX_FM_COEX_CFG
 * set the FM co-existence parameters.
 */
struct wl1271_acx_fm_coex {
	struct acx_header header;
	/* enable(1) / disable(0) the FM Coex feature */
	u8 enable;
	/*
	 * Swallow period used in COEX PLL swallowing mechanism.
	 * 0xFF = use FW default
	 */
	u8 swallow_period;
	/*
	 * The N divider used in COEX PLL swallowing mechanism for Fref of
	 * 38.4/19.2 Mhz. 0xFF = use FW default
	 */
	u8 n_divider_fref_set_1;
	/*
	 * The N divider used in COEX PLL swallowing mechanism for Fref of
	 * 26/52 Mhz. 0xFF = use FW default
	 */
	u8 n_divider_fref_set_2;
	/*
	 * The M divider used in COEX PLL swallowing mechanism for Fref of
	 * 38.4/19.2 Mhz. 0xFFFF = use FW default
	 */
	__le16 m_divider_fref_set_1;
	/*
	 * The M divider used in COEX PLL swallowing mechanism for Fref of
	 * 26/52 Mhz. 0xFFFF = use FW default
	 */
	__le16 m_divider_fref_set_2;
	/*
	 * The time duration in uSec required for COEX PLL to stabilize.
	 * 0xFFFFFFFF = use FW default
	 */
	__le32 coex_pll_stabilization_time;
	/*
	 * The time duration in uSec required for LDO to stabilize.
	 * 0xFFFFFFFF = use FW default
	 */
	__le16 ldo_stabilization_time;
	/*
	 * The disturbed frequency band margin around the disturbed frequency
	 * center (single sided).
	 * For example, if 2 is configured, the following channels will be
	 * considered disturbed channel:
	 *   80 +- 0.1 MHz, 91 +- 0.1 MHz, 98 +- 0.1 MHz, 102 +- 0.1 MH
	 * 0xFF = use FW default
	 */
	u8 fm_disturbed_band_margin;
	/*
	 * The swallow clock difference of the swallowing mechanism.
	 * 0xFF = use FW default
	 */
	u8 swallow_clk_diff;
} __packed;

1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147
#define ACX_RATE_MGMT_ALL_PARAMS 0xff
struct wl12xx_acx_set_rate_mgmt_params {
	struct acx_header header;

	u8 index; /* 0xff to configure all params */
	u8 padding1;
	__le16 rate_retry_score;
	__le16 per_add;
	__le16 per_th1;
	__le16 per_th2;
	__le16 max_per;
	u8 inverse_curiosity_factor;
	u8 tx_fail_low_th;
	u8 tx_fail_high_th;
	u8 per_alpha_shift;
	u8 per_add_shift;
	u8 per_beta1_shift;
	u8 per_beta2_shift;
	u8 rate_check_up;
	u8 rate_check_down;
	u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES];
	u8 padding2[2];
} __packed;

1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164
struct wl12xx_acx_config_hangover {
	struct acx_header header;

	__le32 recover_time;
	u8 hangover_period;
	u8 dynamic_mode;
	u8 early_termination_mode;
	u8 max_period;
	u8 min_period;
	u8 increase_delta;
	u8 decrease_delta;
	u8 quiet_time;
	u8 increase_time;
	u8 window_size;
	u8 padding[2];
} __packed;

1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187 1188 1189
enum {
	ACX_WAKE_UP_CONDITIONS      = 0x0002,
	ACX_MEM_CFG                 = 0x0003,
	ACX_SLOT                    = 0x0004,
	ACX_AC_CFG                  = 0x0007,
	ACX_MEM_MAP                 = 0x0008,
	ACX_AID                     = 0x000A,
	ACX_MEDIUM_USAGE            = 0x000F,
	ACX_TX_QUEUE_CFG            = 0x0011, /* FIXME: only used by wl1251 */
	ACX_STATISTICS              = 0x0013, /* Debug API */
	ACX_PWR_CONSUMPTION_STATISTICS = 0x0014,
	ACX_FEATURE_CFG             = 0x0015,
	ACX_TID_CFG                 = 0x001A,
	ACX_PS_RX_STREAMING         = 0x001B,
	ACX_BEACON_FILTER_OPT       = 0x001F,
	ACX_NOISE_HIST              = 0x0021,
	ACX_HDK_VERSION             = 0x0022, /* ??? */
	ACX_PD_THRESHOLD            = 0x0023,
	ACX_TX_CONFIG_OPT           = 0x0024,
	ACX_CCA_THRESHOLD           = 0x0025,
	ACX_EVENT_MBOX_MASK         = 0x0026,
	ACX_CONN_MONIT_PARAMS       = 0x002D,
	ACX_BCN_DTIM_OPTIONS        = 0x0031,
	ACX_SG_ENABLE               = 0x0032,
	ACX_SG_CFG                  = 0x0033,
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	ACX_FM_COEX_CFG             = 0x0034,
1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209
	ACX_BEACON_FILTER_TABLE     = 0x0038,
	ACX_ARP_IP_FILTER           = 0x0039,
	ACX_ROAMING_STATISTICS_TBL  = 0x003B,
	ACX_RATE_POLICY             = 0x003D,
	ACX_CTS_PROTECTION          = 0x003E,
	ACX_SLEEP_AUTH              = 0x003F,
	ACX_PREAMBLE_TYPE	    = 0x0040,
	ACX_ERROR_CNT               = 0x0041,
	ACX_IBSS_FILTER		    = 0x0044,
	ACX_SERVICE_PERIOD_TIMEOUT  = 0x0045,
	ACX_TSF_INFO                = 0x0046,
	ACX_CONFIG_PS_WMM           = 0x0049,
	ACX_ENABLE_RX_DATA_FILTER   = 0x004A,
	ACX_SET_RX_DATA_FILTER      = 0x004B,
	ACX_GET_DATA_FILTER_STATISTICS = 0x004C,
	ACX_RX_CONFIG_OPT           = 0x004E,
	ACX_FRAG_CFG                = 0x004F,
	ACX_BET_ENABLE              = 0x0050,
	ACX_RSSI_SNR_TRIGGER        = 0x0051,
1210
	ACX_RSSI_SNR_WEIGHTS        = 0x0052,
1211
	ACX_KEEP_ALIVE_MODE         = 0x0053,
1212
	ACX_SET_KEEP_ALIVE_CONFIG   = 0x0054,
1213
	ACX_BA_SESSION_INIT_POLICY  = 0x0055,
1214
	ACX_BA_SESSION_RX_SETUP     = 0x0056,
1215 1216 1217
	ACX_PEER_HT_CAP             = 0x0057,
	ACX_HT_BSS_OPERATION        = 0x0058,
	ACX_COEX_ACTIVITY           = 0x0059,
1218 1219 1220
	ACX_BURST_MODE              = 0x005C,
	ACX_SET_RATE_MGMT_PARAMS    = 0x005D,
	ACX_SET_RATE_ADAPT_PARAMS   = 0x0060,
1221
	ACX_SET_DCO_ITRIM_PARAMS    = 0x0061,
1222 1223
	ACX_GEN_FW_CMD              = 0x0070,
	ACX_HOST_IF_CFG_BITMAP      = 0x0071,
1224
	ACX_MAX_TX_FAILURE          = 0x0072,
1225
	ACX_UPDATE_INCONNECTION_STA_LIST = 0x0073,
1226 1227 1228 1229 1230
	DOT11_RX_MSDU_LIFE_TIME     = 0x1004,
	DOT11_CUR_TX_PWR            = 0x100D,
	DOT11_RX_DOT11_MODE         = 0x1012,
	DOT11_RTS_THRESHOLD         = 0x1013,
	DOT11_GROUP_ADDRESS_TBL     = 0x1014,
1231
	ACX_PM_CONFIG               = 0x1016,
1232
	ACX_CONFIG_PS               = 0x1017,
1233
	ACX_CONFIG_HANGOVER         = 0x1018,
1234 1235 1236
};


1237 1238
int wl1271_acx_wake_up_conditions(struct wl1271 *wl,
				  struct wl12xx_vif *wlvif);
1239
int wl1271_acx_sleep_auth(struct wl1271 *wl, u8 sleep_auth);
1240 1241 1242
int wl1271_acx_tx_power(struct wl1271 *wl, struct wl12xx_vif *wlvif,
			int power);
int wl1271_acx_feature_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1243 1244
int wl1271_acx_mem_map(struct wl1271 *wl,
		       struct acx_header *mem_map, size_t len);
1245
int wl1271_acx_rx_msdu_life_time(struct wl1271 *wl);
1246
int wl1271_acx_pd_threshold(struct wl1271 *wl);
1247 1248 1249 1250 1251 1252 1253 1254
int wl1271_acx_slot(struct wl1271 *wl, struct wl12xx_vif *wlvif,
		    enum acx_slot_type slot_time);
int wl1271_acx_group_address_tbl(struct wl1271 *wl, struct wl12xx_vif *wlvif,
				 bool enable, void *mc_list, u32 mc_list_len);
int wl1271_acx_service_period_timeout(struct wl1271 *wl,
				      struct wl12xx_vif *wlvif);
int wl1271_acx_rts_threshold(struct wl1271 *wl, struct wl12xx_vif *wlvif,
			     u32 rts_threshold);
1255
int wl1271_acx_dco_itrim_params(struct wl1271 *wl);
1256 1257 1258 1259 1260 1261
int wl1271_acx_beacon_filter_opt(struct wl1271 *wl, struct wl12xx_vif *wlvif,
				 bool enable_filter);
int wl1271_acx_beacon_filter_table(struct wl1271 *wl,
				   struct wl12xx_vif *wlvif);
int wl1271_acx_conn_monit_params(struct wl1271 *wl, struct wl12xx_vif *wlvif,
				 bool enable);
1262
int wl1271_acx_sg_enable(struct wl1271 *wl, bool enable);
1263
int wl12xx_acx_sg_cfg(struct wl1271 *wl);
1264
int wl1271_acx_cca_threshold(struct wl1271 *wl);
1265 1266
int wl1271_acx_bcn_dtim_options(struct wl1271 *wl, struct wl12xx_vif *wlvif);
int wl1271_acx_aid(struct wl1271 *wl, struct wl12xx_vif *wlvif, u16 aid);
1267
int wl1271_acx_event_mbox_mask(struct wl1271 *wl, u32 event_mask);
1268 1269 1270
int wl1271_acx_set_preamble(struct wl1271 *wl, struct wl12xx_vif *wlvif,
			    enum acx_preamble_type preamble);
int wl1271_acx_cts_protect(struct wl1271 *wl, struct wl12xx_vif *wlvif,
1271
			   enum acx_ctsprotect_type ctsprotect);
1272
int wl1271_acx_statistics(struct wl1271 *wl, struct acx_statistics *stats);
1273
int wl1271_acx_sta_rate_policies(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1274 1275
int wl1271_acx_ap_rate_policy(struct wl1271 *wl, struct conf_tx_rate_class *c,
		      u8 idx);
1276 1277 1278 1279
int wl1271_acx_ac_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif,
		      u8 ac, u8 cw_min, u16 cw_max, u8 aifsn, u16 txop);
int wl1271_acx_tid_cfg(struct wl1271 *wl, struct wl12xx_vif *wlvif,
		       u8 queue_id, u8 channel_type,
1280 1281
		       u8 tsid, u8 ps_scheme, u8 ack_policy,
		       u32 apsd_conf0, u32 apsd_conf1);
1282
int wl1271_acx_frag_threshold(struct wl1271 *wl, u32 frag_threshold);
1283
int wl1271_acx_tx_config_options(struct wl1271 *wl);
1284
int wl12xx_acx_mem_cfg(struct wl1271 *wl);
1285
int wl1271_acx_init_mem_config(struct wl1271 *wl);
1286
int wl1271_acx_host_if_cfg_bitmap(struct wl1271 *wl, u32 host_cfg_bitmap);
1287
int wl1271_acx_init_rx_interrupt(struct wl1271 *wl);
1288
int wl1271_acx_smart_reflex(struct wl1271 *wl);
1289 1290 1291 1292
int wl1271_acx_bet_enable(struct wl1271 *wl, struct wl12xx_vif *wlvif,
			  bool enable);
int wl1271_acx_arp_ip_filter(struct wl1271 *wl, struct wl12xx_vif *wlvif,
			     u8 enable, __be32 address);
1293
int wl1271_acx_pm_config(struct wl1271 *wl);
1294 1295 1296 1297 1298 1299 1300 1301
int wl1271_acx_keep_alive_mode(struct wl1271 *wl, struct wl12xx_vif *vif,
			       bool enable);
int wl1271_acx_keep_alive_config(struct wl1271 *wl, struct wl12xx_vif *wlvif,
				 u8 index, u8 tpl_valid);
int wl1271_acx_rssi_snr_trigger(struct wl1271 *wl, struct wl12xx_vif *wlvif,
				bool enable, s16 thold, u8 hyst);
int wl1271_acx_rssi_snr_avg_weights(struct wl1271 *wl,
				    struct wl12xx_vif *wlvif);
1302 1303
int wl1271_acx_set_ht_capabilities(struct wl1271 *wl,
				    struct ieee80211_sta_ht_cap *ht_cap,
1304
				    bool allow_ht_operation, u8 hlid);
1305
int wl1271_acx_set_ht_information(struct wl1271 *wl,
1306
				   struct wl12xx_vif *wlvif,
1307
				   u16 ht_operation_mode);
1308 1309
int wl12xx_acx_set_ba_initiator_policy(struct wl1271 *wl,
				       struct wl12xx_vif *wlvif);
1310 1311
int wl12xx_acx_set_ba_receiver_session(struct wl1271 *wl, u8 tid_index,
				       u16 ssn, bool enable, u8 peer_hlid);
1312
int wl1271_acx_tsf_info(struct wl1271 *wl, u64 *mactime);
1313
int wl1271_acx_ps_rx_streaming(struct wl1271 *wl, bool enable);
1314
int wl1271_acx_ap_max_tx_retry(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1315
int wl12xx_acx_config_ps(struct wl1271 *wl, struct wl12xx_vif *wlvif);
1316
int wl1271_acx_set_inconnection_sta(struct wl1271 *wl, u8 *addr);
S
Shahar Levi 已提交
1317
int wl1271_acx_fm_coex(struct wl1271 *wl);
1318
int wl12xx_acx_set_rate_mgmt_params(struct wl1271 *wl);
1319
int wl12xx_acx_config_hangover(struct wl1271 *wl);
1320 1321

#endif /* __WL1271_ACX_H__ */
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