sata_promise.c 26.5 KB
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/*
 *  sata_promise.c - Promise SATA
 *
 *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2003-2004 Red Hat, Inc.
 *
 *
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 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/DocBook/libata.*
 *
 *  Hardware information only available under NDA.
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 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
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#include <linux/device.h>
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#include <scsi/scsi.h>
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#include <scsi/scsi_host.h>
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#include <scsi/scsi_cmnd.h>
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#include <linux/libata.h>
#include "sata_promise.h"

#define DRV_NAME	"sata_promise"
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#define DRV_VERSION	"2.05"
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enum {
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	PDC_MAX_PORTS		= 4,
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	PDC_MMIO_BAR		= 3,

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	/* register offsets */
	PDC_FEATURE		= 0x04, /* Feature/Error reg (per port) */
	PDC_SECTOR_COUNT	= 0x08, /* Sector count reg (per port) */
	PDC_SECTOR_NUMBER	= 0x0C, /* Sector number reg (per port) */
	PDC_CYLINDER_LOW	= 0x10, /* Cylinder low reg (per port) */
	PDC_CYLINDER_HIGH	= 0x14, /* Cylinder high reg (per port) */
	PDC_DEVICE		= 0x18, /* Device/Head reg (per port) */
	PDC_COMMAND		= 0x1C, /* Command/status reg (per port) */
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	PDC_ALTSTATUS		= 0x38, /* Alternate-status/device-control reg (per port) */
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	PDC_PKT_SUBMIT		= 0x40, /* Command packet pointer addr */
	PDC_INT_SEQMASK		= 0x40,	/* Mask of asserted SEQ INTs */
	PDC_FLASH_CTL		= 0x44, /* Flash control register */
	PDC_GLOBAL_CTL		= 0x48, /* Global control/status (per port) */
	PDC_CTLSTAT		= 0x60,	/* IDE control and status (per port) */
	PDC_SATA_PLUG_CSR	= 0x6C, /* SATA Plug control/status reg */
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	PDC2_SATA_PLUG_CSR	= 0x60, /* SATAII Plug control/status reg */
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	PDC_TBG_MODE		= 0x41C, /* TBG mode (not SATAII) */
	PDC_SLEW_CTL		= 0x470, /* slew rate control reg (not SATAII) */
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	/* PDC_GLOBAL_CTL bit definitions */
	PDC_PH_ERR		= (1 <<  8), /* PCI error while loading packet */
	PDC_SH_ERR		= (1 <<  9), /* PCI error while loading S/G table */
	PDC_DH_ERR		= (1 << 10), /* PCI error while loading data */
	PDC2_HTO_ERR		= (1 << 12), /* host bus timeout */
	PDC2_ATA_HBA_ERR	= (1 << 13), /* error during SATA DATA FIS transmission */
	PDC2_ATA_DMA_CNT_ERR	= (1 << 14), /* DMA DATA FIS size differs from S/G count */
	PDC_OVERRUN_ERR		= (1 << 19), /* S/G byte count larger than HD requires */
	PDC_UNDERRUN_ERR	= (1 << 20), /* S/G byte count less than HD requires */
	PDC_DRIVE_ERR		= (1 << 21), /* drive error */
	PDC_PCI_SYS_ERR		= (1 << 22), /* PCI system error */
	PDC1_PCI_PARITY_ERR	= (1 << 23), /* PCI parity error (from SATA150 driver) */
	PDC1_ERR_MASK		= PDC1_PCI_PARITY_ERR,
	PDC2_ERR_MASK		= PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR,
	PDC_ERR_MASK		= (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC_OVERRUN_ERR
				   | PDC_UNDERRUN_ERR | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR
				   | PDC1_ERR_MASK | PDC2_ERR_MASK),
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	board_2037x		= 0,	/* FastTrak S150 TX2plus */
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	board_2037x_pata	= 1,	/* FastTrak S150 TX2plus PATA port */
	board_20319		= 2,	/* FastTrak S150 TX4 */
	board_20619		= 3,	/* FastTrak TX4000 */
	board_2057x		= 4,	/* SATAII150 Tx2plus */
	board_2057x_pata	= 5,	/* SATAII150 Tx2plus */
	board_40518		= 6,	/* SATAII150 Tx4 */
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	PDC_HAS_PATA		= (1 << 1), /* PDC20375/20575 has PATA */
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	/* Sequence counter control registers bit definitions */
	PDC_SEQCNTRL_INT_MASK	= (1 << 5), /* Sequence Interrupt Mask */

	/* Feature register values */
	PDC_FEATURE_ATAPI_PIO	= 0x00, /* ATAPI data xfer by PIO */
	PDC_FEATURE_ATAPI_DMA	= 0x01, /* ATAPI data xfer by DMA */

	/* Device/Head register values */
	PDC_DEVICE_SATA		= 0xE0, /* Device/Head value for SATA devices */

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	/* PDC_CTLSTAT bit definitions */
	PDC_DMA_ENABLE		= (1 << 7),
	PDC_IRQ_DISABLE		= (1 << 10),
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	PDC_RESET		= (1 << 11), /* HDMA reset */
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	PDC_COMMON_FLAGS	= ATA_FLAG_NO_LEGACY |
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				  ATA_FLAG_MMIO |
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				  ATA_FLAG_PIO_POLLING,
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	/* ap->flags bits */
	PDC_FLAG_GEN_II		= (1 << 24),
	PDC_FLAG_SATA_PATA	= (1 << 25), /* supports SATA + PATA */
	PDC_FLAG_4_PORTS	= (1 << 26), /* 4 ports */
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};


struct pdc_port_priv {
	u8			*pkt;
	dma_addr_t		pkt_dma;
};

static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
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static int pdc_common_port_start(struct ata_port *ap);
static int pdc_sata_port_start(struct ata_port *ap);
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static void pdc_qc_prep(struct ata_queued_cmd *qc);
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static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
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static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
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static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
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static void pdc_irq_clear(struct ata_port *ap);
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static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
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static void pdc_freeze(struct ata_port *ap);
static void pdc_thaw(struct ata_port *ap);
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static void pdc_pata_error_handler(struct ata_port *ap);
static void pdc_sata_error_handler(struct ata_port *ap);
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static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
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static int pdc_pata_cable_detect(struct ata_port *ap);
static int pdc_sata_cable_detect(struct ata_port *ap);
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static struct scsi_host_template pdc_ata_sht = {
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	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
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	.slave_destroy		= ata_scsi_slave_destroy,
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	.bios_param		= ata_std_bios_param,
};

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static const struct ata_port_operations pdc_sata_ops = {
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	.port_disable		= ata_port_disable,
	.tf_load		= pdc_tf_load_mmio,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= pdc_exec_command_mmio,
	.dev_select		= ata_std_dev_select,
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	.check_atapi_dma	= pdc_check_atapi_dma,

	.qc_prep		= pdc_qc_prep,
	.qc_issue		= pdc_qc_issue_prot,
	.freeze			= pdc_freeze,
	.thaw			= pdc_thaw,
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	.error_handler		= pdc_sata_error_handler,
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	.post_internal_cmd	= pdc_post_internal_cmd,
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	.cable_detect		= pdc_sata_cable_detect,
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	.data_xfer		= ata_data_xfer,
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	.irq_clear		= pdc_irq_clear,
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	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,
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	.scr_read		= pdc_sata_scr_read,
	.scr_write		= pdc_sata_scr_write,
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	.port_start		= pdc_sata_port_start,
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};

/* First-generation chips need a more restrictive ->check_atapi_dma op */
static const struct ata_port_operations pdc_old_sata_ops = {
	.port_disable		= ata_port_disable,
	.tf_load		= pdc_tf_load_mmio,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= pdc_exec_command_mmio,
	.dev_select		= ata_std_dev_select,
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	.check_atapi_dma	= pdc_old_sata_check_atapi_dma,
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	.qc_prep		= pdc_qc_prep,
	.qc_issue		= pdc_qc_issue_prot,
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	.freeze			= pdc_freeze,
	.thaw			= pdc_thaw,
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	.error_handler		= pdc_sata_error_handler,
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	.post_internal_cmd	= pdc_post_internal_cmd,
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	.cable_detect		= pdc_sata_cable_detect,
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	.data_xfer		= ata_data_xfer,
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	.irq_clear		= pdc_irq_clear,
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	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,
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	.scr_read		= pdc_sata_scr_read,
	.scr_write		= pdc_sata_scr_write,
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	.port_start		= pdc_sata_port_start,
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};

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static const struct ata_port_operations pdc_pata_ops = {
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	.port_disable		= ata_port_disable,
	.tf_load		= pdc_tf_load_mmio,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= pdc_exec_command_mmio,
	.dev_select		= ata_std_dev_select,
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	.check_atapi_dma	= pdc_check_atapi_dma,
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	.qc_prep		= pdc_qc_prep,
	.qc_issue		= pdc_qc_issue_prot,
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	.freeze			= pdc_freeze,
	.thaw			= pdc_thaw,
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	.error_handler		= pdc_pata_error_handler,
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	.post_internal_cmd	= pdc_post_internal_cmd,
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	.cable_detect		= pdc_pata_cable_detect,
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	.data_xfer		= ata_data_xfer,
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	.irq_clear		= pdc_irq_clear,
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	.irq_on			= ata_irq_on,
	.irq_ack		= ata_irq_ack,
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	.port_start		= pdc_common_port_start,
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};

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static const struct ata_port_info pdc_port_info[] = {
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	/* board_2037x */
	{
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		.flags		= PDC_COMMON_FLAGS | ATA_FLAG_SATA |
				  PDC_FLAG_SATA_PATA,
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		.pio_mask	= 0x1f, /* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= 0x7f, /* udma0-6 ; FIXME */
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		.port_ops	= &pdc_old_sata_ops,
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	},

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	/* board_2037x_pata */
	{
		.flags		= PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
		.pio_mask	= 0x1f, /* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= 0x7f, /* udma0-6 ; FIXME */
		.port_ops	= &pdc_pata_ops,
	},

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	/* board_20319 */
	{
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		.flags		= PDC_COMMON_FLAGS | ATA_FLAG_SATA |
				  PDC_FLAG_4_PORTS,
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		.pio_mask	= 0x1f, /* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= 0x7f, /* udma0-6 ; FIXME */
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		.port_ops	= &pdc_old_sata_ops,
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	},
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	/* board_20619 */
	{
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		.flags		= PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
				  PDC_FLAG_4_PORTS,
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		.pio_mask	= 0x1f, /* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= 0x7f, /* udma0-6 ; FIXME */
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		.port_ops	= &pdc_pata_ops,
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	},
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	/* board_2057x */
	{
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		.flags		= PDC_COMMON_FLAGS | ATA_FLAG_SATA |
				  PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
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		.pio_mask	= 0x1f, /* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= 0x7f, /* udma0-6 ; FIXME */
		.port_ops	= &pdc_sata_ops,
	},

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	/* board_2057x_pata */
	{
		.flags		= PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
				  PDC_FLAG_GEN_II,
		.pio_mask	= 0x1f, /* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= 0x7f, /* udma0-6 ; FIXME */
		.port_ops	= &pdc_pata_ops,
	},

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	/* board_40518 */
	{
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		.flags		= PDC_COMMON_FLAGS | ATA_FLAG_SATA |
				  PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
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		.pio_mask	= 0x1f, /* pio0-4 */
		.mwdma_mask	= 0x07, /* mwdma0-2 */
		.udma_mask	= 0x7f, /* udma0-6 ; FIXME */
		.port_ops	= &pdc_sata_ops,
	},
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};

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static const struct pci_device_id pdc_ata_pci_tbl[] = {
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	{ PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
	{ PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
	{ PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
	{ PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
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	{ PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
	{ PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
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	{ PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
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	{ PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
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	{ PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
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	{ PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },

	{ PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
	{ PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
	{ PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
	{ PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
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	{ PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
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	{ PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },

	{ PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
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	{ }	/* terminate list */
};


static struct pci_driver pdc_ata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= pdc_ata_pci_tbl,
	.probe			= pdc_ata_init_one,
	.remove			= ata_pci_remove_one,
};


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static int pdc_common_port_start(struct ata_port *ap)
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{
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	struct device *dev = ap->host->dev;
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	struct pdc_port_priv *pp;
	int rc;

	rc = ata_port_start(ap);
	if (rc)
		return rc;

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	pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
	if (!pp)
		return -ENOMEM;
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	pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
	if (!pp->pkt)
		return -ENOMEM;
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	ap->private_data = pp;

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	return 0;
}

static int pdc_sata_port_start(struct ata_port *ap)
{
	int rc;

	rc = pdc_common_port_start(ap);
	if (rc)
		return rc;

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	/* fix up PHYMODE4 align timing */
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	if (ap->flags & PDC_FLAG_GEN_II) {
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		void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
		unsigned int tmp;

		tmp = readl(mmio + 0x014);
		tmp = (tmp & ~3) | 1;	/* set bits 1:0 = 0:1 */
		writel(tmp, mmio + 0x014);
	}

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	return 0;
}

static void pdc_reset_port(struct ata_port *ap)
{
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	void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
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	unsigned int i;
	u32 tmp;

	for (i = 11; i > 0; i--) {
		tmp = readl(mmio);
		if (tmp & PDC_RESET)
			break;

		udelay(100);

		tmp |= PDC_RESET;
		writel(tmp, mmio);
	}

	tmp &= ~PDC_RESET;
	writel(tmp, mmio);
	readl(mmio);	/* flush */
}

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static int pdc_pata_cable_detect(struct ata_port *ap)
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{
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	u8 tmp;
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	void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
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	tmp = readb(mmio);
	if (tmp & 0x01)
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static int pdc_sata_cable_detect(struct ata_port *ap)
{
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	return ATA_CBL_SATA;
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}
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static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
{
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	if (sc_reg > SCR_CONTROL)
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		return 0xffffffffU;
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	return readl(ap->ioaddr.scr_addr + (sc_reg * 4));
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}


static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
			       u32 val)
{
445
	if (sc_reg > SCR_CONTROL)
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		return;
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	writel(val, ap->ioaddr.scr_addr + (sc_reg * 4));
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}

450
static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
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{
452 453 454 455 456 457
	struct ata_port *ap = qc->ap;
	dma_addr_t sg_table = ap->prd_dma;
	unsigned int cdb_len = qc->dev->cdb_len;
	u8 *cdb = qc->cdb;
	struct pdc_port_priv *pp = ap->private_data;
	u8 *buf = pp->pkt;
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458
	u32 *buf32 = (u32 *) buf;
459
	unsigned int dev_sel, feature, nbytes;
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460 461 462 463

	/* set control bits (byte 0), zero delay seq id (byte 3),
	 * and seq id (byte 2)
	 */
464 465 466 467 468 469 470 471 472 473 474 475 476 477
	switch (qc->tf.protocol) {
	case ATA_PROT_ATAPI_DMA:
		if (!(qc->tf.flags & ATA_TFLAG_WRITE))
			buf32[0] = cpu_to_le32(PDC_PKT_READ);
		else
			buf32[0] = 0;
		break;
	case ATA_PROT_ATAPI_NODATA:
		buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
		break;
	default:
		BUG();
		break;
	}
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	buf32[1] = cpu_to_le32(sg_table);	/* S/G table addr */
	buf32[2] = 0;				/* no next-packet */

481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525
	/* select drive */
	if (sata_scr_valid(ap)) {
		dev_sel = PDC_DEVICE_SATA;
	} else {
		dev_sel = ATA_DEVICE_OBS;
		if (qc->dev->devno != 0)
			dev_sel |= ATA_DEV1;
	}
	buf[12] = (1 << 5) | ATA_REG_DEVICE;
	buf[13] = dev_sel;
	buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
	buf[15] = dev_sel; /* once more, waiting for BSY to clear */

	buf[16] = (1 << 5) | ATA_REG_NSECT;
	buf[17] = 0x00;
	buf[18] = (1 << 5) | ATA_REG_LBAL;
	buf[19] = 0x00;

	/* set feature and byte counter registers */
	if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) {
		feature = PDC_FEATURE_ATAPI_PIO;
		/* set byte counter register to real transfer byte count */
		nbytes = qc->nbytes;
		if (nbytes > 0xffff)
			nbytes = 0xffff;
	} else {
		feature = PDC_FEATURE_ATAPI_DMA;
		/* set byte counter register to 0 */
		nbytes = 0;
	}
	buf[20] = (1 << 5) | ATA_REG_FEATURE;
	buf[21] = feature;
	buf[22] = (1 << 5) | ATA_REG_BYTEL;
	buf[23] = nbytes & 0xFF;
	buf[24] = (1 << 5) | ATA_REG_BYTEH;
	buf[25] = (nbytes >> 8) & 0xFF;

	/* send ATAPI packet command 0xA0 */
	buf[26] = (1 << 5) | ATA_REG_CMD;
	buf[27] = ATA_CMD_PACKET;

	/* select drive and check DRQ */
	buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
	buf[29] = dev_sel;

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	/* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
	BUG_ON(cdb_len & ~0x1E);

529 530 531
	/* append the CDB as the final part */
	buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
	memcpy(buf+31, cdb, cdb_len);
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}

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static void pdc_qc_prep(struct ata_queued_cmd *qc)
{
	struct pdc_port_priv *pp = qc->ap->private_data;
	unsigned int i;

	VPRINTK("ENTER\n");

	switch (qc->tf.protocol) {
	case ATA_PROT_DMA:
		ata_qc_prep(qc);
		/* fall through */

	case ATA_PROT_NODATA:
		i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
				   qc->dev->devno, pp->pkt);

		if (qc->tf.flags & ATA_TFLAG_LBA48)
			i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
		else
			i = pdc_prep_lba28(&qc->tf, pp->pkt, i);

		pdc_pkt_footer(&qc->tf, pp->pkt, i);
		break;

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	case ATA_PROT_ATAPI:
		ata_qc_prep(qc);
		break;

	case ATA_PROT_ATAPI_DMA:
		ata_qc_prep(qc);
564 565 566
		/*FALLTHROUGH*/
	case ATA_PROT_ATAPI_NODATA:
		pdc_atapi_pkt(qc);
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		break;

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	default:
		break;
	}
}

574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600
static void pdc_freeze(struct ata_port *ap)
{
	void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
	u32 tmp;

	tmp = readl(mmio + PDC_CTLSTAT);
	tmp |= PDC_IRQ_DISABLE;
	tmp &= ~PDC_DMA_ENABLE;
	writel(tmp, mmio + PDC_CTLSTAT);
	readl(mmio + PDC_CTLSTAT); /* flush */
}

static void pdc_thaw(struct ata_port *ap)
{
	void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
	u32 tmp;

	/* clear IRQ */
	readl(mmio + PDC_INT_SEQMASK);

	/* turn IRQ back on */
	tmp = readl(mmio + PDC_CTLSTAT);
	tmp &= ~PDC_IRQ_DISABLE;
	writel(tmp, mmio + PDC_CTLSTAT);
	readl(mmio + PDC_CTLSTAT); /* flush */
}

601
static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset)
602 603 604 605 606
{
	if (!(ap->pflags & ATA_PFLAG_FROZEN))
		pdc_reset_port(ap);

	/* perform recovery */
607
	ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
608 609 610
		  ata_std_postreset);
}

611 612 613 614 615 616 617 618 619 620
static void pdc_pata_error_handler(struct ata_port *ap)
{
	pdc_common_error_handler(ap, NULL);
}

static void pdc_sata_error_handler(struct ata_port *ap)
{
	pdc_common_error_handler(ap, sata_std_hardreset);
}

621 622 623 624 625
static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;

	/* make DMA engine forget about the failed command */
626
	if (qc->flags & ATA_QCFLAG_FAILED)
627 628 629
		pdc_reset_port(ap);
}

630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649
static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
			   u32 port_status, u32 err_mask)
{
	struct ata_eh_info *ehi = &ap->eh_info;
	unsigned int ac_err_mask = 0;

	ata_ehi_clear_desc(ehi);
	ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
	port_status &= err_mask;

	if (port_status & PDC_DRIVE_ERR)
		ac_err_mask |= AC_ERR_DEV;
	if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
		ac_err_mask |= AC_ERR_HSM;
	if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
		ac_err_mask |= AC_ERR_ATA_BUS;
	if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
			   | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
		ac_err_mask |= AC_ERR_HOST_BUS;

650 651 652
	if (sata_scr_valid(ap))
		ehi->serror |= pdc_sata_scr_read(ap, SCR_ERROR);

653
	qc->err_mask |= ac_err_mask;
654 655

	pdc_reset_port(ap);
656 657
}

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static inline unsigned int pdc_host_intr( struct ata_port *ap,
                                          struct ata_queued_cmd *qc)
{
661
	unsigned int handled = 0;
662 663 664 665
	void __iomem *port_mmio = ap->ioaddr.cmd_addr;
	u32 port_status, err_mask;

	err_mask = PDC_ERR_MASK;
666
	if (ap->flags & PDC_FLAG_GEN_II)
667 668 669 670 671 672 673
		err_mask &= ~PDC1_ERR_MASK;
	else
		err_mask &= ~PDC2_ERR_MASK;
	port_status = readl(port_mmio + PDC_GLOBAL_CTL);
	if (unlikely(port_status & err_mask)) {
		pdc_error_intr(ap, qc, port_status, err_mask);
		return 1;
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	}

	switch (qc->tf.protocol) {
	case ATA_PROT_DMA:
	case ATA_PROT_NODATA:
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	case ATA_PROT_ATAPI_DMA:
680
	case ATA_PROT_ATAPI_NODATA:
681 682
		qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
		ata_qc_complete(qc);
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683 684 685 686
		handled = 1;
		break;

        default:
687 688
		ap->stats.idle_irq++;
		break;
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689 690
        }

691
	return handled;
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}

static void pdc_irq_clear(struct ata_port *ap)
{
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	struct ata_host *host = ap->host;
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	void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
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	readl(mmio + PDC_INT_SEQMASK);
}

702
static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
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{
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704
	struct ata_host *host = dev_instance;
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	struct ata_port *ap;
	u32 mask = 0;
	unsigned int i, tmp;
	unsigned int handled = 0;
709
	void __iomem *mmio_base;
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	VPRINTK("ENTER\n");

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	if (!host || !host->iomap[PDC_MMIO_BAR]) {
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		VPRINTK("QUICK EXIT\n");
		return IRQ_NONE;
	}

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	mmio_base = host->iomap[PDC_MMIO_BAR];
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	/* reading should also clear interrupts */
	mask = readl(mmio_base + PDC_INT_SEQMASK);

	if (mask == 0xffffffff) {
		VPRINTK("QUICK EXIT 2\n");
		return IRQ_NONE;
	}
727

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	spin_lock(&host->lock);
729

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	mask &= 0xffff;		/* only 16 tags possible */
	if (!mask) {
		VPRINTK("QUICK EXIT 3\n");
733
		goto done_irq;
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734 735 736 737
	}

	writel(mask, mmio_base + PDC_INT_SEQMASK);

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	for (i = 0; i < host->n_ports; i++) {
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		VPRINTK("port %u\n", i);
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		ap = host->ports[i];
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		tmp = mask & (1 << (i + 1));
742
		if (tmp && ap &&
J
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743
		    !(ap->flags & ATA_FLAG_DISABLED)) {
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			struct ata_queued_cmd *qc;

			qc = ata_qc_from_tag(ap, ap->active_tag);
747
			if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
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748 749 750 751 752 753
				handled += pdc_host_intr(ap, qc);
		}
	}

	VPRINTK("EXIT\n");

754
done_irq:
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	spin_unlock(&host->lock);
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	return IRQ_RETVAL(handled);
}

static inline void pdc_packet_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct pdc_port_priv *pp = ap->private_data;
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	void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
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	unsigned int port_no = ap->port_no;
	u8 seq = (u8) (port_no + 1);

	VPRINTK("ENTER, ap %p\n", ap);

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	writel(0x00000001, mmio + (seq * 4));
	readl(mmio + (seq * 4));	/* flush */
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	pp->pkt[2] = seq;
	wmb();			/* flush PRD, pkt writes */
T
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	writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
	readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
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}

778
static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
L
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779 780
{
	switch (qc->tf.protocol) {
781 782 783 784
	case ATA_PROT_ATAPI_NODATA:
		if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
			break;
		/*FALLTHROUGH*/
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	case ATA_PROT_ATAPI_DMA:
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786 787 788 789 790 791 792 793 794 795 796 797
	case ATA_PROT_DMA:
	case ATA_PROT_NODATA:
		pdc_packet_start(qc);
		return 0;

	default:
		break;
	}

	return ata_qc_issue_prot(qc);
}

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798
static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
L
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799 800 801 802 803 804 805
{
	WARN_ON (tf->protocol == ATA_PROT_DMA ||
		 tf->protocol == ATA_PROT_NODATA);
	ata_tf_load(ap, tf);
}


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Jeff Garzik 已提交
806
static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
L
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807 808 809 810 811 812
{
	WARN_ON (tf->protocol == ATA_PROT_DMA ||
		 tf->protocol == ATA_PROT_NODATA);
	ata_exec_command(ap, tf);
}

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Mikael Pettersson 已提交
813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839
static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
{
	u8 *scsicmd = qc->scsicmd->cmnd;
	int pio = 1; /* atapi dma off by default */

	/* Whitelist commands that may use DMA. */
	switch (scsicmd[0]) {
	case WRITE_12:
	case WRITE_10:
	case WRITE_6:
	case READ_12:
	case READ_10:
	case READ_6:
	case 0xad: /* READ_DVD_STRUCTURE */
	case 0xbe: /* READ_CD */
		pio = 0;
	}
	/* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
	if (scsicmd[0] == WRITE_10) {
		unsigned int lba;
		lba = (scsicmd[2] << 24) | (scsicmd[3] << 16) | (scsicmd[4] << 8) | scsicmd[5];
		if (lba >= 0xFFFF4FA2)
			pio = 1;
	}
	return pio;
}

840
static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
M
Mikael Pettersson 已提交
841 842
{
	/* First generation chips cannot use ATAPI DMA on SATA ports */
843
	return 1;
M
Mikael Pettersson 已提交
844
}
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845

846 847
static void pdc_ata_setup_port(struct ata_port *ap,
			       void __iomem *base, void __iomem *scr_addr)
L
Linus Torvalds 已提交
848
{
849 850 851 852 853 854 855 856 857 858 859 860 861 862
	ap->ioaddr.cmd_addr		= base;
	ap->ioaddr.data_addr		= base;
	ap->ioaddr.feature_addr		=
	ap->ioaddr.error_addr		= base + 0x4;
	ap->ioaddr.nsect_addr		= base + 0x8;
	ap->ioaddr.lbal_addr		= base + 0xc;
	ap->ioaddr.lbam_addr		= base + 0x10;
	ap->ioaddr.lbah_addr		= base + 0x14;
	ap->ioaddr.device_addr		= base + 0x18;
	ap->ioaddr.command_addr		=
	ap->ioaddr.status_addr		= base + 0x1c;
	ap->ioaddr.altstatus_addr	=
	ap->ioaddr.ctl_addr		= base + 0x38;
	ap->ioaddr.scr_addr		= scr_addr;
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863 864 865
}


866
static void pdc_host_init(struct ata_host *host)
L
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867
{
868 869
	void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
	int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
870
	int hotplug_offset;
L
Linus Torvalds 已提交
871 872
	u32 tmp;

873
	if (is_gen2)
874 875 876 877
		hotplug_offset = PDC2_SATA_PLUG_CSR;
	else
		hotplug_offset = PDC_SATA_PLUG_CSR;

L
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878 879 880 881 882 883
	/*
	 * Except for the hotplug stuff, this is voodoo from the
	 * Promise driver.  Label this entire section
	 * "TODO: figure out why we do this"
	 */

884
	/* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
L
Linus Torvalds 已提交
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	tmp = readl(mmio + PDC_FLASH_CTL);
886
	tmp |= 0x02000;	/* bit 13 (enable bmr burst) */
887
	if (!is_gen2)
888
		tmp |= 0x10000;	/* bit 16 (fifo threshold at 8 dw) */
L
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889 890 891
	writel(tmp, mmio + PDC_FLASH_CTL);

	/* clear plug/unplug flags for all ports */
892 893
	tmp = readl(mmio + hotplug_offset);
	writel(tmp | 0xff, mmio + hotplug_offset);
L
Linus Torvalds 已提交
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	/* mask plug/unplug ints */
896 897
	tmp = readl(mmio + hotplug_offset);
	writel(tmp | 0xff0000, mmio + hotplug_offset);
L
Linus Torvalds 已提交
898

899
	/* don't initialise TBG or SLEW on 2nd generation chips */
900
	if (is_gen2)
901 902
		return;

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903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921
	/* reduce TBG clock to 133 Mhz. */
	tmp = readl(mmio + PDC_TBG_MODE);
	tmp &= ~0x30000; /* clear bit 17, 16*/
	tmp |= 0x10000;  /* set bit 17:16 = 0:1 */
	writel(tmp, mmio + PDC_TBG_MODE);

	readl(mmio + PDC_TBG_MODE);	/* flush */
	msleep(10);

	/* adjust slew rate control register. */
	tmp = readl(mmio + PDC_SLEW_CTL);
	tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
	tmp  |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
	writel(tmp, mmio + PDC_SLEW_CTL);
}

static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
{
	static int printed_version;
922 923 924
	const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
	const struct ata_port_info *ppi[PDC_MAX_PORTS];
	struct ata_host *host;
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	void __iomem *base;
926
	int n_ports, i, rc;
L
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	if (!printed_version++)
929
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
L
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930

931
	/* enable and acquire resources */
932
	rc = pcim_enable_device(pdev);
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933 934 935
	if (rc)
		return rc;

T
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936 937
	rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
	if (rc == -EBUSY)
938
		pcim_pin_device(pdev);
T
Tejun Heo 已提交
939
	if (rc)
940
		return rc;
941
	base = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
L
Linus Torvalds 已提交
942

943 944 945 946 947 948
	/* determine port configuration and setup host */
	n_ports = 2;
	if (pi->flags & PDC_FLAG_4_PORTS)
		n_ports = 4;
	for (i = 0; i < n_ports; i++)
		ppi[i] = pi;
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950 951 952 953 954 955 956
	if (pi->flags & PDC_FLAG_SATA_PATA) {
		u8 tmp = readb(base + PDC_FLASH_CTL+1);
		if (!(tmp & 0x80)) {
			ppi[n_ports++] = pi + 1;
			dev_printk(KERN_INFO, &pdev->dev, "PATA port found\n");
		}
	}
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	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	if (!host) {
		dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n");
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		return -ENOMEM;
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	}
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	host->iomap = pcim_iomap_table(pdev);
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	for (i = 0; i < host->n_ports; i++)
		pdc_ata_setup_port(host->ports[i],
				   base + 0x200 + i * 0x80,
				   base + 0x400 + i * 0x100);
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	/* initialize adapter */
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	pdc_host_init(host);
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	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
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	/* start host, request IRQ and attach */
	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
				 &pdc_ata_sht);
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}


static int __init pdc_ata_init(void)
{
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	return pci_register_driver(&pdc_ata_pci_driver);
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}


static void __exit pdc_ata_exit(void)
{
	pci_unregister_driver(&pdc_ata_pci_driver);
}


MODULE_AUTHOR("Jeff Garzik");
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MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
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MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
MODULE_VERSION(DRV_VERSION);

module_init(pdc_ata_init);
module_exit(pdc_ata_exit);