pm34xx.c 21.7 KB
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/*
 * OMAP3 Power Management Routines
 *
 * Copyright (C) 2006-2008 Nokia Corporation
 * Tony Lindgren <tony@atomide.com>
 * Jouni Hogander
 *
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 * Copyright (C) 2007 Texas Instruments, Inc.
 * Rajendra Nayak <rnayak@ti.com>
 *
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 * Copyright (C) 2005 Texas Instruments, Inc.
 * Richard Woodruff <r-woodruff2@ti.com>
 *
 * Based on pm.c for omap1
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/pm.h>
#include <linux/suspend.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/err.h>
#include <linux/gpio.h>
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <trace/events/power.h>
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#include <asm/suspend.h>
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#include <asm/system_misc.h>
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#include <plat/sram.h>
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#include "clockdomain.h"
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#include "powerdomain.h"
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#include <plat/sdrc.h>
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#include <plat/prcm.h>
#include <plat/gpmc.h>
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#include <plat/dma.h>
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#include "common.h"
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#include "cm2xxx_3xxx.h"
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#include "cm-regbits-34xx.h"
#include "prm-regbits-34xx.h"

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#include "prm2xxx_3xxx.h"
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#include "pm.h"
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#include "sdrc.h"
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#include "control.h"
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/* pm34xx errata defined in pm.h */
u16 pm34xx_errata;

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struct power_state {
	struct powerdomain *pwrdm;
	u32 next_state;
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#ifdef CONFIG_SUSPEND
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	u32 saved_state;
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#endif
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	struct list_head node;
};

static LIST_HEAD(pwrst_list);

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static int (*_omap_save_secure_sram)(u32 *addr);
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void (*omap3_do_wfi_sram)(void);
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static struct powerdomain *mpu_pwrdm, *neon_pwrdm;
static struct powerdomain *core_pwrdm, *per_pwrdm;
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static struct powerdomain *cam_pwrdm;
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static void omap3_enable_io_chain(void)
{
	int timeout = 0;

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	omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
				   PM_WKEN);
	/* Do a readback to assure write has been done */
	omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN);

	while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) &
		 OMAP3430_ST_IO_CHAIN_MASK)) {
		timeout++;
		if (timeout > 1000) {
			pr_err("Wake up daisy chain activation failed.\n");
			return;
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		}
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		omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK,
					   WKUP_MOD, PM_WKEN);
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	}
}

static void omap3_disable_io_chain(void)
{
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	omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD,
				     PM_WKEN);
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}

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static void omap3_core_save_context(void)
{
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	omap3_ctrl_save_padconf();
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	/*
	 * Force write last pad into memory, as this can fail in some
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	 * cases according to errata 1.157, 1.185
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	 */
	omap_ctrl_writel(omap_ctrl_readl(OMAP343X_PADCONF_ETK_D14),
		OMAP343X_CONTROL_MEM_WKUP + 0x2a0);

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	/* Save the Interrupt controller context */
	omap_intc_save_context();
	/* Save the GPMC context */
	omap3_gpmc_save_context();
	/* Save the system control module context, padconf already save above*/
	omap3_control_save_context();
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	omap_dma_global_context_save();
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}

static void omap3_core_restore_context(void)
{
	/* Restore the control module context, padconf restored by h/w */
	omap3_control_restore_context();
	/* Restore the GPMC context */
	omap3_gpmc_restore_context();
	/* Restore the interrupt controller context */
	omap_intc_restore_context();
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	omap_dma_global_context_restore();
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}

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/*
 * FIXME: This function should be called before entering off-mode after
 * OMAP3 secure services have been accessed. Currently it is only called
 * once during boot sequence, but this works as we are not using secure
 * services.
 */
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static void omap3_save_secure_ram_context(void)
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{
	u32 ret;
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	int mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
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	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
		/*
		 * MPU next state must be set to POWER_ON temporarily,
		 * otherwise the WFI executed inside the ROM code
		 * will hang the system.
		 */
		pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
		ret = _omap_save_secure_sram((u32 *)
				__pa(omap3_secure_ram_storage));
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		pwrdm_set_next_pwrst(mpu_pwrdm, mpu_next_state);
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		/* Following is for error tracking, it should not happen */
		if (ret) {
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			pr_err("save_secure_sram() returns %08x\n", ret);
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			while (1)
				;
		}
	}
}

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/*
 * PRCM Interrupt Handler Helper Function
 *
 * The purpose of this function is to clear any wake-up events latched
 * in the PRCM PM_WKST_x registers. It is possible that a wake-up event
 * may occur whilst attempting to clear a PM_WKST_x register and thus
 * set another bit in this register. A while loop is used to ensure
 * that any peripheral wake-up events occurring while attempting to
 * clear the PM_WKST_x are detected and cleared.
 */
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static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits)
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{
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	u32 wkst, fclk, iclk, clken;
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	u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1;
	u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1;
	u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1;
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	u16 grpsel_off = (regs == 3) ?
		OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL;
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	int c = 0;
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	wkst = omap2_prm_read_mod_reg(module, wkst_off);
	wkst &= omap2_prm_read_mod_reg(module, grpsel_off);
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	wkst &= ~ignore_bits;
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	if (wkst) {
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		iclk = omap2_cm_read_mod_reg(module, iclk_off);
		fclk = omap2_cm_read_mod_reg(module, fclk_off);
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		while (wkst) {
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			clken = wkst;
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			omap2_cm_set_mod_reg_bits(clken, module, iclk_off);
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			/*
			 * For USBHOST, we don't know whether HOST1 or
			 * HOST2 woke us up, so enable both f-clocks
			 */
			if (module == OMAP3430ES2_USBHOST_MOD)
				clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT;
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			omap2_cm_set_mod_reg_bits(clken, module, fclk_off);
			omap2_prm_write_mod_reg(wkst, module, wkst_off);
			wkst = omap2_prm_read_mod_reg(module, wkst_off);
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			wkst &= ~ignore_bits;
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			c++;
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		}
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		omap2_cm_write_mod_reg(iclk, module, iclk_off);
		omap2_cm_write_mod_reg(fclk, module, fclk_off);
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	}
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	return c;
}

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static irqreturn_t _prcm_int_handle_io(int irq, void *unused)
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{
	int c;

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	c = prcm_clear_mod_irqs(WKUP_MOD, 1,
		~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK));
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	return c ? IRQ_HANDLED : IRQ_NONE;
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}
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static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused)
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{
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	int c;
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	/*
	 * Clear all except ST_IO and ST_IO_CHAIN for wkup module,
	 * these are handled in a separate handler to avoid acking
	 * IO events before parsing in mux code
	 */
	c = prcm_clear_mod_irqs(WKUP_MOD, 1,
		OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK);
	c += prcm_clear_mod_irqs(CORE_MOD, 1, 0);
	c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0);
	if (omap_rev() > OMAP3430_REV_ES1_0) {
		c += prcm_clear_mod_irqs(CORE_MOD, 3, 0);
		c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0);
	}
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	return c ? IRQ_HANDLED : IRQ_NONE;
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}

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static void omap34xx_save_context(u32 *save)
{
	u32 val;

	/* Read Auxiliary Control Register */
	asm("mrc p15, 0, %0, c1, c0, 1" : "=r" (val));
	*save++ = 1;
	*save++ = val;

	/* Read L2 AUX ctrl register */
	asm("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
	*save++ = 1;
	*save++ = val;
}

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static int omap34xx_do_sram_idle(unsigned long save_state)
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{
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	omap34xx_cpu_suspend(save_state);
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	return 0;
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}

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void omap_sram_idle(void)
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{
	/* Variable to tell what needs to be saved and restored
	 * in omap_sram_idle*/
	/* save_state = 0 => Nothing to save and restored */
	/* save_state = 1 => Only L1 and logic lost */
	/* save_state = 2 => Only L2 lost */
	/* save_state = 3 => L1, L2 and logic lost */
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	int save_state = 0;
	int mpu_next_state = PWRDM_POWER_ON;
	int per_next_state = PWRDM_POWER_ON;
	int core_next_state = PWRDM_POWER_ON;
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	int per_going_off;
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	int core_prev_state;
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	u32 sdrc_pwr = 0;
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	mpu_next_state = pwrdm_read_next_pwrst(mpu_pwrdm);
	switch (mpu_next_state) {
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	case PWRDM_POWER_ON:
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	case PWRDM_POWER_RET:
		/* No need to save context */
		save_state = 0;
		break;
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	case PWRDM_POWER_OFF:
		save_state = 3;
		break;
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	default:
		/* Invalid state */
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		pr_err("Invalid mpu state in sram_idle\n");
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		return;
	}
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	/* NEON control */
	if (pwrdm_read_pwrst(neon_pwrdm) == PWRDM_POWER_ON)
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		pwrdm_set_next_pwrst(neon_pwrdm, mpu_next_state);
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	/* Enable IO-PAD and IO-CHAIN wakeups */
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	per_next_state = pwrdm_read_next_pwrst(per_pwrdm);
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	core_next_state = pwrdm_read_next_pwrst(core_pwrdm);
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	if (omap3_has_io_wakeup() &&
	    (per_next_state < PWRDM_POWER_ON ||
	     core_next_state < PWRDM_POWER_ON)) {
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		omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN);
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		if (omap3_has_io_chain_ctrl())
			omap3_enable_io_chain();
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	}

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	pwrdm_pre_transition();

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	/* PER */
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	if (per_next_state < PWRDM_POWER_ON) {
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		per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0;
		omap2_gpio_prepare_for_idle(per_going_off);
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	}

	/* CORE */
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	if (core_next_state < PWRDM_POWER_ON) {
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		if (core_next_state == PWRDM_POWER_OFF) {
			omap3_core_save_context();
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			omap3_cm_save_context();
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		}
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	}
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	omap3_intc_prepare_idle();
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	/*
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	 * On EMU/HS devices ROM code restores a SRDC value
	 * from scratchpad which has automatic self refresh on timeout
	 * of AUTO_CNT = 1 enabled. This takes care of erratum ID i443.
	 * Hence store/restore the SDRC_POWER register here.
	 */
	if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
	    (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
	     omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
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	    core_next_state == PWRDM_POWER_OFF)
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		sdrc_pwr = sdrc_read_reg(SDRC_POWER);

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	/*
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	 * omap3_arm_context is the location where some ARM context
	 * get saved. The rest is placed on the stack, and restored
	 * from there before resuming.
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	 */
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	if (save_state)
		omap34xx_save_context(omap3_arm_context);
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	if (save_state == 1 || save_state == 3)
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		cpu_suspend(save_state, omap34xx_do_sram_idle);
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	else
		omap34xx_do_sram_idle(save_state);
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	/* Restore normal SDRC POWER settings */
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	if (cpu_is_omap3430() && omap_rev() >= OMAP3430_REV_ES3_0 &&
	    (omap_type() == OMAP2_DEVICE_TYPE_EMU ||
	     omap_type() == OMAP2_DEVICE_TYPE_SEC) &&
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	    core_next_state == PWRDM_POWER_OFF)
		sdrc_write_reg(sdrc_pwr, SDRC_POWER);

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	/* CORE */
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	if (core_next_state < PWRDM_POWER_ON) {
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		core_prev_state = pwrdm_read_prev_pwrst(core_pwrdm);
		if (core_prev_state == PWRDM_POWER_OFF) {
			omap3_core_restore_context();
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			omap3_cm_restore_context();
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			omap3_sram_restore_context();
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			omap2_sms_restore_context();
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		}
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		if (core_next_state == PWRDM_POWER_OFF)
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			omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK,
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					       OMAP3430_GR_MOD,
					       OMAP3_PRM_VOLTCTRL_OFFSET);
	}
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	omap3_intc_resume_idle();
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	pwrdm_post_transition();

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	/* PER */
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	if (per_next_state < PWRDM_POWER_ON)
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		omap2_gpio_resume_after_idle();
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	/* Disable IO-PAD and IO-CHAIN wakeup */
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	if (omap3_has_io_wakeup() &&
	    (per_next_state < PWRDM_POWER_ON ||
	     core_next_state < PWRDM_POWER_ON)) {
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		omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD,
					     PM_WKEN);
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		if (omap3_has_io_chain_ctrl())
			omap3_disable_io_chain();
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	}
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	clkdm_allow_idle(mpu_pwrdm->pwrdm_clkdms[0]);
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}

static void omap3_pm_idle(void)
{
	local_fiq_disable();

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	if (omap_irq_pending())
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		goto out;

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	trace_power_start(POWER_CSTATE, 1, smp_processor_id());
	trace_cpu_idle(1, smp_processor_id());

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	omap_sram_idle();

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	trace_power_end(smp_processor_id());
	trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());

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out:
	local_fiq_enable();
}

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#ifdef CONFIG_SUSPEND
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static int omap3_pm_suspend(void)
{
	struct power_state *pwrst;
	int state, ret = 0;

	/* Read current next_pwrsts */
	list_for_each_entry(pwrst, &pwrst_list, node)
		pwrst->saved_state = pwrdm_read_next_pwrst(pwrst->pwrdm);
	/* Set ones wanted by suspend */
	list_for_each_entry(pwrst, &pwrst_list, node) {
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		if (omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state))
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			goto restore;
		if (pwrdm_clear_all_prev_pwrst(pwrst->pwrdm))
			goto restore;
	}

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	omap3_intc_suspend();

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	omap_sram_idle();

restore:
	/* Restore next_pwrsts */
	list_for_each_entry(pwrst, &pwrst_list, node) {
		state = pwrdm_read_prev_pwrst(pwrst->pwrdm);
		if (state > pwrst->next_state) {
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			pr_info("Powerdomain (%s) didn't enter "
				"target state %d\n",
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			       pwrst->pwrdm->name, pwrst->next_state);
			ret = -1;
		}
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		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
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	}
	if (ret)
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		pr_err("Could not enter target state in pm_suspend\n");
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	else
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		pr_info("Successfully put all powerdomains to target state\n");
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	return ret;
}

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#endif /* CONFIG_SUSPEND */
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/**
 * omap3_iva_idle(): ensure IVA is in idle so it can be put into
 *                   retention
 *
 * In cases where IVA2 is activated by bootcode, it may prevent
 * full-chip retention or off-mode because it is not idle.  This
 * function forces the IVA2 into idle state so it can go
 * into retention/off and thus allow full-chip retention/off.
 *
 **/
static void __init omap3_iva_idle(void)
{
	/* ensure IVA2 clock is disabled */
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	omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
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	/* if no clock activity, nothing else to do */
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	if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) &
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	      OMAP3430_CLKACTIVITY_IVA2_MASK))
		return;

	/* Reset IVA2 */
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	omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
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			  OMAP3430_RST2_IVA2_MASK |
			  OMAP3430_RST3_IVA2_MASK,
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			  OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
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	/* Enable IVA2 clock */
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	omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK,
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			 OMAP3430_IVA2_MOD, CM_FCLKEN);

	/* Set IVA2 boot mode to 'idle' */
	omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE,
			 OMAP343X_CONTROL_IVA2_BOOTMOD);

	/* Un-reset IVA2 */
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	omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
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	/* Disable IVA2 clock */
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	omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN);
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	/* Reset IVA2 */
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	omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK |
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			  OMAP3430_RST2_IVA2_MASK |
			  OMAP3430_RST3_IVA2_MASK,
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			  OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
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}

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static void __init omap3_d2d_idle(void)
505
{
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	u16 mask, padconf;

	/* In a stand alone OMAP3430 where there is not a stacked
	 * modem for the D2D Idle Ack and D2D MStandby must be pulled
	 * high. S CONTROL_PADCONF_SAD2D_IDLEACK and
	 * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */
	mask = (1 << 4) | (1 << 3); /* pull-up, enabled */
	padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY);
	padconf |= mask;
	omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY);

	padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK);
	padconf |= mask;
	omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK);

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	/* reset modem */
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	omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK |
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			  OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK,
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			  CORE_MOD, OMAP2_RM_RSTCTRL);
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	omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL);
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}
527

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static void __init prcm_setup_regs(void)
{
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	u32 omap3630_en_uart4_mask = cpu_is_omap3630() ?
					OMAP3630_EN_UART4_MASK : 0;
	u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ?
					OMAP3630_GRPSEL_UART4_MASK : 0;

535
	/* XXX This should be handled by hwmod code or SCM init code */
536
	omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG);
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	/*
	 * Enable control of expternal oscillator through
	 * sys_clkreq. In the long run clock framework should
	 * take care of this.
	 */
543
	omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK,
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			     1 << OMAP_AUTOEXTCLKMODE_SHIFT,
			     OMAP3430_GR_MOD,
			     OMAP3_PRM_CLKSRC_CTRL_OFFSET);

	/* setup wakup source */
549
	omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK |
550
			  OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK,
551 552
			  WKUP_MOD, PM_WKEN);
	/* No need to write EN_IO, that is always enabled */
553
	omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK |
554 555
			  OMAP3430_GRPSEL_GPT1_MASK |
			  OMAP3430_GRPSEL_GPT12_MASK,
556
			  WKUP_MOD, OMAP3430_PM_MPUGRPSEL);
557

558
	/* Enable PM_WKEN to support DSS LPR */
559
	omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK,
560 561
				OMAP3430_DSS_MOD, PM_WKEN);

562
	/* Enable wakeups in PER */
563
	omap2_prm_write_mod_reg(omap3630_en_uart4_mask |
564
			  OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK |
565 566 567 568
			  OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK |
			  OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK |
			  OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK |
			  OMAP3430_EN_MCBSP4_MASK,
569
			  OMAP3430_PER_MOD, PM_WKEN);
570
	/* and allow them to wake up MPU */
571
	omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask |
572
			  OMAP3430_GRPSEL_GPIO2_MASK |
573 574 575 576 577 578 579 580
			  OMAP3430_GRPSEL_GPIO3_MASK |
			  OMAP3430_GRPSEL_GPIO4_MASK |
			  OMAP3430_GRPSEL_GPIO5_MASK |
			  OMAP3430_GRPSEL_GPIO6_MASK |
			  OMAP3430_GRPSEL_UART3_MASK |
			  OMAP3430_GRPSEL_MCBSP2_MASK |
			  OMAP3430_GRPSEL_MCBSP3_MASK |
			  OMAP3430_GRPSEL_MCBSP4_MASK,
581 582
			  OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL);

583
	/* Don't attach IVA interrupts */
584 585 586 587
	omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL);
	omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1);
	omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3);
	omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL);
588

589
	/* Clear any pending 'reset' flags */
590 591 592 593 594 595 596
	omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST);
	omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST);
	omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST);
	omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST);
	omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST);
	omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST);
	omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST);
597

598
	/* Clear any pending PRCM interrupts */
599
	omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET);
600

601
	omap3_iva_idle();
602
	omap3_d2d_idle();
603 604
}

605 606 607 608 609 610 611 612 613 614 615
void omap3_pm_off_mode_enable(int enable)
{
	struct power_state *pwrst;
	u32 state;

	if (enable)
		state = PWRDM_POWER_OFF;
	else
		state = PWRDM_POWER_RET;

	list_for_each_entry(pwrst, &pwrst_list, node) {
616 617 618 619
		if (IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583) &&
				pwrst->pwrdm == core_pwrdm &&
				state == PWRDM_POWER_OFF) {
			pwrst->next_state = PWRDM_POWER_RET;
620
			pr_warn("%s: Core OFF disabled due to errata i583\n",
621 622 623 624 625
				__func__);
		} else {
			pwrst->next_state = state;
		}
		omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
626 627 628
	}
}

629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652
int omap3_pm_get_suspend_state(struct powerdomain *pwrdm)
{
	struct power_state *pwrst;

	list_for_each_entry(pwrst, &pwrst_list, node) {
		if (pwrst->pwrdm == pwrdm)
			return pwrst->next_state;
	}
	return -EINVAL;
}

int omap3_pm_set_suspend_state(struct powerdomain *pwrdm, int state)
{
	struct power_state *pwrst;

	list_for_each_entry(pwrst, &pwrst_list, node) {
		if (pwrst->pwrdm == pwrdm) {
			pwrst->next_state = state;
			return 0;
		}
	}
	return -EINVAL;
}

653
static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
654 655 656 657 658 659
{
	struct power_state *pwrst;

	if (!pwrdm->pwrsts)
		return 0;

660
	pwrst = kmalloc(sizeof(struct power_state), GFP_ATOMIC);
661 662 663 664 665 666 667 668 669
	if (!pwrst)
		return -ENOMEM;
	pwrst->pwrdm = pwrdm;
	pwrst->next_state = PWRDM_POWER_RET;
	list_add(&pwrst->node, &pwrst_list);

	if (pwrdm_has_hdwr_sar(pwrdm))
		pwrdm_enable_hdwr_sar(pwrdm);

670
	return omap_set_pwrdm_state(pwrst->pwrdm, pwrst->next_state);
671 672
}

673 674 675 676 677 678 679
/*
 * Push functions to SRAM
 *
 * The minimum set of functions is pushed to SRAM for execution:
 * - omap3_do_wfi for erratum i581 WA,
 * - save_secure_ram_context for security extensions.
 */
680 681
void omap_push_sram_idle(void)
{
682 683
	omap3_do_wfi_sram = omap_sram_push(omap3_do_wfi, omap3_do_wfi_sz);

684 685 686
	if (omap_type() != OMAP2_DEVICE_TYPE_GP)
		_omap_save_secure_sram = omap_sram_push(save_secure_ram_context,
				save_secure_ram_context_sz);
687 688
}

689 690
static void __init pm_errata_configure(void)
{
691
	if (cpu_is_omap3630()) {
692
		pm34xx_errata |= PM_RTA_ERRATUM_i608;
693 694
		/* Enable the l2 cache toggling in sleep logic */
		enable_omap3630_toggle_l2_on_restore();
695 696
		if (omap_rev() < OMAP3630_REV_ES1_2)
			pm34xx_errata |= PM_SDRC_WAKEUP_ERRATUM_i583;
697
	}
698 699
}

700
int __init omap3_pm_init(void)
701 702
{
	struct power_state *pwrst, *tmp;
703
	struct clockdomain *neon_clkdm, *mpu_clkdm;
704 705
	int ret;

706 707 708
	if (!omap3_has_io_chain_ctrl())
		pr_warning("PM: no software I/O chain control; some wakeups may be lost\n");

709 710
	pm_errata_configure();

711 712 713 714
	/* XXX prcm_setup_regs needs to be before enabling hw
	 * supervised mode for powerdomains */
	prcm_setup_regs();

715 716 717 718 719 720 721 722 723 724 725 726
	ret = request_irq(omap_prcm_event_to_irq("wkup"),
		_prcm_int_handle_wakeup, IRQF_NO_SUSPEND, "pm_wkup", NULL);

	if (ret) {
		pr_err("pm: Failed to request pm_wkup irq\n");
		goto err1;
	}

	/* IO interrupt is shared with mux code */
	ret = request_irq(omap_prcm_event_to_irq("io"),
		_prcm_int_handle_io, IRQF_SHARED | IRQF_NO_SUSPEND, "pm_io",
		omap3_pm_init);
727
	enable_irq(omap_prcm_event_to_irq("io"));
728

729
	if (ret) {
730
		pr_err("pm: Failed to request pm_io irq\n");
731
		goto err2;
732 733
	}

734
	ret = pwrdm_for_each(pwrdms_setup, NULL);
735
	if (ret) {
736
		pr_err("Failed to setup powerdomains\n");
737
		goto err3;
738 739
	}

740
	(void) clkdm_for_each(omap_pm_clkdms_setup, NULL);
741 742 743

	mpu_pwrdm = pwrdm_lookup("mpu_pwrdm");
	if (mpu_pwrdm == NULL) {
744
		pr_err("Failed to get mpu_pwrdm\n");
745 746
		ret = -EINVAL;
		goto err3;
747 748
	}

749 750 751
	neon_pwrdm = pwrdm_lookup("neon_pwrdm");
	per_pwrdm = pwrdm_lookup("per_pwrdm");
	core_pwrdm = pwrdm_lookup("core_pwrdm");
752
	cam_pwrdm = pwrdm_lookup("cam_pwrdm");
753

754 755 756
	neon_clkdm = clkdm_lookup("neon_clkdm");
	mpu_clkdm = clkdm_lookup("mpu_clkdm");

757
#ifdef CONFIG_SUSPEND
758 759
	omap_pm_suspend = omap3_pm_suspend;
#endif
760

761
	arm_pm_idle = omap3_pm_idle;
762
	omap3_idle_init();
763

764 765 766 767 768 769 770 771
	/*
	 * RTA is disabled during initialization as per erratum i608
	 * it is safer to disable RTA by the bootloader, but we would like
	 * to be doubly sure here and prevent any mishaps.
	 */
	if (IS_PM34XX_ERRATUM(PM_RTA_ERRATUM_i608))
		omap3630_ctrl_disable_rta();

772
	clkdm_add_wkdep(neon_clkdm, mpu_clkdm);
773 774 775 776
	if (omap_type() != OMAP2_DEVICE_TYPE_GP) {
		omap3_secure_ram_storage =
			kmalloc(0x803F, GFP_KERNEL);
		if (!omap3_secure_ram_storage)
777 778
			pr_err("Memory allocation failed when "
			       "allocating for secure sram context\n");
779 780 781 782 783

		local_irq_disable();
		local_fiq_disable();

		omap_dma_global_context_save();
784
		omap3_save_secure_ram_context();
785 786 787 788
		omap_dma_global_context_restore();

		local_irq_enable();
		local_fiq_enable();
789 790
	}

791
	omap3_save_scratchpad_contents();
792
	return ret;
793 794

err3:
795 796 797 798
	list_for_each_entry_safe(pwrst, tmp, &pwrst_list, node) {
		list_del(&pwrst->node);
		kfree(pwrst);
	}
799 800 801 802
	free_irq(omap_prcm_event_to_irq("io"), omap3_pm_init);
err2:
	free_irq(omap_prcm_event_to_irq("wkup"), NULL);
err1:
803 804
	return ret;
}