mr.c 45.7 KB
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/*
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 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
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 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */


#include <linux/kref.h>
#include <linux/random.h>
#include <linux/debugfs.h>
#include <linux/export.h>
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#include <linux/delay.h>
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#include <rdma/ib_umem.h>
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#include <rdma/ib_umem_odp.h>
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#include <rdma/ib_verbs.h>
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#include "mlx5_ib.h"

enum {
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	MAX_PENDING_REG_MR = 8,
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};

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#define MLX5_UMR_ALIGN 2048
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static int clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
static int dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
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static int mr_cache_max_order(struct mlx5_ib_dev *dev);
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static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
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static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
{
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	int err = mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey);
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#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
	/* Wait until all page fault handlers using the mr complete. */
	synchronize_srcu(&dev->mr_srcu);
#endif

	return err;
}

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static int order2idx(struct mlx5_ib_dev *dev, int order)
{
	struct mlx5_mr_cache *cache = &dev->cache;

	if (order < cache->ent[0].order)
		return 0;
	else
		return order - cache->ent[0].order;
}

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static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length)
{
	return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >=
		length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1));
}

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#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
static void update_odp_mr(struct mlx5_ib_mr *mr)
{
	if (mr->umem->odp_data) {
		/*
		 * This barrier prevents the compiler from moving the
		 * setting of umem->odp_data->private to point to our
		 * MR, before reg_umr finished, to ensure that the MR
		 * initialization have finished before starting to
		 * handle invalidations.
		 */
		smp_wmb();
		mr->umem->odp_data->private = mr;
		/*
		 * Make sure we will see the new
		 * umem->odp_data->private value in the invalidation
		 * routines, before we can get page faults on the
		 * MR. Page faults can happen once we put the MR in
		 * the tree, below this line. Without the barrier,
		 * there can be a fault handling and an invalidation
		 * before umem->odp_data->private == mr is visible to
		 * the invalidation handler.
		 */
		smp_wmb();
	}
}
#endif

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static void reg_mr_callback(int status, void *context)
{
	struct mlx5_ib_mr *mr = context;
	struct mlx5_ib_dev *dev = mr->dev;
	struct mlx5_mr_cache *cache = &dev->cache;
	int c = order2idx(dev, mr->order);
	struct mlx5_cache_ent *ent = &cache->ent[c];
	u8 key;
	unsigned long flags;
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	struct mlx5_mkey_table *table = &dev->mdev->priv.mkey_table;
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	int err;
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	spin_lock_irqsave(&ent->lock, flags);
	ent->pending--;
	spin_unlock_irqrestore(&ent->lock, flags);
	if (status) {
		mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status);
		kfree(mr);
		dev->fill_delay = 1;
		mod_timer(&dev->delay_timer, jiffies + HZ);
		return;
	}

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	mr->mmkey.type = MLX5_MKEY_MR;
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	spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags);
	key = dev->mdev->priv.mkey_key++;
	spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags);
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	mr->mmkey.key = mlx5_idx_to_mkey(MLX5_GET(create_mkey_out, mr->out, mkey_index)) | key;
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	cache->last_add = jiffies;

	spin_lock_irqsave(&ent->lock, flags);
	list_add_tail(&mr->list, &ent->head);
	ent->cur++;
	ent->size++;
	spin_unlock_irqrestore(&ent->lock, flags);
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	write_lock_irqsave(&table->lock, flags);
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	err = radix_tree_insert(&table->tree, mlx5_base_mkey(mr->mmkey.key),
				&mr->mmkey);
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	if (err)
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		pr_err("Error inserting to mkey tree. 0x%x\n", -err);
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	write_unlock_irqrestore(&table->lock, flags);
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	if (!completion_done(&ent->compl))
		complete(&ent->compl);
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}

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static int add_keys(struct mlx5_ib_dev *dev, int c, int num)
{
	struct mlx5_mr_cache *cache = &dev->cache;
	struct mlx5_cache_ent *ent = &cache->ent[c];
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	int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
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	struct mlx5_ib_mr *mr;
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	void *mkc;
	u32 *in;
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	int err = 0;
	int i;

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	in = kzalloc(inlen, GFP_KERNEL);
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	if (!in)
		return -ENOMEM;

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	mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
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	for (i = 0; i < num; i++) {
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		if (ent->pending >= MAX_PENDING_REG_MR) {
			err = -EAGAIN;
			break;
		}

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		mr = kzalloc(sizeof(*mr), GFP_KERNEL);
		if (!mr) {
			err = -ENOMEM;
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			break;
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		}
		mr->order = ent->order;
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		mr->allocated_from_cache = 1;
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		mr->dev = dev;
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		MLX5_SET(mkc, mkc, free, 1);
		MLX5_SET(mkc, mkc, umr_en, 1);
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		MLX5_SET(mkc, mkc, access_mode, ent->access_mode);
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		MLX5_SET(mkc, mkc, qpn, 0xffffff);
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		MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt);
		MLX5_SET(mkc, mkc, log_page_size, ent->page);
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		spin_lock_irq(&ent->lock);
		ent->pending++;
		spin_unlock_irq(&ent->lock);
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		err = mlx5_core_create_mkey_cb(dev->mdev, &mr->mmkey,
					       in, inlen,
					       mr->out, sizeof(mr->out),
					       reg_mr_callback, mr);
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		if (err) {
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			spin_lock_irq(&ent->lock);
			ent->pending--;
			spin_unlock_irq(&ent->lock);
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			mlx5_ib_warn(dev, "create mkey failed %d\n", err);
			kfree(mr);
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			break;
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		}
	}

	kfree(in);
	return err;
}

static void remove_keys(struct mlx5_ib_dev *dev, int c, int num)
{
	struct mlx5_mr_cache *cache = &dev->cache;
	struct mlx5_cache_ent *ent = &cache->ent[c];
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	struct mlx5_ib_mr *tmp_mr;
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	struct mlx5_ib_mr *mr;
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	LIST_HEAD(del_list);
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	int i;

	for (i = 0; i < num; i++) {
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		spin_lock_irq(&ent->lock);
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		if (list_empty(&ent->head)) {
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			spin_unlock_irq(&ent->lock);
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			break;
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		}
		mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
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		list_move(&mr->list, &del_list);
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		ent->cur--;
		ent->size--;
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		spin_unlock_irq(&ent->lock);
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		mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey);
	}

#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
	synchronize_srcu(&dev->mr_srcu);
#endif

	list_for_each_entry_safe(mr, tmp_mr, &del_list, list) {
		list_del(&mr->list);
		kfree(mr);
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	}
}

static ssize_t size_write(struct file *filp, const char __user *buf,
			  size_t count, loff_t *pos)
{
	struct mlx5_cache_ent *ent = filp->private_data;
	struct mlx5_ib_dev *dev = ent->dev;
	char lbuf[20];
	u32 var;
	int err;
	int c;

	if (copy_from_user(lbuf, buf, sizeof(lbuf)))
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		return -EFAULT;
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	c = order2idx(dev, ent->order);
	lbuf[sizeof(lbuf) - 1] = 0;

	if (sscanf(lbuf, "%u", &var) != 1)
		return -EINVAL;

	if (var < ent->limit)
		return -EINVAL;

	if (var > ent->size) {
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		do {
			err = add_keys(dev, c, var - ent->size);
			if (err && err != -EAGAIN)
				return err;

			usleep_range(3000, 5000);
		} while (err);
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	} else if (var < ent->size) {
		remove_keys(dev, c, ent->size - var);
	}

	return count;
}

static ssize_t size_read(struct file *filp, char __user *buf, size_t count,
			 loff_t *pos)
{
	struct mlx5_cache_ent *ent = filp->private_data;
	char lbuf[20];
	int err;

	if (*pos)
		return 0;

	err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size);
	if (err < 0)
		return err;

	if (copy_to_user(buf, lbuf, err))
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		return -EFAULT;
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	*pos += err;

	return err;
}

static const struct file_operations size_fops = {
	.owner	= THIS_MODULE,
	.open	= simple_open,
	.write	= size_write,
	.read	= size_read,
};

static ssize_t limit_write(struct file *filp, const char __user *buf,
			   size_t count, loff_t *pos)
{
	struct mlx5_cache_ent *ent = filp->private_data;
	struct mlx5_ib_dev *dev = ent->dev;
	char lbuf[20];
	u32 var;
	int err;
	int c;

	if (copy_from_user(lbuf, buf, sizeof(lbuf)))
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		return -EFAULT;
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	c = order2idx(dev, ent->order);
	lbuf[sizeof(lbuf) - 1] = 0;

	if (sscanf(lbuf, "%u", &var) != 1)
		return -EINVAL;

	if (var > ent->size)
		return -EINVAL;

	ent->limit = var;

	if (ent->cur < ent->limit) {
		err = add_keys(dev, c, 2 * ent->limit - ent->cur);
		if (err)
			return err;
	}

	return count;
}

static ssize_t limit_read(struct file *filp, char __user *buf, size_t count,
			  loff_t *pos)
{
	struct mlx5_cache_ent *ent = filp->private_data;
	char lbuf[20];
	int err;

	if (*pos)
		return 0;

	err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit);
	if (err < 0)
		return err;

	if (copy_to_user(buf, lbuf, err))
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		return -EFAULT;
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	*pos += err;

	return err;
}

static const struct file_operations limit_fops = {
	.owner	= THIS_MODULE,
	.open	= simple_open,
	.write	= limit_write,
	.read	= limit_read,
};

static int someone_adding(struct mlx5_mr_cache *cache)
{
	int i;

	for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
		if (cache->ent[i].cur < cache->ent[i].limit)
			return 1;
	}

	return 0;
}

static void __cache_work_func(struct mlx5_cache_ent *ent)
{
	struct mlx5_ib_dev *dev = ent->dev;
	struct mlx5_mr_cache *cache = &dev->cache;
	int i = order2idx(dev, ent->order);
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	int err;
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	if (cache->stopped)
		return;

	ent = &dev->cache.ent[i];
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	if (ent->cur < 2 * ent->limit && !dev->fill_delay) {
		err = add_keys(dev, i, 1);
		if (ent->cur < 2 * ent->limit) {
			if (err == -EAGAIN) {
				mlx5_ib_dbg(dev, "returned eagain, order %d\n",
					    i + 2);
				queue_delayed_work(cache->wq, &ent->dwork,
						   msecs_to_jiffies(3));
			} else if (err) {
				mlx5_ib_warn(dev, "command failed order %d, err %d\n",
					     i + 2, err);
				queue_delayed_work(cache->wq, &ent->dwork,
						   msecs_to_jiffies(1000));
			} else {
				queue_work(cache->wq, &ent->work);
			}
		}
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	} else if (ent->cur > 2 * ent->limit) {
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		/*
		 * The remove_keys() logic is performed as garbage collection
		 * task. Such task is intended to be run when no other active
		 * processes are running.
		 *
		 * The need_resched() will return TRUE if there are user tasks
		 * to be activated in near future.
		 *
		 * In such case, we don't execute remove_keys() and postpone
		 * the garbage collection work to try to run in next cycle,
		 * in order to free CPU resources to other tasks.
		 */
		if (!need_resched() && !someone_adding(cache) &&
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		    time_after(jiffies, cache->last_add + 300 * HZ)) {
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			remove_keys(dev, i, 1);
			if (ent->cur > ent->limit)
				queue_work(cache->wq, &ent->work);
		} else {
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			queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ);
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		}
	}
}

static void delayed_cache_work_func(struct work_struct *work)
{
	struct mlx5_cache_ent *ent;

	ent = container_of(work, struct mlx5_cache_ent, dwork.work);
	__cache_work_func(ent);
}

static void cache_work_func(struct work_struct *work)
{
	struct mlx5_cache_ent *ent;

	ent = container_of(work, struct mlx5_cache_ent, work);
	__cache_work_func(ent);
}

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struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry)
{
	struct mlx5_mr_cache *cache = &dev->cache;
	struct mlx5_cache_ent *ent;
	struct mlx5_ib_mr *mr;
	int err;

	if (entry < 0 || entry >= MAX_MR_CACHE_ENTRIES) {
		mlx5_ib_err(dev, "cache entry %d is out of range\n", entry);
		return NULL;
	}

	ent = &cache->ent[entry];
	while (1) {
		spin_lock_irq(&ent->lock);
		if (list_empty(&ent->head)) {
			spin_unlock_irq(&ent->lock);

			err = add_keys(dev, entry, 1);
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			if (err && err != -EAGAIN)
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				return ERR_PTR(err);

			wait_for_completion(&ent->compl);
		} else {
			mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
					      list);
			list_del(&mr->list);
			ent->cur--;
			spin_unlock_irq(&ent->lock);
			if (ent->cur < ent->limit)
				queue_work(cache->wq, &ent->work);
			return mr;
		}
	}
}

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static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order)
{
	struct mlx5_mr_cache *cache = &dev->cache;
	struct mlx5_ib_mr *mr = NULL;
	struct mlx5_cache_ent *ent;
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	int last_umr_cache_entry;
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	int c;
	int i;

	c = order2idx(dev, order);
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	last_umr_cache_entry = order2idx(dev, mr_cache_max_order(dev));
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	if (c < 0 || c > last_umr_cache_entry) {
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		mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
		return NULL;
	}

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	for (i = c; i <= last_umr_cache_entry; i++) {
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		ent = &cache->ent[i];

		mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);

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		spin_lock_irq(&ent->lock);
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		if (!list_empty(&ent->head)) {
			mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
					      list);
			list_del(&mr->list);
			ent->cur--;
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			spin_unlock_irq(&ent->lock);
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			if (ent->cur < ent->limit)
				queue_work(cache->wq, &ent->work);
			break;
		}
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		spin_unlock_irq(&ent->lock);
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		queue_work(cache->wq, &ent->work);
	}

	if (!mr)
		cache->ent[c].miss++;

	return mr;
}

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void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
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{
	struct mlx5_mr_cache *cache = &dev->cache;
	struct mlx5_cache_ent *ent;
	int shrink = 0;
	int c;

	c = order2idx(dev, mr->order);
	if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
		mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c);
		return;
	}
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	if (unreg_umr(dev, mr))
		return;

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	ent = &cache->ent[c];
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	spin_lock_irq(&ent->lock);
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	list_add_tail(&mr->list, &ent->head);
	ent->cur++;
	if (ent->cur > 2 * ent->limit)
		shrink = 1;
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	spin_unlock_irq(&ent->lock);
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	if (shrink)
		queue_work(cache->wq, &ent->work);
}

static void clean_keys(struct mlx5_ib_dev *dev, int c)
{
	struct mlx5_mr_cache *cache = &dev->cache;
	struct mlx5_cache_ent *ent = &cache->ent[c];
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	struct mlx5_ib_mr *tmp_mr;
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	struct mlx5_ib_mr *mr;
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	LIST_HEAD(del_list);
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	cancel_delayed_work(&ent->dwork);
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	while (1) {
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		spin_lock_irq(&ent->lock);
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		if (list_empty(&ent->head)) {
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			spin_unlock_irq(&ent->lock);
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			break;
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		}
		mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
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		list_move(&mr->list, &del_list);
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		ent->cur--;
		ent->size--;
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		spin_unlock_irq(&ent->lock);
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		mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey);
	}

#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
	synchronize_srcu(&dev->mr_srcu);
#endif

	list_for_each_entry_safe(mr, tmp_mr, &del_list, list) {
		list_del(&mr->list);
		kfree(mr);
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	}
}

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static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev)
{
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	if (!mlx5_debugfs_root || dev->rep)
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		return;

	debugfs_remove_recursive(dev->cache.root);
	dev->cache.root = NULL;
}

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static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev)
{
	struct mlx5_mr_cache *cache = &dev->cache;
	struct mlx5_cache_ent *ent;
	int i;

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	if (!mlx5_debugfs_root || dev->rep)
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		return 0;

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	cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root);
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	if (!cache->root)
		return -ENOMEM;

	for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
		ent = &cache->ent[i];
		sprintf(ent->name, "%d", ent->order);
		ent->dir = debugfs_create_dir(ent->name,  cache->root);
		if (!ent->dir)
627
			goto err;
628 629 630 631

		ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent,
						 &size_fops);
		if (!ent->fsize)
632
			goto err;
633 634 635 636

		ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent,
						  &limit_fops);
		if (!ent->flimit)
637
			goto err;
638 639 640 641

		ent->fcur = debugfs_create_u32("cur", 0400, ent->dir,
					       &ent->cur);
		if (!ent->fcur)
642
			goto err;
643 644 645 646

		ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir,
						&ent->miss);
		if (!ent->fmiss)
647
			goto err;
648 649 650
	}

	return 0;
651 652
err:
	mlx5_mr_cache_debugfs_cleanup(dev);
653

654
	return -ENOMEM;
655 656
}

657
static void delay_time_func(struct timer_list *t)
E
Eli Cohen 已提交
658
{
659
	struct mlx5_ib_dev *dev = from_timer(dev, t, delay_timer);
E
Eli Cohen 已提交
660 661 662 663

	dev->fill_delay = 0;
}

664 665 666 667 668 669 670
int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
{
	struct mlx5_mr_cache *cache = &dev->cache;
	struct mlx5_cache_ent *ent;
	int err;
	int i;

671
	mutex_init(&dev->slow_path_mutex);
672
	cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM);
673 674 675 676 677
	if (!cache->wq) {
		mlx5_ib_warn(dev, "failed to create work queue\n");
		return -ENOMEM;
	}

678
	timer_setup(&dev->delay_timer, delay_time_func, 0);
679 680 681 682 683 684
	for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
		ent = &cache->ent[i];
		INIT_LIST_HEAD(&ent->head);
		spin_lock_init(&ent->lock);
		ent->order = i + 2;
		ent->dev = dev;
685
		ent->limit = 0;
686

687
		init_completion(&ent->compl);
688 689 690
		INIT_WORK(&ent->work, cache_work_func);
		INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
		queue_work(cache->wq, &ent->work);
691

692
		if (i > MR_CACHE_LAST_STD_ENTRY) {
693
			mlx5_odp_init_mr_cache_entry(ent);
694
			continue;
695
		}
696

697
		if (ent->order > mr_cache_max_order(dev))
698 699 700 701 702 703 704
			continue;

		ent->page = PAGE_SHIFT;
		ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) /
			   MLX5_IB_UMR_OCTOWORD;
		ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
		if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) &&
705
		    !dev->rep &&
706 707 708 709
		    mlx5_core_is_pf(dev->mdev))
			ent->limit = dev->mdev->profile->mr_cache[i].limit;
		else
			ent->limit = 0;
710 711 712 713 714 715
	}

	err = mlx5_mr_cache_debugfs_init(dev);
	if (err)
		mlx5_ib_warn(dev, "cache debugfs failure\n");

716 717 718 719 720
	/*
	 * We don't want to fail driver if debugfs failed to initialize,
	 * so we are not forwarding error to the user.
	 */

721 722 723
	return 0;
}

724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750
static void wait_for_async_commands(struct mlx5_ib_dev *dev)
{
	struct mlx5_mr_cache *cache = &dev->cache;
	struct mlx5_cache_ent *ent;
	int total = 0;
	int i;
	int j;

	for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
		ent = &cache->ent[i];
		for (j = 0 ; j < 1000; j++) {
			if (!ent->pending)
				break;
			msleep(50);
		}
	}
	for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
		ent = &cache->ent[i];
		total += ent->pending;
	}

	if (total)
		mlx5_ib_warn(dev, "aborted while there are %d pending mr requests\n", total);
	else
		mlx5_ib_warn(dev, "done with all pending requests\n");
}

751 752 753 754 755
int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
{
	int i;

	dev->cache.stopped = 1;
756
	flush_workqueue(dev->cache.wq);
757 758 759 760 761 762

	mlx5_mr_cache_debugfs_cleanup(dev);

	for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++)
		clean_keys(dev, i);

763
	destroy_workqueue(dev->cache.wq);
764
	wait_for_async_commands(dev);
E
Eli Cohen 已提交
765
	del_timer_sync(&dev->delay_timer);
766

767 768 769 770 771 772
	return 0;
}

struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc)
{
	struct mlx5_ib_dev *dev = to_mdev(pd->device);
773
	int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
774
	struct mlx5_core_dev *mdev = dev->mdev;
775
	struct mlx5_ib_mr *mr;
776 777
	void *mkc;
	u32 *in;
778 779 780 781 782 783
	int err;

	mr = kzalloc(sizeof(*mr), GFP_KERNEL);
	if (!mr)
		return ERR_PTR(-ENOMEM);

784
	in = kzalloc(inlen, GFP_KERNEL);
785 786 787 788 789
	if (!in) {
		err = -ENOMEM;
		goto err_free;
	}

790 791 792 793 794 795 796 797
	mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);

	MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_PA);
	MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC));
	MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE));
	MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ));
	MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE));
	MLX5_SET(mkc, mkc, lr, 1);
798

799 800 801 802 803 804
	MLX5_SET(mkc, mkc, length64, 1);
	MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
	MLX5_SET(mkc, mkc, qpn, 0xffffff);
	MLX5_SET64(mkc, mkc, start_addr, 0);

	err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen);
805 806 807 808
	if (err)
		goto err_in;

	kfree(in);
A
Artemy Kovalyov 已提交
809
	mr->mmkey.type = MLX5_MKEY_MR;
810 811
	mr->ibmr.lkey = mr->mmkey.key;
	mr->ibmr.rkey = mr->mmkey.key;
812 813 814 815 816 817 818 819 820 821 822 823 824
	mr->umem = NULL;

	return &mr->ibmr;

err_in:
	kfree(in);

err_free:
	kfree(mr);

	return ERR_PTR(err);
}

825
static int get_octo_len(u64 addr, u64 len, int page_shift)
826
{
827
	u64 page_size = 1ULL << page_shift;
828 829 830 831
	u64 offset;
	int npages;

	offset = addr & (page_size - 1);
832
	npages = ALIGN(len + offset, page_size) >> page_shift;
833 834 835
	return (npages + 1) / 2;
}

836
static int mr_cache_max_order(struct mlx5_ib_dev *dev)
837
{
838
	if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
839
		return MR_CACHE_LAST_STD_ENTRY + 2;
840 841 842
	return MLX5_MAX_UMR_SHIFT;
}

843 844 845 846
static int mr_umem_get(struct ib_pd *pd, u64 start, u64 length,
		       int access_flags, struct ib_umem **umem,
		       int *npages, int *page_shift, int *ncont,
		       int *order)
847 848
{
	struct mlx5_ib_dev *dev = to_mdev(pd->device);
849 850 851 852 853
	int err;

	*umem = ib_umem_get(pd->uobject->context, start, length,
			    access_flags, 0);
	err = PTR_ERR_OR_ZERO(*umem);
854 855
	if (err) {
		*umem = NULL;
D
Dan Carpenter 已提交
856
		mlx5_ib_err(dev, "umem get failed (%d)\n", err);
857
		return err;
858 859
	}

860
	mlx5_ib_cont_pages(*umem, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages,
861
			   page_shift, ncont, order);
862 863
	if (!*npages) {
		mlx5_ib_warn(dev, "avoid zero region\n");
864 865
		ib_umem_release(*umem);
		return -EINVAL;
866 867 868 869 870
	}

	mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n",
		    *npages, *ncont, *order, *page_shift);

871
	return 0;
872 873
}

874
static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc)
875
{
876 877
	struct mlx5_ib_umr_context *context =
		container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe);
878

879 880 881
	context->status = wc->status;
	complete(&context->done);
}
882

883 884 885 886 887
static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context)
{
	context->cqe.done = mlx5_ib_umr_done;
	context->status = -1;
	init_completion(&context->done);
888 889
}

890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916
static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev,
				  struct mlx5_umr_wr *umrwr)
{
	struct umr_common *umrc = &dev->umrc;
	struct ib_send_wr *bad;
	int err;
	struct mlx5_ib_umr_context umr_context;

	mlx5_ib_init_umr_context(&umr_context);
	umrwr->wr.wr_cqe = &umr_context.cqe;

	down(&umrc->sem);
	err = ib_post_send(umrc->qp, &umrwr->wr, &bad);
	if (err) {
		mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err);
	} else {
		wait_for_completion(&umr_context.done);
		if (umr_context.status != IB_WC_SUCCESS) {
			mlx5_ib_warn(dev, "reg umr failed (%u)\n",
				     umr_context.status);
			err = -EFAULT;
		}
	}
	up(&umrc->sem);
	return err;
}

917 918
static struct mlx5_ib_mr *alloc_mr_from_cache(
				  struct ib_pd *pd, struct ib_umem *umem,
919 920 921 922 923
				  u64 virt_addr, u64 len, int npages,
				  int page_shift, int order, int access_flags)
{
	struct mlx5_ib_dev *dev = to_mdev(pd->device);
	struct mlx5_ib_mr *mr;
924
	int err = 0;
925 926
	int i;

E
Eli Cohen 已提交
927
	for (i = 0; i < 1; i++) {
928 929 930 931 932
		mr = alloc_cached_mr(dev, order);
		if (mr)
			break;

		err = add_keys(dev, order2idx(dev, order), 1);
E
Eli Cohen 已提交
933 934
		if (err && err != -EAGAIN) {
			mlx5_ib_warn(dev, "add_keys failed, err %d\n", err);
935 936 937 938 939 940 941
			break;
		}
	}

	if (!mr)
		return ERR_PTR(-EAGAIN);

942 943 944 945
	mr->ibmr.pd = pd;
	mr->umem = umem;
	mr->access_flags = access_flags;
	mr->desc_size = sizeof(struct mlx5_mtt);
946 947 948
	mr->mmkey.iova = virt_addr;
	mr->mmkey.size = len;
	mr->mmkey.pd = to_mpd(pd)->pdn;
949

950 951 952
	return mr;
}

953 954 955
static inline int populate_xlt(struct mlx5_ib_mr *mr, int idx, int npages,
			       void *xlt, int page_shift, size_t size,
			       int flags)
956 957 958
{
	struct mlx5_ib_dev *dev = mr->dev;
	struct ib_umem *umem = mr->umem;
959 960 961 962
	if (flags & MLX5_IB_UPD_XLT_INDIRECT) {
		mlx5_odp_populate_klm(xlt, idx, npages, mr, flags);
		return npages;
	}
963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987

	npages = min_t(size_t, npages, ib_umem_num_pages(umem) - idx);

	if (!(flags & MLX5_IB_UPD_XLT_ZAP)) {
		__mlx5_ib_populate_pas(dev, umem, page_shift,
				       idx, npages, xlt,
				       MLX5_IB_MTT_PRESENT);
		/* Clear padding after the pages
		 * brought from the umem.
		 */
		memset(xlt + (npages * sizeof(struct mlx5_mtt)), 0,
		       size - npages * sizeof(struct mlx5_mtt));
	}

	return npages;
}

#define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \
			    MLX5_UMR_MTT_ALIGNMENT)
#define MLX5_SPARE_UMR_CHUNK 0x10000

int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
		       int page_shift, int flags)
{
	struct mlx5_ib_dev *dev = mr->dev;
988
	struct device *ddev = dev->ib_dev.dev.parent;
989
	int size;
990
	void *xlt;
991
	dma_addr_t dma;
C
Christoph Hellwig 已提交
992
	struct mlx5_umr_wr wr;
993 994
	struct ib_sge sg;
	int err = 0;
995 996 997
	int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT)
			       ? sizeof(struct mlx5_klm)
			       : sizeof(struct mlx5_mtt);
998 999
	const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size;
	const int page_mask = page_align - 1;
1000 1001 1002
	size_t pages_mapped = 0;
	size_t pages_to_map = 0;
	size_t pages_iter = 0;
1003
	gfp_t gfp;
1004
	bool use_emergency_page = false;
1005 1006

	/* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes,
1007 1008 1009 1010 1011
	 * so we need to align the offset and length accordingly
	 */
	if (idx & page_mask) {
		npages += idx & page_mask;
		idx &= ~page_mask;
1012 1013
	}

1014 1015
	gfp = flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : GFP_KERNEL;
	gfp |= __GFP_ZERO | __GFP_NOWARN;
1016

1017 1018 1019
	pages_to_map = ALIGN(npages, page_align);
	size = desc_size * pages_to_map;
	size = min_t(int, size, MLX5_MAX_UMR_CHUNK);
1020

1021 1022 1023 1024 1025 1026 1027
	xlt = (void *)__get_free_pages(gfp, get_order(size));
	if (!xlt && size > MLX5_SPARE_UMR_CHUNK) {
		mlx5_ib_dbg(dev, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n",
			    size, get_order(size), MLX5_SPARE_UMR_CHUNK);

		size = MLX5_SPARE_UMR_CHUNK;
		xlt = (void *)__get_free_pages(gfp, get_order(size));
1028
	}
1029 1030 1031

	if (!xlt) {
		mlx5_ib_warn(dev, "Using XLT emergency buffer\n");
1032
		xlt = (void *)mlx5_ib_get_xlt_emergency_page();
1033 1034
		size = PAGE_SIZE;
		memset(xlt, 0, size);
1035
		use_emergency_page = true;
1036 1037 1038
	}
	pages_iter = size / desc_size;
	dma = dma_map_single(ddev, xlt, size, DMA_TO_DEVICE);
1039
	if (dma_mapping_error(ddev, dma)) {
1040
		mlx5_ib_err(dev, "unable to map DMA during XLT update.\n");
1041
		err = -ENOMEM;
1042
		goto free_xlt;
1043 1044
	}

1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062
	sg.addr = dma;
	sg.lkey = dev->umrc.pd->local_dma_lkey;

	memset(&wr, 0, sizeof(wr));
	wr.wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT;
	if (!(flags & MLX5_IB_UPD_XLT_ENABLE))
		wr.wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE;
	wr.wr.sg_list = &sg;
	wr.wr.num_sge = 1;
	wr.wr.opcode = MLX5_IB_WR_UMR;

	wr.pd = mr->ibmr.pd;
	wr.mkey = mr->mmkey.key;
	wr.length = mr->mmkey.size;
	wr.virt_addr = mr->mmkey.iova;
	wr.access_flags = mr->access_flags;
	wr.page_shift = page_shift;

1063 1064
	for (pages_mapped = 0;
	     pages_mapped < pages_to_map && !err;
1065
	     pages_mapped += pages_iter, idx += pages_iter) {
1066
		npages = min_t(int, pages_iter, pages_to_map - pages_mapped);
1067
		dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE);
1068
		npages = populate_xlt(mr, idx, npages, xlt,
1069
				      page_shift, size, flags);
1070 1071 1072

		dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE);

1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089
		sg.length = ALIGN(npages * desc_size,
				  MLX5_UMR_MTT_ALIGNMENT);

		if (pages_mapped + pages_iter >= pages_to_map) {
			if (flags & MLX5_IB_UPD_XLT_ENABLE)
				wr.wr.send_flags |=
					MLX5_IB_SEND_UMR_ENABLE_MR |
					MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS |
					MLX5_IB_SEND_UMR_UPDATE_TRANSLATION;
			if (flags & MLX5_IB_UPD_XLT_PD ||
			    flags & MLX5_IB_UPD_XLT_ACCESS)
				wr.wr.send_flags |=
					MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
			if (flags & MLX5_IB_UPD_XLT_ADDR)
				wr.wr.send_flags |=
					MLX5_IB_SEND_UMR_UPDATE_TRANSLATION;
		}
1090

1091
		wr.offset = idx * desc_size;
1092
		wr.xlt_size = sg.length;
1093

1094
		err = mlx5_ib_post_send_wait(dev, &wr);
1095 1096 1097
	}
	dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE);

1098
free_xlt:
1099 1100
	if (use_emergency_page)
		mlx5_ib_put_xlt_emergency_page();
1101
	else
1102
		free_pages((unsigned long)xlt, get_order(size));
1103 1104 1105 1106

	return err;
}

1107 1108 1109 1110 1111 1112 1113
/*
 * If ibmr is NULL it will be allocated by reg_create.
 * Else, the given ibmr will be used.
 */
static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd,
				     u64 virt_addr, u64 length,
				     struct ib_umem *umem, int npages,
1114 1115
				     int page_shift, int access_flags,
				     bool populate)
1116 1117 1118
{
	struct mlx5_ib_dev *dev = to_mdev(pd->device);
	struct mlx5_ib_mr *mr;
1119 1120
	__be64 *pas;
	void *mkc;
1121
	int inlen;
1122
	u32 *in;
1123
	int err;
1124
	bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg));
1125

1126
	mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL);
1127 1128 1129
	if (!mr)
		return ERR_PTR(-ENOMEM);

1130 1131 1132 1133 1134 1135
	mr->ibmr.pd = pd;
	mr->access_flags = access_flags;

	inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
	if (populate)
		inlen += sizeof(*pas) * roundup(npages, 2);
1136
	in = kvzalloc(inlen, GFP_KERNEL);
1137 1138 1139 1140
	if (!in) {
		err = -ENOMEM;
		goto err_1;
	}
1141
	pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
1142
	if (populate && !(access_flags & IB_ACCESS_ON_DEMAND))
1143 1144
		mlx5_ib_populate_pas(dev, umem, page_shift, pas,
				     pg_cap ? MLX5_IB_MTT_PRESENT : 0);
1145

1146
	/* The pg_access bit allows setting the access flags
1147
	 * in the page list submitted with the command. */
1148 1149 1150
	MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap));

	mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1151
	MLX5_SET(mkc, mkc, free, !populate);
1152 1153 1154 1155 1156 1157
	MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_MTT);
	MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
	MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
	MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ));
	MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE));
	MLX5_SET(mkc, mkc, lr, 1);
1158
	MLX5_SET(mkc, mkc, umr_en, 1);
1159 1160 1161 1162 1163 1164

	MLX5_SET64(mkc, mkc, start_addr, virt_addr);
	MLX5_SET64(mkc, mkc, len, length);
	MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
	MLX5_SET(mkc, mkc, bsf_octword_size, 0);
	MLX5_SET(mkc, mkc, translations_octword_size,
1165
		 get_octo_len(virt_addr, length, page_shift));
1166 1167
	MLX5_SET(mkc, mkc, log_page_size, page_shift);
	MLX5_SET(mkc, mkc, qpn, 0xffffff);
1168 1169
	if (populate) {
		MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
1170
			 get_octo_len(virt_addr, length, page_shift));
1171
	}
1172 1173

	err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen);
1174 1175 1176 1177
	if (err) {
		mlx5_ib_warn(dev, "create mkey failed\n");
		goto err_2;
	}
A
Artemy Kovalyov 已提交
1178
	mr->mmkey.type = MLX5_MKEY_MR;
1179
	mr->desc_size = sizeof(struct mlx5_mtt);
1180
	mr->dev = dev;
A
Al Viro 已提交
1181
	kvfree(in);
1182

1183
	mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key);
1184 1185 1186 1187

	return mr;

err_2:
A
Al Viro 已提交
1188
	kvfree(in);
1189 1190

err_1:
1191 1192
	if (!ibmr)
		kfree(mr);
1193 1194 1195 1196

	return ERR_PTR(err);
}

1197 1198 1199 1200 1201
static void set_mr_fileds(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr,
			  int npages, u64 length, int access_flags)
{
	mr->npages = npages;
	atomic_add(npages, &dev->mdev->priv.reg_pages);
1202 1203
	mr->ibmr.lkey = mr->mmkey.key;
	mr->ibmr.rkey = mr->mmkey.key;
1204
	mr->ibmr.length = length;
1205
	mr->access_flags = access_flags;
1206 1207
}

1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219
struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
				  u64 virt_addr, int access_flags,
				  struct ib_udata *udata)
{
	struct mlx5_ib_dev *dev = to_mdev(pd->device);
	struct mlx5_ib_mr *mr = NULL;
	struct ib_umem *umem;
	int page_shift;
	int npages;
	int ncont;
	int order;
	int err;
1220
	bool use_umr = true;
1221

1222 1223 1224
	if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM))
		return ERR_PTR(-EINVAL);

1225 1226
	mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
		    start, virt_addr, length, access_flags);
1227 1228 1229 1230 1231 1232 1233 1234

#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
	if (!start && length == U64_MAX) {
		if (!(access_flags & IB_ACCESS_ON_DEMAND) ||
		    !(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT))
			return ERR_PTR(-EINVAL);

		mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), access_flags);
1235 1236
		if (IS_ERR(mr))
			return ERR_CAST(mr);
1237 1238 1239 1240
		return &mr->ibmr;
	}
#endif

1241
	err = mr_umem_get(pd, start, length, access_flags, &umem, &npages,
1242
			   &page_shift, &ncont, &order);
1243

1244
	if (err < 0)
1245
		return ERR_PTR(err);
1246

1247
	if (order <= mr_cache_max_order(dev)) {
1248 1249
		mr = alloc_mr_from_cache(pd, umem, virt_addr, length, ncont,
					 page_shift, order, access_flags);
1250
		if (PTR_ERR(mr) == -EAGAIN) {
1251
			mlx5_ib_dbg(dev, "cache empty for order %d\n", order);
1252 1253
			mr = NULL;
		}
1254 1255 1256
	} else if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) {
		if (access_flags & IB_ACCESS_ON_DEMAND) {
			err = -EINVAL;
1257
			pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB\n");
1258 1259 1260
			goto error;
		}
		use_umr = false;
1261 1262
	}

1263 1264
	if (!mr) {
		mutex_lock(&dev->slow_path_mutex);
1265
		mr = reg_create(NULL, pd, virt_addr, length, umem, ncont,
1266
				page_shift, access_flags, !use_umr);
1267 1268
		mutex_unlock(&dev->slow_path_mutex);
	}
1269 1270 1271 1272 1273 1274

	if (IS_ERR(mr)) {
		err = PTR_ERR(mr);
		goto error;
	}

1275
	mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key);
1276 1277

	mr->umem = umem;
1278
	set_mr_fileds(dev, mr, npages, length, access_flags);
1279

1280
#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1281
	update_odp_mr(mr);
1282 1283
#endif

1284 1285 1286 1287 1288
	if (use_umr) {
		int update_xlt_flags = MLX5_IB_UPD_XLT_ENABLE;

		if (access_flags & IB_ACCESS_ON_DEMAND)
			update_xlt_flags |= MLX5_IB_UPD_XLT_ZAP;
1289

1290 1291
		err = mlx5_ib_update_xlt(mr, 0, ncont, page_shift,
					 update_xlt_flags);
1292

1293
		if (err) {
1294
			dereg_mr(dev, mr);
1295 1296 1297 1298 1299 1300
			return ERR_PTR(err);
		}
	}

	mr->live = 1;
	return &mr->ibmr;
1301 1302 1303 1304 1305 1306 1307
error:
	ib_umem_release(umem);
	return ERR_PTR(err);
}

static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
{
1308
	struct mlx5_core_dev *mdev = dev->mdev;
1309
	struct mlx5_umr_wr umrwr = {};
1310

1311 1312 1313
	if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
		return 0;

1314 1315 1316 1317
	umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR |
			      MLX5_IB_SEND_UMR_FAIL_IF_FREE;
	umrwr.wr.opcode = MLX5_IB_WR_UMR;
	umrwr.mkey = mr->mmkey.key;
1318

1319
	return mlx5_ib_post_send_wait(dev, &umrwr);
1320 1321
}

1322
static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1323 1324 1325 1326 1327 1328 1329 1330
		     int access_flags, int flags)
{
	struct mlx5_ib_dev *dev = to_mdev(pd->device);
	struct mlx5_umr_wr umrwr = {};
	int err;

	umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE;

1331 1332
	umrwr.wr.opcode = MLX5_IB_WR_UMR;
	umrwr.mkey = mr->mmkey.key;
1333

1334
	if (flags & IB_MR_REREG_PD || flags & IB_MR_REREG_ACCESS) {
1335 1336
		umrwr.pd = pd;
		umrwr.access_flags = access_flags;
1337
		umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
1338 1339
	}

1340
	err = mlx5_ib_post_send_wait(dev, &umrwr);
1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357

	return err;
}

int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
			  u64 length, u64 virt_addr, int new_access_flags,
			  struct ib_pd *new_pd, struct ib_udata *udata)
{
	struct mlx5_ib_dev *dev = to_mdev(ib_mr->device);
	struct mlx5_ib_mr *mr = to_mmr(ib_mr);
	struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd;
	int access_flags = flags & IB_MR_REREG_ACCESS ?
			    new_access_flags :
			    mr->access_flags;
	u64 addr = (flags & IB_MR_REREG_TRANS) ? virt_addr : mr->umem->address;
	u64 len = (flags & IB_MR_REREG_TRANS) ? length : mr->umem->length;
	int page_shift = 0;
1358
	int upd_flags = 0;
1359 1360 1361 1362 1363 1364 1365 1366
	int npages = 0;
	int ncont = 0;
	int order = 0;
	int err;

	mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
		    start, virt_addr, length, access_flags);

1367 1368
	atomic_sub(mr->npages, &dev->mdev->priv.reg_pages);

1369 1370 1371 1372 1373 1374 1375
	if (flags != IB_MR_REREG_PD) {
		/*
		 * Replace umem. This needs to be done whether or not UMR is
		 * used.
		 */
		flags |= IB_MR_REREG_TRANS;
		ib_umem_release(mr->umem);
1376 1377 1378
		err = mr_umem_get(pd, addr, len, access_flags, &mr->umem,
				  &npages, &page_shift, &ncont, &order);
		if (err < 0) {
1379
			clean_mr(dev, mr);
1380 1381 1382 1383 1384 1385 1386 1387
			return err;
		}
	}

	if (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len)) {
		/*
		 * UMR can't be used - MKey needs to be replaced.
		 */
1388
		if (mr->allocated_from_cache) {
1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400
			err = unreg_umr(dev, mr);
			if (err)
				mlx5_ib_warn(dev, "Failed to unregister MR\n");
		} else {
			err = destroy_mkey(dev, mr);
			if (err)
				mlx5_ib_warn(dev, "Failed to destroy MKey\n");
		}
		if (err)
			return err;

		mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont,
1401
				page_shift, access_flags, true);
1402 1403 1404 1405

		if (IS_ERR(mr))
			return PTR_ERR(mr);

1406
		mr->allocated_from_cache = 0;
1407
		mr->live = 1;
1408 1409 1410 1411
	} else {
		/*
		 * Send a UMR WQE
		 */
1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429
		mr->ibmr.pd = pd;
		mr->access_flags = access_flags;
		mr->mmkey.iova = addr;
		mr->mmkey.size = len;
		mr->mmkey.pd = to_mpd(pd)->pdn;

		if (flags & IB_MR_REREG_TRANS) {
			upd_flags = MLX5_IB_UPD_XLT_ADDR;
			if (flags & IB_MR_REREG_PD)
				upd_flags |= MLX5_IB_UPD_XLT_PD;
			if (flags & IB_MR_REREG_ACCESS)
				upd_flags |= MLX5_IB_UPD_XLT_ACCESS;
			err = mlx5_ib_update_xlt(mr, 0, npages, page_shift,
						 upd_flags);
		} else {
			err = rereg_umr(pd, mr, access_flags, flags);
		}

1430 1431
		if (err) {
			mlx5_ib_warn(dev, "Failed to rereg UMR\n");
1432
			ib_umem_release(mr->umem);
1433
			mr->umem = NULL;
1434
			clean_mr(dev, mr);
1435 1436 1437 1438
			return err;
		}
	}

1439
	set_mr_fileds(dev, mr, npages, len, access_flags);
1440 1441 1442 1443 1444 1445 1446

#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
	update_odp_mr(mr);
#endif
	return 0;
}

1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464
static int
mlx5_alloc_priv_descs(struct ib_device *device,
		      struct mlx5_ib_mr *mr,
		      int ndescs,
		      int desc_size)
{
	int size = ndescs * desc_size;
	int add_size;
	int ret;

	add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0);

	mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL);
	if (!mr->descs_alloc)
		return -ENOMEM;

	mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN);

1465
	mr->desc_map = dma_map_single(device->dev.parent, mr->descs,
1466
				      size, DMA_TO_DEVICE);
1467
	if (dma_mapping_error(device->dev.parent, mr->desc_map)) {
1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485
		ret = -ENOMEM;
		goto err;
	}

	return 0;
err:
	kfree(mr->descs_alloc);

	return ret;
}

static void
mlx5_free_priv_descs(struct mlx5_ib_mr *mr)
{
	if (mr->descs) {
		struct ib_device *device = mr->ibmr.device;
		int size = mr->max_descs * mr->desc_size;

1486
		dma_unmap_single(device->dev.parent, mr->desc_map,
1487 1488 1489 1490 1491 1492
				 size, DMA_TO_DEVICE);
		kfree(mr->descs_alloc);
		mr->descs = NULL;
	}
}

1493
static int clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
1494
{
1495
	int allocated_from_cache = mr->allocated_from_cache;
1496 1497
	int err;

1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510
	if (mr->sig) {
		if (mlx5_core_destroy_psv(dev->mdev,
					  mr->sig->psv_memory.psv_idx))
			mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
				     mr->sig->psv_memory.psv_idx);
		if (mlx5_core_destroy_psv(dev->mdev,
					  mr->sig->psv_wire.psv_idx))
			mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
				     mr->sig->psv_wire.psv_idx);
		kfree(mr->sig);
		mr->sig = NULL;
	}

1511 1512
	mlx5_free_priv_descs(mr);

1513
	if (!allocated_from_cache) {
1514 1515
		u32 key = mr->mmkey.key;

1516
		err = destroy_mkey(dev, mr);
1517 1518
		if (err) {
			mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n",
1519
				     key, err);
1520 1521 1522 1523
			return err;
		}
	}

1524 1525 1526
	return 0;
}

1527
static int dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
1528 1529 1530 1531 1532
{
	int npages = mr->npages;
	struct ib_umem *umem = mr->umem;

#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1533 1534 1535
	if (umem && umem->odp_data) {
		/* Prevent new page faults from succeeding */
		mr->live = 0;
1536 1537
		/* Wait for all running page-fault handlers to finish. */
		synchronize_srcu(&dev->mr_srcu);
1538
		/* Destroy all page mappings */
1539 1540 1541 1542 1543
		if (umem->odp_data->page_list)
			mlx5_ib_invalidate_range(umem, ib_umem_start(umem),
						 ib_umem_end(umem));
		else
			mlx5_ib_free_implicit_mr(mr);
1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554
		/*
		 * We kill the umem before the MR for ODP,
		 * so that there will not be any invalidations in
		 * flight, looking at the *mr struct.
		 */
		ib_umem_release(umem);
		atomic_sub(npages, &dev->mdev->priv.reg_pages);

		/* Avoid double-freeing the umem. */
		umem = NULL;
	}
1555 1556
#endif

1557
	clean_mr(dev, mr);
1558

1559 1560
	if (umem) {
		ib_umem_release(umem);
1561
		atomic_sub(npages, &dev->mdev->priv.reg_pages);
1562 1563
	}

1564 1565 1566 1567 1568
	if (!mr->allocated_from_cache)
		kfree(mr);
	else
		mlx5_mr_cache_free(dev, mr);

1569 1570 1571
	return 0;
}

1572 1573 1574 1575 1576 1577 1578 1579
int mlx5_ib_dereg_mr(struct ib_mr *ibmr)
{
	struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
	struct mlx5_ib_mr *mr = to_mmr(ibmr);

	return dereg_mr(dev, mr);
}

S
Sagi Grimberg 已提交
1580 1581 1582
struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd,
			       enum ib_mr_type mr_type,
			       u32 max_num_sg)
1583 1584
{
	struct mlx5_ib_dev *dev = to_mdev(pd->device);
1585
	int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1586
	int ndescs = ALIGN(max_num_sg, 4);
1587 1588 1589
	struct mlx5_ib_mr *mr;
	void *mkc;
	u32 *in;
1590
	int err;
1591 1592 1593 1594 1595

	mr = kzalloc(sizeof(*mr), GFP_KERNEL);
	if (!mr)
		return ERR_PTR(-ENOMEM);

1596
	in = kzalloc(inlen, GFP_KERNEL);
1597 1598 1599 1600 1601
	if (!in) {
		err = -ENOMEM;
		goto err_free;
	}

1602 1603 1604 1605 1606
	mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
	MLX5_SET(mkc, mkc, free, 1);
	MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
	MLX5_SET(mkc, mkc, qpn, 0xffffff);
	MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1607

S
Sagi Grimberg 已提交
1608
	if (mr_type == IB_MR_TYPE_MEM_REG) {
1609 1610
		mr->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
		MLX5_SET(mkc, mkc, log_page_size, PAGE_SHIFT);
1611
		err = mlx5_alloc_priv_descs(pd->device, mr,
1612
					    ndescs, sizeof(struct mlx5_mtt));
1613 1614 1615
		if (err)
			goto err_free_in;

1616
		mr->desc_size = sizeof(struct mlx5_mtt);
1617
		mr->max_descs = ndescs;
1618
	} else if (mr_type == IB_MR_TYPE_SG_GAPS) {
1619
		mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS;
1620 1621 1622 1623 1624 1625 1626

		err = mlx5_alloc_priv_descs(pd->device, mr,
					    ndescs, sizeof(struct mlx5_klm));
		if (err)
			goto err_free_in;
		mr->desc_size = sizeof(struct mlx5_klm);
		mr->max_descs = ndescs;
S
Sagi Grimberg 已提交
1627
	} else if (mr_type == IB_MR_TYPE_SIGNATURE) {
1628 1629
		u32 psv_index[2];

1630 1631
		MLX5_SET(mkc, mkc, bsf_en, 1);
		MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE);
1632 1633 1634 1635 1636 1637 1638
		mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL);
		if (!mr->sig) {
			err = -ENOMEM;
			goto err_free_in;
		}

		/* create mem & wire PSVs */
1639
		err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn,
1640 1641 1642 1643
					   2, psv_index);
		if (err)
			goto err_free_sig;

1644
		mr->access_mode = MLX5_MKC_ACCESS_MODE_KLMS;
1645 1646
		mr->sig->psv_memory.psv_idx = psv_index[0];
		mr->sig->psv_wire.psv_idx = psv_index[1];
1647 1648 1649 1650 1651

		mr->sig->sig_status_checked = true;
		mr->sig->sig_err_exists = false;
		/* Next UMR, Arm SIGERR */
		++mr->sig->sigerr_count;
S
Sagi Grimberg 已提交
1652 1653 1654 1655
	} else {
		mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type);
		err = -EINVAL;
		goto err_free_in;
1656 1657
	}

1658 1659 1660
	MLX5_SET(mkc, mkc, access_mode, mr->access_mode);
	MLX5_SET(mkc, mkc, umr_en, 1);

1661
	mr->ibmr.device = pd->device;
1662
	err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen);
1663 1664 1665
	if (err)
		goto err_destroy_psv;

A
Artemy Kovalyov 已提交
1666
	mr->mmkey.type = MLX5_MKEY_MR;
1667 1668
	mr->ibmr.lkey = mr->mmkey.key;
	mr->ibmr.rkey = mr->mmkey.key;
1669 1670 1671 1672 1673 1674 1675
	mr->umem = NULL;
	kfree(in);

	return &mr->ibmr;

err_destroy_psv:
	if (mr->sig) {
1676
		if (mlx5_core_destroy_psv(dev->mdev,
1677 1678 1679
					  mr->sig->psv_memory.psv_idx))
			mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
				     mr->sig->psv_memory.psv_idx);
1680
		if (mlx5_core_destroy_psv(dev->mdev,
1681 1682 1683 1684
					  mr->sig->psv_wire.psv_idx))
			mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
				     mr->sig->psv_wire.psv_idx);
	}
1685
	mlx5_free_priv_descs(mr);
1686 1687 1688 1689 1690 1691 1692 1693 1694
err_free_sig:
	kfree(mr->sig);
err_free_in:
	kfree(in);
err_free:
	kfree(mr);
	return ERR_PTR(err);
}

1695 1696 1697 1698
struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
			       struct ib_udata *udata)
{
	struct mlx5_ib_dev *dev = to_mdev(pd->device);
1699
	int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1700
	struct mlx5_ib_mw *mw = NULL;
1701 1702
	u32 *in = NULL;
	void *mkc;
1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725
	int ndescs;
	int err;
	struct mlx5_ib_alloc_mw req = {};
	struct {
		__u32	comp_mask;
		__u32	response_length;
	} resp = {};

	err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
	if (err)
		return ERR_PTR(err);

	if (req.comp_mask || req.reserved1 || req.reserved2)
		return ERR_PTR(-EOPNOTSUPP);

	if (udata->inlen > sizeof(req) &&
	    !ib_is_udata_cleared(udata, sizeof(req),
				 udata->inlen - sizeof(req)))
		return ERR_PTR(-EOPNOTSUPP);

	ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4);

	mw = kzalloc(sizeof(*mw), GFP_KERNEL);
1726
	in = kzalloc(inlen, GFP_KERNEL);
1727 1728 1729 1730 1731
	if (!mw || !in) {
		err = -ENOMEM;
		goto free;
	}

1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743
	mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);

	MLX5_SET(mkc, mkc, free, 1);
	MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
	MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
	MLX5_SET(mkc, mkc, umr_en, 1);
	MLX5_SET(mkc, mkc, lr, 1);
	MLX5_SET(mkc, mkc, access_mode, MLX5_MKC_ACCESS_MODE_KLMS);
	MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2)));
	MLX5_SET(mkc, mkc, qpn, 0xffffff);

	err = mlx5_core_create_mkey(dev->mdev, &mw->mmkey, in, inlen);
1744 1745 1746
	if (err)
		goto free;

A
Artemy Kovalyov 已提交
1747
	mw->mmkey.type = MLX5_MKEY_MW;
1748
	mw->ibmw.rkey = mw->mmkey.key;
A
Artemy Kovalyov 已提交
1749
	mw->ndescs = ndescs;
1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781

	resp.response_length = min(offsetof(typeof(resp), response_length) +
				   sizeof(resp.response_length), udata->outlen);
	if (resp.response_length) {
		err = ib_copy_to_udata(udata, &resp, resp.response_length);
		if (err) {
			mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey);
			goto free;
		}
	}

	kfree(in);
	return &mw->ibmw;

free:
	kfree(mw);
	kfree(in);
	return ERR_PTR(err);
}

int mlx5_ib_dealloc_mw(struct ib_mw *mw)
{
	struct mlx5_ib_mw *mmw = to_mmw(mw);
	int err;

	err =  mlx5_core_destroy_mkey((to_mdev(mw->device))->mdev,
				      &mmw->mmkey);
	if (!err)
		kfree(mmw);
	return err;
}

1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821
int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
			    struct ib_mr_status *mr_status)
{
	struct mlx5_ib_mr *mmr = to_mmr(ibmr);
	int ret = 0;

	if (check_mask & ~IB_MR_CHECK_SIG_STATUS) {
		pr_err("Invalid status check mask\n");
		ret = -EINVAL;
		goto done;
	}

	mr_status->fail_status = 0;
	if (check_mask & IB_MR_CHECK_SIG_STATUS) {
		if (!mmr->sig) {
			ret = -EINVAL;
			pr_err("signature status check requested on a non-signature enabled MR\n");
			goto done;
		}

		mmr->sig->sig_status_checked = true;
		if (!mmr->sig->sig_err_exists)
			goto done;

		if (ibmr->lkey == mmr->sig->err_item.key)
			memcpy(&mr_status->sig_err, &mmr->sig->err_item,
			       sizeof(mr_status->sig_err));
		else {
			mr_status->sig_err.err_type = IB_SIG_BAD_GUARD;
			mr_status->sig_err.sig_err_offset = 0;
			mr_status->sig_err.key = mmr->sig->err_item.key;
		}

		mmr->sig->sig_err_exists = false;
		mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS;
	}

done:
	return ret;
}
1822

1823 1824 1825
static int
mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr,
		   struct scatterlist *sgl,
1826
		   unsigned short sg_nents,
1827
		   unsigned int *sg_offset_p)
1828 1829 1830
{
	struct scatterlist *sg = sgl;
	struct mlx5_klm *klms = mr->descs;
1831
	unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0;
1832 1833 1834
	u32 lkey = mr->ibmr.pd->local_dma_lkey;
	int i;

1835
	mr->ibmr.iova = sg_dma_address(sg) + sg_offset;
1836 1837 1838
	mr->ibmr.length = 0;

	for_each_sg(sgl, sg, sg_nents, i) {
1839
		if (unlikely(i >= mr->max_descs))
1840
			break;
1841 1842
		klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset);
		klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset);
1843
		klms[i].key = cpu_to_be32(lkey);
1844
		mr->ibmr.length += sg_dma_len(sg) - sg_offset;
1845 1846

		sg_offset = 0;
1847
	}
1848
	mr->ndescs = i;
1849

1850 1851 1852
	if (sg_offset_p)
		*sg_offset_p = sg_offset;

1853 1854 1855
	return i;
}

1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869
static int mlx5_set_page(struct ib_mr *ibmr, u64 addr)
{
	struct mlx5_ib_mr *mr = to_mmr(ibmr);
	__be64 *descs;

	if (unlikely(mr->ndescs == mr->max_descs))
		return -ENOMEM;

	descs = mr->descs;
	descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR);

	return 0;
}

1870
int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1871
		      unsigned int *sg_offset)
1872 1873 1874 1875 1876 1877 1878 1879 1880 1881
{
	struct mlx5_ib_mr *mr = to_mmr(ibmr);
	int n;

	mr->ndescs = 0;

	ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map,
				   mr->desc_size * mr->max_descs,
				   DMA_TO_DEVICE);

1882
	if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
1883
		n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset);
1884
	else
1885 1886
		n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset,
				mlx5_set_page);
1887 1888 1889 1890 1891 1892 1893

	ib_dma_sync_single_for_device(ibmr->device, mr->desc_map,
				      mr->desc_size * mr->max_descs,
				      DMA_TO_DEVICE);

	return n;
}