time_64.c 3.2 KB
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/*
 *  "High Precision Event Timer" based timekeeping.
 *
 *  Copyright (c) 1991,1992,1995  Linus Torvalds
 *  Copyright (c) 1994  Alan Modra
 *  Copyright (c) 1995  Markus Kuhn
 *  Copyright (c) 1996  Ingo Molnar
 *  Copyright (c) 1998  Andrea Arcangeli
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 *  Copyright (c) 2002,2006  Vojtech Pavlik
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 *  Copyright (c) 2003  Andi Kleen
 *  RTC support code taken from arch/i386/kernel/timers/time_hpet.c
 */

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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/time.h>
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#include <asm/i8253.h>
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#include <asm/hpet.h>
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#include <asm/nmi.h>
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#include <asm/vgtod.h>
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#include <asm/time.h>
#include <asm/timer.h>
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volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES;

unsigned long profile_pc(struct pt_regs *regs)
{
	unsigned long pc = instruction_pointer(regs);

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	/* Assume the lock function has either no stack frame or a copy
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	   of flags from PUSHF
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	   Eflags always has bits 22 and up cleared unlike kernel addresses. */
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	if (!user_mode_vm(regs) && in_lock_functions(pc)) {
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#ifdef CONFIG_FRAME_POINTER
		return *(unsigned long *)(regs->bp + sizeof(long));
#else
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		unsigned long *sp = (unsigned long *)regs->sp;
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		if (sp[0] >> 22)
			return sp[0];
		if (sp[1] >> 22)
			return sp[1];
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#endif
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	}
	return pc;
}
EXPORT_SYMBOL(profile_pc);

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static irqreturn_t timer_event_interrupt(int irq, void *dev_id)
{
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	add_pda(irq0_irqs, 1);

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	global_clock_event->event_handler(global_clock_event);

	return IRQ_HANDLED;
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}

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/* calibrate_cpu is used on systems with fixed rate TSCs to determine
 * processor frequency */
#define TICK_COUNT 100000000
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unsigned long __init calibrate_cpu(void)
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{
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	int tsc_start, tsc_now;
	int i, no_ctr_free;
	unsigned long evntsel3 = 0, pmc3 = 0, pmc_now = 0;
	unsigned long flags;

	for (i = 0; i < 4; i++)
		if (avail_to_resrv_perfctr_nmi_bit(i))
			break;
	no_ctr_free = (i == 4);
	if (no_ctr_free) {
		i = 3;
		rdmsrl(MSR_K7_EVNTSEL3, evntsel3);
		wrmsrl(MSR_K7_EVNTSEL3, 0);
		rdmsrl(MSR_K7_PERFCTR3, pmc3);
	} else {
		reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i);
		reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
	}
	local_irq_save(flags);
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	/* start measuring cycles, incrementing from 0 */
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	wrmsrl(MSR_K7_PERFCTR0 + i, 0);
	wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76);
	rdtscl(tsc_start);
	do {
		rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now);
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		tsc_now = get_cycles();
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	} while ((tsc_now - tsc_start) < TICK_COUNT);

	local_irq_restore(flags);
	if (no_ctr_free) {
		wrmsrl(MSR_K7_EVNTSEL3, 0);
		wrmsrl(MSR_K7_PERFCTR3, pmc3);
		wrmsrl(MSR_K7_EVNTSEL3, evntsel3);
	} else {
		release_perfctr_nmi(MSR_K7_PERFCTR0 + i);
		release_evntsel_nmi(MSR_K7_EVNTSEL0 + i);
	}

	return pmc_now * tsc_khz / (tsc_now - tsc_start);
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}
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static struct irqaction irq0 = {
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	.handler	= timer_event_interrupt,
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	.flags		= IRQF_DISABLED | IRQF_IRQPOLL | IRQF_NOBALANCING,
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	.mask		= CPU_MASK_NONE,
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	.name		= "timer"
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};

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void __init hpet_time_init(void)
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{
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	if (!hpet_enable())
		setup_pit_timer();
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	irq0.mask = cpumask_of_cpu(0);
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	setup_irq(0, &irq0);
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}
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void __init time_init(void)
{
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	tsc_init();
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	if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
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		vgetcpu_mode = VGETCPU_RDTSCP;
	else
		vgetcpu_mode = VGETCPU_LSL;

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	late_time_init = choose_time_init();
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}