omapdss.h 28.0 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
/*
 * Copyright (C) 2008 Nokia Corporation
 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published by
 * the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */

18 19
#ifndef __OMAP_OMAPDSS_H
#define __OMAP_OMAPDSS_H
20 21 22 23

#include <linux/list.h>
#include <linux/kobject.h>
#include <linux/device.h>
T
Tomi Valkeinen 已提交
24
#include <linux/interrupt.h>
25

26 27
#include <video/videomode.h>

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
#define DISPC_IRQ_FRAMEDONE		(1 << 0)
#define DISPC_IRQ_VSYNC			(1 << 1)
#define DISPC_IRQ_EVSYNC_EVEN		(1 << 2)
#define DISPC_IRQ_EVSYNC_ODD		(1 << 3)
#define DISPC_IRQ_ACBIAS_COUNT_STAT	(1 << 4)
#define DISPC_IRQ_PROG_LINE_NUM		(1 << 5)
#define DISPC_IRQ_GFX_FIFO_UNDERFLOW	(1 << 6)
#define DISPC_IRQ_GFX_END_WIN		(1 << 7)
#define DISPC_IRQ_PAL_GAMMA_MASK	(1 << 8)
#define DISPC_IRQ_OCP_ERR		(1 << 9)
#define DISPC_IRQ_VID1_FIFO_UNDERFLOW	(1 << 10)
#define DISPC_IRQ_VID1_END_WIN		(1 << 11)
#define DISPC_IRQ_VID2_FIFO_UNDERFLOW	(1 << 12)
#define DISPC_IRQ_VID2_END_WIN		(1 << 13)
#define DISPC_IRQ_SYNC_LOST		(1 << 14)
#define DISPC_IRQ_SYNC_LOST_DIGIT	(1 << 15)
#define DISPC_IRQ_WAKEUP		(1 << 16)
45 46
#define DISPC_IRQ_SYNC_LOST2		(1 << 17)
#define DISPC_IRQ_VSYNC2		(1 << 18)
47 48
#define DISPC_IRQ_VID3_END_WIN		(1 << 19)
#define DISPC_IRQ_VID3_FIFO_UNDERFLOW	(1 << 20)
49 50
#define DISPC_IRQ_ACBIAS_COUNT_STAT2	(1 << 21)
#define DISPC_IRQ_FRAMEDONE2		(1 << 22)
51 52 53
#define DISPC_IRQ_FRAMEDONEWB		(1 << 23)
#define DISPC_IRQ_FRAMEDONETV		(1 << 24)
#define DISPC_IRQ_WBBUFFEROVERFLOW	(1 << 25)
54 55 56 57
#define DISPC_IRQ_SYNC_LOST3		(1 << 27)
#define DISPC_IRQ_VSYNC3		(1 << 28)
#define DISPC_IRQ_ACBIAS_COUNT_STAT3	(1 << 29)
#define DISPC_IRQ_FRAMEDONE3		(1 << 30)
58 59 60

struct omap_dss_device;
struct omap_overlay_manager;
61
struct dss_lcd_mgr_config;
62 63
struct snd_aes_iec958;
struct snd_cea_861_aud_if;
64 65 66 67 68 69 70 71

enum omap_display_type {
	OMAP_DISPLAY_TYPE_NONE		= 0,
	OMAP_DISPLAY_TYPE_DPI		= 1 << 0,
	OMAP_DISPLAY_TYPE_DBI		= 1 << 1,
	OMAP_DISPLAY_TYPE_SDI		= 1 << 2,
	OMAP_DISPLAY_TYPE_DSI		= 1 << 3,
	OMAP_DISPLAY_TYPE_VENC		= 1 << 4,
72
	OMAP_DISPLAY_TYPE_HDMI		= 1 << 5,
73 74 75 76 77
};

enum omap_plane {
	OMAP_DSS_GFX	= 0,
	OMAP_DSS_VIDEO1	= 1,
78 79
	OMAP_DSS_VIDEO2	= 2,
	OMAP_DSS_VIDEO3	= 3,
80
	OMAP_DSS_WB	= 4,
81 82 83 84 85
};

enum omap_channel {
	OMAP_DSS_CHANNEL_LCD	= 0,
	OMAP_DSS_CHANNEL_DIGIT	= 1,
86
	OMAP_DSS_CHANNEL_LCD2	= 2,
87
	OMAP_DSS_CHANNEL_LCD3	= 3,
88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
};

enum omap_color_mode {
	OMAP_DSS_COLOR_CLUT1	= 1 << 0,  /* BITMAP 1 */
	OMAP_DSS_COLOR_CLUT2	= 1 << 1,  /* BITMAP 2 */
	OMAP_DSS_COLOR_CLUT4	= 1 << 2,  /* BITMAP 4 */
	OMAP_DSS_COLOR_CLUT8	= 1 << 3,  /* BITMAP 8 */
	OMAP_DSS_COLOR_RGB12U	= 1 << 4,  /* RGB12, 16-bit container */
	OMAP_DSS_COLOR_ARGB16	= 1 << 5,  /* ARGB16 */
	OMAP_DSS_COLOR_RGB16	= 1 << 6,  /* RGB16 */
	OMAP_DSS_COLOR_RGB24U	= 1 << 7,  /* RGB24, 32-bit container */
	OMAP_DSS_COLOR_RGB24P	= 1 << 8,  /* RGB24, 24-bit container */
	OMAP_DSS_COLOR_YUV2	= 1 << 9,  /* YUV2 4:2:2 co-sited */
	OMAP_DSS_COLOR_UYVY	= 1 << 10, /* UYVY 4:2:2 co-sited */
	OMAP_DSS_COLOR_ARGB32	= 1 << 11, /* ARGB32 */
	OMAP_DSS_COLOR_RGBA32	= 1 << 12, /* RGBA32 */
	OMAP_DSS_COLOR_RGBX32	= 1 << 13, /* RGBx32 */
105 106 107 108 109
	OMAP_DSS_COLOR_NV12		= 1 << 14, /* NV12 format: YUV 4:2:0 */
	OMAP_DSS_COLOR_RGBA16		= 1 << 15, /* RGBA16 - 4444 */
	OMAP_DSS_COLOR_RGBX16		= 1 << 16, /* RGBx16 - 4444 */
	OMAP_DSS_COLOR_ARGB16_1555	= 1 << 17, /* ARGB16 - 1555 */
	OMAP_DSS_COLOR_XRGB16_1555	= 1 << 18, /* xRGB16 - 1555 */
110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
};

enum omap_dss_load_mode {
	OMAP_DSS_LOAD_CLUT_AND_FRAME	= 0,
	OMAP_DSS_LOAD_CLUT_ONLY		= 1,
	OMAP_DSS_LOAD_FRAME_ONLY	= 2,
	OMAP_DSS_LOAD_CLUT_ONCE_FRAME	= 3,
};

enum omap_dss_trans_key_type {
	OMAP_DSS_COLOR_KEY_GFX_DST = 0,
	OMAP_DSS_COLOR_KEY_VID_SRC = 1,
};

enum omap_rfbi_te_mode {
	OMAP_DSS_RFBI_TE_MODE_1 = 1,
	OMAP_DSS_RFBI_TE_MODE_2 = 2,
};

129 130 131 132 133 134 135 136 137 138 139
enum omap_dss_signal_level {
	OMAPDSS_SIG_ACTIVE_HIGH	= 0,
	OMAPDSS_SIG_ACTIVE_LOW	= 1,
};

enum omap_dss_signal_edge {
	OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES,
	OMAPDSS_DRIVE_SIG_RISING_EDGE,
	OMAPDSS_DRIVE_SIG_FALLING_EDGE,
};

140 141 142 143 144
enum omap_dss_venc_type {
	OMAP_DSS_VENC_TYPE_COMPOSITE,
	OMAP_DSS_VENC_TYPE_SVIDEO,
};

145 146 147 148 149 150 151
enum omap_dss_dsi_pixel_format {
	OMAP_DSS_DSI_FMT_RGB888,
	OMAP_DSS_DSI_FMT_RGB666,
	OMAP_DSS_DSI_FMT_RGB666_PACKED,
	OMAP_DSS_DSI_FMT_RGB565,
};

152 153 154 155 156
enum omap_dss_dsi_mode {
	OMAP_DSS_DSI_CMD_MODE = 0,
	OMAP_DSS_DSI_VIDEO_MODE,
};

157 158 159 160 161 162 163 164 165 166
enum omap_display_caps {
	OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE	= 1 << 0,
	OMAP_DSS_DISPLAY_CAP_TEAR_ELIM		= 1 << 1,
};

enum omap_dss_display_state {
	OMAP_DSS_DISPLAY_DISABLED = 0,
	OMAP_DSS_DISPLAY_ACTIVE,
};

167 168 169 170 171 172 173
enum omap_dss_audio_state {
	OMAP_DSS_AUDIO_DISABLED = 0,
	OMAP_DSS_AUDIO_ENABLED,
	OMAP_DSS_AUDIO_CONFIGURED,
	OMAP_DSS_AUDIO_PLAYING,
};

174
enum omap_dss_rotation_type {
175 176 177
	OMAP_DSS_ROT_DMA	= 1 << 0,
	OMAP_DSS_ROT_VRFB	= 1 << 1,
	OMAP_DSS_ROT_TILER	= 1 << 2,
178 179 180 181 182 183 184 185 186 187 188 189
};

/* clockwise rotation angle */
enum omap_dss_rotation_angle {
	OMAP_DSS_ROT_0   = 0,
	OMAP_DSS_ROT_90  = 1,
	OMAP_DSS_ROT_180 = 2,
	OMAP_DSS_ROT_270 = 3,
};

enum omap_overlay_caps {
	OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
190 191
	OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
	OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
192
	OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
193 194
	OMAP_DSS_OVL_CAP_POS = 1 << 4,
	OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
195 196 197
};

enum omap_overlay_manager_caps {
198
	OMAP_DSS_DUMMY_VALUE, /* add a dummy value to prevent compiler error */
199 200
};

201 202 203 204 205 206 207
enum omap_dss_clk_source {
	OMAP_DSS_CLK_SRC_FCK = 0,		/* OMAP2/3: DSS1_ALWON_FCLK
						 * OMAP4: DSS_FCLK */
	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC,	/* OMAP3: DSI1_PLL_FCLK
						 * OMAP4: PLL1_CLK1 */
	OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI,	/* OMAP3: DSI2_PLL_FCLK
						 * OMAP4: PLL1_CLK2 */
208 209
	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC,	/* OMAP4: PLL2_CLK1 */
	OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI,	/* OMAP4: PLL2_CLK2 */
210 211
};

212 213 214 215
enum omap_hdmi_flags {
	OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
};

216 217 218 219 220 221 222 223 224 225
enum omap_dss_output_id {
	OMAP_DSS_OUTPUT_DPI	= 1 << 0,
	OMAP_DSS_OUTPUT_DBI	= 1 << 1,
	OMAP_DSS_OUTPUT_SDI	= 1 << 2,
	OMAP_DSS_OUTPUT_DSI1	= 1 << 3,
	OMAP_DSS_OUTPUT_DSI2	= 1 << 4,
	OMAP_DSS_OUTPUT_VENC	= 1 << 5,
	OMAP_DSS_OUTPUT_HDMI	= 1 << 6,
};

226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256
/* RFBI */

struct rfbi_timings {
	int cs_on_time;
	int cs_off_time;
	int we_on_time;
	int we_off_time;
	int re_on_time;
	int re_off_time;
	int we_cycle_time;
	int re_cycle_time;
	int cs_pulse_width;
	int access_time;

	int clk_div;

	u32 tim[5];             /* set by rfbi_convert_timings() */

	int converted;
};

void omap_rfbi_write_command(const void *buf, u32 len);
void omap_rfbi_read_data(void *buf, u32 len);
void omap_rfbi_write_data(const void *buf, u32 len);
void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
		u16 x, u16 y,
		u16 w, u16 h);
int omap_rfbi_enable_te(bool enable, unsigned line);
int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
			     unsigned hs_pulse_time, unsigned vs_pulse_time,
			     int hs_pol_inv, int vs_pol_inv, int extif_div);
257 258
void rfbi_bus_lock(void);
void rfbi_bus_unlock(void);
259 260

/* DSI */
261

262 263 264 265 266 267 268 269 270
enum omap_dss_dsi_trans_mode {
	/* Sync Pulses: both sync start and end packets sent */
	OMAP_DSS_DSI_PULSE_MODE,
	/* Sync Events: only sync start packets sent */
	OMAP_DSS_DSI_EVENT_MODE,
	/* Burst: only sync start packets sent, pixels are time compressed */
	OMAP_DSS_DSI_BURST_MODE,
};

271
struct omap_dss_dsi_videomode_timings {
272 273 274 275 276 277 278 279 280 281
	unsigned long hsclk;

	unsigned ndl;
	unsigned bitspp;

	/* pixels */
	u16 hact;
	/* lines */
	u16 vact;

282 283
	/* DSI video mode blanking data */
	/* Unit: byte clock cycles */
284
	u16 hss;
285
	u16 hsa;
286
	u16 hse;
287 288 289 290 291 292 293 294 295 296 297 298 299
	u16 hfp;
	u16 hbp;
	/* Unit: line clocks */
	u16 vsa;
	u16 vfp;
	u16 vbp;

	/* DSI blanking modes */
	int blanking_mode;
	int hsa_blanking_mode;
	int hbp_blanking_mode;
	int hfp_blanking_mode;

300
	enum omap_dss_dsi_trans_mode trans_mode;
301 302 303 304 305

	bool ddr_clk_always_on;
	int window_sync;
};

306 307 308 309 310
struct omap_dss_dsi_config {
	enum omap_dss_dsi_mode mode;
	enum omap_dss_dsi_pixel_format pixel_format;
	const struct omap_video_timings *timings;

311 312 313 314 315
	unsigned long hs_clk_min, hs_clk_max;
	unsigned long lp_clk_min, lp_clk_max;

	bool ddr_clk_always_on;
	enum omap_dss_dsi_trans_mode trans_mode;
316 317
};

318 319 320 321
void dsi_bus_lock(struct omap_dss_device *dssdev);
void dsi_bus_unlock(struct omap_dss_device *dssdev);
int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
		int len);
322 323 324 325
int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
		int len);
int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd);
int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel);
326 327
int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 param);
328 329 330 331
int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
		u8 param);
int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
		u8 param1, u8 param2);
332 333
int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
		u8 *data, int len);
334 335
int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
		u8 *data, int len);
336 337
int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
		u8 *buf, int buflen);
338 339 340 341 342 343
int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
		int buflen);
int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
		u8 *buf, int buflen);
int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
		u8 param1, u8 param2, u8 *buf, int buflen);
344 345 346 347
int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
		u16 len);
int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
348 349
int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel);
void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel);
350

T
Tomi Valkeinen 已提交
351 352 353 354 355 356 357 358 359 360 361 362 363
enum omapdss_version {
	OMAPDSS_VER_UNKNOWN = 0,
	OMAPDSS_VER_OMAP24xx,
	OMAPDSS_VER_OMAP34xx_ES1,	/* OMAP3430 ES1.0, 2.0 */
	OMAPDSS_VER_OMAP34xx_ES3,	/* OMAP3430 ES3.0+ */
	OMAPDSS_VER_OMAP3630,
	OMAPDSS_VER_AM35xx,
	OMAPDSS_VER_OMAP4430_ES1,	/* OMAP4430 ES1.0 */
	OMAPDSS_VER_OMAP4430_ES2,	/* OMAP4430 ES2.0, 2.1, 2.2 */
	OMAPDSS_VER_OMAP4,		/* All other OMAP4s */
	OMAPDSS_VER_OMAP5,
};

364 365
/* Board specific data */
struct omap_dss_board_info {
366
	int (*get_context_loss_count)(struct device *dev);
367 368 369
	int num_devices;
	struct omap_dss_device **devices;
	struct omap_dss_device *default_device;
370
	const char *default_display_name;
371 372
	int (*dsi_enable_pads)(int dsi_id, unsigned lane_mask);
	void (*dsi_disable_pads)(int dsi_id, unsigned lane_mask);
373
	int (*set_min_bus_tput)(struct device *dev, unsigned long r);
T
Tomi Valkeinen 已提交
374
	enum omapdss_version version;
375 376
};

377 378
/* Init with the board info */
extern int omap_display_init(struct omap_dss_board_info *board_data);
379
/* HDMI mux init*/
380
extern int omap_hdmi_init(enum omap_hdmi_flags flags);
381

382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
struct omap_video_timings {
	/* Unit: pixels */
	u16 x_res;
	/* Unit: pixels */
	u16 y_res;
	/* Unit: KHz */
	u32 pixel_clock;
	/* Unit: pixel clocks */
	u16 hsw;	/* Horizontal synchronization pulse width */
	/* Unit: pixel clocks */
	u16 hfp;	/* Horizontal front porch */
	/* Unit: pixel clocks */
	u16 hbp;	/* Horizontal back porch */
	/* Unit: line clocks */
	u16 vsw;	/* Vertical synchronization pulse width */
	/* Unit: line clocks */
	u16 vfp;	/* Vertical front porch */
	/* Unit: line clocks */
	u16 vbp;	/* Vertical back porch */
401 402 403 404 405

	/* Vsync logic level */
	enum omap_dss_signal_level vsync_level;
	/* Hsync logic level */
	enum omap_dss_signal_level hsync_level;
406 407
	/* Interlaced or Progressive timings */
	bool interlace;
408 409 410 411 412 413
	/* Pixel clock edge to drive LCD data */
	enum omap_dss_signal_edge data_pclk_edge;
	/* Data enable logic level */
	enum omap_dss_signal_level de_level;
	/* Pixel clock edges to drive HSYNC and VSYNC signals */
	enum omap_dss_signal_edge sync_pclk_edge;
414 415 416 417 418 419 420
};

#ifdef CONFIG_OMAP2_DSS_VENC
/* Hardcoded timings for tv modes. Venc only uses these to
 * identify the mode, and does not actually use the configs
 * itself. However, the configs should be something that
 * a normal monitor can also show */
421 422
extern const struct omap_video_timings omap_dss_pal_timings;
extern const struct omap_video_timings omap_dss_ntsc_timings;
423 424
#endif

425 426 427 428 429 430
struct omap_dss_cpr_coefs {
	s16 rr, rg, rb;
	s16 gr, gg, gb;
	s16 br, bg, bb;
};

431 432
struct omap_overlay_info {
	u32 paddr;
433
	u32 p_uv_addr;  /* for NV12 format */
434 435 436 437 438 439 440 441 442 443 444 445 446
	u16 screen_width;
	u16 width;
	u16 height;
	enum omap_color_mode color_mode;
	u8 rotation;
	enum omap_dss_rotation_type rotation_type;
	bool mirror;

	u16 pos_x;
	u16 pos_y;
	u16 out_width;	/* if 0, out_width == width */
	u16 out_height;	/* if 0, out_height == height */
	u8 global_alpha;
447
	u8 pre_mult_alpha;
448
	u8 zorder;
449 450 451 452 453 454 455 456
};

struct omap_overlay {
	struct kobject kobj;
	struct list_head list;

	/* static fields */
	const char *name;
457
	enum omap_plane id;
458 459 460 461 462 463
	enum omap_color_mode supported_modes;
	enum omap_overlay_caps caps;

	/* dynamic fields */
	struct omap_overlay_manager *manager;

464 465 466 467 468 469 470 471 472 473 474
	/*
	 * The following functions do not block:
	 *
	 * is_enabled
	 * set_overlay_info
	 * get_overlay_info
	 *
	 * The rest of the functions may block and cannot be called from
	 * interrupt context
	 */

475 476 477 478
	int (*enable)(struct omap_overlay *ovl);
	int (*disable)(struct omap_overlay *ovl);
	bool (*is_enabled)(struct omap_overlay *ovl);

479 480 481 482 483 484 485 486 487 488
	int (*set_manager)(struct omap_overlay *ovl,
		struct omap_overlay_manager *mgr);
	int (*unset_manager)(struct omap_overlay *ovl);

	int (*set_overlay_info)(struct omap_overlay *ovl,
			struct omap_overlay_info *info);
	void (*get_overlay_info)(struct omap_overlay *ovl,
			struct omap_overlay_info *info);

	int (*wait_for_go)(struct omap_overlay *ovl);
489 490

	struct omap_dss_device *(*get_device)(struct omap_overlay *ovl);
491 492 493 494 495 496 497 498 499
};

struct omap_overlay_manager_info {
	u32 default_color;

	enum omap_dss_trans_key_type trans_key_type;
	u32 trans_key;
	bool trans_enabled;

500
	bool partial_alpha_enabled;
501 502 503

	bool cpr_enable;
	struct omap_dss_cpr_coefs cpr_coefs;
504 505 506 507 508 509 510
};

struct omap_overlay_manager {
	struct kobject kobj;

	/* static fields */
	const char *name;
511
	enum omap_channel id;
512
	enum omap_overlay_manager_caps caps;
513
	struct list_head overlays;
514
	enum omap_display_type supported_displays;
515
	enum omap_dss_output_id supported_outputs;
516 517

	/* dynamic fields */
518
	struct omap_dss_device *output;
519

520 521 522 523 524 525 526 527 528 529 530
	/*
	 * The following functions do not block:
	 *
	 * set_manager_info
	 * get_manager_info
	 * apply
	 *
	 * The rest of the functions may block and cannot be called from
	 * interrupt context
	 */

531
	int (*set_output)(struct omap_overlay_manager *mgr,
532
		struct omap_dss_device *output);
533
	int (*unset_output)(struct omap_overlay_manager *mgr);
534 535 536 537 538 539 540 541

	int (*set_manager_info)(struct omap_overlay_manager *mgr,
			struct omap_overlay_manager_info *info);
	void (*get_manager_info)(struct omap_overlay_manager *mgr,
			struct omap_overlay_manager_info *info);

	int (*apply)(struct omap_overlay_manager *mgr);
	int (*wait_for_go)(struct omap_overlay_manager *mgr);
T
Tomi Valkeinen 已提交
542
	int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
543 544

	struct omap_dss_device *(*get_device)(struct omap_overlay_manager *mgr);
545 546
};

547 548 549 550 551 552 553 554 555 556 557 558 559 560 561
/* 22 pins means 1 clk lane and 10 data lanes */
#define OMAP_DSS_MAX_DSI_PINS 22

struct omap_dsi_pin_config {
	int num_pins;
	/*
	 * pin numbers in the following order:
	 * clk+, clk-
	 * data1+, data1-
	 * data2+, data2-
	 * ...
	 */
	int pins[OMAP_DSS_MAX_DSI_PINS];
};

562 563 564 565 566 567 568 569 570 571 572 573 574
struct omap_dss_writeback_info {
	u32 paddr;
	u32 p_uv_addr;
	u16 buf_width;
	u16 width;
	u16 height;
	enum omap_color_mode color_mode;
	u8 rotation;
	enum omap_dss_rotation_type rotation_type;
	bool mirror;
	u8 pre_mult_alpha;
};

575
struct omap_dss_device {
576 577 578 579 580
	/* old device, to be removed */
	struct device old_dev;

	/* new device, pointer to panel device */
	struct device *dev;
581

T
Tomi Valkeinen 已提交
582 583 584 585 586
	struct list_head panel_list;

	/* alias in the form of "display%d" */
	char alias[16];

587
	enum omap_display_type type;
588
	enum omap_display_type output_type;
589

590
	/* obsolete, to be removed */
591 592
	enum omap_channel channel;

593 594 595 596 597 598 599 600 601 602 603 604 605 606 607
	union {
		struct {
			u8 data_lines;
		} dpi;

		struct {
			u8 channel;
			u8 data_lines;
		} rfbi;

		struct {
			u8 datapairs;
		} sdi;

		struct {
608 609
			int module;

610 611 612 613 614 615 616 617 618 619 620 621 622
			bool ext_te;
			u8 ext_te_gpio;
		} dsi;

		struct {
			enum omap_dss_venc_type type;
			bool invert_polarity;
		} venc;
	} phy;

	struct {
		struct omap_video_timings timings;

623
		enum omap_dss_dsi_pixel_format dsi_pix_fmt;
624
		enum omap_dss_dsi_mode dsi_mode;
625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649
	} panel;

	struct {
		u8 pixel_size;
		struct rfbi_timings rfbi_timings;
	} ctrl;

	int reset_gpio;

	int max_backlight_level;

	const char *name;

	/* used to match device to driver */
	const char *driver_name;

	void *data;

	struct omap_dss_driver *driver;

	/* helper variable for driver suspend/resume */
	bool activate_after_resume;

	enum omap_display_caps caps;

650
	struct omap_dss_device *output;
651 652 653

	enum omap_dss_display_state state;

654 655
	enum omap_dss_audio_state audio_state;

656 657 658 659 660
	/* platform specific  */
	int (*platform_enable)(struct omap_dss_device *dssdev);
	void (*platform_disable)(struct omap_dss_device *dssdev);
	int (*set_backlight)(struct omap_dss_device *dssdev, int level);
	int (*get_backlight)(struct omap_dss_device *dssdev);
661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676


	/* OMAP DSS output specific fields */

	struct list_head list;

	/* DISPC channel for this output */
	enum omap_channel dispc_channel;

	/* output instance */
	enum omap_dss_output_id id;

	/* dynamic fields */
	struct omap_overlay_manager *manager;

	struct omap_dss_device *device;
677 678
};

T
Tomi Valkeinen 已提交
679 680
struct omap_dss_hdmi_data
{
681 682
	int ct_cp_hpd_gpio;
	int ls_oe_gpio;
T
Tomi Valkeinen 已提交
683 684 685
	int hpd_gpio;
};

686 687 688 689 690
struct omap_dss_audio {
	struct snd_aes_iec958 *iec;
	struct snd_cea_861_aud_if *cea;
};

691 692 693 694 695 696
struct omap_dss_driver {
	struct device_driver driver;

	int (*probe)(struct omap_dss_device *);
	void (*remove)(struct omap_dss_device *);

697 698 699
	int (*connect)(struct omap_dss_device *dssdev);
	void (*disconnect)(struct omap_dss_device *dssdev);

700 701 702 703
	int (*enable)(struct omap_dss_device *display);
	void (*disable)(struct omap_dss_device *display);
	int (*run_test)(struct omap_dss_device *display, int test);

704 705 706 707
	int (*update)(struct omap_dss_device *dssdev,
			       u16 x, u16 y, u16 w, u16 h);
	int (*sync)(struct omap_dss_device *dssdev);

708
	int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
709
	int (*get_te)(struct omap_dss_device *dssdev);
710 711 712 713 714 715 716 717 718 719

	u8 (*get_rotate)(struct omap_dss_device *dssdev);
	int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);

	bool (*get_mirror)(struct omap_dss_device *dssdev);
	int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);

	int (*memory_read)(struct omap_dss_device *dssdev,
			void *buf, size_t size,
			u16 x, u16 y, u16 w, u16 h);
720 721 722

	void (*get_resolution)(struct omap_dss_device *dssdev,
			u16 *xres, u16 *yres);
723 724
	void (*get_dimensions)(struct omap_dss_device *dssdev,
			u32 *width, u32 *height);
725
	int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
T
Tomi Valkeinen 已提交
726

727 728 729 730 731 732 733
	int (*check_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
	void (*set_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
	void (*get_timings)(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);

T
Tomi Valkeinen 已提交
734 735
	int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
	u32 (*get_wss)(struct omap_dss_device *dssdev);
736 737

	int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
738
	bool (*detect)(struct omap_dss_device *dssdev);
739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756

	/*
	 * For display drivers that support audio. This encompasses
	 * HDMI and DisplayPort at the moment.
	 */
	/*
	 * Note: These functions might sleep. Do not call while
	 * holding a spinlock/readlock.
	 */
	int (*audio_enable)(struct omap_dss_device *dssdev);
	void (*audio_disable)(struct omap_dss_device *dssdev);
	bool (*audio_supported)(struct omap_dss_device *dssdev);
	int (*audio_config)(struct omap_dss_device *dssdev,
		struct omap_dss_audio *audio);
	/* Note: These functions may not sleep */
	int (*audio_start)(struct omap_dss_device *dssdev);
	void (*audio_stop)(struct omap_dss_device *dssdev);

757 758
};

759
enum omapdss_version omapdss_get_version(void);
T
Tomi Valkeinen 已提交
760
bool omapdss_is_initialized(void);
761

762 763 764
int omap_dss_register_driver(struct omap_dss_driver *);
void omap_dss_unregister_driver(struct omap_dss_driver *);

T
Tomi Valkeinen 已提交
765 766 767
int omapdss_register_display(struct omap_dss_device *dssdev);
void omapdss_unregister_display(struct omap_dss_device *dssdev);

768 769 770 771 772 773
void omap_dss_get_device(struct omap_dss_device *dssdev);
void omap_dss_put_device(struct omap_dss_device *dssdev);
#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
struct omap_dss_device *omap_dss_find_device(void *data,
		int (*match)(struct omap_dss_device *dssdev, void *data));
774
const char *omapdss_get_default_display_name(void);
775

776 777 778 779 780
void videomode_to_omap_video_timings(const struct videomode *vm,
		struct omap_video_timings *ovt);
void omap_video_timings_to_videomode(const struct omap_video_timings *ovt,
		struct videomode *vm);

781 782 783 784 785 786 787 788
int dss_feat_get_num_mgrs(void);
int dss_feat_get_num_ovls(void);
enum omap_display_type dss_feat_get_supported_displays(enum omap_channel channel);
enum omap_dss_output_id dss_feat_get_supported_outputs(enum omap_channel channel);
enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);



789 790 791 792 793 794
int omap_dss_get_num_overlay_managers(void);
struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);

int omap_dss_get_num_overlays(void);
struct omap_overlay *omap_dss_get_overlay(int num);

795 796 797 798
struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
struct omap_dss_device *omap_dss_find_output(const char *name);
struct omap_dss_device *omap_dss_find_output_by_node(struct device_node *node);
int omapdss_output_set_device(struct omap_dss_device *out,
799
		struct omap_dss_device *dssdev);
800
int omapdss_output_unset_device(struct omap_dss_device *out);
801

802
struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
803 804
struct omap_overlay_manager *omapdss_find_mgr_from_display(struct omap_dss_device *dssdev);

805 806
void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
		u16 *xres, u16 *yres);
807
int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
808 809
void omapdss_default_get_timings(struct omap_dss_device *dssdev,
		struct omap_video_timings *timings);
810

811 812 813 814
typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);

T
Tomi Valkeinen 已提交
815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852
u32 dispc_read_irqstatus(void);
void dispc_clear_irqstatus(u32 mask);
u32 dispc_read_irqenable(void);
void dispc_write_irqenable(u32 mask);

int dispc_request_irq(irq_handler_t handler, void *dev_id);
void dispc_free_irq(void *dev_id);

int dispc_runtime_get(void);
void dispc_runtime_put(void);

void dispc_mgr_enable(enum omap_channel channel, bool enable);
bool dispc_mgr_is_enabled(enum omap_channel channel);
u32 dispc_mgr_get_vsync_irq(enum omap_channel channel);
u32 dispc_mgr_get_framedone_irq(enum omap_channel channel);
u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel);
bool dispc_mgr_go_busy(enum omap_channel channel);
void dispc_mgr_go(enum omap_channel channel);
void dispc_mgr_set_lcd_config(enum omap_channel channel,
		const struct dss_lcd_mgr_config *config);
void dispc_mgr_set_timings(enum omap_channel channel,
		const struct omap_video_timings *timings);
void dispc_mgr_setup(enum omap_channel channel,
		const struct omap_overlay_manager_info *info);

int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
		const struct omap_overlay_info *oi,
		const struct omap_video_timings *timings,
		int *x_predecim, int *y_predecim);

int dispc_ovl_enable(enum omap_plane plane, bool enable);
bool dispc_ovl_enabled(enum omap_plane plane);
void dispc_ovl_set_channel_out(enum omap_plane plane,
		enum omap_channel channel);
int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
		bool replication, const struct omap_video_timings *mgr_timings,
		bool mem_to_mem);

853
#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
854
#define to_dss_device(x) container_of((x), struct omap_dss_device, old_dev)
855

856 857
void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
		bool enable);
858
int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
859 860
int omapdss_dsi_set_config(struct omap_dss_device *dssdev,
		const struct omap_dss_dsi_config *config);
861

862
int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
863
		void (*callback)(int, void *), void *data);
864 865 866
int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
867 868
int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
		const struct omap_dsi_pin_config *pin_cfg);
869

870
int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
871
void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
872
		bool disconnect_lanes, bool enter_ulps);
873 874 875

int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
876 877
void omapdss_dpi_set_timings(struct omap_dss_device *dssdev,
		struct omap_video_timings *timings);
878 879
int dpi_check_timings(struct omap_dss_device *dssdev,
			struct omap_video_timings *timings);
880
void omapdss_dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines);
881 882 883

int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
884 885
void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
		struct omap_video_timings *timings);
886
void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs);
887 888 889

int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
890 891
int omap_rfbi_update(struct omap_dss_device *dssdev, void (*callback)(void *),
		void *data);
892
int omap_rfbi_configure(struct omap_dss_device *dssdev);
893
void omapdss_rfbi_set_size(struct omap_dss_device *dssdev, u16 w, u16 h);
894 895
void omapdss_rfbi_set_pixel_size(struct omap_dss_device *dssdev,
		int pixel_size);
896 897
void omapdss_rfbi_set_data_lines(struct omap_dss_device *dssdev,
		int data_lines);
898 899
void omapdss_rfbi_set_interface_timings(struct omap_dss_device *dssdev,
		struct rfbi_timings *timings);
900

901 902 903
int omapdss_compat_init(void);
void omapdss_compat_uninit(void);

904
struct dss_mgr_ops {
905
	int (*connect)(struct omap_overlay_manager *mgr,
906
		struct omap_dss_device *dst);
907
	void (*disconnect)(struct omap_overlay_manager *mgr,
908
		struct omap_dss_device *dst);
909

910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925
	void (*start_update)(struct omap_overlay_manager *mgr);
	int (*enable)(struct omap_overlay_manager *mgr);
	void (*disable)(struct omap_overlay_manager *mgr);
	void (*set_timings)(struct omap_overlay_manager *mgr,
			const struct omap_video_timings *timings);
	void (*set_lcd_config)(struct omap_overlay_manager *mgr,
			const struct dss_lcd_mgr_config *config);
	int (*register_framedone_handler)(struct omap_overlay_manager *mgr,
			void (*handler)(void *), void *data);
	void (*unregister_framedone_handler)(struct omap_overlay_manager *mgr,
			void (*handler)(void *), void *data);
};

int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
void dss_uninstall_mgr_ops(void);

926
int dss_mgr_connect(struct omap_overlay_manager *mgr,
927
		struct omap_dss_device *dst);
928
void dss_mgr_disconnect(struct omap_overlay_manager *mgr,
929
		struct omap_dss_device *dst);
930 931 932 933 934 935 936 937 938 939 940
void dss_mgr_set_timings(struct omap_overlay_manager *mgr,
		const struct omap_video_timings *timings);
void dss_mgr_set_lcd_config(struct omap_overlay_manager *mgr,
		const struct dss_lcd_mgr_config *config);
int dss_mgr_enable(struct omap_overlay_manager *mgr);
void dss_mgr_disable(struct omap_overlay_manager *mgr);
void dss_mgr_start_update(struct omap_overlay_manager *mgr);
int dss_mgr_register_framedone_handler(struct omap_overlay_manager *mgr,
		void (*handler)(void *), void *data);
void dss_mgr_unregister_framedone_handler(struct omap_overlay_manager *mgr,
		void (*handler)(void *), void *data);
941 942 943 944 945 946 947 948 949 950 951

static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
{
	return dssdev->output;
}

static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
{
	return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
}

952
#endif