ramgk104.c 48.8 KB
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/*
 * Copyright 2013 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */
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#define gk104_ram(p) container_of((p), struct gk104_ram, base)
#include "ram.h"
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#include "ramfuc.h"
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#include <core/option.h>
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#include <subdev/bios.h>
#include <subdev/bios/init.h>
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#include <subdev/bios/M0205.h>
#include <subdev/bios/M0209.h>
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#include <subdev/bios/pll.h>
#include <subdev/bios/rammap.h>
#include <subdev/bios/timing.h>
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#include <subdev/clk.h>
#include <subdev/clk/pll.h>
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#include <subdev/gpio.h>
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struct gk104_ramfuc {
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	struct ramfuc base;

	struct nvbios_pll refpll;
	struct nvbios_pll mempll;

	struct ramfuc_reg r_gpioMV;
	u32 r_funcMV[2];
	struct ramfuc_reg r_gpio2E;
	u32 r_func2E[2];
	struct ramfuc_reg r_gpiotrig;

	struct ramfuc_reg r_0x132020;
	struct ramfuc_reg r_0x132028;
	struct ramfuc_reg r_0x132024;
	struct ramfuc_reg r_0x132030;
	struct ramfuc_reg r_0x132034;
	struct ramfuc_reg r_0x132000;
	struct ramfuc_reg r_0x132004;
	struct ramfuc_reg r_0x132040;

	struct ramfuc_reg r_0x10f248;
	struct ramfuc_reg r_0x10f290;
	struct ramfuc_reg r_0x10f294;
	struct ramfuc_reg r_0x10f298;
	struct ramfuc_reg r_0x10f29c;
	struct ramfuc_reg r_0x10f2a0;
	struct ramfuc_reg r_0x10f2a4;
	struct ramfuc_reg r_0x10f2a8;
	struct ramfuc_reg r_0x10f2ac;
	struct ramfuc_reg r_0x10f2cc;
	struct ramfuc_reg r_0x10f2e8;
	struct ramfuc_reg r_0x10f250;
	struct ramfuc_reg r_0x10f24c;
	struct ramfuc_reg r_0x10fec4;
	struct ramfuc_reg r_0x10fec8;
	struct ramfuc_reg r_0x10f604;
	struct ramfuc_reg r_0x10f614;
	struct ramfuc_reg r_0x10f610;
	struct ramfuc_reg r_0x100770;
	struct ramfuc_reg r_0x100778;
	struct ramfuc_reg r_0x10f224;

	struct ramfuc_reg r_0x10f870;
	struct ramfuc_reg r_0x10f698;
	struct ramfuc_reg r_0x10f694;
	struct ramfuc_reg r_0x10f6b8;
	struct ramfuc_reg r_0x10f808;
	struct ramfuc_reg r_0x10f670;
	struct ramfuc_reg r_0x10f60c;
	struct ramfuc_reg r_0x10f830;
	struct ramfuc_reg r_0x1373ec;
	struct ramfuc_reg r_0x10f800;
	struct ramfuc_reg r_0x10f82c;

	struct ramfuc_reg r_0x10f978;
	struct ramfuc_reg r_0x10f910;
	struct ramfuc_reg r_0x10f914;

	struct ramfuc_reg r_mr[16]; /* MR0 - MR8, MR15 */

	struct ramfuc_reg r_0x62c000;
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	struct ramfuc_reg r_0x10f200;
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	struct ramfuc_reg r_0x10f210;
	struct ramfuc_reg r_0x10f310;
	struct ramfuc_reg r_0x10f314;
	struct ramfuc_reg r_0x10f318;
	struct ramfuc_reg r_0x10f090;
	struct ramfuc_reg r_0x10f69c;
	struct ramfuc_reg r_0x10f824;
	struct ramfuc_reg r_0x1373f0;
	struct ramfuc_reg r_0x1373f4;
	struct ramfuc_reg r_0x137320;
	struct ramfuc_reg r_0x10f65c;
	struct ramfuc_reg r_0x10f6bc;
	struct ramfuc_reg r_0x100710;
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	struct ramfuc_reg r_0x100750;
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};

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struct gk104_ram {
	struct nvkm_ram base;
	struct gk104_ramfuc fuc;
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	struct list_head cfg;
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	u32 parts;
	u32 pmask;
	u32 pnuts;

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	struct nvbios_ramcfg diff;
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	int from;
	int mode;
	int N1, fN1, M1, P1;
	int N2, M2, P2;
};

/*******************************************************************************
 * GDDR5
 ******************************************************************************/
static void
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gk104_ram_train(struct gk104_ramfuc *fuc, u32 mask, u32 data)
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{
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	struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
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	u32 addr = 0x110974, i;
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	ram_mask(fuc, 0x10f910, mask, data);
	ram_mask(fuc, 0x10f914, mask, data);
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	for (i = 0; (data & 0x80000000) && i < ram->parts; addr += 0x1000, i++) {
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		if (ram->pmask & (1 << i))
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			continue;
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		ram_wait(fuc, addr, 0x0000000f, 0x00000000, 500000);
	}
}

static void
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r1373f4_init(struct gk104_ramfuc *fuc)
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{
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	struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
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	const u32 mcoef = ((--ram->P2 << 28) | (ram->N2 << 8) | ram->M2);
	const u32 rcoef = ((  ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
	const u32 runk0 = ram->fN1 << 16;
	const u32 runk1 = ram->fN1;

	if (ram->from == 2) {
		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
	} else {
		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
	}

	ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
	ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);

	/* (re)program refpll, if required */
	if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
	    (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
		ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
		ram_wr32(fuc, 0x137320, 0x00000000);
		ram_mask(fuc, 0x132030, 0xffff0000, runk0);
		ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
		ram_wr32(fuc, 0x132024, rcoef);
		ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
		ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
		ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
		ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
	}

	/* (re)program mempll, if required */
	if (ram->mode == 2) {
		ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
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		ram_mask(fuc, 0x132000, 0x80000000, 0x80000000);
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		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
		ram_mask(fuc, 0x132004, 0x103fffff, mcoef);
		ram_mask(fuc, 0x132000, 0x00000001, 0x00000001);
		ram_wait(fuc, 0x137390, 0x00000002, 0x00000002, 64000);
		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00001100);
	} else {
		ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010100);
	}

	ram_mask(fuc, 0x1373f4, 0x00000000, 0x00000010);
}

static void
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r1373f4_fini(struct gk104_ramfuc *fuc)
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{
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	struct gk104_ram *ram = container_of(fuc, typeof(*ram), fuc);
	struct nvkm_ram_data *next = ram->base.next;
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	u8 v0 = next->bios.ramcfg_11_03_c0;
	u8 v1 = next->bios.ramcfg_11_03_30;
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	u32 tmp;

	tmp = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
	ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16));
	ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000);
	if (ram->mode == 2) {
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		ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000002);
		ram_mask(fuc, 0x1373f4, 0x00001100, 0x00000000);
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	} else {
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		ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
		ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);
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	}
	ram_mask(fuc, 0x10f800, 0x00000030, (v0 ^ v1) << 4);
}

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static void
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gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg,
	       u32 _mask, u32 _data, u32 _copy)
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{
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	struct nvkm_fb *fb = ram->base.fb;
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	struct ramfuc *fuc = &ram->fuc.base;
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	struct nvkm_device *device = fb->subdev.device;
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	u32 addr = 0x110000 + (reg->addr & 0xfff);
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	u32 mask = _mask | _copy;
	u32 data = (_data & _mask) | (reg->data & _copy);
	u32 i;

	for (i = 0; i < 16; i++, addr += 0x1000) {
		if (ram->pnuts & (1 << i)) {
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			u32 prev = nvkm_rd32(device, addr);
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			u32 next = (prev & ~mask) | data;
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			nvkm_memx_wr32(fuc->memx, addr, next);
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		}
	}
}
#define ram_nuts(s,r,m,d,c)                                                    \
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	gk104_ram_nuts((s), &(s)->fuc.r_##r, (m), (d), (c))
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static int
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gk104_ram_calc_gddr5(struct gk104_ram *ram, u32 freq)
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{
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	struct gk104_ramfuc *fuc = &ram->fuc;
	struct nvkm_ram_data *next = ram->base.next;
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	int vc = !next->bios.ramcfg_11_02_08;
	int mv = !next->bios.ramcfg_11_02_04;
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	u32 mask, data;
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	ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
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	ram_block(fuc);
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	if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP))
		ram_wr32(fuc, 0x62c000, 0x0f0f0000);
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	/* MR1: turn termination on early, for some reason.. */
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	if ((ram->base.mr[1] & 0x03c) != 0x030) {
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		ram_mask(fuc, mr[1], 0x03c, ram->base.mr[1] & 0x03c);
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		ram_nuts(ram, mr[1], 0x03c, ram->base.mr1_nuts & 0x03c, 0x000);
	}
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	if (vc == 1 && ram_have(fuc, gpio2E)) {
		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
		if (temp != ram_rd32(fuc, gpio2E)) {
			ram_wr32(fuc, gpiotrig, 1);
			ram_nsec(fuc, 20000);
		}
	}

	ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);

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	gk104_ram_train(fuc, 0x01020000, 0x000c0000);
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	ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
	ram_nsec(fuc, 1000);
	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
	ram_nsec(fuc, 1000);

	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
	ram_wr32(fuc, 0x10f090, 0x00000061);
	ram_wr32(fuc, 0x10f090, 0xc000007f);
	ram_nsec(fuc, 1000);

	ram_wr32(fuc, 0x10f698, 0x00000000);
	ram_wr32(fuc, 0x10f69c, 0x00000000);

	/*XXX: there does appear to be some kind of condition here, simply
	 *     modifying these bits in the vbios from the default pl0
	 *     entries shows no change.  however, the data does appear to
	 *     be correct and may be required for the transition back
	 */
	mask = 0x800f07e0;
	data = 0x00030000;
	if (ram_rd32(fuc, 0x10f978) & 0x00800000)
		data |= 0x00040000;

	if (1) {
		data |= 0x800807e0;
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		switch (next->bios.ramcfg_11_03_c0) {
		case 3: data &= ~0x00000040; break;
		case 2: data &= ~0x00000100; break;
		case 1: data &= ~0x80000000; break;
		case 0: data &= ~0x00000400; break;
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		}

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		switch (next->bios.ramcfg_11_03_30) {
		case 3: data &= ~0x00000020; break;
		case 2: data &= ~0x00000080; break;
		case 1: data &= ~0x00080000; break;
		case 0: data &= ~0x00000200; break;
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		}
	}

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	if (next->bios.ramcfg_11_02_80)
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		mask |= 0x03000000;
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	if (next->bios.ramcfg_11_02_40)
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		mask |= 0x00002000;
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	if (next->bios.ramcfg_11_07_10)
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		mask |= 0x00004000;
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	if (next->bios.ramcfg_11_07_08)
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		mask |= 0x00000003;
	else {
		mask |= 0x34000000;
		if (ram_rd32(fuc, 0x10f978) & 0x00800000)
			mask |= 0x40000000;
	}
	ram_mask(fuc, 0x10f824, mask, data);

	ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);

	if (ram->from == 2 && ram->mode != 2) {
		ram_mask(fuc, 0x10f808, 0x00080000, 0x00000000);
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		ram_mask(fuc, 0x10f200, 0x18008000, 0x00008000);
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		ram_mask(fuc, 0x10f800, 0x00000000, 0x00000004);
		ram_mask(fuc, 0x10f830, 0x00008000, 0x01040010);
		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
		r1373f4_init(fuc);
		ram_mask(fuc, 0x1373f0, 0x00000002, 0x00000001);
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		r1373f4_fini(fuc);
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		ram_mask(fuc, 0x10f830, 0x00c00000, 0x00240001);
	} else
	if (ram->from != 2 && ram->mode != 2) {
		r1373f4_init(fuc);
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		r1373f4_fini(fuc);
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	}

	if (ram_have(fuc, gpioMV)) {
		u32 temp  = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
		if (temp != ram_rd32(fuc, gpioMV)) {
			ram_wr32(fuc, gpiotrig, 1);
			ram_nsec(fuc, 64000);
		}
	}

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	if (next->bios.ramcfg_11_02_40 ||
	    next->bios.ramcfg_11_07_10) {
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		ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
		ram_nsec(fuc, 20000);
	}

	if (ram->from != 2 && ram->mode == 2) {
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		if (0 /*XXX: Titan */)
			ram_mask(fuc, 0x10f200, 0x18000000, 0x18000000);
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		ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
		ram_mask(fuc, 0x1373f0, 0x00000000, 0x00000002);
		ram_mask(fuc, 0x10f830, 0x00800001, 0x00408010);
		r1373f4_init(fuc);
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		r1373f4_fini(fuc);
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		ram_mask(fuc, 0x10f808, 0x00000000, 0x00080000);
		ram_mask(fuc, 0x10f200, 0x00808000, 0x00800000);
	} else
	if (ram->from == 2 && ram->mode == 2) {
		ram_mask(fuc, 0x10f800, 0x00000004, 0x00000000);
		r1373f4_init(fuc);
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		r1373f4_fini(fuc);
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	}

	if (ram->mode != 2) /*XXX*/ {
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		if (next->bios.ramcfg_11_07_40)
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			ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
	}

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	ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
	ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
	ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
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	if (!next->bios.ramcfg_11_07_08 && !next->bios.ramcfg_11_07_04) {
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		ram_wr32(fuc, 0x10f698, 0x01010101 * next->bios.ramcfg_11_04);
		ram_wr32(fuc, 0x10f69c, 0x01010101 * next->bios.ramcfg_11_04);
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	} else
	if (!next->bios.ramcfg_11_07_08) {
		ram_wr32(fuc, 0x10f698, 0x00000000);
		ram_wr32(fuc, 0x10f69c, 0x00000000);
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	}

	if (ram->mode != 2) {
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		u32 data = 0x01000100 * next->bios.ramcfg_11_04;
		ram_nuke(fuc, 0x10f694);
		ram_mask(fuc, 0x10f694, 0xff00ff00, data);
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	}

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	if (ram->mode == 2 && next->bios.ramcfg_11_08_10)
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		data = 0x00000080;
	else
		data = 0x00000000;
	ram_mask(fuc, 0x10f60c, 0x00000080, data);

	mask = 0x00070000;
	data = 0x00000000;
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	if (!next->bios.ramcfg_11_02_80)
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		data |= 0x03000000;
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	if (!next->bios.ramcfg_11_02_40)
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		data |= 0x00002000;
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	if (!next->bios.ramcfg_11_07_10)
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		data |= 0x00004000;
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	if (!next->bios.ramcfg_11_07_08)
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		data |= 0x00000003;
	else
		data |= 0x74000000;
	ram_mask(fuc, 0x10f824, mask, data);

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	if (next->bios.ramcfg_11_01_08)
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		data = 0x00000000;
	else
		data = 0x00001000;
	ram_mask(fuc, 0x10f200, 0x00001000, data);

	if (ram_rd32(fuc, 0x10f670) & 0x80000000) {
		ram_nsec(fuc, 10000);
		ram_mask(fuc, 0x10f670, 0x80000000, 0x00000000);
	}

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	if (next->bios.ramcfg_11_08_01)
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		data = 0x00100000;
	else
		data = 0x00000000;
	ram_mask(fuc, 0x10f82c, 0x00100000, data);

	data = 0x00000000;
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	if (next->bios.ramcfg_11_08_08)
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		data |= 0x00002000;
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	if (next->bios.ramcfg_11_08_04)
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		data |= 0x00001000;
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	if (next->bios.ramcfg_11_08_02)
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		data |= 0x00004000;
	ram_mask(fuc, 0x10f830, 0x00007000, data);

	/* PFB timing */
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	ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
	ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
	ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
	ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
	ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
	ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
	ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
	ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
	ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
	ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
	ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
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	data = mask = 0x00000000;
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	if (ram->diff.ramcfg_11_08_20) {
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		if (next->bios.ramcfg_11_08_20)
			data |= 0x01000000;
		mask |= 0x01000000;
	}
	ram_mask(fuc, 0x10f200, mask, data);

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	data = mask = 0x00000000;
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	if (ram->diff.ramcfg_11_02_03) {
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		data |= next->bios.ramcfg_11_02_03 << 8;
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		mask |= 0x00000300;
	}
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	if (ram->diff.ramcfg_11_01_10) {
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		if (next->bios.ramcfg_11_01_10)
488
			data |= 0x70000000;
489 490 491
		mask |= 0x70000000;
	}
	ram_mask(fuc, 0x10f604, mask, data);
492

493
	data = mask = 0x00000000;
494
	if (ram->diff.timing_20_30_07) {
495
		data |= next->bios.timing_20_30_07 << 28;
496 497
		mask |= 0x70000000;
	}
498
	if (ram->diff.ramcfg_11_01_01) {
499
		if (next->bios.ramcfg_11_01_01)
500
			data |= 0x00000100;
501 502 503
		mask |= 0x00000100;
	}
	ram_mask(fuc, 0x10f614, mask, data);
504

505
	data = mask = 0x00000000;
506
	if (ram->diff.timing_20_30_07) {
507
		data |= next->bios.timing_20_30_07 << 28;
508 509
		mask |= 0x70000000;
	}
510
	if (ram->diff.ramcfg_11_01_02) {
511
		if (next->bios.ramcfg_11_01_02)
512
			data |= 0x00000100;
513
		mask |= 0x00000100;
514
	}
515
	ram_mask(fuc, 0x10f610, mask, data);
516 517 518

	mask = 0x33f00000;
	data = 0x00000000;
519
	if (!next->bios.ramcfg_11_01_04)
520
		data |= 0x20200000;
521
	if (!next->bios.ramcfg_11_07_80)
522 523 524 525
		data |= 0x12800000;
	/*XXX: see note above about there probably being some condition
	 *     for the 10f824 stuff that uses ramcfg 3...
	 */
526
	if (next->bios.ramcfg_11_03_f0) {
527
		if (next->bios.rammap_11_08_0c) {
528
			if (!next->bios.ramcfg_11_07_80)
529 530 531 532 533 534 535 536 537 538 539 540
				mask |= 0x00000020;
			else
				data |= 0x00000020;
			mask |= 0x00000004;
		}
	} else {
		mask |= 0x40000020;
		data |= 0x00000004;
	}

	ram_mask(fuc, 0x10f808, mask, data);

541
	ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
542

543
	data = mask = 0x00000000;
544
	if (ram->diff.ramcfg_11_02_03) {
545
		data |= next->bios.ramcfg_11_02_03;
546 547
		mask |= 0x00000003;
	}
548
	if (ram->diff.ramcfg_11_01_10) {
549
		if (next->bios.ramcfg_11_01_10)
550 551 552 553 554 555
			data |= 0x00000004;
		mask |= 0x00000004;
	}

	if ((ram_mask(fuc, 0x100770, mask, data) & mask & 4) != (data & 4)) {
		ram_mask(fuc, 0x100750, 0x00000008, 0x00000008);
556 557 558 559
		ram_wr32(fuc, 0x100710, 0x00000000);
		ram_wait(fuc, 0x100710, 0x80000000, 0x80000000, 200000);
	}

560
	data = next->bios.timing_20_30_07 << 8;
561
	if (next->bios.ramcfg_11_01_01)
562 563 564
		data |= 0x80000000;
	ram_mask(fuc, 0x100778, 0x00000700, data);

565
	ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
566 567 568 569
	data = (next->bios.timing[10] & 0x7f000000) >> 24;
	if (data < next->bios.timing_20_2c_1fc0)
		data = next->bios.timing_20_2c_1fc0;
	ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);
570
	ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
571

572 573 574 575 576 577
	ram_mask(fuc, 0x10fec4, 0x041e0f07, next->bios.timing_20_31_0800 << 26 |
					    next->bios.timing_20_31_0780 << 17 |
					    next->bios.timing_20_31_0078 << 8 |
					    next->bios.timing_20_31_0007);
	ram_mask(fuc, 0x10fec8, 0x00000027, next->bios.timing_20_31_8000 << 5 |
					    next->bios.timing_20_31_7000);
578 579

	ram_wr32(fuc, 0x10f090, 0x4000007e);
580
	ram_nsec(fuc, 2000);
581 582 583 584
	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
	ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */

585
	if (next->bios.ramcfg_11_08_10 && (ram->mode == 2) /*XXX*/) {
586
		u32 temp = ram_mask(fuc, 0x10f294, 0xff000000, 0x24000000);
587
		gk104_ram_train(fuc, 0xbc0e0000, 0xa4010000); /*XXX*/
588 589 590 591 592 593 594 595 596
		ram_nsec(fuc, 1000);
		ram_wr32(fuc, 0x10f294, temp);
	}

	ram_mask(fuc, mr[3], 0xfff, ram->base.mr[3]);
	ram_wr32(fuc, mr[0], ram->base.mr[0]);
	ram_mask(fuc, mr[8], 0xfff, ram->base.mr[8]);
	ram_nsec(fuc, 1000);
	ram_mask(fuc, mr[1], 0xfff, ram->base.mr[1]);
597
	ram_mask(fuc, mr[5], 0xfff, ram->base.mr[5] & ~0x004); /* LP3 later */
598 599 600 601 602 603 604 605 606 607 608 609 610 611 612
	ram_mask(fuc, mr[6], 0xfff, ram->base.mr[6]);
	ram_mask(fuc, mr[7], 0xfff, ram->base.mr[7]);

	if (vc == 0 && ram_have(fuc, gpio2E)) {
		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
		if (temp != ram_rd32(fuc, gpio2E)) {
			ram_wr32(fuc, gpiotrig, 1);
			ram_nsec(fuc, 20000);
		}
	}

	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
	ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
	ram_nsec(fuc, 1000);
613
	ram_nuts(ram, 0x10f200, 0x18808800, 0x00000000, 0x18808800);
614 615 616 617

	data  = ram_rd32(fuc, 0x10f978);
	data &= ~0x00046144;
	data |=  0x0000000b;
618 619
	if (!next->bios.ramcfg_11_07_08) {
		if (!next->bios.ramcfg_11_07_04)
620 621 622 623 624 625 626 627 628 629 630 631 632
			data |= 0x0000200c;
		else
			data |= 0x00000000;
	} else {
		data |= 0x00040044;
	}
	ram_wr32(fuc, 0x10f978, data);

	if (ram->mode == 1) {
		data = ram_rd32(fuc, 0x10f830) | 0x00000001;
		ram_wr32(fuc, 0x10f830, data);
	}

633
	if (!next->bios.ramcfg_11_07_08) {
634
		data = 0x88020000;
635
		if ( next->bios.ramcfg_11_07_04)
636
			data |= 0x10000000;
637
		if (!next->bios.rammap_11_08_10)
638 639 640 641
			data |= 0x00080000;
	} else {
		data = 0xa40e0000;
	}
642
	gk104_ram_train(fuc, 0xbc0f0000, data);
643 644
	if (1) /* XXX: not always? */
		ram_nsec(fuc, 1000);
645 646 647 648 649

	if (ram->mode == 2) { /*XXX*/
		ram_mask(fuc, 0x10f800, 0x00000004, 0x00000004);
	}

650 651 652
	/* LP3 */
	if (ram_mask(fuc, mr[5], 0x004, ram->base.mr[5]) != ram->base.mr[5])
		ram_nsec(fuc, 1000);
653 654 655 656 657 658

	if (ram->mode != 2) {
		ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
	}

659
	if (next->bios.ramcfg_11_07_02)
660
		gk104_ram_train(fuc, 0x80020000, 0x01000000);
661

662
	ram_unblock(fuc);
663 664 665

	if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP))
		ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
666

667
	if (next->bios.rammap_11_08_01)
668 669 670 671
		data = 0x00000800;
	else
		data = 0x00000000;
	ram_mask(fuc, 0x10f200, 0x00000800, data);
672
	ram_nuts(ram, 0x10f200, 0x18808800, data, 0x18808800);
673 674 675 676 677 678 679
	return 0;
}

/*******************************************************************************
 * DDR3
 ******************************************************************************/

680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698
static void
nvkm_sddr3_dll_reset(struct gk104_ramfuc *fuc)
{
	ram_nuke(fuc, mr[0]);
	ram_mask(fuc, mr[0], 0x100, 0x100);
	ram_mask(fuc, mr[0], 0x100, 0x000);
}

static void
nvkm_sddr3_dll_disable(struct gk104_ramfuc *fuc)
{
	u32 mr1_old = ram_rd32(fuc, mr[1]);

	if (!(mr1_old & 0x1)) {
		ram_mask(fuc, mr[1], 0x1, 0x1);
		ram_nsec(fuc, 1000);
	}
}

699
static int
700
gk104_ram_calc_sddr3(struct gk104_ram *ram, u32 freq)
701
{
702
	struct gk104_ramfuc *fuc = &ram->fuc;
703 704 705
	const u32 rcoef = ((  ram->P1 << 16) | (ram->N1 << 8) | ram->M1);
	const u32 runk0 = ram->fN1 << 16;
	const u32 runk1 = ram->fN1;
706
	struct nvkm_ram_data *next = ram->base.next;
707 708
	int vc = !next->bios.ramcfg_11_02_08;
	int mv = !next->bios.ramcfg_11_02_04;
709 710 711
	u32 mask, data;

	ram_mask(fuc, 0x10f808, 0x40000000, 0x40000000);
712
	ram_block(fuc);
713 714 715

	if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP))
		ram_wr32(fuc, 0x62c000, 0x0f0f0000);
716 717 718 719 720 721 722 723 724 725

	if (vc == 1 && ram_have(fuc, gpio2E)) {
		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[1]);
		if (temp != ram_rd32(fuc, gpio2E)) {
			ram_wr32(fuc, gpiotrig, 1);
			ram_nsec(fuc, 20000);
		}
	}

	ram_mask(fuc, 0x10f200, 0x00000800, 0x00000000);
726
	if (next->bios.ramcfg_11_03_f0)
727 728 729
		ram_mask(fuc, 0x10f808, 0x04000000, 0x04000000);

	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
730 731 732 733

	if (next->bios.ramcfg_DLLoff)
		nvkm_sddr3_dll_disable(fuc);

734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754
	ram_wr32(fuc, 0x10f210, 0x00000000); /* REFRESH_AUTO = 0 */
	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
	ram_nsec(fuc, 1000);

	ram_wr32(fuc, 0x10f090, 0x00000060);
	ram_wr32(fuc, 0x10f090, 0xc000007e);

	/*XXX: there does appear to be some kind of condition here, simply
	 *     modifying these bits in the vbios from the default pl0
	 *     entries shows no change.  however, the data does appear to
	 *     be correct and may be required for the transition back
	 */
	mask = 0x00010000;
	data = 0x00010000;

	if (1) {
		mask |= 0x800807e0;
		data |= 0x800807e0;
755 756 757 758 759
		switch (next->bios.ramcfg_11_03_c0) {
		case 3: data &= ~0x00000040; break;
		case 2: data &= ~0x00000100; break;
		case 1: data &= ~0x80000000; break;
		case 0: data &= ~0x00000400; break;
760 761
		}

762 763 764 765 766
		switch (next->bios.ramcfg_11_03_30) {
		case 3: data &= ~0x00000020; break;
		case 2: data &= ~0x00000080; break;
		case 1: data &= ~0x00080000; break;
		case 0: data &= ~0x00000200; break;
767 768 769
		}
	}

770
	if (next->bios.ramcfg_11_02_80)
771
		mask |= 0x03000000;
772
	if (next->bios.ramcfg_11_02_40)
773
		mask |= 0x00002000;
774
	if (next->bios.ramcfg_11_07_10)
775
		mask |= 0x00004000;
776
	if (next->bios.ramcfg_11_07_08)
777 778 779 780 781 782 783 784 785
		mask |= 0x00000003;
	else
		mask |= 0x14000000;
	ram_mask(fuc, 0x10f824, mask, data);

	ram_mask(fuc, 0x132040, 0x00010000, 0x00000000);

	ram_mask(fuc, 0x1373f4, 0x00000000, 0x00010010);
	data  = ram_rd32(fuc, 0x1373ec) & ~0x00030000;
786
	data |= next->bios.ramcfg_11_03_30 << 16;
787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817
	ram_wr32(fuc, 0x1373ec, data);
	ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000000);
	ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000000);

	/* (re)program refpll, if required */
	if ((ram_rd32(fuc, 0x132024) & 0xffffffff) != rcoef ||
	    (ram_rd32(fuc, 0x132034) & 0x0000ffff) != runk1) {
		ram_mask(fuc, 0x132000, 0x00000001, 0x00000000);
		ram_mask(fuc, 0x132020, 0x00000001, 0x00000000);
		ram_wr32(fuc, 0x137320, 0x00000000);
		ram_mask(fuc, 0x132030, 0xffff0000, runk0);
		ram_mask(fuc, 0x132034, 0x0000ffff, runk1);
		ram_wr32(fuc, 0x132024, rcoef);
		ram_mask(fuc, 0x132028, 0x00080000, 0x00080000);
		ram_mask(fuc, 0x132020, 0x00000001, 0x00000001);
		ram_wait(fuc, 0x137390, 0x00020000, 0x00020000, 64000);
		ram_mask(fuc, 0x132028, 0x00080000, 0x00000000);
	}

	ram_mask(fuc, 0x1373f4, 0x00000010, 0x00000010);
	ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
	ram_mask(fuc, 0x1373f4, 0x00010000, 0x00000000);

	if (ram_have(fuc, gpioMV)) {
		u32 temp  = ram_mask(fuc, gpioMV, 0x3000, fuc->r_funcMV[mv]);
		if (temp != ram_rd32(fuc, gpioMV)) {
			ram_wr32(fuc, gpiotrig, 1);
			ram_nsec(fuc, 64000);
		}
	}

818 819
	if (next->bios.ramcfg_11_02_40 ||
	    next->bios.ramcfg_11_07_10) {
820 821 822 823 824
		ram_mask(fuc, 0x132040, 0x00010000, 0x00010000);
		ram_nsec(fuc, 20000);
	}

	if (ram->mode != 2) /*XXX*/ {
825
		if (next->bios.ramcfg_11_07_40)
826 827 828
			ram_mask(fuc, 0x10f670, 0x80000000, 0x80000000);
	}

829 830 831
	ram_wr32(fuc, 0x10f65c, 0x00000011 * next->bios.rammap_11_11_0c);
	ram_wr32(fuc, 0x10f6b8, 0x01010101 * next->bios.ramcfg_11_09);
	ram_wr32(fuc, 0x10f6bc, 0x01010101 * next->bios.ramcfg_11_09);
832 833 834

	mask = 0x00010000;
	data = 0x00000000;
835
	if (!next->bios.ramcfg_11_02_80)
836
		data |= 0x03000000;
837
	if (!next->bios.ramcfg_11_02_40)
838
		data |= 0x00002000;
839
	if (!next->bios.ramcfg_11_07_10)
840
		data |= 0x00004000;
841
	if (!next->bios.ramcfg_11_07_08)
842 843 844 845 846 847
		data |= 0x00000003;
	else
		data |= 0x14000000;
	ram_mask(fuc, 0x10f824, mask, data);
	ram_nsec(fuc, 1000);

848
	if (next->bios.ramcfg_11_08_01)
849 850 851 852 853 854
		data = 0x00100000;
	else
		data = 0x00000000;
	ram_mask(fuc, 0x10f82c, 0x00100000, data);

	/* PFB timing */
855 856 857 858 859 860 861 862 863 864 865
	ram_mask(fuc, 0x10f248, 0xffffffff, next->bios.timing[10]);
	ram_mask(fuc, 0x10f290, 0xffffffff, next->bios.timing[0]);
	ram_mask(fuc, 0x10f294, 0xffffffff, next->bios.timing[1]);
	ram_mask(fuc, 0x10f298, 0xffffffff, next->bios.timing[2]);
	ram_mask(fuc, 0x10f29c, 0xffffffff, next->bios.timing[3]);
	ram_mask(fuc, 0x10f2a0, 0xffffffff, next->bios.timing[4]);
	ram_mask(fuc, 0x10f2a4, 0xffffffff, next->bios.timing[5]);
	ram_mask(fuc, 0x10f2a8, 0xffffffff, next->bios.timing[6]);
	ram_mask(fuc, 0x10f2ac, 0xffffffff, next->bios.timing[7]);
	ram_mask(fuc, 0x10f2cc, 0xffffffff, next->bios.timing[8]);
	ram_mask(fuc, 0x10f2e8, 0xffffffff, next->bios.timing[9]);
866 867 868

	mask = 0x33f00000;
	data = 0x00000000;
869
	if (!next->bios.ramcfg_11_01_04)
870
		data |= 0x20200000;
871
	if (!next->bios.ramcfg_11_07_80)
872 873 874 875
		data |= 0x12800000;
	/*XXX: see note above about there probably being some condition
	 *     for the 10f824 stuff that uses ramcfg 3...
	 */
876
	if (next->bios.ramcfg_11_03_f0) {
877
		if (next->bios.rammap_11_08_0c) {
878
			if (!next->bios.ramcfg_11_07_80)
879 880 881 882 883 884 885 886 887 888 889 890 891
				mask |= 0x00000020;
			else
				data |= 0x00000020;
			mask |= 0x08000004;
		}
		data |= 0x04000000;
	} else {
		mask |= 0x44000020;
		data |= 0x08000004;
	}

	ram_mask(fuc, 0x10f808, mask, data);

892
	ram_wr32(fuc, 0x10f870, 0x11111111 * next->bios.ramcfg_11_03_0f);
893

894
	ram_mask(fuc, 0x10f250, 0x000003f0, next->bios.timing_20_2c_003f << 4);
895

896
	data = (next->bios.timing[10] & 0x7f000000) >> 24;
897
	if (data < next->bios.timing_20_2c_1fc0)
898
		data = next->bios.timing_20_2c_1fc0;
899 900
	ram_mask(fuc, 0x10f24c, 0x7f000000, data << 24);

901
	ram_mask(fuc, 0x10f224, 0x001f0000, next->bios.timing_20_30_f8 << 16);
902 903 904 905 906 907 908 909 910

	ram_wr32(fuc, 0x10f090, 0x4000007f);
	ram_nsec(fuc, 1000);

	ram_wr32(fuc, 0x10f314, 0x00000001); /* PRECHARGE */
	ram_wr32(fuc, 0x10f310, 0x00000001); /* REFRESH */
	ram_wr32(fuc, 0x10f210, 0x80000000); /* REFRESH_AUTO = 1 */
	ram_nsec(fuc, 1000);

911 912 913 914
	if (!next->bios.ramcfg_DLLoff) {
		ram_mask(fuc, mr[1], 0x1, 0x0);
		nvkm_sddr3_dll_reset(fuc);
	}
915

916 917
	ram_mask(fuc, mr[2], 0x00000fff, ram->base.mr[2]);
	ram_mask(fuc, mr[1], 0xffffffff, ram->base.mr[1]);
918 919 920
	ram_wr32(fuc, mr[0], ram->base.mr[0]);
	ram_nsec(fuc, 1000);

921 922 923 924
	if (!next->bios.ramcfg_DLLoff) {
		nvkm_sddr3_dll_reset(fuc);
		ram_nsec(fuc, 1000);
	}
925 926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943

	if (vc == 0 && ram_have(fuc, gpio2E)) {
		u32 temp  = ram_mask(fuc, gpio2E, 0x3000, fuc->r_func2E[0]);
		if (temp != ram_rd32(fuc, gpio2E)) {
			ram_wr32(fuc, gpiotrig, 1);
			ram_nsec(fuc, 20000);
		}
	}

	if (ram->mode != 2) {
		ram_mask(fuc, 0x10f830, 0x01000000, 0x01000000);
		ram_mask(fuc, 0x10f830, 0x01000000, 0x00000000);
	}

	ram_mask(fuc, 0x10f200, 0x80000000, 0x80000000);
	ram_wr32(fuc, 0x10f318, 0x00000001); /* NOP? */
	ram_mask(fuc, 0x10f200, 0x80000000, 0x00000000);
	ram_nsec(fuc, 1000);

944
	ram_unblock(fuc);
945 946 947

	if (nvkm_device_engine(ram->base.fb->subdev.device, NVKM_ENGINE_DISP))
		ram_wr32(fuc, 0x62c000, 0x0f0f0f00);
948

949
	if (next->bios.rammap_11_08_01)
950 951 952 953 954 955 956 957 958 959 960 961
		data = 0x00000800;
	else
		data = 0x00000000;
	ram_mask(fuc, 0x10f200, 0x00000800, data);
	return 0;
}

/*******************************************************************************
 * main hooks
 ******************************************************************************/

static int
962
gk104_ram_calc_data(struct gk104_ram *ram, u32 khz, struct nvkm_ram_data *data)
963
{
964
	struct nvkm_subdev *subdev = &ram->base.fb->subdev;
965
	struct nvkm_ram_data *cfg;
966 967 968 969 970 971 972 973
	u32 mhz = khz / 1000;

	list_for_each_entry(cfg, &ram->cfg, head) {
		if (mhz >= cfg->bios.rammap_min &&
		    mhz <= cfg->bios.rammap_max) {
			*data = *cfg;
			data->freq = khz;
			return 0;
974 975 976
		}
	}

977
	nvkm_error(subdev, "ramcfg data for %dMHz not found\n", mhz);
978
	return -EINVAL;
979 980
}

981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041
static int
gk104_calc_pll_output(int fN, int M, int N, int P, int clk)
{
	return ((clk * N) + (((u16)(fN + 4096) * clk) >> 13)) / (M * P);
}

static int
gk104_pll_calc_hiclk(int target_khz, int crystal,
		int *N1, int *fN1, int *M1, int *P1,
		int *N2, int *M2, int *P2)
{
	int best_clk = 0, best_err = target_khz, p_ref, n_ref;
	bool upper = false;

	*M1 = 1;
	/* M has to be 1, otherwise it gets unstable */
	*M2 = 1;
	/* can be 1 or 2, sticking with 1 for simplicity */
	*P2 = 1;

	for (p_ref = 0x7; p_ref >= 0x5; --p_ref) {
		for (n_ref = 0x25; n_ref <= 0x2b; ++n_ref) {
			int cur_N, cur_clk, cur_err;

			cur_clk = gk104_calc_pll_output(0, 1, n_ref, p_ref, crystal);
			cur_N = target_khz / cur_clk;
			cur_err = target_khz
				- gk104_calc_pll_output(0xf000, 1, cur_N, 1, cur_clk);

			/* we found a better combination */
			if (cur_err < best_err) {
				best_err = cur_err;
				best_clk = cur_clk;
				*N2 = cur_N;
				*N1 = n_ref;
				*P1 = p_ref;
				upper = false;
			}

			cur_N += 1;
			cur_err = gk104_calc_pll_output(0xf000, 1, cur_N, 1, cur_clk)
				- target_khz;
			if (cur_err < best_err) {
				best_err = cur_err;
				best_clk = cur_clk;
				*N2 = cur_N;
				*N1 = n_ref;
				*P1 = p_ref;
				upper = true;
			}
		}
	}

	/* adjust fN to get closer to the target clock */
	*fN1 = (u16)((((best_err / *N2 * *P2) * (*P1 * *M1)) << 13) / crystal);
	if (upper)
		*fN1 = (u16)(1 - *fN1);

	return gk104_calc_pll_output(*fN1, 1, *N1, *P1, crystal);
}

1042
static int
1043
gk104_ram_calc_xits(struct gk104_ram *ram, struct nvkm_ram_data *next)
1044
{
1045
	struct gk104_ramfuc *fuc = &ram->fuc;
1046
	struct nvkm_subdev *subdev = &ram->base.fb->subdev;
1047 1048
	int refclk, i;
	int ret;
1049

1050
	ret = ram_init(fuc, ram->base.fb);
1051 1052 1053
	if (ret)
		return ret;

1054
	ram->mode = (next->freq > fuc->refpll.vco1.max_freq) ? 2 : 1;
1055 1056 1057 1058 1059 1060 1061 1062 1063 1064
	ram->from = ram_rd32(fuc, 0x1373f4) & 0x0000000f;

	/* XXX: this is *not* what nvidia do.  on fermi nvidia generally
	 * select, based on some unknown condition, one of the two possible
	 * reference frequencies listed in the vbios table for mempll and
	 * program refpll to that frequency.
	 *
	 * so far, i've seen very weird values being chosen by nvidia on
	 * kepler boards, no idea how/why they're chosen.
	 */
1065
	refclk = next->freq;
1066
	if (ram->mode == 2) {
1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081
		ret = gk104_pll_calc_hiclk(next->freq, subdev->device->crystal,
				&ram->N1, &ram->fN1, &ram->M1, &ram->P1,
				&ram->N2, &ram->M2, &ram->P2);
		fuc->mempll.refclk = ret;
		if (ret <= 0) {
			nvkm_error(subdev, "unable to calc plls\n");
			return -EINVAL;
		}
		nvkm_debug(subdev, "sucessfully calced PLLs for clock %i kHz"
				" (refclock: %i kHz)\n", next->freq, ret);
	} else {
		/* calculate refpll coefficients */
		ret = gt215_pll_calc(subdev, &fuc->refpll, refclk, &ram->N1,
				     &ram->fN1, &ram->M1, &ram->P1);
		fuc->mempll.refclk = ret;
1082
		if (ret <= 0) {
1083
			nvkm_error(subdev, "unable to calc refpll\n");
1084 1085 1086 1087 1088 1089 1090 1091
			return -EINVAL;
		}
	}

	for (i = 0; i < ARRAY_SIZE(fuc->r_mr); i++) {
		if (ram_have(fuc, mr[i]))
			ram->base.mr[i] = ram_rd32(fuc, mr[i]);
	}
1092
	ram->base.freq = next->freq;
1093 1094

	switch (ram->base.type) {
1095
	case NVKM_RAM_TYPE_DDR3:
1096
		ret = nvkm_sddr3_calc(&ram->base);
1097
		if (ret == 0)
1098
			ret = gk104_ram_calc_sddr3(ram, next->freq);
1099
		break;
1100
	case NVKM_RAM_TYPE_GDDR5:
1101
		ret = nvkm_gddr5_calc(&ram->base, ram->pnuts != 0);
1102
		if (ret == 0)
1103
			ret = gk104_ram_calc_gddr5(ram, next->freq);
1104 1105 1106 1107 1108 1109 1110 1111 1112
		break;
	default:
		ret = -ENOSYS;
		break;
	}

	return ret;
}

1113
static int
1114
gk104_ram_calc(struct nvkm_ram *base, u32 freq)
1115
{
1116 1117
	struct gk104_ram *ram = gk104_ram(base);
	struct nvkm_clk *clk = ram->base.fb->subdev.device->clk;
1118 1119
	struct nvkm_ram_data *xits = &ram->base.xition;
	struct nvkm_ram_data *copy;
1120 1121 1122
	int ret;

	if (ram->base.next == NULL) {
1123 1124
		ret = gk104_ram_calc_data(ram,
					  nvkm_clk_read(clk, nv_clk_src_mem),
1125
					  &ram->base.former);
1126 1127 1128
		if (ret)
			return ret;

1129
		ret = gk104_ram_calc_data(ram, freq, &ram->base.target);
1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152
		if (ret)
			return ret;

		if (ram->base.target.freq < ram->base.former.freq) {
			*xits = ram->base.target;
			copy = &ram->base.former;
		} else {
			*xits = ram->base.former;
			copy = &ram->base.target;
		}

		xits->bios.ramcfg_11_02_04 = copy->bios.ramcfg_11_02_04;
		xits->bios.ramcfg_11_02_03 = copy->bios.ramcfg_11_02_03;
		xits->bios.timing_20_30_07 = copy->bios.timing_20_30_07;

		ram->base.next = &ram->base.target;
		if (memcmp(xits, &ram->base.former, sizeof(xits->bios)))
			ram->base.next = &ram->base.xition;
	} else {
		BUG_ON(ram->base.next != &ram->base.xition);
		ram->base.next = &ram->base.target;
	}

1153
	return gk104_ram_calc_xits(ram, ram->base.next);
1154 1155
}

1156
static void
1157
gk104_ram_prog_0(struct gk104_ram *ram, u32 freq)
1158
{
1159
	struct nvkm_device *device = ram->base.fb->subdev.device;
1160
	struct nvkm_ram_data *cfg;
1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180
	u32 mhz = freq / 1000;
	u32 mask, data;

	list_for_each_entry(cfg, &ram->cfg, head) {
		if (mhz >= cfg->bios.rammap_min &&
		    mhz <= cfg->bios.rammap_max)
			break;
	}

	if (&cfg->head == &ram->cfg)
		return;

	if (mask = 0, data = 0, ram->diff.rammap_11_0a_03fe) {
		data |= cfg->bios.rammap_11_0a_03fe << 12;
		mask |= 0x001ff000;
	}
	if (ram->diff.rammap_11_09_01ff) {
		data |= cfg->bios.rammap_11_09_01ff;
		mask |= 0x000001ff;
	}
1181
	nvkm_mask(device, 0x10f468, mask, data);
1182 1183 1184 1185 1186

	if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) {
		data |= cfg->bios.rammap_11_0a_0400;
		mask |= 0x00000001;
	}
1187
	nvkm_mask(device, 0x10f420, mask, data);
1188 1189 1190 1191 1192

	if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) {
		data |= cfg->bios.rammap_11_0a_0800;
		mask |= 0x00000001;
	}
1193
	nvkm_mask(device, 0x10f430, mask, data);
1194 1195 1196 1197 1198

	if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) {
		data |= cfg->bios.rammap_11_0b_01f0;
		mask |= 0x0000001f;
	}
1199
	nvkm_mask(device, 0x10f400, mask, data);
1200 1201 1202 1203 1204

	if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) {
		data |= cfg->bios.rammap_11_0b_0200 << 9;
		mask |= 0x00000200;
	}
1205
	nvkm_mask(device, 0x10f410, mask, data);
1206 1207 1208 1209 1210 1211 1212 1213 1214

	if (mask = 0, data = 0, ram->diff.rammap_11_0d) {
		data |= cfg->bios.rammap_11_0d << 16;
		mask |= 0x00ff0000;
	}
	if (ram->diff.rammap_11_0f) {
		data |= cfg->bios.rammap_11_0f << 8;
		mask |= 0x0000ff00;
	}
1215
	nvkm_mask(device, 0x10f440, mask, data);
1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228

	if (mask = 0, data = 0, ram->diff.rammap_11_0e) {
		data |= cfg->bios.rammap_11_0e << 8;
		mask |= 0x0000ff00;
	}
	if (ram->diff.rammap_11_0b_0800) {
		data |= cfg->bios.rammap_11_0b_0800 << 7;
		mask |= 0x00000080;
	}
	if (ram->diff.rammap_11_0b_0400) {
		data |= cfg->bios.rammap_11_0b_0400 << 5;
		mask |= 0x00000020;
	}
1229
	nvkm_mask(device, 0x10f444, mask, data);
1230 1231
}

1232
static int
1233
gk104_ram_prog(struct nvkm_ram *base)
1234
{
1235
	struct gk104_ram *ram = gk104_ram(base);
1236
	struct gk104_ramfuc *fuc = &ram->fuc;
1237
	struct nvkm_device *device = ram->base.fb->subdev.device;
1238
	struct nvkm_ram_data *next = ram->base.next;
1239

1240
	if (!nvkm_boolopt(device->cfgopt, "NvMemExec", true)) {
1241 1242 1243 1244
		ram_exec(fuc, false);
		return (ram->base.next == &ram->base.xition);
	}

1245
	gk104_ram_prog_0(ram, 1000);
1246
	ram_exec(fuc, true);
1247
	gk104_ram_prog_0(ram, next->freq);
1248

1249
	return (ram->base.next == &ram->base.xition);
1250 1251 1252
}

static void
1253
gk104_ram_tidy(struct nvkm_ram *base)
1254
{
1255
	struct gk104_ram *ram = gk104_ram(base);
1256
	ram->base.next = NULL;
1257
	ram_exec(&ram->fuc, false);
1258 1259
}

1260
struct gk104_ram_train {
1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272
	u16 mask;
	struct nvbios_M0209S remap;
	struct nvbios_M0209S type00;
	struct nvbios_M0209S type01;
	struct nvbios_M0209S type04;
	struct nvbios_M0209S type06;
	struct nvbios_M0209S type07;
	struct nvbios_M0209S type08;
	struct nvbios_M0209S type09;
};

static int
1273
gk104_ram_train_type(struct nvkm_ram *ram, int i, u8 ramcfg,
1274
		     struct gk104_ram_train *train)
1275
{
1276
	struct nvkm_bios *bios = ram->fb->subdev.device->bios;
1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333
	struct nvbios_M0205E M0205E;
	struct nvbios_M0205S M0205S;
	struct nvbios_M0209E M0209E;
	struct nvbios_M0209S *remap = &train->remap;
	struct nvbios_M0209S *value;
	u8  ver, hdr, cnt, len;
	u32 data;

	/* determine type of data for this index */
	if (!(data = nvbios_M0205Ep(bios, i, &ver, &hdr, &cnt, &len, &M0205E)))
		return -ENOENT;

	switch (M0205E.type) {
	case 0x00: value = &train->type00; break;
	case 0x01: value = &train->type01; break;
	case 0x04: value = &train->type04; break;
	case 0x06: value = &train->type06; break;
	case 0x07: value = &train->type07; break;
	case 0x08: value = &train->type08; break;
	case 0x09: value = &train->type09; break;
	default:
		return 0;
	}

	/* training data index determined by ramcfg strap */
	if (!(data = nvbios_M0205Sp(bios, i, ramcfg, &ver, &hdr, &M0205S)))
		return -EINVAL;
	i = M0205S.data;

	/* training data format information */
	if (!(data = nvbios_M0209Ep(bios, i, &ver, &hdr, &cnt, &len, &M0209E)))
		return -EINVAL;

	/* ... and the raw data */
	if (!(data = nvbios_M0209Sp(bios, i, 0, &ver, &hdr, value)))
		return -EINVAL;

	if (M0209E.v02_07 == 2) {
		/* of course! why wouldn't we have a pointer to another entry
		 * in the same table, and use the first one as an array of
		 * remap indices...
		 */
		if (!(data = nvbios_M0209Sp(bios, M0209E.v03, 0, &ver, &hdr,
					    remap)))
			return -EINVAL;

		for (i = 0; i < ARRAY_SIZE(value->data); i++)
			value->data[i] = remap->data[value->data[i]];
	} else
	if (M0209E.v02_07 != 1)
		return -EINVAL;

	train->mask |= 1 << M0205E.type;
	return 0;
}

static int
1334
gk104_ram_train_init_0(struct nvkm_ram *ram, struct gk104_ram_train *train)
1335
{
1336
	struct nvkm_subdev *subdev = &ram->fb->subdev;
1337
	struct nvkm_device *device = subdev->device;
1338 1339 1340
	int i, j;

	if ((train->mask & 0x03d3) != 0x03d3) {
1341
		nvkm_warn(subdev, "missing link training data\n");
1342 1343 1344 1345 1346
		return -EINVAL;
	}

	for (i = 0; i < 0x30; i++) {
		for (j = 0; j < 8; j += 4) {
1347 1348
			nvkm_wr32(device, 0x10f968 + j, 0x00000000 | (i << 8));
			nvkm_wr32(device, 0x10f920 + j, 0x00000000 |
1349 1350
						   train->type08.data[i] << 4 |
						   train->type06.data[i]);
1351 1352
			nvkm_wr32(device, 0x10f918 + j, train->type00.data[i]);
			nvkm_wr32(device, 0x10f920 + j, 0x00000100 |
1353 1354
						   train->type09.data[i] << 4 |
						   train->type07.data[i]);
1355
			nvkm_wr32(device, 0x10f918 + j, train->type01.data[i]);
1356 1357 1358 1359 1360
		}
	}

	for (j = 0; j < 8; j += 4) {
		for (i = 0; i < 0x100; i++) {
1361 1362
			nvkm_wr32(device, 0x10f968 + j, i);
			nvkm_wr32(device, 0x10f900 + j, train->type04.data[i]);
1363 1364 1365 1366 1367 1368 1369
		}
	}

	return 0;
}

static int
1370
gk104_ram_train_init(struct nvkm_ram *ram)
1371
{
1372
	u8 ramcfg = nvbios_ramcfg_index(&ram->fb->subdev);
1373
	struct gk104_ram_train *train;
B
Ben Skeggs 已提交
1374
	int ret, i;
1375

B
Ben Skeggs 已提交
1376 1377 1378 1379
	if (!(train = kzalloc(sizeof(*train), GFP_KERNEL)))
		return -ENOMEM;

	for (i = 0; i < 0x100; i++) {
1380
		ret = gk104_ram_train_type(ram, i, ramcfg, train);
B
Ben Skeggs 已提交
1381 1382
		if (ret && ret != -ENOENT)
			break;
1383 1384
	}

1385 1386 1387
	switch (ram->type) {
	case NVKM_RAM_TYPE_GDDR5:
		ret = gk104_ram_train_init_0(ram, train);
1388 1389 1390 1391 1392 1393 1394 1395 1396 1397
		break;
	default:
		ret = 0;
		break;
	}

	kfree(train);
	return ret;
}

1398
int
1399
gk104_ram_init(struct nvkm_ram *ram)
1400
{
1401 1402
	struct nvkm_subdev *subdev = &ram->fb->subdev;
	struct nvkm_device *device = subdev->device;
1403
	struct nvkm_bios *bios = device->bios;
1404 1405
	u8  ver, hdr, cnt, len, snr, ssz;
	u32 data, save;
1406
	int i;
1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418

	/* run a bunch of tables from rammap table.  there's actually
	 * individual pointers for each rammap entry too, but, nvidia
	 * seem to just run the last two entries' scripts early on in
	 * their init, and never again.. we'll just run 'em all once
	 * for now.
	 *
	 * i strongly suspect that each script is for a separate mode
	 * (likely selected by 0x10f65c's lower bits?), and the
	 * binary driver skips the one that's already been setup by
	 * the init tables.
	 */
1419
	data = nvbios_rammapTe(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
1420 1421 1422
	if (!data || hdr < 0x15)
		return -EINVAL;

1423 1424
	cnt  = nvbios_rd08(bios, data + 0x14); /* guess at count */
	data = nvbios_rd32(bios, data + 0x10); /* guess u32... */
1425
	save = nvkm_rd32(device, 0x10f65c) & 0x000000f0;
1426 1427
	for (i = 0; i < cnt; i++, data += 4) {
		if (i != save >> 4) {
1428
			nvkm_mask(device, 0x10f65c, 0x000000f0, i << 4);
1429
			nvbios_exec(&(struct nvbios_init) {
1430
					.subdev = subdev,
1431
					.bios = bios,
1432
					.offset = nvbios_rd32(bios, data),
1433 1434 1435
					.execute = 1,
				    });
		}
1436
	}
1437 1438 1439 1440
	nvkm_mask(device, 0x10f65c, 0x000000f0, save);
	nvkm_mask(device, 0x10f584, 0x11000000, 0x00000000);
	nvkm_wr32(device, 0x10ecc0, 0xffffffff);
	nvkm_mask(device, 0x10f160, 0x00000010, 0x00000010);
1441

1442
	return gk104_ram_train_init(ram);
1443 1444
}

1445
static int
1446
gk104_ram_ctor_data(struct gk104_ram *ram, u8 ramcfg, int i)
1447
{
1448
	struct nvkm_bios *bios = ram->base.fb->subdev.device->bios;
1449
	struct nvkm_ram_data *cfg;
1450 1451
	struct nvbios_ramcfg *d = &ram->diff;
	struct nvbios_ramcfg *p, *n;
1452 1453 1454 1455 1456 1457
	u8  ver, hdr, cnt, len;
	u32 data;
	int ret;

	if (!(cfg = kmalloc(sizeof(*cfg), GFP_KERNEL)))
		return -ENOMEM;
1458 1459
	p = &list_last_entry(&ram->cfg, typeof(*cfg), head)->bios;
	n = &cfg->bios;
1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487

	/* memory config data for a range of target frequencies */
	data = nvbios_rammapEp(bios, i, &ver, &hdr, &cnt, &len, &cfg->bios);
	if (ret = -ENOENT, !data)
		goto done;
	if (ret = -ENOSYS, ver != 0x11 || hdr < 0x12)
		goto done;

	/* ... and a portion specific to the attached memory */
	data = nvbios_rammapSp(bios, data, ver, hdr, cnt, len, ramcfg,
			       &ver, &hdr, &cfg->bios);
	if (ret = -EINVAL, !data)
		goto done;
	if (ret = -ENOSYS, ver != 0x11 || hdr < 0x0a)
		goto done;

	/* lookup memory timings, if bios says they're present */
	if (cfg->bios.ramcfg_timing != 0xff) {
		data = nvbios_timingEp(bios, cfg->bios.ramcfg_timing,
				       &ver, &hdr, &cnt, &len,
				       &cfg->bios);
		if (ret = -EINVAL, !data)
			goto done;
		if (ret = -ENOSYS, ver != 0x20 || hdr < 0x33)
			goto done;
	}

	list_add_tail(&cfg->head, &ram->cfg);
1488 1489 1490
	if (ret = 0, i == 0)
		goto done;

1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501
	d->rammap_11_0a_03fe |= p->rammap_11_0a_03fe != n->rammap_11_0a_03fe;
	d->rammap_11_09_01ff |= p->rammap_11_09_01ff != n->rammap_11_09_01ff;
	d->rammap_11_0a_0400 |= p->rammap_11_0a_0400 != n->rammap_11_0a_0400;
	d->rammap_11_0a_0800 |= p->rammap_11_0a_0800 != n->rammap_11_0a_0800;
	d->rammap_11_0b_01f0 |= p->rammap_11_0b_01f0 != n->rammap_11_0b_01f0;
	d->rammap_11_0b_0200 |= p->rammap_11_0b_0200 != n->rammap_11_0b_0200;
	d->rammap_11_0d |= p->rammap_11_0d != n->rammap_11_0d;
	d->rammap_11_0f |= p->rammap_11_0f != n->rammap_11_0f;
	d->rammap_11_0e |= p->rammap_11_0e != n->rammap_11_0e;
	d->rammap_11_0b_0800 |= p->rammap_11_0b_0800 != n->rammap_11_0b_0800;
	d->rammap_11_0b_0400 |= p->rammap_11_0b_0400 != n->rammap_11_0b_0400;
1502 1503 1504 1505 1506 1507
	d->ramcfg_11_01_01 |= p->ramcfg_11_01_01 != n->ramcfg_11_01_01;
	d->ramcfg_11_01_02 |= p->ramcfg_11_01_02 != n->ramcfg_11_01_02;
	d->ramcfg_11_01_10 |= p->ramcfg_11_01_10 != n->ramcfg_11_01_10;
	d->ramcfg_11_02_03 |= p->ramcfg_11_02_03 != n->ramcfg_11_02_03;
	d->ramcfg_11_08_20 |= p->ramcfg_11_08_20 != n->ramcfg_11_08_20;
	d->timing_20_30_07 |= p->timing_20_30_07 != n->timing_20_30_07;
1508 1509 1510 1511 1512 1513
done:
	if (ret)
		kfree(cfg);
	return ret;
}

1514 1515
static void *
gk104_ram_dtor(struct nvkm_ram *base)
1516
{
1517
	struct gk104_ram *ram = gk104_ram(base);
1518
	struct nvkm_ram_data *cfg, *tmp;
1519 1520 1521 1522 1523

	list_for_each_entry_safe(cfg, tmp, &ram->cfg, head) {
		kfree(cfg);
	}

1524
	return ram;
1525 1526
}

1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539
static const struct nvkm_ram_func
gk104_ram_func = {
	.dtor = gk104_ram_dtor,
	.init = gk104_ram_init,
	.get = gf100_ram_get,
	.put = gf100_ram_put,
	.calc = gk104_ram_calc,
	.prog = gk104_ram_prog,
	.tidy = gk104_ram_tidy,
};

int
gk104_ram_new(struct nvkm_fb *fb, struct nvkm_ram **pram)
1540
{
1541 1542
	struct nvkm_subdev *subdev = &fb->subdev;
	struct nvkm_device *device = subdev->device;
1543 1544
	struct nvkm_bios *bios = device->bios;
	struct nvkm_gpio *gpio = device->gpio;
1545
	struct dcb_gpio_func func;
1546
	struct gk104_ram *ram;
1547
	int ret, i;
1548
	u8  ramcfg = nvbios_ramcfg_index(subdev);
1549
	u32 tmp;
1550

1551 1552 1553 1554 1555
	if (!(ram = kzalloc(sizeof(*ram), GFP_KERNEL)))
		return -ENOMEM;
	*pram = &ram->base;

	ret = gf100_ram_ctor(&gk104_ram_func, fb, 0x022554, &ram->base);
1556 1557 1558
	if (ret)
		return ret;

1559 1560
	INIT_LIST_HEAD(&ram->cfg);

1561 1562 1563 1564 1565
	/* calculate a mask of differently configured memory partitions,
	 * because, of course reclocking wasn't complicated enough
	 * already without having to treat some of them differently to
	 * the others....
	 */
1566 1567
	ram->parts = nvkm_rd32(device, 0x022438);
	ram->pmask = nvkm_rd32(device, 0x022554);
1568 1569 1570
	ram->pnuts = 0;
	for (i = 0, tmp = 0; i < ram->parts; i++) {
		if (!(ram->pmask & (1 << i))) {
1571
			u32 cfg1 = nvkm_rd32(device, 0x110204 + (i * 0x1000));
1572 1573 1574 1575 1576 1577 1578 1579
			if (tmp && tmp != cfg1) {
				ram->pnuts |= (1 << i);
				continue;
			}
			tmp = cfg1;
		}
	}

1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590
	/* parse bios data for all rammap table entries up-front, and
	 * build information on whether certain fields differ between
	 * any of the entries.
	 *
	 * the binary driver appears to completely ignore some fields
	 * when all entries contain the same value.  at first, it was
	 * hoped that these were mere optimisations and the bios init
	 * tables had configured as per the values here, but there is
	 * evidence now to suggest that this isn't the case and we do
	 * need to treat this condition as a "don't touch" indicator.
	 */
1591
	for (i = 0; !ret; i++) {
1592
		ret = gk104_ram_ctor_data(ram, ramcfg, i);
1593
		if (ret && ret != -ENOENT) {
1594
			nvkm_error(subdev, "failed to parse ramcfg data\n");
1595 1596 1597 1598 1599
			return ret;
		}
	}

	/* parse bios data for both pll's */
1600 1601
	ret = nvbios_pll_parse(bios, 0x0c, &ram->fuc.refpll);
	if (ret) {
1602
		nvkm_error(subdev, "mclk refpll data not found\n");
1603 1604 1605 1606 1607
		return ret;
	}

	ret = nvbios_pll_parse(bios, 0x04, &ram->fuc.mempll);
	if (ret) {
1608
		nvkm_error(subdev, "mclk pll data not found\n");
1609 1610 1611
		return ret;
	}

1612
	/* lookup memory voltage gpios */
1613
	ret = nvkm_gpio_find(gpio, 0, 0x18, DCB_GPIO_UNUSED, &func);
1614 1615 1616 1617 1618 1619
	if (ret == 0) {
		ram->fuc.r_gpioMV = ramfuc_reg(0x00d610 + (func.line * 0x04));
		ram->fuc.r_funcMV[0] = (func.log[0] ^ 2) << 12;
		ram->fuc.r_funcMV[1] = (func.log[1] ^ 2) << 12;
	}

1620
	ret = nvkm_gpio_find(gpio, 0, 0x2e, DCB_GPIO_UNUSED, &func);
1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676
	if (ret == 0) {
		ram->fuc.r_gpio2E = ramfuc_reg(0x00d610 + (func.line * 0x04));
		ram->fuc.r_func2E[0] = (func.log[0] ^ 2) << 12;
		ram->fuc.r_func2E[1] = (func.log[1] ^ 2) << 12;
	}

	ram->fuc.r_gpiotrig = ramfuc_reg(0x00d604);

	ram->fuc.r_0x132020 = ramfuc_reg(0x132020);
	ram->fuc.r_0x132028 = ramfuc_reg(0x132028);
	ram->fuc.r_0x132024 = ramfuc_reg(0x132024);
	ram->fuc.r_0x132030 = ramfuc_reg(0x132030);
	ram->fuc.r_0x132034 = ramfuc_reg(0x132034);
	ram->fuc.r_0x132000 = ramfuc_reg(0x132000);
	ram->fuc.r_0x132004 = ramfuc_reg(0x132004);
	ram->fuc.r_0x132040 = ramfuc_reg(0x132040);

	ram->fuc.r_0x10f248 = ramfuc_reg(0x10f248);
	ram->fuc.r_0x10f290 = ramfuc_reg(0x10f290);
	ram->fuc.r_0x10f294 = ramfuc_reg(0x10f294);
	ram->fuc.r_0x10f298 = ramfuc_reg(0x10f298);
	ram->fuc.r_0x10f29c = ramfuc_reg(0x10f29c);
	ram->fuc.r_0x10f2a0 = ramfuc_reg(0x10f2a0);
	ram->fuc.r_0x10f2a4 = ramfuc_reg(0x10f2a4);
	ram->fuc.r_0x10f2a8 = ramfuc_reg(0x10f2a8);
	ram->fuc.r_0x10f2ac = ramfuc_reg(0x10f2ac);
	ram->fuc.r_0x10f2cc = ramfuc_reg(0x10f2cc);
	ram->fuc.r_0x10f2e8 = ramfuc_reg(0x10f2e8);
	ram->fuc.r_0x10f250 = ramfuc_reg(0x10f250);
	ram->fuc.r_0x10f24c = ramfuc_reg(0x10f24c);
	ram->fuc.r_0x10fec4 = ramfuc_reg(0x10fec4);
	ram->fuc.r_0x10fec8 = ramfuc_reg(0x10fec8);
	ram->fuc.r_0x10f604 = ramfuc_reg(0x10f604);
	ram->fuc.r_0x10f614 = ramfuc_reg(0x10f614);
	ram->fuc.r_0x10f610 = ramfuc_reg(0x10f610);
	ram->fuc.r_0x100770 = ramfuc_reg(0x100770);
	ram->fuc.r_0x100778 = ramfuc_reg(0x100778);
	ram->fuc.r_0x10f224 = ramfuc_reg(0x10f224);

	ram->fuc.r_0x10f870 = ramfuc_reg(0x10f870);
	ram->fuc.r_0x10f698 = ramfuc_reg(0x10f698);
	ram->fuc.r_0x10f694 = ramfuc_reg(0x10f694);
	ram->fuc.r_0x10f6b8 = ramfuc_reg(0x10f6b8);
	ram->fuc.r_0x10f808 = ramfuc_reg(0x10f808);
	ram->fuc.r_0x10f670 = ramfuc_reg(0x10f670);
	ram->fuc.r_0x10f60c = ramfuc_reg(0x10f60c);
	ram->fuc.r_0x10f830 = ramfuc_reg(0x10f830);
	ram->fuc.r_0x1373ec = ramfuc_reg(0x1373ec);
	ram->fuc.r_0x10f800 = ramfuc_reg(0x10f800);
	ram->fuc.r_0x10f82c = ramfuc_reg(0x10f82c);

	ram->fuc.r_0x10f978 = ramfuc_reg(0x10f978);
	ram->fuc.r_0x10f910 = ramfuc_reg(0x10f910);
	ram->fuc.r_0x10f914 = ramfuc_reg(0x10f914);

	switch (ram->base.type) {
1677
	case NVKM_RAM_TYPE_GDDR5:
1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688
		ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
		ram->fuc.r_mr[1] = ramfuc_reg(0x10f330);
		ram->fuc.r_mr[2] = ramfuc_reg(0x10f334);
		ram->fuc.r_mr[3] = ramfuc_reg(0x10f338);
		ram->fuc.r_mr[4] = ramfuc_reg(0x10f33c);
		ram->fuc.r_mr[5] = ramfuc_reg(0x10f340);
		ram->fuc.r_mr[6] = ramfuc_reg(0x10f344);
		ram->fuc.r_mr[7] = ramfuc_reg(0x10f348);
		ram->fuc.r_mr[8] = ramfuc_reg(0x10f354);
		ram->fuc.r_mr[15] = ramfuc_reg(0x10f34c);
		break;
1689
	case NVKM_RAM_TYPE_DDR3:
1690
		ram->fuc.r_mr[0] = ramfuc_reg(0x10f300);
1691
		ram->fuc.r_mr[1] = ramfuc_reg(0x10f304);
1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712
		ram->fuc.r_mr[2] = ramfuc_reg(0x10f320);
		break;
	default:
		break;
	}

	ram->fuc.r_0x62c000 = ramfuc_reg(0x62c000);
	ram->fuc.r_0x10f200 = ramfuc_reg(0x10f200);
	ram->fuc.r_0x10f210 = ramfuc_reg(0x10f210);
	ram->fuc.r_0x10f310 = ramfuc_reg(0x10f310);
	ram->fuc.r_0x10f314 = ramfuc_reg(0x10f314);
	ram->fuc.r_0x10f318 = ramfuc_reg(0x10f318);
	ram->fuc.r_0x10f090 = ramfuc_reg(0x10f090);
	ram->fuc.r_0x10f69c = ramfuc_reg(0x10f69c);
	ram->fuc.r_0x10f824 = ramfuc_reg(0x10f824);
	ram->fuc.r_0x1373f0 = ramfuc_reg(0x1373f0);
	ram->fuc.r_0x1373f4 = ramfuc_reg(0x1373f4);
	ram->fuc.r_0x137320 = ramfuc_reg(0x137320);
	ram->fuc.r_0x10f65c = ramfuc_reg(0x10f65c);
	ram->fuc.r_0x10f6bc = ramfuc_reg(0x10f6bc);
	ram->fuc.r_0x100710 = ramfuc_reg(0x100710);
B
Ben Skeggs 已提交
1713
	ram->fuc.r_0x100750 = ramfuc_reg(0x100750);
1714 1715
	return 0;
}