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6625f55c
编写于
8月 20, 2015
作者:
B
Ben Skeggs
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
drm/nouveau/clk: convert to new-style nvkm_subdev
Signed-off-by:
N
Ben Skeggs
<
bskeggs@redhat.com
>
上级
bb23f9d7
变更
31
隐藏空白更改
内联
并排
Showing
31 changed file
with
537 addition
and
706 deletion
+537
-706
drivers/gpu/drm/nouveau/include/nvif/device.h
drivers/gpu/drm/nouveau/include/nvif/device.h
+1
-1
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
+14
-54
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+66
-66
drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
+2
-2
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
+0
-9
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
+0
-8
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+0
-3
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
+0
-2
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
+0
-8
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
+0
-4
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
+0
-5
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
+0
-16
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+0
-14
drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
+1
-0
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
+62
-43
drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c
+21
-20
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
+42
-55
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
+35
-48
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
+42
-63
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
+37
-50
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
+48
-61
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
+15
-32
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
+31
-44
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
+74
-79
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
+11
-11
drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h
drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h
+26
-0
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
+2
-2
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
+2
-1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
+1
-1
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
+3
-3
未找到文件。
drivers/gpu/drm/nouveau/include/nvif/device.h
浏览文件 @
6625f55c
...
...
@@ -55,7 +55,7 @@ u64 nvif_device_time(struct nvif_device *);
#define nvxx_mmu(a) nvkm_mmu(nvxx_device(a))
#define nvxx_bar(a) nvxx_device(a)->bar
#define nvxx_gpio(a) nvkm_gpio(nvxx_device(a))
#define nvxx_clk(a) nv
km_clk(nvxx_device(a))
#define nvxx_clk(a) nv
xx_device(a)->clk
#define nvxx_i2c(a) nvkm_i2c(nvxx_device(a))
#define nvxx_therm(a) nvkm_therm(nvxx_device(a))
...
...
drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h
浏览文件 @
6625f55c
...
...
@@ -71,9 +71,10 @@ struct nvkm_domain {
};
struct
nvkm_clk
{
const
struct
nvkm_clk_func
*
func
;
struct
nvkm_subdev
subdev
;
struct
nvkm_domain
*
domains
;
const
struct
nvkm_domain
*
domains
;
struct
nvkm_pstate
bstate
;
struct
list_head
states
;
...
...
@@ -94,68 +95,27 @@ struct nvkm_clk {
bool
allow_reclock
;
int
(
*
read
)(
struct
nvkm_clk
*
,
enum
nv_clk_src
);
int
(
*
calc
)(
struct
nvkm_clk
*
,
struct
nvkm_cstate
*
);
int
(
*
prog
)(
struct
nvkm_clk
*
);
void
(
*
tidy
)(
struct
nvkm_clk
*
);
/*XXX: die, these are here *only* to support the completely
* bat-shit insane what-was-n
vkm
_hw.c code
* bat-shit insane what-was-n
ouveau
_hw.c code
*/
int
(
*
pll_calc
)(
struct
nvkm_clk
*
,
struct
nvbios_pll
*
,
int
clk
,
struct
nvkm_pll_vals
*
pv
);
int
(
*
pll_prog
)(
struct
nvkm_clk
*
,
u32
reg1
,
struct
nvkm_pll_vals
*
pv
);
};
static
inline
struct
nvkm_clk
*
nvkm_clk
(
void
*
obj
)
{
return
(
void
*
)
nvkm_subdev
(
obj
,
NVDEV_SUBDEV_CLK
);
}
#define nvkm_clk_create(p,e,o,i,r,s,n,d) \
nvkm_clk_create_((p), (e), (o), (i), (r), (s), (n), sizeof(**d), \
(void **)d)
#define nvkm_clk_destroy(p) ({ \
struct nvkm_clk *_clk = (p); \
_nvkm_clk_dtor(nv_object(_clk)); \
})
#define nvkm_clk_init(p) ({ \
struct nvkm_clk *_clk = (p); \
_nvkm_clk_init(nv_object(_clk)); \
})
#define nvkm_clk_fini(p,s) ({ \
struct nvkm_clk *_clk = (p); \
_nvkm_clk_fini(nv_object(_clk), (s)); \
})
int
nvkm_clk_create_
(
struct
nvkm_object
*
,
struct
nvkm_object
*
,
struct
nvkm_oclass
*
,
struct
nvkm_domain
*
,
struct
nvkm_pstate
*
,
int
,
bool
,
int
,
void
**
);
void
_nvkm_clk_dtor
(
struct
nvkm_object
*
);
int
_nvkm_clk_init
(
struct
nvkm_object
*
);
int
_nvkm_clk_fini
(
struct
nvkm_object
*
,
bool
);
extern
struct
nvkm_oclass
nv04_clk_oclass
;
extern
struct
nvkm_oclass
nv40_clk_oclass
;
extern
struct
nvkm_oclass
*
nv50_clk_oclass
;
extern
struct
nvkm_oclass
*
g84_clk_oclass
;
extern
struct
nvkm_oclass
*
mcp77_clk_oclass
;
extern
struct
nvkm_oclass
gt215_clk_oclass
;
extern
struct
nvkm_oclass
gf100_clk_oclass
;
extern
struct
nvkm_oclass
gk104_clk_oclass
;
extern
struct
nvkm_oclass
gk20a_clk_oclass
;
int
nv04_clk_pll_set
(
struct
nvkm_clk
*
,
u32
type
,
u32
freq
);
int
nv04_clk_pll_calc
(
struct
nvkm_clk
*
,
struct
nvbios_pll
*
,
int
clk
,
struct
nvkm_pll_vals
*
);
int
nv04_clk_pll_prog
(
struct
nvkm_clk
*
,
u32
reg1
,
struct
nvkm_pll_vals
*
);
int
gt215_clk_pll_calc
(
struct
nvkm_clk
*
,
struct
nvbios_pll
*
,
int
clk
,
struct
nvkm_pll_vals
*
);
int
nvkm_clk_read
(
struct
nvkm_clk
*
,
enum
nv_clk_src
);
int
nvkm_clk_ustate
(
struct
nvkm_clk
*
,
int
req
,
int
pwr
);
int
nvkm_clk_astate
(
struct
nvkm_clk
*
,
int
req
,
int
rel
,
bool
wait
);
int
nvkm_clk_dstate
(
struct
nvkm_clk
*
,
int
req
,
int
rel
);
int
nvkm_clk_tstate
(
struct
nvkm_clk
*
,
int
req
,
int
rel
);
int
nv04_clk_new
(
struct
nvkm_device
*
,
int
,
struct
nvkm_clk
**
);
int
nv40_clk_new
(
struct
nvkm_device
*
,
int
,
struct
nvkm_clk
**
);
int
nv50_clk_new
(
struct
nvkm_device
*
,
int
,
struct
nvkm_clk
**
);
int
g84_clk_new
(
struct
nvkm_device
*
,
int
,
struct
nvkm_clk
**
);
int
mcp77_clk_new
(
struct
nvkm_device
*
,
int
,
struct
nvkm_clk
**
);
int
gt215_clk_new
(
struct
nvkm_device
*
,
int
,
struct
nvkm_clk
**
);
int
gf100_clk_new
(
struct
nvkm_device
*
,
int
,
struct
nvkm_clk
**
);
int
gk104_clk_new
(
struct
nvkm_device
*
,
int
,
struct
nvkm_clk
**
);
int
gk20a_clk_new
(
struct
nvkm_device
*
,
int
,
struct
nvkm_clk
**
);
#endif
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
浏览文件 @
6625f55c
...
...
@@ -78,7 +78,7 @@ nv4_chipset = {
.
name
=
"NV04"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv04_devinit_new,
// .fb = nv04_fb_new,
// .i2c = nv04_i2c_new,
...
...
@@ -98,7 +98,7 @@ nv5_chipset = {
.
name
=
"NV05"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv05_devinit_new,
// .fb = nv04_fb_new,
// .i2c = nv04_i2c_new,
...
...
@@ -118,7 +118,7 @@ nv10_chipset = {
.
name
=
"NV10"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -137,7 +137,7 @@ nv11_chipset = {
.
name
=
"NV11"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -158,7 +158,7 @@ nv15_chipset = {
.
name
=
"NV15"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -179,7 +179,7 @@ nv17_chipset = {
.
name
=
"NV17"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -200,7 +200,7 @@ nv18_chipset = {
.
name
=
"NV18"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -221,7 +221,7 @@ nv1a_chipset = {
.
name
=
"nForce"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv1a_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -242,7 +242,7 @@ nv1f_chipset = {
.
name
=
"nForce2"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv1a_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -263,7 +263,7 @@ nv20_chipset = {
.
name
=
"NV20"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv20_devinit_new,
// .fb = nv20_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -284,7 +284,7 @@ nv25_chipset = {
.
name
=
"NV25"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -305,7 +305,7 @@ nv28_chipset = {
.
name
=
"NV28"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -326,7 +326,7 @@ nv2a_chipset = {
.
name
=
"NV2A"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv20_devinit_new,
// .fb = nv25_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -347,7 +347,7 @@ nv30_chipset = {
.
name
=
"NV30"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv20_devinit_new,
// .fb = nv30_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -368,7 +368,7 @@ nv31_chipset = {
.
name
=
"NV31"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv20_devinit_new,
// .fb = nv30_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -390,7 +390,7 @@ nv34_chipset = {
.
name
=
"NV34"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv10_devinit_new,
// .fb = nv10_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -412,7 +412,7 @@ nv35_chipset = {
.
name
=
"NV35"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv04_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv20_devinit_new,
// .fb = nv35_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -433,7 +433,7 @@ nv36_chipset = {
.
name
=
"NV36"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv04_clk_new,
.
clk
=
nv04_clk_new
,
// .devinit = nv20_devinit_new,
// .fb = nv36_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -455,7 +455,7 @@ nv40_chipset = {
.
name
=
"NV40"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv40_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -480,7 +480,7 @@ nv41_chipset = {
.
name
=
"NV41"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -505,7 +505,7 @@ nv42_chipset = {
.
name
=
"NV42"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -530,7 +530,7 @@ nv43_chipset = {
.
name
=
"NV43"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv41_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -555,7 +555,7 @@ nv44_chipset = {
.
name
=
"NV44"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv44_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -580,7 +580,7 @@ nv45_chipset = {
.
name
=
"NV45"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv40_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -605,7 +605,7 @@ nv46_chipset = {
.
name
=
"G72"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -630,7 +630,7 @@ nv47_chipset = {
.
name
=
"G70"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv47_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -655,7 +655,7 @@ nv49_chipset = {
.
name
=
"G71"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv49_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -680,7 +680,7 @@ nv4a_chipset = {
.
name
=
"NV44A"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv44_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -705,7 +705,7 @@ nv4b_chipset = {
.
name
=
"G73"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv49_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -730,7 +730,7 @@ nv4c_chipset = {
.
name
=
"C61"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -755,7 +755,7 @@ nv4e_chipset = {
.
name
=
"C51"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv4e_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -781,7 +781,7 @@ nv50_chipset = {
.
bar
=
nv50_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv50_bus_new
,
//
.clk = nv50_clk_new,
.
clk
=
nv50_clk_new
,
// .devinit = nv50_devinit_new,
// .fb = nv50_fb_new,
// .fuse = nv50_fuse_new,
...
...
@@ -808,7 +808,7 @@ nv63_chipset = {
.
name
=
"C73"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -833,7 +833,7 @@ nv67_chipset = {
.
name
=
"C67"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -858,7 +858,7 @@ nv68_chipset = {
.
name
=
"C68"
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv31_bus_new
,
//
.clk = nv40_clk_new,
.
clk
=
nv40_clk_new
,
// .devinit = nv1a_devinit_new,
// .fb = nv46_fb_new,
// .gpio = nv10_gpio_new,
...
...
@@ -884,7 +884,7 @@ nv84_chipset = {
.
bar
=
g84_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv50_bus_new
,
//
.clk = g84_clk_new,
.
clk
=
g84_clk_new
,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
...
...
@@ -915,7 +915,7 @@ nv86_chipset = {
.
bar
=
g84_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv50_bus_new
,
//
.clk = g84_clk_new,
.
clk
=
g84_clk_new
,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
...
...
@@ -946,7 +946,7 @@ nv92_chipset = {
.
bar
=
g84_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
nv50_bus_new
,
//
.clk = g84_clk_new,
.
clk
=
g84_clk_new
,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
...
...
@@ -977,7 +977,7 @@ nv94_chipset = {
.
bar
=
g84_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
g94_bus_new
,
//
.clk = g84_clk_new,
.
clk
=
g84_clk_new
,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
...
...
@@ -1009,7 +1009,7 @@ nv96_chipset = {
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .fuse = nv50_fuse_new,
//
.clk = g84_clk_new,
.
clk
=
g84_clk_new
,
// .therm = g84_therm_new,
// .mxm = nv50_mxm_new,
// .devinit = g84_devinit_new,
...
...
@@ -1040,7 +1040,7 @@ nv98_chipset = {
// .gpio = g94_gpio_new,
// .i2c = g94_i2c_new,
// .fuse = nv50_fuse_new,
//
.clk = g84_clk_new,
.
clk
=
g84_clk_new
,
// .therm = g84_therm_new,
// .mxm = nv50_mxm_new,
// .devinit = g98_devinit_new,
...
...
@@ -1070,7 +1070,7 @@ nva0_chipset = {
.
bar
=
g84_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
g94_bus_new
,
//
.clk = g84_clk_new,
.
clk
=
g84_clk_new
,
// .devinit = g84_devinit_new,
// .fb = g84_fb_new,
// .fuse = nv50_fuse_new,
...
...
@@ -1101,7 +1101,7 @@ nva3_chipset = {
.
bar
=
g84_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
g94_bus_new
,
//
.clk = gt215_clk_new,
.
clk
=
gt215_clk_new
,
// .devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
// .fuse = nv50_fuse_new,
...
...
@@ -1134,7 +1134,7 @@ nva5_chipset = {
.
bar
=
g84_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
g94_bus_new
,
//
.clk = gt215_clk_new,
.
clk
=
gt215_clk_new
,
// .devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
// .fuse = nv50_fuse_new,
...
...
@@ -1166,7 +1166,7 @@ nva8_chipset = {
.
bar
=
g84_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
g94_bus_new
,
//
.clk = gt215_clk_new,
.
clk
=
gt215_clk_new
,
// .devinit = gt215_devinit_new,
// .fb = gt215_fb_new,
// .fuse = nv50_fuse_new,
...
...
@@ -1198,7 +1198,7 @@ nvaa_chipset = {
.
bar
=
g84_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
g94_bus_new
,
//
.clk = mcp77_clk_new,
.
clk
=
mcp77_clk_new
,
// .devinit = g98_devinit_new,
// .fb = mcp77_fb_new,
// .fuse = nv50_fuse_new,
...
...
@@ -1229,7 +1229,7 @@ nvac_chipset = {
.
bar
=
g84_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
g94_bus_new
,
//
.clk = mcp77_clk_new,
.
clk
=
mcp77_clk_new
,
// .devinit = g98_devinit_new,
// .fb = mcp77_fb_new,
// .fuse = nv50_fuse_new,
...
...
@@ -1260,7 +1260,7 @@ nvaf_chipset = {
.
bar
=
g84_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
g94_bus_new
,
//
.clk = gt215_clk_new,
.
clk
=
gt215_clk_new
,
// .devinit = mcp89_devinit_new,
// .fb = mcp89_fb_new,
// .fuse = nv50_fuse_new,
...
...
@@ -1292,7 +1292,7 @@ nvc0_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gf100_clk_new,
.
clk
=
gf100_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1327,7 +1327,7 @@ nvc1_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gf100_clk_new,
.
clk
=
gf100_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1361,7 +1361,7 @@ nvc3_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gf100_clk_new,
.
clk
=
gf100_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1395,7 +1395,7 @@ nvc4_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gf100_clk_new,
.
clk
=
gf100_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1430,7 +1430,7 @@ nvc8_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gf100_clk_new,
.
clk
=
gf100_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1465,7 +1465,7 @@ nvce_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gf100_clk_new,
.
clk
=
gf100_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1500,7 +1500,7 @@ nvcf_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gf100_clk_new,
.
clk
=
gf100_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1534,7 +1534,7 @@ nvd7_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gf100_clk_new,
.
clk
=
gf100_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1566,7 +1566,7 @@ nvd9_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gf100_clk_new,
.
clk
=
gf100_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gf100_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1600,7 +1600,7 @@ nve4_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gk104_clk_new,
.
clk
=
gk104_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1636,7 +1636,7 @@ nve6_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gk104_clk_new,
.
clk
=
gk104_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1672,7 +1672,7 @@ nve7_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gk104_clk_new,
.
clk
=
gk104_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1707,7 +1707,7 @@ nvea_chipset = {
.
name
=
"GK20A"
,
.
bar
=
gk20a_bar_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gk20a_clk_new,
.
clk
=
gk20a_clk_new
,
// .fb = gk20a_fb_new,
// .fuse = gf100_fuse_new,
// .ibus = gk20a_ibus_new,
...
...
@@ -1732,7 +1732,7 @@ nvf0_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gk104_clk_new,
.
clk
=
gk104_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1768,7 +1768,7 @@ nvf1_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gk104_clk_new,
.
clk
=
gk104_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1804,7 +1804,7 @@ nv106_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gk104_clk_new,
.
clk
=
gk104_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1839,7 +1839,7 @@ nv108_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gk104_clk_new,
.
clk
=
gk104_clk_new
,
// .devinit = gf100_devinit_new,
// .fb = gk104_fb_new,
// .fuse = gf100_fuse_new,
...
...
@@ -1874,7 +1874,7 @@ nv117_chipset = {
.
bar
=
gf100_bar_new
,
.
bios
=
nvkm_bios_new
,
.
bus
=
gf100_bus_new
,
//
.clk = gk104_clk_new,
.
clk
=
gk104_clk_new
,
// .devinit = gm107_devinit_new,
// .fb = gm107_fb_new,
// .fuse = gm107_fuse_new,
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c
浏览文件 @
6625f55c
...
...
@@ -70,7 +70,7 @@ nvkm_control_mthd_pstate_attr(struct nvkm_control *ctrl, void *data, u32 size)
struct
nvif_control_pstate_attr_v0
v0
;
}
*
args
=
data
;
struct
nvkm_clk
*
clk
=
ctrl
->
device
->
clk
;
struct
nvkm_domain
*
domain
;
const
struct
nvkm_domain
*
domain
;
struct
nvkm_pstate
*
pstate
;
struct
nvkm_cstate
*
cstate
;
int
i
=
0
,
j
=
-
1
;
...
...
@@ -116,7 +116,7 @@ nvkm_control_mthd_pstate_attr(struct nvkm_control *ctrl, void *data, u32 size)
args
->
v0
.
state
=
pstate
->
pstate
;
}
else
{
lo
=
max
(
clk
->
read
(
clk
,
domain
->
name
),
0
);
lo
=
max
(
nvkm_clk_
read
(
clk
,
domain
->
name
),
0
);
hi
=
lo
;
}
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/gf100.c
浏览文件 @
6625f55c
...
...
@@ -31,7 +31,6 @@ gf100_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gf100_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gt215_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -60,7 +59,6 @@ gf100_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gf100_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gt215_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -89,7 +87,6 @@ gf100_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gf100_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gt215_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -117,7 +114,6 @@ gf100_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gf100_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gt215_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -146,7 +142,6 @@ gf100_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gf100_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gt215_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -174,7 +169,6 @@ gf100_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gf100_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gt215_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -202,7 +196,6 @@ gf100_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gf100_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gt215_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -231,7 +224,6 @@ gf100_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
gf110_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
gf110_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gf100_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gf110_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -259,7 +251,6 @@ gf100_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
gf110_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
gf117_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gf100_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gf110_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/gk104.c
浏览文件 @
6625f55c
...
...
@@ -31,7 +31,6 @@ gk104_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
gk104_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
gk104_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gk104_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gf110_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -61,7 +60,6 @@ gk104_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
gk104_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
gk104_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gk104_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gf110_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -91,7 +89,6 @@ gk104_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
gk104_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
gk104_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gk104_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gf110_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -118,7 +115,6 @@ gk104_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_ENGINE_PM
]
=
gk104_pm_oclass
;
break
;
case
0xea
:
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gk20a_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
gk20a_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
gk20a_timer_oclass
;
...
...
@@ -140,7 +136,6 @@ gk104_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
gk104_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
gk104_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gk104_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gf110_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -170,7 +165,6 @@ gk104_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
gk104_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
gf110_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gk104_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gf110_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -200,7 +194,6 @@ gk104_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
gk104_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
gk104_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gk104_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gf110_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
@@ -229,7 +222,6 @@ gk104_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
gk104_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
gk104_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gf100_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gk104_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gf110_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gf100_devinit_oclass
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
浏览文件 @
6625f55c
...
...
@@ -31,7 +31,6 @@ gm100_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
gk104_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
gf110_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gm107_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gk104_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gm107_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gm107_devinit_oclass
;
...
...
@@ -69,7 +68,6 @@ gm100_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gm107_fuse_oclass
;
#if 0
/* looks to be some non-trivial changes */
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
/* priv ring says no to 0x10eb14 writes */
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
#endif
...
...
@@ -106,7 +104,6 @@ gm100_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
gm107_fuse_oclass
;
#if 0
/* looks to be some non-trivial changes */
device->oclass[NVDEV_SUBDEV_CLK ] = &gk104_clk_oclass;
/* priv ring says no to 0x10eb14 writes */
device->oclass[NVDEV_SUBDEV_THERM ] = &gm107_therm_oclass;
#endif
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/nv04.c
浏览文件 @
6625f55c
...
...
@@ -29,7 +29,6 @@ nv04_identify(struct nvkm_device *device)
switch
(
device
->
chipset
)
{
case
0x04
:
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv04_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -44,7 +43,6 @@ nv04_identify(struct nvkm_device *device)
break
;
case
0x05
:
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv05_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/nv10.c
浏览文件 @
6625f55c
...
...
@@ -30,7 +30,6 @@ nv10_identify(struct nvkm_device *device)
case
0x10
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv10_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -44,7 +43,6 @@ nv10_identify(struct nvkm_device *device)
case
0x15
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv10_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -60,7 +58,6 @@ nv10_identify(struct nvkm_device *device)
case
0x16
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv10_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -76,7 +73,6 @@ nv10_identify(struct nvkm_device *device)
case
0x1a
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -92,7 +88,6 @@ nv10_identify(struct nvkm_device *device)
case
0x11
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv10_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -108,7 +103,6 @@ nv10_identify(struct nvkm_device *device)
case
0x17
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv10_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -124,7 +118,6 @@ nv10_identify(struct nvkm_device *device)
case
0x1f
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -140,7 +133,6 @@ nv10_identify(struct nvkm_device *device)
case
0x18
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv10_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/nv20.c
浏览文件 @
6625f55c
...
...
@@ -30,7 +30,6 @@ nv20_identify(struct nvkm_device *device)
case
0x20
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv20_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -46,7 +45,6 @@ nv20_identify(struct nvkm_device *device)
case
0x25
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv20_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -62,7 +60,6 @@ nv20_identify(struct nvkm_device *device)
case
0x28
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv20_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -78,7 +75,6 @@ nv20_identify(struct nvkm_device *device)
case
0x2a
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv20_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/nv30.c
浏览文件 @
6625f55c
...
...
@@ -30,7 +30,6 @@ nv30_identify(struct nvkm_device *device)
case
0x30
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv20_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -46,7 +45,6 @@ nv30_identify(struct nvkm_device *device)
case
0x35
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv20_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -62,7 +60,6 @@ nv30_identify(struct nvkm_device *device)
case
0x31
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv20_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -79,7 +76,6 @@ nv30_identify(struct nvkm_device *device)
case
0x36
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv20_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
@@ -96,7 +92,6 @@ nv30_identify(struct nvkm_device *device)
case
0x34
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv04_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv10_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv04_mc_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_TIMER
]
=
&
nv04_timer_oclass
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/nv40.c
浏览文件 @
6625f55c
...
...
@@ -30,7 +30,6 @@ nv40_identify(struct nvkm_device *device)
case
0x40
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv40_mc_oclass
;
...
...
@@ -50,7 +49,6 @@ nv40_identify(struct nvkm_device *device)
case
0x41
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv40_mc_oclass
;
...
...
@@ -70,7 +68,6 @@ nv40_identify(struct nvkm_device *device)
case
0x42
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv40_mc_oclass
;
...
...
@@ -90,7 +87,6 @@ nv40_identify(struct nvkm_device *device)
case
0x43
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv40_mc_oclass
;
...
...
@@ -110,7 +106,6 @@ nv40_identify(struct nvkm_device *device)
case
0x45
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv40_mc_oclass
;
...
...
@@ -130,7 +125,6 @@ nv40_identify(struct nvkm_device *device)
case
0x47
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv40_mc_oclass
;
...
...
@@ -150,7 +144,6 @@ nv40_identify(struct nvkm_device *device)
case
0x49
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv40_mc_oclass
;
...
...
@@ -170,7 +163,6 @@ nv40_identify(struct nvkm_device *device)
case
0x4b
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv40_mc_oclass
;
...
...
@@ -190,7 +182,6 @@ nv40_identify(struct nvkm_device *device)
case
0x44
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv44_mc_oclass
;
...
...
@@ -210,7 +201,6 @@ nv40_identify(struct nvkm_device *device)
case
0x46
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv4c_mc_oclass
;
...
...
@@ -230,7 +220,6 @@ nv40_identify(struct nvkm_device *device)
case
0x4a
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv44_mc_oclass
;
...
...
@@ -250,7 +239,6 @@ nv40_identify(struct nvkm_device *device)
case
0x4c
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv4c_mc_oclass
;
...
...
@@ -270,7 +258,6 @@ nv40_identify(struct nvkm_device *device)
case
0x4e
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv4e_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv4c_mc_oclass
;
...
...
@@ -290,7 +277,6 @@ nv40_identify(struct nvkm_device *device)
case
0x63
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv4c_mc_oclass
;
...
...
@@ -310,7 +296,6 @@ nv40_identify(struct nvkm_device *device)
case
0x67
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv4c_mc_oclass
;
...
...
@@ -330,7 +315,6 @@ nv40_identify(struct nvkm_device *device)
case
0x68
:
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv10_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv04_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
nv40_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv40_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv1a_devinit_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MC
]
=
nv4c_mc_oclass
;
...
...
drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
浏览文件 @
6625f55c
...
...
@@ -31,7 +31,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv50_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv50_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
nv50_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
nv50_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
nv50_devinit_oclass
;
...
...
@@ -53,7 +52,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv50_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv50_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
g84_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
g84_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
g84_devinit_oclass
;
...
...
@@ -78,7 +76,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv50_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv50_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
g84_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
g84_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
g84_devinit_oclass
;
...
...
@@ -103,7 +100,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
nv50_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv50_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
g84_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
g84_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
g84_devinit_oclass
;
...
...
@@ -128,7 +124,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
g84_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
g84_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
g84_devinit_oclass
;
...
...
@@ -153,7 +148,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
g84_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
g84_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
g84_devinit_oclass
;
...
...
@@ -178,7 +172,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
g84_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
g84_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
g98_devinit_oclass
;
...
...
@@ -203,7 +196,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
nv50_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
g84_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
g84_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
g84_devinit_oclass
;
...
...
@@ -228,7 +220,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
mcp77_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
g84_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
g98_devinit_oclass
;
...
...
@@ -253,7 +244,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
mcp77_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
g84_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
g98_devinit_oclass
;
...
...
@@ -278,7 +268,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gt215_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gt215_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gt215_devinit_oclass
;
...
...
@@ -305,7 +294,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gt215_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gt215_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gt215_devinit_oclass
;
...
...
@@ -331,7 +319,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gt215_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gt215_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
gt215_devinit_oclass
;
...
...
@@ -357,7 +344,6 @@ nv50_identify(struct nvkm_device *device)
device
->
oclass
[
NVDEV_SUBDEV_GPIO
]
=
g94_gpio_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_I2C
]
=
g94_i2c_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_FUSE
]
=
&
nv50_fuse_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_CLK
]
=
&
gt215_clk_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_THERM
]
=
&
gt215_therm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_MXM
]
=
&
nv50_mxm_oclass
;
device
->
oclass
[
NVDEV_SUBDEV_DEVINIT
]
=
mcp89_devinit_oclass
;
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/clk/Kbuild
浏览文件 @
6625f55c
...
...
@@ -8,5 +8,6 @@ nvkm-y += nvkm/subdev/clk/mcp77.o
nvkm-y += nvkm/subdev/clk/gf100.o
nvkm-y += nvkm/subdev/clk/gk104.o
nvkm-y += nvkm/subdev/clk/gk20a.o
nvkm-y += nvkm/subdev/clk/pllnv04.o
nvkm-y += nvkm/subdev/clk/pllgt215.o
drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c
浏览文件 @
6625f55c
...
...
@@ -21,7 +21,8 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/clk.h>
#include "priv.h"
#include <subdev/bios.h>
#include <subdev/bios/boost.h>
#include <subdev/bios/cstep.h>
...
...
@@ -105,10 +106,10 @@ nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
}
}
ret
=
clk
->
calc
(
clk
,
cstate
);
ret
=
clk
->
func
->
calc
(
clk
,
cstate
);
if
(
ret
==
0
)
{
ret
=
clk
->
prog
(
clk
);
clk
->
tidy
(
clk
);
ret
=
clk
->
func
->
prog
(
clk
);
clk
->
func
->
tidy
(
clk
);
}
if
(
volt
)
{
...
...
@@ -137,7 +138,7 @@ static int
nvkm_cstate_new
(
struct
nvkm_clk
*
clk
,
int
idx
,
struct
nvkm_pstate
*
pstate
)
{
struct
nvkm_bios
*
bios
=
clk
->
subdev
.
device
->
bios
;
struct
nvkm_domain
*
domain
=
clk
->
domains
;
const
struct
nvkm_domain
*
domain
=
clk
->
domains
;
struct
nvkm_cstate
*
cstate
=
NULL
;
struct
nvbios_cstepX
cstepX
;
u8
ver
,
hdr
;
...
...
@@ -249,7 +250,7 @@ nvkm_pstate_calc(struct nvkm_clk *clk, bool wait)
static
void
nvkm_pstate_info
(
struct
nvkm_clk
*
clk
,
struct
nvkm_pstate
*
pstate
)
{
struct
nvkm_domain
*
clock
=
clk
->
domains
-
1
;
const
struct
nvkm_domain
*
clock
=
clk
->
domains
-
1
;
struct
nvkm_cstate
*
cstate
;
struct
nvkm_subdev
*
subdev
=
&
clk
->
subdev
;
char
info
[
3
][
32
]
=
{
""
,
""
,
""
};
...
...
@@ -306,7 +307,7 @@ static int
nvkm_pstate_new
(
struct
nvkm_clk
*
clk
,
int
idx
)
{
struct
nvkm_bios
*
bios
=
clk
->
subdev
.
device
->
bios
;
struct
nvkm_domain
*
domain
=
clk
->
domains
-
1
;
const
struct
nvkm_domain
*
domain
=
clk
->
domains
-
1
;
struct
nvkm_pstate
*
pstate
;
struct
nvkm_cstate
*
cstate
;
struct
nvbios_cstepE
cstepE
;
...
...
@@ -475,31 +476,35 @@ nvkm_clk_pwrsrc(struct nvkm_notify *notify)
*****************************************************************************/
int
_nvkm_clk_fini
(
struct
nvkm_object
*
object
,
bool
suspend
)
nvkm_clk_read
(
struct
nvkm_clk
*
clk
,
enum
nv_clk_src
src
)
{
struct
nvkm_clk
*
clk
=
(
void
*
)
object
;
return
clk
->
func
->
read
(
clk
,
src
);
}
static
int
nvkm_clk_fini
(
struct
nvkm_subdev
*
subdev
,
bool
suspend
)
{
struct
nvkm_clk
*
clk
=
nvkm_clk
(
subdev
);
nvkm_notify_put
(
&
clk
->
pwrsrc_ntfy
);
return
nvkm_subdev_fini_old
(
&
clk
->
subdev
,
suspend
);
flush_work
(
&
clk
->
work
);
if
(
clk
->
func
->
fini
)
clk
->
func
->
fini
(
clk
);
return
0
;
}
int
_nvkm_clk_init
(
struct
nvkm_object
*
object
)
static
int
nvkm_clk_init
(
struct
nvkm_subdev
*
subdev
)
{
struct
nvkm_clk
*
clk
=
(
void
*
)
object
;
struct
nvkm_subdev
*
subdev
=
&
clk
->
subdev
;
struct
nvkm_domain
*
clock
=
clk
->
domains
;
struct
nvkm_clk
*
clk
=
nvkm_clk
(
subdev
);
const
struct
nvkm_domain
*
clock
=
clk
->
domains
;
int
ret
;
ret
=
nvkm_subdev_init_old
(
&
clk
->
subdev
);
if
(
ret
)
return
ret
;
memset
(
&
clk
->
bstate
,
0x00
,
sizeof
(
clk
->
bstate
));
INIT_LIST_HEAD
(
&
clk
->
bstate
.
list
);
clk
->
bstate
.
pstate
=
0xff
;
while
(
clock
->
name
!=
nv_clk_src_max
)
{
ret
=
clk
->
read
(
clk
,
clock
->
name
);
ret
=
nvkm_clk_
read
(
clk
,
clock
->
name
);
if
(
ret
<
0
)
{
nvkm_error
(
subdev
,
"%02x freq unknown
\n
"
,
clock
->
name
);
return
ret
;
...
...
@@ -510,6 +515,9 @@ _nvkm_clk_init(struct nvkm_object *object)
nvkm_pstate_info
(
clk
,
&
clk
->
bstate
);
if
(
clk
->
func
->
init
)
return
clk
->
func
->
init
(
clk
);
clk
->
astate
=
clk
->
state_nr
-
1
;
clk
->
tstate
=
0
;
clk
->
dstate
=
0
;
...
...
@@ -518,61 +526,63 @@ _nvkm_clk_init(struct nvkm_object *object)
return
0
;
}
void
_nvkm_clk_dtor
(
struct
nvkm_object
*
object
)
static
void
*
nvkm_clk_dtor
(
struct
nvkm_subdev
*
subdev
)
{
struct
nvkm_clk
*
clk
=
(
void
*
)
object
;
struct
nvkm_clk
*
clk
=
nvkm_clk
(
subdev
)
;
struct
nvkm_pstate
*
pstate
,
*
temp
;
nvkm_notify_fini
(
&
clk
->
pwrsrc_ntfy
);
/* Early return if the pstates have been provided statically */
if
(
clk
->
func
->
pstates
)
return
clk
;
list_for_each_entry_safe
(
pstate
,
temp
,
&
clk
->
states
,
head
)
{
nvkm_pstate_del
(
pstate
);
}
nvkm_subdev_destroy
(
&
clk
->
subdev
)
;
return
clk
;
}
static
const
struct
nvkm_subdev_func
nvkm_clk
=
{
.
dtor
=
nvkm_clk_dtor
,
.
init
=
nvkm_clk_init
,
.
fini
=
nvkm_clk_fini
,
};
int
nvkm_clk_create_
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
struct
nvkm_domain
*
clocks
,
struct
nvkm_pstate
*
pstates
,
int
nb_pstates
,
bool
allow_reclock
,
int
length
,
void
**
object
)
nvkm_clk_ctor
(
const
struct
nvkm_clk_func
*
func
,
struct
nvkm_device
*
device
,
int
index
,
bool
allow_reclock
,
struct
nvkm_clk
*
clk
)
{
struct
nvkm_device
*
device
=
nv_device
(
parent
);
struct
nvkm_clk
*
clk
;
int
ret
,
idx
,
arglen
;
const
char
*
mode
;
ret
=
nvkm_subdev_create_
(
parent
,
engine
,
oclass
,
0
,
"CLK"
,
"clock"
,
length
,
object
);
clk
=
*
object
;
if
(
ret
)
return
ret
;
nvkm_subdev_ctor
(
&
nvkm_clk
,
device
,
index
,
0
,
&
clk
->
subdev
);
clk
->
func
=
func
;
INIT_LIST_HEAD
(
&
clk
->
states
);
clk
->
domains
=
clock
s
;
clk
->
domains
=
func
->
domain
s
;
clk
->
ustate_ac
=
-
1
;
clk
->
ustate_dc
=
-
1
;
clk
->
allow_reclock
=
allow_reclock
;
INIT_WORK
(
&
clk
->
work
,
nvkm_pstate_work
);
init_waitqueue_head
(
&
clk
->
wait
);
atomic_set
(
&
clk
->
waiting
,
0
);
/* If no pstates are provided, try and fetch them from the BIOS */
if
(
!
pstates
)
{
if
(
!
func
->
pstates
)
{
idx
=
0
;
do
{
ret
=
nvkm_pstate_new
(
clk
,
idx
++
);
}
while
(
ret
==
0
);
}
else
{
for
(
idx
=
0
;
idx
<
nb
_pstates
;
idx
++
)
list_add_tail
(
&
pstates
[
idx
].
head
,
&
clk
->
states
);
clk
->
state_nr
=
nb
_pstates
;
for
(
idx
=
0
;
idx
<
func
->
nr
_pstates
;
idx
++
)
list_add_tail
(
&
func
->
pstates
[
idx
].
head
,
&
clk
->
states
);
clk
->
state_nr
=
func
->
nr
_pstates
;
}
clk
->
allow_reclock
=
allow_reclock
;
ret
=
nvkm_notify_init
(
NULL
,
&
device
->
event
,
nvkm_clk_pwrsrc
,
true
,
NULL
,
0
,
0
,
&
clk
->
pwrsrc_ntfy
);
if
(
ret
)
...
...
@@ -594,3 +604,12 @@ nvkm_clk_create_(struct nvkm_object *parent, struct nvkm_object *engine,
return
0
;
}
int
nvkm_clk_new_
(
const
struct
nvkm_clk_func
*
func
,
struct
nvkm_device
*
device
,
int
index
,
bool
allow_reclock
,
struct
nvkm_clk
**
pclk
)
{
if
(
!
(
*
pclk
=
kzalloc
(
sizeof
(
**
pclk
),
GFP_KERNEL
)))
return
-
ENOMEM
;
return
nvkm_clk_ctor
(
func
,
device
,
index
,
allow_reclock
,
*
pclk
);
}
drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.c
浏览文件 @
6625f55c
...
...
@@ -23,25 +23,26 @@
*/
#include "nv50.h"
static
struct
nvkm_domain
g84_domains
[]
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_href
,
0xff
},
{
nv_clk_src_core
,
0xff
,
0
,
"core"
,
1000
},
{
nv_clk_src_shader
,
0xff
,
0
,
"shader"
,
1000
},
{
nv_clk_src_mem
,
0xff
,
0
,
"memory"
,
1000
},
{
nv_clk_src_vdec
,
0xff
},
{
nv_clk_src_max
}
static
const
struct
nvkm_clk_func
g84_clk
=
{
.
read
=
nv50_clk_read
,
.
calc
=
nv50_clk_calc
,
.
prog
=
nv50_clk_prog
,
.
tidy
=
nv50_clk_tidy
,
.
domains
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_href
,
0xff
},
{
nv_clk_src_core
,
0xff
,
0
,
"core"
,
1000
},
{
nv_clk_src_shader
,
0xff
,
0
,
"shader"
,
1000
},
{
nv_clk_src_mem
,
0xff
,
0
,
"memory"
,
1000
},
{
nv_clk_src_vdec
,
0xff
},
{
nv_clk_src_max
}
}
};
struct
nvkm_oclass
*
g84_clk_oclass
=
&
(
struct
nv50_clk_oclass
)
{
.
base
.
handle
=
NV_SUBDEV
(
CLK
,
0x84
),
.
base
.
ofuncs
=
&
(
struct
nvkm_ofuncs
)
{
.
ctor
=
nv50_clk_ctor
,
.
dtor
=
_nvkm_clk_dtor
,
.
init
=
_nvkm_clk_init
,
.
fini
=
_nvkm_clk_fini
,
},
.
domains
=
g84_domains
,
}.
base
;
int
g84_clk_new
(
struct
nvkm_device
*
device
,
int
index
,
struct
nvkm_clk
**
pclk
)
{
return
nv50_clk_new_
(
&
g84_clk
,
device
,
index
,
(
device
->
chipset
==
0xa0
),
pclk
);
}
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.c
浏览文件 @
6625f55c
...
...
@@ -21,7 +21,8 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/clk.h>
#define gf100_clk(p) container_of((p), struct gf100_clk, base)
#include "priv.h"
#include "pll.h"
#include <subdev/bios.h>
...
...
@@ -50,8 +51,8 @@ read_vco(struct gf100_clk *clk, u32 dsrc)
struct
nvkm_device
*
device
=
clk
->
base
.
subdev
.
device
;
u32
ssrc
=
nvkm_rd32
(
device
,
dsrc
);
if
(
!
(
ssrc
&
0x00000100
))
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_sppll0
);
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_sppll1
);
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_sppll0
);
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_sppll1
);
}
static
u32
...
...
@@ -75,10 +76,10 @@ read_pll(struct gf100_clk *clk, u32 pll)
P
=
1
;
break
;
case
0x132000
:
sclk
=
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_mpllsrc
);
sclk
=
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_mpllsrc
);
break
;
case
0x132020
:
sclk
=
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_mpllsrcref
);
sclk
=
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_mpllsrcref
);
break
;
case
0x137000
:
case
0x137020
:
...
...
@@ -146,9 +147,9 @@ read_clk(struct gf100_clk *clk, int idx)
}
static
int
gf100_clk_read
(
struct
nvkm_clk
*
obj
,
enum
nv_clk_src
src
)
gf100_clk_read
(
struct
nvkm_clk
*
base
,
enum
nv_clk_src
src
)
{
struct
gf100_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gf100_clk
*
clk
=
gf100_clk
(
base
);
struct
nvkm_subdev
*
subdev
=
&
clk
->
base
.
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
...
...
@@ -172,8 +173,8 @@ gf100_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
return
read_div
(
clk
,
0
,
0x137300
,
0x137310
);
case
nv_clk_src_mem
:
if
(
nvkm_rd32
(
device
,
0x1373f0
)
&
0x00000002
)
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_mpll
);
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_mdiv
);
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_mpll
);
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_mdiv
);
case
nv_clk_src_gpc
:
return
read_clk
(
clk
,
0x00
);
...
...
@@ -313,9 +314,9 @@ calc_clk(struct gf100_clk *clk, struct nvkm_cstate *cstate, int idx, int dom)
}
static
int
gf100_clk_calc
(
struct
nvkm_clk
*
obj
,
struct
nvkm_cstate
*
cstate
)
gf100_clk_calc
(
struct
nvkm_clk
*
base
,
struct
nvkm_cstate
*
cstate
)
{
struct
gf100_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gf100_clk
*
clk
=
gf100_clk
(
base
);
int
ret
;
if
((
ret
=
calc_clk
(
clk
,
cstate
,
0x00
,
nv_clk_src_gpc
))
||
...
...
@@ -398,9 +399,9 @@ gf100_clk_prog_4(struct gf100_clk *clk, int idx)
}
static
int
gf100_clk_prog
(
struct
nvkm_clk
*
obj
)
gf100_clk_prog
(
struct
nvkm_clk
*
base
)
{
struct
gf100_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gf100_clk
*
clk
=
gf100_clk
(
base
);
struct
{
void
(
*
exec
)(
struct
gf100_clk
*
,
int
);
}
stage
[]
=
{
...
...
@@ -424,56 +425,42 @@ gf100_clk_prog(struct nvkm_clk *obj)
}
static
void
gf100_clk_tidy
(
struct
nvkm_clk
*
obj
)
gf100_clk_tidy
(
struct
nvkm_clk
*
base
)
{
struct
gf100_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gf100_clk
*
clk
=
gf100_clk
(
base
);
memset
(
clk
->
eng
,
0x00
,
sizeof
(
clk
->
eng
));
}
static
struct
nvkm_domain
gf100_domain
[]
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_href
,
0xff
},
{
nv_clk_src_hubk06
,
0x00
},
{
nv_clk_src_hubk01
,
0x01
},
{
nv_clk_src_copy
,
0x02
},
{
nv_clk_src_gpc
,
0x03
,
0
,
"core"
,
2000
},
{
nv_clk_src_rop
,
0x04
},
{
nv_clk_src_mem
,
0x05
,
0
,
"memory"
,
1000
},
{
nv_clk_src_vdec
,
0x06
},
{
nv_clk_src_daemon
,
0x0a
},
{
nv_clk_src_hubk07
,
0x0b
},
{
nv_clk_src_max
}
static
const
struct
nvkm_clk_func
gf100_clk
=
{
.
read
=
gf100_clk_read
,
.
calc
=
gf100_clk_calc
,
.
prog
=
gf100_clk_prog
,
.
tidy
=
gf100_clk_tidy
,
.
domains
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_href
,
0xff
},
{
nv_clk_src_hubk06
,
0x00
},
{
nv_clk_src_hubk01
,
0x01
},
{
nv_clk_src_copy
,
0x02
},
{
nv_clk_src_gpc
,
0x03
,
0
,
"core"
,
2000
},
{
nv_clk_src_rop
,
0x04
},
{
nv_clk_src_mem
,
0x05
,
0
,
"memory"
,
1000
},
{
nv_clk_src_vdec
,
0x06
},
{
nv_clk_src_daemon
,
0x0a
},
{
nv_clk_src_hubk07
,
0x0b
},
{
nv_clk_src_max
}
}
};
static
int
gf100_clk_ctor
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
pobject
)
int
gf100_clk_new
(
struct
nvkm_device
*
device
,
int
index
,
struct
nvkm_clk
**
pclk
)
{
struct
gf100_clk
*
clk
;
int
ret
;
ret
=
nvkm_clk_create
(
parent
,
engine
,
oclass
,
gf100_domain
,
NULL
,
0
,
false
,
&
clk
);
*
pobject
=
nv_object
(
clk
);
if
(
ret
)
return
ret
;
if
(
!
(
clk
=
kzalloc
(
sizeof
(
*
clk
),
GFP_KERNEL
)))
return
-
ENOMEM
;
*
pclk
=
&
clk
->
base
;
clk
->
base
.
read
=
gf100_clk_read
;
clk
->
base
.
calc
=
gf100_clk_calc
;
clk
->
base
.
prog
=
gf100_clk_prog
;
clk
->
base
.
tidy
=
gf100_clk_tidy
;
return
0
;
return
nvkm_clk_ctor
(
&
gf100_clk
,
device
,
index
,
false
,
&
clk
->
base
);
}
struct
nvkm_oclass
gf100_clk_oclass
=
{
.
handle
=
NV_SUBDEV
(
CLK
,
0xc0
),
.
ofuncs
=
&
(
struct
nvkm_ofuncs
)
{
.
ctor
=
gf100_clk_ctor
,
.
dtor
=
_nvkm_clk_dtor
,
.
init
=
_nvkm_clk_init
,
.
fini
=
_nvkm_clk_fini
,
},
};
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.c
浏览文件 @
6625f55c
...
...
@@ -21,7 +21,8 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/clk.h>
#define gk104_clk(p) container_of((p), struct gk104_clk, base)
#include "priv.h"
#include "pll.h"
#include <subdev/timer.h>
...
...
@@ -185,9 +186,9 @@ read_clk(struct gk104_clk *clk, int idx)
}
static
int
gk104_clk_read
(
struct
nvkm_clk
*
obj
,
enum
nv_clk_src
src
)
gk104_clk_read
(
struct
nvkm_clk
*
base
,
enum
nv_clk_src
src
)
{
struct
gk104_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gk104_clk
*
clk
=
gk104_clk
(
base
);
struct
nvkm_subdev
*
subdev
=
&
clk
->
base
.
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
...
...
@@ -335,9 +336,9 @@ calc_clk(struct gk104_clk *clk,
}
static
int
gk104_clk_calc
(
struct
nvkm_clk
*
obj
,
struct
nvkm_cstate
*
cstate
)
gk104_clk_calc
(
struct
nvkm_clk
*
base
,
struct
nvkm_cstate
*
cstate
)
{
struct
gk104_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gk104_clk
*
clk
=
gk104_clk
(
base
);
int
ret
;
if
((
ret
=
calc_clk
(
clk
,
cstate
,
0x00
,
nv_clk_src_gpc
))
||
...
...
@@ -438,9 +439,9 @@ gk104_clk_prog_4_1(struct gk104_clk *clk, int idx)
}
static
int
gk104_clk_prog
(
struct
nvkm_clk
*
obj
)
gk104_clk_prog
(
struct
nvkm_clk
*
base
)
{
struct
gk104_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gk104_clk
*
clk
=
gk104_clk
(
base
);
struct
{
u32
mask
;
void
(
*
exec
)(
struct
gk104_clk
*
,
int
);
...
...
@@ -469,55 +470,41 @@ gk104_clk_prog(struct nvkm_clk *obj)
}
static
void
gk104_clk_tidy
(
struct
nvkm_clk
*
obj
)
gk104_clk_tidy
(
struct
nvkm_clk
*
base
)
{
struct
gk104_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gk104_clk
*
clk
=
gk104_clk
(
base
);
memset
(
clk
->
eng
,
0x00
,
sizeof
(
clk
->
eng
));
}
static
struct
nvkm_domain
gk104_domain
[]
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_href
,
0xff
},
{
nv_clk_src_gpc
,
0x00
,
NVKM_CLK_DOM_FLAG_CORE
,
"core"
,
2000
},
{
nv_clk_src_hubk07
,
0x01
,
NVKM_CLK_DOM_FLAG_CORE
},
{
nv_clk_src_rop
,
0x02
,
NVKM_CLK_DOM_FLAG_CORE
},
{
nv_clk_src_mem
,
0x03
,
0
,
"memory"
,
500
},
{
nv_clk_src_hubk06
,
0x04
,
NVKM_CLK_DOM_FLAG_CORE
},
{
nv_clk_src_hubk01
,
0x05
},
{
nv_clk_src_vdec
,
0x06
},
{
nv_clk_src_daemon
,
0x07
},
{
nv_clk_src_max
}
static
const
struct
nvkm_clk_func
gk104_clk
=
{
.
read
=
gk104_clk_read
,
.
calc
=
gk104_clk_calc
,
.
prog
=
gk104_clk_prog
,
.
tidy
=
gk104_clk_tidy
,
.
domains
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_href
,
0xff
},
{
nv_clk_src_gpc
,
0x00
,
NVKM_CLK_DOM_FLAG_CORE
,
"core"
,
2000
},
{
nv_clk_src_hubk07
,
0x01
,
NVKM_CLK_DOM_FLAG_CORE
},
{
nv_clk_src_rop
,
0x02
,
NVKM_CLK_DOM_FLAG_CORE
},
{
nv_clk_src_mem
,
0x03
,
0
,
"memory"
,
500
},
{
nv_clk_src_hubk06
,
0x04
,
NVKM_CLK_DOM_FLAG_CORE
},
{
nv_clk_src_hubk01
,
0x05
},
{
nv_clk_src_vdec
,
0x06
},
{
nv_clk_src_daemon
,
0x07
},
{
nv_clk_src_max
}
}
};
static
int
gk104_clk_ctor
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
pobject
)
int
gk104_clk_new
(
struct
nvkm_device
*
device
,
int
index
,
struct
nvkm_clk
**
pclk
)
{
struct
gk104_clk
*
clk
;
int
ret
;
ret
=
nvkm_clk_create
(
parent
,
engine
,
oclass
,
gk104_domain
,
NULL
,
0
,
true
,
&
clk
);
*
pobject
=
nv_object
(
clk
);
if
(
ret
)
return
ret
;
if
(
!
(
clk
=
kzalloc
(
sizeof
(
*
clk
),
GFP_KERNEL
)))
return
-
ENOMEM
;
*
pclk
=
&
clk
->
base
;
clk
->
base
.
read
=
gk104_clk_read
;
clk
->
base
.
calc
=
gk104_clk_calc
;
clk
->
base
.
prog
=
gk104_clk_prog
;
clk
->
base
.
tidy
=
gk104_clk_tidy
;
return
0
;
return
nvkm_clk_ctor
(
&
gk104_clk
,
device
,
index
,
true
,
&
clk
->
base
);
}
struct
nvkm_oclass
gk104_clk_oclass
=
{
.
handle
=
NV_SUBDEV
(
CLK
,
0xe0
),
.
ofuncs
=
&
(
struct
nvkm_ofuncs
)
{
.
ctor
=
gk104_clk_ctor
,
.
dtor
=
_nvkm_clk_dtor
,
.
init
=
_nvkm_clk_init
,
.
fini
=
_nvkm_clk_fini
,
},
};
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c
浏览文件 @
6625f55c
...
...
@@ -22,7 +22,9 @@
* Shamelessly ripped off from ChromeOS's gk20a/clk_pllg.c
*
*/
#include <subdev/clk.h>
#define gk20a_clk(p) container_of((p), struct gk20a_clk, base)
#include "priv.h"
#include <subdev/timer.h>
#ifdef __KERNEL__
...
...
@@ -121,7 +123,6 @@ struct gk20a_clk {
u32
m
,
n
,
pl
;
u32
parent_rate
;
};
#define to_gk20a_clk(base) container_of(base, struct gk20a_clk, base)
static
void
gk20a_pllg_read_mnp
(
struct
gk20a_clk
*
clk
)
...
...
@@ -467,13 +468,6 @@ gk20a_pllg_disable(struct gk20a_clk *clk)
#define GK20A_CLK_GPC_MDIV 1000
static
struct
nvkm_domain
gk20a_domains
[]
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_gpc
,
0xff
,
0
,
"core"
,
GK20A_CLK_GPC_MDIV
},
{
nv_clk_src_max
}
};
static
struct
nvkm_pstate
gk20a_pstates
[]
=
{
{
...
...
@@ -569,9 +563,9 @@ gk20a_pstates[] = {
};
static
int
gk20a_clk_read
(
struct
nvkm_clk
*
obj
,
enum
nv_clk_src
src
)
gk20a_clk_read
(
struct
nvkm_clk
*
base
,
enum
nv_clk_src
src
)
{
struct
gk20a_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gk20a_clk
*
clk
=
gk20a_clk
(
base
);
struct
nvkm_subdev
*
subdev
=
&
clk
->
base
.
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
...
...
@@ -588,54 +582,44 @@ gk20a_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
}
static
int
gk20a_clk_calc
(
struct
nvkm_clk
*
obj
,
struct
nvkm_cstate
*
cstate
)
gk20a_clk_calc
(
struct
nvkm_clk
*
base
,
struct
nvkm_cstate
*
cstate
)
{
struct
gk20a_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gk20a_clk
*
clk
=
gk20a_clk
(
base
);
return
gk20a_pllg_calc_mnp
(
clk
,
cstate
->
domain
[
nv_clk_src_gpc
]
*
GK20A_CLK_GPC_MDIV
);
}
static
int
gk20a_clk_prog
(
struct
nvkm_clk
*
obj
)
gk20a_clk_prog
(
struct
nvkm_clk
*
base
)
{
struct
gk20a_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gk20a_clk
*
clk
=
gk20a_clk
(
base
);
return
gk20a_pllg_program_mnp
(
clk
);
}
static
void
gk20a_clk_tidy
(
struct
nvkm_clk
*
obj
)
gk20a_clk_tidy
(
struct
nvkm_clk
*
base
)
{
}
static
int
gk20a_clk_fini
(
struct
nvkm_
object
*
object
,
bool
suspend
)
static
void
gk20a_clk_fini
(
struct
nvkm_
clk
*
base
)
{
struct
gk20a_clk
*
clk
=
(
void
*
)
object
;
int
ret
;
ret
=
nvkm_clk_fini
(
&
clk
->
base
,
false
);
struct
gk20a_clk
*
clk
=
gk20a_clk
(
base
);
gk20a_pllg_disable
(
clk
);
return
ret
;
}
static
int
gk20a_clk_init
(
struct
nvkm_
object
*
object
)
gk20a_clk_init
(
struct
nvkm_
clk
*
base
)
{
struct
gk20a_clk
*
clk
=
(
void
*
)
object
;
struct
gk20a_clk
*
clk
=
gk20a_clk
(
base
)
;
struct
nvkm_subdev
*
subdev
=
&
clk
->
base
.
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
int
ret
;
nvkm_mask
(
device
,
GPC2CLK_OUT
,
GPC2CLK_OUT_INIT_MASK
,
GPC2CLK_OUT_INIT_VAL
);
ret
=
nvkm_clk_init
(
&
clk
->
base
);
if
(
ret
)
return
ret
;
ret
=
gk20a_clk_prog
(
&
clk
->
base
);
if
(
ret
)
{
nvkm_error
(
subdev
,
"cannot initialize clock
\n
"
);
...
...
@@ -645,15 +629,32 @@ gk20a_clk_init(struct nvkm_object *object)
return
0
;
}
static
int
gk20a_clk_ctor
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
pobject
)
static
const
struct
nvkm_clk_func
gk20a_clk
=
{
.
init
=
gk20a_clk_init
,
.
fini
=
gk20a_clk_fini
,
.
read
=
gk20a_clk_read
,
.
calc
=
gk20a_clk_calc
,
.
prog
=
gk20a_clk_prog
,
.
tidy
=
gk20a_clk_tidy
,
.
pstates
=
gk20a_pstates
,
.
nr_pstates
=
ARRAY_SIZE
(
gk20a_pstates
),
.
domains
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_gpc
,
0xff
,
0
,
"core"
,
GK20A_CLK_GPC_MDIV
},
{
nv_clk_src_max
}
}
};
int
gk20a_clk_new
(
struct
nvkm_device
*
device
,
int
index
,
struct
nvkm_clk
**
pclk
)
{
struct
nvkm_device
*
device
=
(
void
*
)
parent
;
struct
gk20a_clk
*
clk
;
int
ret
;
int
i
;
int
ret
,
i
;
if
(
!
(
clk
=
kzalloc
(
sizeof
(
*
clk
),
GFP_KERNEL
)))
return
-
ENOMEM
;
*
pclk
=
&
clk
->
base
;
/* Finish initializing the pstates */
for
(
i
=
0
;
i
<
ARRAY_SIZE
(
gk20a_pstates
);
i
++
)
{
...
...
@@ -661,33 +662,11 @@ gk20a_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
gk20a_pstates
[
i
].
pstate
=
i
+
1
;
}
ret
=
nvkm_clk_create
(
parent
,
engine
,
oclass
,
gk20a_domains
,
gk20a_pstates
,
ARRAY_SIZE
(
gk20a_pstates
),
true
,
&
clk
);
*
pobject
=
nv_object
(
clk
);
if
(
ret
)
return
ret
;
clk
->
params
=
&
gk20a_pllg_params
;
clk
->
parent_rate
=
clk_get_rate
(
device
->
gpu
->
clk
);
ret
=
nvkm_clk_ctor
(
&
gk20a_clk
,
device
,
index
,
true
,
&
clk
->
base
);
nvkm_info
(
&
clk
->
base
.
subdev
,
"parent clock rate: %d Mhz
\n
"
,
clk
->
parent_rate
/
MHZ
);
clk
->
base
.
read
=
gk20a_clk_read
;
clk
->
base
.
calc
=
gk20a_clk_calc
;
clk
->
base
.
prog
=
gk20a_clk_prog
;
clk
->
base
.
tidy
=
gk20a_clk_tidy
;
return
0
;
return
ret
;
}
struct
nvkm_oclass
gk20a_clk_oclass
=
{
.
handle
=
NV_SUBDEV
(
CLK
,
0xea
),
.
ofuncs
=
&
(
struct
nvkm_ofuncs
)
{
.
ctor
=
gk20a_clk_ctor
,
.
dtor
=
_nvkm_subdev_dtor
,
.
init
=
gk20a_clk_init
,
.
fini
=
gk20a_clk_fini
,
},
};
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.c
浏览文件 @
6625f55c
...
...
@@ -22,6 +22,7 @@
* Authors: Ben Skeggs
* Roy Spliet
*/
#define gt215_clk(p) container_of((p), struct gt215_clk, base)
#include "gt215.h"
#include "pll.h"
...
...
@@ -136,9 +137,9 @@ read_pll(struct gt215_clk *clk, int idx, u32 pll)
}
static
int
gt215_clk_read
(
struct
nvkm_clk
*
obj
,
enum
nv_clk_src
src
)
gt215_clk_read
(
struct
nvkm_clk
*
base
,
enum
nv_clk_src
src
)
{
struct
gt215_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gt215_clk
*
clk
=
gt215_clk
(
base
);
struct
nvkm_subdev
*
subdev
=
&
clk
->
base
.
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
u32
hsrc
;
...
...
@@ -180,10 +181,10 @@ gt215_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
}
int
gt215_clk_info
(
struct
nvkm_clk
*
obj
,
int
idx
,
u32
khz
,
gt215_clk_info
(
struct
nvkm_clk
*
base
,
int
idx
,
u32
khz
,
struct
gt215_clk_info
*
info
)
{
struct
gt215_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gt215_clk
*
clk
=
gt215_clk
(
base
);
u32
oclk
,
sclk
,
sdiv
;
s32
diff
;
...
...
@@ -228,10 +229,10 @@ gt215_clk_info(struct nvkm_clk *obj, int idx, u32 khz,
}
int
gt215_pll_info
(
struct
nvkm_clk
*
clock
,
int
idx
,
u32
pll
,
u32
khz
,
gt215_pll_info
(
struct
nvkm_clk
*
base
,
int
idx
,
u32
pll
,
u32
khz
,
struct
gt215_clk_info
*
info
)
{
struct
gt215_clk
*
clk
=
(
void
*
)
clock
;
struct
gt215_clk
*
clk
=
gt215_clk
(
base
)
;
struct
nvkm_subdev
*
subdev
=
&
clk
->
base
.
subdev
;
struct
nvbios_pll
limits
;
int
P
,
N
,
M
,
diff
;
...
...
@@ -241,7 +242,7 @@ gt215_pll_info(struct nvkm_clk *clock, int idx, u32 pll, u32 khz,
/* If we can get a within [-2, 3) MHz of a divider, we'll disable the
* PLL and use the divider instead. */
ret
=
gt215_clk_info
(
clock
,
idx
,
khz
,
info
);
ret
=
gt215_clk_info
(
&
clk
->
base
,
idx
,
khz
,
info
);
diff
=
khz
-
ret
;
if
(
!
pll
||
(
diff
>=
-
2000
&&
diff
<
3000
))
{
goto
out
;
...
...
@@ -252,7 +253,7 @@ gt215_pll_info(struct nvkm_clk *clock, int idx, u32 pll, u32 khz,
if
(
ret
)
return
ret
;
ret
=
gt215_clk_info
(
clock
,
idx
-
0x10
,
limits
.
refclk
,
info
);
ret
=
gt215_clk_info
(
&
clk
->
base
,
idx
-
0x10
,
limits
.
refclk
,
info
);
if
(
ret
!=
limits
.
refclk
)
return
-
EINVAL
;
...
...
@@ -452,9 +453,9 @@ prog_core(struct gt215_clk *clk, int dom)
}
static
int
gt215_clk_calc
(
struct
nvkm_clk
*
obj
,
struct
nvkm_cstate
*
cstate
)
gt215_clk_calc
(
struct
nvkm_clk
*
base
,
struct
nvkm_cstate
*
cstate
)
{
struct
gt215_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gt215_clk
*
clk
=
gt215_clk
(
base
);
struct
gt215_clk_info
*
core
=
&
clk
->
eng
[
nv_clk_src_core
];
int
ret
;
...
...
@@ -479,9 +480,9 @@ gt215_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
}
static
int
gt215_clk_prog
(
struct
nvkm_clk
*
obj
)
gt215_clk_prog
(
struct
nvkm_clk
*
base
)
{
struct
gt215_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
gt215_clk
*
clk
=
gt215_clk
(
base
);
struct
gt215_clk_info
*
core
=
&
clk
->
eng
[
nv_clk_src_core
];
int
ret
=
0
;
unsigned
long
flags
;
...
...
@@ -509,51 +510,37 @@ gt215_clk_prog(struct nvkm_clk *obj)
}
static
void
gt215_clk_tidy
(
struct
nvkm_clk
*
obj
)
gt215_clk_tidy
(
struct
nvkm_clk
*
base
)
{
}
static
struct
nvkm_domain
gt215_domain
[]
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_core
,
0x00
,
0
,
"core"
,
1000
},
{
nv_clk_src_shader
,
0x01
,
0
,
"shader"
,
1000
},
{
nv_clk_src_mem
,
0x02
,
0
,
"memory"
,
1000
},
{
nv_clk_src_vdec
,
0x03
},
{
nv_clk_src_disp
,
0x04
},
{
nv_clk_src_host
,
0x05
},
{
nv_clk_src_core_intm
,
0x06
},
{
nv_clk_src_max
}
static
const
struct
nvkm_clk_func
gt215_clk
=
{
.
read
=
gt215_clk_read
,
.
calc
=
gt215_clk_calc
,
.
prog
=
gt215_clk_prog
,
.
tidy
=
gt215_clk_tidy
,
.
domains
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_core
,
0x00
,
0
,
"core"
,
1000
},
{
nv_clk_src_shader
,
0x01
,
0
,
"shader"
,
1000
},
{
nv_clk_src_mem
,
0x02
,
0
,
"memory"
,
1000
},
{
nv_clk_src_vdec
,
0x03
},
{
nv_clk_src_disp
,
0x04
},
{
nv_clk_src_host
,
0x05
},
{
nv_clk_src_core_intm
,
0x06
},
{
nv_clk_src_max
}
}
};
static
int
gt215_clk_ctor
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
pobject
)
int
gt215_clk_new
(
struct
nvkm_device
*
device
,
int
index
,
struct
nvkm_clk
**
pclk
)
{
struct
gt215_clk
*
clk
;
int
ret
;
ret
=
nvkm_clk_create
(
parent
,
engine
,
oclass
,
gt215_domain
,
NULL
,
0
,
true
,
&
clk
);
*
pobject
=
nv_object
(
clk
);
if
(
ret
)
return
ret
;
if
(
!
(
clk
=
kzalloc
(
sizeof
(
*
clk
),
GFP_KERNEL
)))
return
-
ENOMEM
;
*
pclk
=
&
clk
->
base
;
clk
->
base
.
read
=
gt215_clk_read
;
clk
->
base
.
calc
=
gt215_clk_calc
;
clk
->
base
.
prog
=
gt215_clk_prog
;
clk
->
base
.
tidy
=
gt215_clk_tidy
;
return
0
;
return
nvkm_clk_ctor
(
&
gt215_clk
,
device
,
index
,
true
,
&
clk
->
base
);
}
struct
nvkm_oclass
gt215_clk_oclass
=
{
.
handle
=
NV_SUBDEV
(
CLK
,
0xa3
),
.
ofuncs
=
&
(
struct
nvkm_ofuncs
)
{
.
ctor
=
gt215_clk_ctor
,
.
dtor
=
_nvkm_clk_dtor
,
.
init
=
_nvkm_clk_init
,
.
fini
=
_nvkm_clk_fini
,
},
};
drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.h
浏览文件 @
6625f55c
#ifndef __NVKM_CLK_NVA3_H__
#define __NVKM_CLK_NVA3_H__
#include
<subdev/clk.h>
#include
"priv.h"
struct
gt215_clk_info
{
u32
clk
;
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.c
浏览文件 @
6625f55c
...
...
@@ -21,6 +21,7 @@
*
* Authors: Ben Skeggs
*/
#define mcp77_clk(p) container_of((p), struct mcp77_clk, base)
#include "gt215.h"
#include "pll.h"
...
...
@@ -50,7 +51,7 @@ read_pll(struct mcp77_clk *clk, u32 base)
struct
nvkm_device
*
device
=
clk
->
base
.
subdev
.
device
;
u32
ctrl
=
nvkm_rd32
(
device
,
base
+
0
);
u32
coef
=
nvkm_rd32
(
device
,
base
+
4
);
u32
ref
=
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
);
u32
ref
=
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
);
u32
post_div
=
0
;
u32
clock
=
0
;
int
N1
,
M1
;
...
...
@@ -77,9 +78,9 @@ read_pll(struct mcp77_clk *clk, u32 base)
}
static
int
mcp77_clk_read
(
struct
nvkm_clk
*
obj
,
enum
nv_clk_src
src
)
mcp77_clk_read
(
struct
nvkm_clk
*
base
,
enum
nv_clk_src
src
)
{
struct
mcp77_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
mcp77_clk
*
clk
=
mcp77_clk
(
base
);
struct
nvkm_subdev
*
subdev
=
&
clk
->
base
.
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
u32
mast
=
nvkm_rd32
(
device
,
0x00c054
);
...
...
@@ -91,38 +92,38 @@ mcp77_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
case
nv_clk_src_href
:
return
100000
;
/* PCIE reference clock */
case
nv_clk_src_hclkm4
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
)
*
4
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
)
*
4
;
case
nv_clk_src_hclkm2d3
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
)
*
2
/
3
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
)
*
2
/
3
;
case
nv_clk_src_host
:
switch
(
mast
&
0x000c0000
)
{
case
0x00000000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclkm2d3
);
case
0x00000000
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclkm2d3
);
case
0x00040000
:
break
;
case
0x00080000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclkm4
);
case
0x000c0000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_cclk
);
case
0x00080000
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclkm4
);
case
0x000c0000
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_cclk
);
}
break
;
case
nv_clk_src_core
:
P
=
(
nvkm_rd32
(
device
,
0x004028
)
&
0x00070000
)
>>
16
;
switch
(
mast
&
0x00000003
)
{
case
0x00000000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_crystal
)
>>
P
;
case
0x00000000
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_crystal
)
>>
P
;
case
0x00000001
:
return
0
;
case
0x00000002
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclkm4
)
>>
P
;
case
0x00000002
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclkm4
)
>>
P
;
case
0x00000003
:
return
read_pll
(
clk
,
0x004028
)
>>
P
;
}
break
;
case
nv_clk_src_cclk
:
if
((
mast
&
0x03000000
)
!=
0x03000000
)
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_core
);
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_core
);
if
((
mast
&
0x00000200
)
==
0x00000000
)
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_core
);
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_core
);
switch
(
mast
&
0x00000c00
)
{
case
0x00000000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
);
case
0x00000400
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclkm4
);
case
0x00000800
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclkm2d3
);
case
0x00000000
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
);
case
0x00000400
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclkm4
);
case
0x00000800
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclkm2d3
);
default:
return
0
;
}
case
nv_clk_src_shader
:
...
...
@@ -130,8 +131,8 @@ mcp77_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
switch
(
mast
&
0x00000030
)
{
case
0x00000000
:
if
(
mast
&
0x00000040
)
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
)
>>
P
;
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_crystal
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_crystal
)
>>
P
;
case
0x00000010
:
break
;
case
0x00000020
:
return
read_pll
(
clk
,
0x004028
)
>>
P
;
case
0x00000030
:
return
read_pll
(
clk
,
0x004020
)
>>
P
;
...
...
@@ -145,7 +146,7 @@ mcp77_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
switch
(
mast
&
0x00400000
)
{
case
0x00400000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_core
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_core
)
>>
P
;
break
;
default:
return
500000
>>
P
;
...
...
@@ -173,7 +174,7 @@ calc_pll(struct mcp77_clk *clk, u32 reg,
return
0
;
pll
.
vco2
.
max_freq
=
0
;
pll
.
refclk
=
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
);
pll
.
refclk
=
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
);
if
(
!
pll
.
refclk
)
return
0
;
...
...
@@ -199,9 +200,9 @@ calc_P(u32 src, u32 target, int *div)
}
static
int
mcp77_clk_calc
(
struct
nvkm_clk
*
obj
,
struct
nvkm_cstate
*
cstate
)
mcp77_clk_calc
(
struct
nvkm_clk
*
base
,
struct
nvkm_cstate
*
cstate
)
{
struct
mcp77_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
mcp77_clk
*
clk
=
mcp77_clk
(
base
);
const
int
shader
=
cstate
->
domain
[
nv_clk_src_shader
];
const
int
core
=
cstate
->
domain
[
nv_clk_src_core
];
const
int
vdec
=
cstate
->
domain
[
nv_clk_src_vdec
];
...
...
@@ -211,8 +212,8 @@ mcp77_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
int
divs
=
0
;
/* cclk: find suitable source, disable PLL if we can */
if
(
core
<
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclkm4
))
out
=
calc_P
(
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclkm4
),
core
,
&
divs
);
if
(
core
<
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclkm4
))
out
=
calc_P
(
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclkm4
),
core
,
&
divs
);
/* Calculate clock * 2, so shader clock can use it too */
clock
=
calc_pll
(
clk
,
0x4028
,
(
core
<<
1
),
&
N
,
&
M
,
&
P1
);
...
...
@@ -238,7 +239,7 @@ mcp77_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
/* sclk: nvpll + divisor, href or spll */
out
=
0
;
if
(
shader
==
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
))
{
if
(
shader
==
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
))
{
clk
->
ssrc
=
nv_clk_src_href
;
}
else
{
clock
=
calc_pll
(
clk
,
0x4020
,
shader
,
&
N
,
&
M
,
&
P1
);
...
...
@@ -295,9 +296,9 @@ mcp77_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
}
static
int
mcp77_clk_prog
(
struct
nvkm_clk
*
obj
)
mcp77_clk_prog
(
struct
nvkm_clk
*
base
)
{
struct
mcp77_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
mcp77_clk
*
clk
=
mcp77_clk
(
base
);
struct
nvkm_subdev
*
subdev
=
&
clk
->
base
.
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
u32
pllmask
=
0
,
mast
;
...
...
@@ -389,48 +390,34 @@ mcp77_clk_prog(struct nvkm_clk *obj)
}
static
void
mcp77_clk_tidy
(
struct
nvkm_clk
*
obj
)
mcp77_clk_tidy
(
struct
nvkm_clk
*
base
)
{
}
static
struct
nvkm_domain
mcp77_domains
[]
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_href
,
0xff
},
{
nv_clk_src_core
,
0xff
,
0
,
"core"
,
1000
},
{
nv_clk_src_shader
,
0xff
,
0
,
"shader"
,
1000
},
{
nv_clk_src_vdec
,
0xff
,
0
,
"vdec"
,
1000
},
{
nv_clk_src_max
}
static
const
struct
nvkm_clk_func
mcp77_clk
=
{
.
read
=
mcp77_clk_read
,
.
calc
=
mcp77_clk_calc
,
.
prog
=
mcp77_clk_prog
,
.
tidy
=
mcp77_clk_tidy
,
.
domains
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_href
,
0xff
},
{
nv_clk_src_core
,
0xff
,
0
,
"core"
,
1000
},
{
nv_clk_src_shader
,
0xff
,
0
,
"shader"
,
1000
},
{
nv_clk_src_vdec
,
0xff
,
0
,
"vdec"
,
1000
},
{
nv_clk_src_max
}
}
};
static
int
mcp77_clk_ctor
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
pobject
)
int
mcp77_clk_new
(
struct
nvkm_device
*
device
,
int
index
,
struct
nvkm_clk
**
pclk
)
{
struct
mcp77_clk
*
clk
;
int
ret
;
ret
=
nvkm_clk_create
(
parent
,
engine
,
oclass
,
mcp77_domains
,
NULL
,
0
,
true
,
&
clk
);
*
pobject
=
nv_object
(
clk
);
if
(
ret
)
return
ret
;
if
(
!
(
clk
=
kzalloc
(
sizeof
(
*
clk
),
GFP_KERNEL
)))
return
-
ENOMEM
;
*
pclk
=
&
clk
->
base
;
clk
->
base
.
read
=
mcp77_clk_read
;
clk
->
base
.
calc
=
mcp77_clk_calc
;
clk
->
base
.
prog
=
mcp77_clk_prog
;
clk
->
base
.
tidy
=
mcp77_clk_tidy
;
return
0
;
return
nvkm_clk_ctor
(
&
mcp77_clk
,
device
,
index
,
true
,
&
clk
->
base
);
}
struct
nvkm_oclass
*
mcp77_clk_oclass
=
&
(
struct
nvkm_oclass
)
{
.
handle
=
NV_SUBDEV
(
CLK
,
0xaa
),
.
ofuncs
=
&
(
struct
nvkm_ofuncs
)
{
.
ctor
=
mcp77_clk_ctor
,
.
dtor
=
_nvkm_clk_dtor
,
.
init
=
_nvkm_clk_init
,
.
fini
=
_nvkm_clk_fini
,
},
};
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c
浏览文件 @
6625f55c
...
...
@@ -21,7 +21,7 @@
*
* Authors: Ben Skeggs
*/
#include
<subdev/clk.h>
#include
"priv.h"
#include "pll.h"
#include <subdev/bios.h>
...
...
@@ -33,7 +33,7 @@ nv04_clk_pll_calc(struct nvkm_clk *clock, struct nvbios_pll *info,
int
clk
,
struct
nvkm_pll_vals
*
pv
)
{
int
N1
,
M1
,
N2
,
M2
,
P
;
int
ret
=
nv04_pll_calc
(
nv_subdev
(
clock
)
,
info
,
clk
,
&
N1
,
&
M1
,
&
N2
,
&
M2
,
&
P
);
int
ret
=
nv04_pll_calc
(
&
clock
->
subdev
,
info
,
clk
,
&
N1
,
&
M1
,
&
N2
,
&
M2
,
&
P
);
if
(
ret
)
{
pv
->
refclk
=
info
->
refclk
;
pv
->
N1
=
N1
;
...
...
@@ -64,37 +64,20 @@ nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv)
return
0
;
}
static
struct
nvkm_domain
nv04_domain
[]
=
{
{
nv_clk_src_max
}
static
const
struct
nvkm_clk_func
nv04_clk
=
{
.
domains
=
{
{
nv_clk_src_max
}
}
};
static
int
nv04_clk_ctor
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
pobject
)
int
nv04_clk_new
(
struct
nvkm_device
*
device
,
int
index
,
struct
nvkm_clk
**
pclk
)
{
struct
nvkm_clk
*
clk
;
int
ret
;
ret
=
nvkm_clk_create
(
parent
,
engine
,
oclass
,
nv04_domain
,
NULL
,
0
,
false
,
&
clk
);
*
pobject
=
nv_object
(
clk
);
if
(
ret
)
return
ret
;
clk
->
pll_calc
=
nv04_clk_pll_calc
;
clk
->
pll_prog
=
nv04_clk_pll_prog
;
return
0
;
int
ret
=
nvkm_clk_new_
(
&
nv04_clk
,
device
,
index
,
false
,
pclk
);
if
(
ret
==
0
)
{
(
*
pclk
)
->
pll_calc
=
nv04_clk_pll_calc
;
(
*
pclk
)
->
pll_prog
=
nv04_clk_pll_prog
;
}
return
ret
;
}
struct
nvkm_oclass
nv04_clk_oclass
=
{
.
handle
=
NV_SUBDEV
(
CLK
,
0x04
),
.
ofuncs
=
&
(
struct
nvkm_ofuncs
)
{
.
ctor
=
nv04_clk_ctor
,
.
dtor
=
_nvkm_clk_dtor
,
.
init
=
_nvkm_clk_init
,
.
fini
=
_nvkm_clk_fini
,
},
};
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.c
浏览文件 @
6625f55c
...
...
@@ -21,7 +21,8 @@
*
* Authors: Ben Skeggs
*/
#include <subdev/clk.h>
#define nv40_clk(p) container_of((p), struct nv40_clk, base)
#include "priv.h"
#include "pll.h"
#include <subdev/bios.h>
...
...
@@ -35,16 +36,6 @@ struct nv40_clk {
u32
spll
;
};
static
struct
nvkm_domain
nv40_domain
[]
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_href
,
0xff
},
{
nv_clk_src_core
,
0xff
,
0
,
"core"
,
1000
},
{
nv_clk_src_shader
,
0xff
,
0
,
"shader"
,
1000
},
{
nv_clk_src_mem
,
0xff
,
0
,
"memory"
,
1000
},
{
nv_clk_src_max
}
};
static
u32
read_pll_1
(
struct
nv40_clk
*
clk
,
u32
reg
)
{
...
...
@@ -103,9 +94,9 @@ read_clk(struct nv40_clk *clk, u32 src)
}
static
int
nv40_clk_read
(
struct
nvkm_clk
*
obj
,
enum
nv_clk_src
src
)
nv40_clk_read
(
struct
nvkm_clk
*
base
,
enum
nv_clk_src
src
)
{
struct
nv40_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
nv40_clk
*
clk
=
nv40_clk
(
base
);
struct
nvkm_subdev
*
subdev
=
&
clk
->
base
.
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
u32
mast
=
nvkm_rd32
(
device
,
0x00c040
);
...
...
@@ -152,9 +143,9 @@ nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz,
}
static
int
nv40_clk_calc
(
struct
nvkm_clk
*
obj
,
struct
nvkm_cstate
*
cstate
)
nv40_clk_calc
(
struct
nvkm_clk
*
base
,
struct
nvkm_cstate
*
cstate
)
{
struct
nv40_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
nv40_clk
*
clk
=
nv40_clk
(
base
);
int
gclk
=
cstate
->
domain
[
nv_clk_src_core
];
int
sclk
=
cstate
->
domain
[
nv_clk_src_shader
];
int
N1
,
M1
,
N2
,
M2
,
log2P
;
...
...
@@ -192,9 +183,9 @@ nv40_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
}
static
int
nv40_clk_prog
(
struct
nvkm_clk
*
obj
)
nv40_clk_prog
(
struct
nvkm_clk
*
base
)
{
struct
nv40_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
nv40_clk
*
clk
=
nv40_clk
(
base
);
struct
nvkm_device
*
device
=
clk
->
base
.
subdev
.
device
;
nvkm_mask
(
device
,
0x00c040
,
0x00000333
,
0x00000000
);
nvkm_wr32
(
device
,
0x004004
,
clk
->
npll_coef
);
...
...
@@ -210,36 +201,32 @@ nv40_clk_tidy(struct nvkm_clk *obj)
{
}
static
int
nv40_clk_ctor
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
pobject
)
static
const
struct
nvkm_clk_func
nv40_clk
=
{
.
read
=
nv40_clk_read
,
.
calc
=
nv40_clk_calc
,
.
prog
=
nv40_clk_prog
,
.
tidy
=
nv40_clk_tidy
,
.
domains
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_href
,
0xff
},
{
nv_clk_src_core
,
0xff
,
0
,
"core"
,
1000
},
{
nv_clk_src_shader
,
0xff
,
0
,
"shader"
,
1000
},
{
nv_clk_src_mem
,
0xff
,
0
,
"memory"
,
1000
},
{
nv_clk_src_max
}
}
};
int
nv40_clk_new
(
struct
nvkm_device
*
device
,
int
index
,
struct
nvkm_clk
**
pclk
)
{
struct
nv40_clk
*
clk
;
int
ret
;
ret
=
nvkm_clk_create
(
parent
,
engine
,
oclass
,
nv40_domain
,
NULL
,
0
,
true
,
&
clk
);
*
pobject
=
nv_object
(
clk
);
if
(
ret
)
return
ret
;
if
(
!
(
clk
=
kzalloc
(
sizeof
(
*
clk
),
GFP_KERNEL
)))
return
-
ENOMEM
;
clk
->
base
.
pll_calc
=
nv04_clk_pll_calc
;
clk
->
base
.
pll_prog
=
nv04_clk_pll_prog
;
clk
->
base
.
read
=
nv40_clk_read
;
clk
->
base
.
calc
=
nv40_clk_calc
;
clk
->
base
.
prog
=
nv40_clk_prog
;
clk
->
base
.
tidy
=
nv40_clk_tidy
;
return
0
;
}
*
pclk
=
&
clk
->
base
;
struct
nvkm_oclass
nv40_clk_oclass
=
{
.
handle
=
NV_SUBDEV
(
CLK
,
0x40
),
.
ofuncs
=
&
(
struct
nvkm_ofuncs
)
{
.
ctor
=
nv40_clk_ctor
,
.
dtor
=
_nvkm_clk_dtor
,
.
init
=
_nvkm_clk_init
,
.
fini
=
_nvkm_clk_fini
,
},
};
return
nvkm_clk_ctor
(
&
nv40_clk
,
device
,
index
,
true
,
&
clk
->
base
);
}
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.c
浏览文件 @
6625f55c
...
...
@@ -53,7 +53,7 @@ read_pll_src(struct nv50_clk *clk, u32 base)
{
struct
nvkm_subdev
*
subdev
=
&
clk
->
base
.
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
u32
coef
,
ref
=
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_crystal
);
u32
coef
,
ref
=
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_crystal
);
u32
rsel
=
nvkm_rd32
(
device
,
0x00e18c
);
int
P
,
N
,
M
,
id
;
...
...
@@ -100,8 +100,8 @@ read_pll_src(struct nv50_clk *clk, u32 base)
switch
(
rsel
)
{
case
0
:
id
=
1
;
break
;
case
1
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_crystal
);
case
2
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
);
case
1
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_crystal
);
case
2
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
);
case
3
:
id
=
0
;
break
;
}
...
...
@@ -142,14 +142,14 @@ read_pll_ref(struct nv50_clk *clk, u32 base)
src
=
!!
(
mast
&
0x02000000
);
break
;
case
0x00e810
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_crystal
);
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_crystal
);
default:
nvkm_error
(
subdev
,
"bad pll %06x
\n
"
,
base
);
return
0
;
}
if
(
src
)
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
);
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
);
return
read_pll_src
(
clk
,
base
);
}
...
...
@@ -168,7 +168,7 @@ read_pll(struct nv50_clk *clk, u32 base)
if
(
base
==
0x004028
&&
(
mast
&
0x00100000
))
{
/* wtf, appears to only disable post-divider on gt200 */
if
(
device
->
chipset
!=
0xa0
)
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_dom6
);
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_dom6
);
}
N2
=
(
coef
&
0xff000000
)
>>
24
;
...
...
@@ -188,10 +188,10 @@ read_pll(struct nv50_clk *clk, u32 base)
return
freq
;
}
static
int
nv50_clk_read
(
struct
nvkm_clk
*
obj
,
enum
nv_clk_src
src
)
int
nv50_clk_read
(
struct
nvkm_clk
*
base
,
enum
nv_clk_src
src
)
{
struct
nv50_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
nv50_clk
*
clk
=
nv50_clk
(
base
);
struct
nvkm_subdev
*
subdev
=
&
clk
->
base
.
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
u32
mast
=
nvkm_rd32
(
device
,
0x00c040
);
...
...
@@ -203,25 +203,25 @@ nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
case
nv_clk_src_href
:
return
100000
;
/* PCIE reference clock */
case
nv_clk_src_hclk
:
return
div_u64
((
u64
)
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
)
*
27778
,
10000
);
return
div_u64
((
u64
)
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
)
*
27778
,
10000
);
case
nv_clk_src_hclkm3
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclk
)
*
3
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclk
)
*
3
;
case
nv_clk_src_hclkm3d2
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclk
)
*
3
/
2
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclk
)
*
3
/
2
;
case
nv_clk_src_host
:
switch
(
mast
&
0x30000000
)
{
case
0x00000000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
);
case
0x00000000
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
);
case
0x10000000
:
break
;
case
0x20000000
:
/* !0x50 */
case
0x30000000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclk
);
case
0x30000000
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclk
);
}
break
;
case
nv_clk_src_core
:
if
(
!
(
mast
&
0x00100000
))
P
=
(
nvkm_rd32
(
device
,
0x004028
)
&
0x00070000
)
>>
16
;
switch
(
mast
&
0x00000003
)
{
case
0x00000000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_crystal
)
>>
P
;
case
0x00000001
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_dom6
);
case
0x00000000
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_crystal
)
>>
P
;
case
0x00000001
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_dom6
);
case
0x00000002
:
return
read_pll
(
clk
,
0x004020
)
>>
P
;
case
0x00000003
:
return
read_pll
(
clk
,
0x004028
)
>>
P
;
}
...
...
@@ -231,8 +231,8 @@ nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
switch
(
mast
&
0x00000030
)
{
case
0x00000000
:
if
(
mast
&
0x00000080
)
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_host
)
>>
P
;
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_crystal
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_host
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_crystal
)
>>
P
;
case
0x00000010
:
break
;
case
0x00000020
:
return
read_pll
(
clk
,
0x004028
)
>>
P
;
case
0x00000030
:
return
read_pll
(
clk
,
0x004020
)
>>
P
;
...
...
@@ -243,10 +243,10 @@ nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
if
(
nvkm_rd32
(
device
,
0x004008
)
&
0x00000200
)
{
switch
(
mast
&
0x0000c000
)
{
case
0x00000000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_crystal
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_crystal
)
>>
P
;
case
0x00008000
:
case
0x0000c000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
)
>>
P
;
}
}
else
{
return
read_pll
(
clk
,
0x004008
)
>>
P
;
...
...
@@ -264,8 +264,8 @@ nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
switch
(
mast
&
0x00000c00
)
{
case
0x00000000
:
if
(
device
->
chipset
==
0xa0
)
/* wtf?? */
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_core
)
>>
P
;
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_crystal
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_core
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_crystal
)
>>
P
;
case
0x00000400
:
return
0
;
case
0x00000800
:
...
...
@@ -273,19 +273,19 @@ nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
return
read_pll
(
clk
,
0x004028
)
>>
P
;
return
read_pll
(
clk
,
0x004030
)
>>
P
;
case
0x00000c00
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_core
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_core
)
>>
P
;
}
break
;
case
0x98
:
switch
(
mast
&
0x00000c00
)
{
case
0x00000000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_core
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_core
)
>>
P
;
case
0x00000400
:
return
0
;
case
0x00000800
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclkm3d2
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclkm3d2
)
>>
P
;
case
0x00000c00
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_mem
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_mem
)
>>
P
;
}
break
;
}
...
...
@@ -303,11 +303,11 @@ nv50_clk_read(struct nvkm_clk *obj, enum nv_clk_src src)
case
0x98
:
P
=
(
read_div
(
clk
)
&
0x00000007
)
>>
0
;
switch
(
mast
&
0x0c000000
)
{
case
0x00000000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
);
case
0x00000000
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
);
case
0x04000000
:
break
;
case
0x08000000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclk
);
case
0x08000000
:
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclk
);
case
0x0c000000
:
return
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclkm3
)
>>
P
;
return
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclkm3
)
>>
P
;
}
break
;
default:
...
...
@@ -364,11 +364,13 @@ clk_same(u32 a, u32 b)
return
((
a
/
1000
)
==
(
b
/
1000
));
}
static
int
nv50_clk_calc
(
struct
nvkm_clk
*
obj
,
struct
nvkm_cstate
*
cstate
)
int
nv50_clk_calc
(
struct
nvkm_clk
*
base
,
struct
nvkm_cstate
*
cstate
)
{
struct
nv50_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
nv50_clk
*
clk
=
nv50_clk
(
base
);
struct
nv50_clk_hwsq
*
hwsq
=
&
clk
->
hwsq
;
struct
nvkm_subdev
*
subdev
=
&
clk
->
base
.
subdev
;
struct
nvkm_device
*
device
=
subdev
->
device
;
const
int
shader
=
cstate
->
domain
[
nv_clk_src_shader
];
const
int
core
=
cstate
->
domain
[
nv_clk_src_core
];
const
int
vdec
=
cstate
->
domain
[
nv_clk_src_vdec
];
...
...
@@ -379,7 +381,7 @@ nv50_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
int
freq
,
out
;
/* prepare a hwsq script from which we'll perform the reclock */
out
=
clk_init
(
hwsq
,
nv_subdev
(
clk
)
);
out
=
clk_init
(
hwsq
,
subdev
);
if
(
out
)
return
out
;
...
...
@@ -397,15 +399,15 @@ nv50_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
freq
=
calc_div
(
core
,
vdec
,
&
P1
);
/* see how close we can get using xpll/hclk as a source */
if
(
nv_device
(
clk
)
->
chipset
!=
0x98
)
if
(
device
->
chipset
!=
0x98
)
out
=
read_pll
(
clk
,
0x004030
);
else
out
=
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclkm3d2
);
out
=
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclkm3d2
);
out
=
calc_div
(
out
,
vdec
,
&
P2
);
/* select whichever gets us closest */
if
(
abs
(
vdec
-
freq
)
<=
abs
(
vdec
-
out
))
{
if
(
nv_device
(
clk
)
->
chipset
!=
0x98
)
if
(
device
->
chipset
!=
0x98
)
mastv
|=
0x00000c00
;
divsv
|=
P1
<<
8
;
}
else
{
...
...
@@ -421,13 +423,13 @@ nv50_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
* of the host clock frequency
*/
if
(
dom6
)
{
if
(
clk_same
(
dom6
,
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_href
)))
{
if
(
clk_same
(
dom6
,
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_href
)))
{
mastv
|=
0x00000000
;
}
else
if
(
clk_same
(
dom6
,
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclk
)))
{
if
(
clk_same
(
dom6
,
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclk
)))
{
mastv
|=
0x08000000
;
}
else
{
freq
=
clk
->
base
.
read
(
&
clk
->
base
,
nv_clk_src_hclk
)
*
3
;
freq
=
nvkm_clk_
read
(
&
clk
->
base
,
nv_clk_src_hclk
)
*
3
;
calc_div
(
freq
,
dom6
,
&
P1
);
mastv
|=
0x0c000000
;
...
...
@@ -448,7 +450,7 @@ nv50_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
/* core/shader: disconnect nvclk/sclk from their PLLs (nvclk to dom6,
* sclk to hclk) before reprogramming
*/
if
(
nv_device
(
clk
)
->
chipset
<
0x92
)
if
(
device
->
chipset
<
0x92
)
clk_mask
(
hwsq
,
mast
,
0x001000b0
,
0x00100080
);
else
clk_mask
(
hwsq
,
mast
,
0x000000b3
,
0x00000081
);
...
...
@@ -489,33 +491,31 @@ nv50_clk_calc(struct nvkm_clk *obj, struct nvkm_cstate *cstate)
return
0
;
}
static
int
nv50_clk_prog
(
struct
nvkm_clk
*
obj
)
int
nv50_clk_prog
(
struct
nvkm_clk
*
base
)
{
struct
nv50_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
nv50_clk
*
clk
=
nv50_clk
(
base
);
return
clk_exec
(
&
clk
->
hwsq
,
true
);
}
static
void
nv50_clk_tidy
(
struct
nvkm_clk
*
obj
)
void
nv50_clk_tidy
(
struct
nvkm_clk
*
base
)
{
struct
nv50_clk
*
clk
=
container_of
(
obj
,
typeof
(
*
clk
),
base
);
struct
nv50_clk
*
clk
=
nv50_clk
(
base
);
clk_exec
(
&
clk
->
hwsq
,
false
);
}
int
nv50_clk_ctor
(
struct
nvkm_object
*
parent
,
struct
nvkm_object
*
engine
,
struct
nvkm_oclass
*
oclass
,
void
*
data
,
u32
size
,
struct
nvkm_object
**
pobject
)
nv50_clk_new_
(
const
struct
nvkm_clk_func
*
func
,
struct
nvkm_device
*
device
,
int
index
,
bool
allow_reclock
,
struct
nvkm_clk
**
pclk
)
{
struct
nv50_clk_oclass
*
pclass
=
(
void
*
)
oclass
;
struct
nv50_clk
*
clk
;
int
ret
;
ret
=
nvkm_clk_create
(
parent
,
engine
,
oclass
,
pclass
->
domains
,
NULL
,
0
,
nv_device
(
parent
)
->
chipset
==
0xa0
,
&
clk
);
*
p
object
=
nv_object
(
clk
)
;
if
(
!
(
clk
=
kzalloc
(
sizeof
(
*
clk
),
GFP_KERNEL
)))
return
-
ENOMEM
;
ret
=
nvkm_clk_ctor
(
func
,
device
,
index
,
allow_reclock
,
&
clk
->
base
);
*
p
clk
=
&
clk
->
base
;
if
(
ret
)
return
ret
;
...
...
@@ -524,7 +524,7 @@ nv50_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
clk
->
hwsq
.
r_spll
[
1
]
=
hwsq_reg
(
0x004024
);
clk
->
hwsq
.
r_nvpll
[
0
]
=
hwsq_reg
(
0x004028
);
clk
->
hwsq
.
r_nvpll
[
1
]
=
hwsq_reg
(
0x00402c
);
switch
(
nv_device
(
clk
)
->
chipset
)
{
switch
(
device
->
chipset
)
{
case
0x92
:
case
0x94
:
case
0x96
:
...
...
@@ -535,32 +535,27 @@ nv50_clk_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
break
;
}
clk
->
hwsq
.
r_mast
=
hwsq_reg
(
0x00c040
);
clk
->
base
.
read
=
nv50_clk_read
;
clk
->
base
.
calc
=
nv50_clk_calc
;
clk
->
base
.
prog
=
nv50_clk_prog
;
clk
->
base
.
tidy
=
nv50_clk_tidy
;
return
0
;
}
static
struct
nvkm_domain
nv50_domains
[]
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_href
,
0xff
},
{
nv_clk_src_core
,
0xff
,
0
,
"core"
,
1000
},
{
nv_clk_src_shader
,
0xff
,
0
,
"shader"
,
1000
},
{
nv_clk_src_mem
,
0xff
,
0
,
"memory"
,
1000
},
{
nv_clk_src_max
}
static
const
struct
nvkm_clk_func
nv50_clk
=
{
.
read
=
nv50_clk_read
,
.
calc
=
nv50_clk_calc
,
.
prog
=
nv50_clk_prog
,
.
tidy
=
nv50_clk_tidy
,
.
domains
=
{
{
nv_clk_src_crystal
,
0xff
},
{
nv_clk_src_href
,
0xff
},
{
nv_clk_src_core
,
0xff
,
0
,
"core"
,
1000
},
{
nv_clk_src_shader
,
0xff
,
0
,
"shader"
,
1000
},
{
nv_clk_src_mem
,
0xff
,
0
,
"memory"
,
1000
},
{
nv_clk_src_max
}
}
};
struct
nvkm_oclass
*
nv50_clk_oclass
=
&
(
struct
nv50_clk_oclass
)
{
.
base
.
handle
=
NV_SUBDEV
(
CLK
,
0x50
),
.
base
.
ofuncs
=
&
(
struct
nvkm_ofuncs
)
{
.
ctor
=
nv50_clk_ctor
,
.
dtor
=
_nvkm_clk_dtor
,
.
init
=
_nvkm_clk_init
,
.
fini
=
_nvkm_clk_fini
,
},
.
domains
=
nv50_domains
,
}.
base
;
int
nv50_clk_new
(
struct
nvkm_device
*
device
,
int
index
,
struct
nvkm_clk
**
pclk
)
{
return
nv50_clk_new_
(
&
nv50_clk
,
device
,
index
,
false
,
pclk
);
}
drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.h
浏览文件 @
6625f55c
#ifndef __NVKM_CLK_NV50_H__
#define __NVKM_CLK_NV50_H__
#ifndef __NV50_CLK_H__
#define __NV50_CLK_H__
#define nv50_clk(p) container_of((p), struct nv50_clk, base)
#include "priv.h"
#include <subdev/bus/hwsq.h>
#include <subdev/clk.h>
struct
nv50_clk_hwsq
{
struct
hwsq
base
;
...
...
@@ -17,12 +19,10 @@ struct nv50_clk {
struct
nv50_clk_hwsq
hwsq
;
};
int
nv50_clk_ctor
(
struct
nvkm_object
*
,
struct
nvkm_object
*
,
struct
nvkm_oclass
*
,
void
*
,
u32
,
struct
nvkm_object
**
);
struct
nv50_clk_oclass
{
struct
nvkm_oclass
base
;
struct
nvkm_domain
*
domains
;
};
int
nv50_clk_new_
(
const
struct
nvkm_clk_func
*
,
struct
nvkm_device
*
,
int
,
bool
,
struct
nvkm_clk
**
);
int
nv50_clk_read
(
struct
nvkm_clk
*
,
enum
nv_clk_src
);
int
nv50_clk_calc
(
struct
nvkm_clk
*
,
struct
nvkm_cstate
*
);
int
nv50_clk_prog
(
struct
nvkm_clk
*
);
void
nv50_clk_tidy
(
struct
nvkm_clk
*
);
#endif
drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h
0 → 100644
浏览文件 @
6625f55c
#ifndef __NVKM_CLK_PRIV_H__
#define __NVKM_CLK_PRIV_H__
#define nvkm_clk(p) container_of((p), struct nvkm_clk, subdev)
#include <subdev/clk.h>
struct
nvkm_clk_func
{
int
(
*
init
)(
struct
nvkm_clk
*
);
void
(
*
fini
)(
struct
nvkm_clk
*
);
int
(
*
read
)(
struct
nvkm_clk
*
,
enum
nv_clk_src
);
int
(
*
calc
)(
struct
nvkm_clk
*
,
struct
nvkm_cstate
*
);
int
(
*
prog
)(
struct
nvkm_clk
*
);
void
(
*
tidy
)(
struct
nvkm_clk
*
);
struct
nvkm_pstate
*
pstates
;
int
nr_pstates
;
struct
nvkm_domain
domains
[];
};
int
nvkm_clk_ctor
(
const
struct
nvkm_clk_func
*
,
struct
nvkm_device
*
,
int
,
bool
allow_reclock
,
struct
nvkm_clk
*
);
int
nvkm_clk_new_
(
const
struct
nvkm_clk_func
*
,
struct
nvkm_device
*
,
int
,
bool
allow_reclock
,
struct
nvkm_clk
**
);
int
nv04_clk_pll_calc
(
struct
nvkm_clk
*
,
struct
nvbios_pll
*
,
int
clk
,
struct
nvkm_pll_vals
*
);
int
nv04_clk_pll_prog
(
struct
nvkm_clk
*
,
u32
reg1
,
struct
nvkm_pll_vals
*
);
#endif
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c
浏览文件 @
6625f55c
...
...
@@ -187,9 +187,9 @@ gf100_ram_calc(struct nvkm_ram *base, u32 freq)
/* determine target mclk configuration */
if
(
!
(
ram_rd32
(
fuc
,
0x137300
)
&
0x00000100
))
ref
=
clk
->
read
(
clk
,
nv_clk_src_sppll0
);
ref
=
nvkm_clk_
read
(
clk
,
nv_clk_src_sppll0
);
else
ref
=
clk
->
read
(
clk
,
nv_clk_src_sppll1
);
ref
=
nvkm_clk_
read
(
clk
,
nv_clk_src_sppll1
);
div
=
max
(
min
((
ref
*
2
)
/
freq
,
(
u32
)
65
),
(
u32
)
2
)
-
2
;
out
=
(
ref
*
2
)
/
(
div
+
2
);
mode
=
freq
!=
out
;
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c
浏览文件 @
6625f55c
...
...
@@ -1032,7 +1032,8 @@ gk104_ram_calc(struct nvkm_ram *base, u32 freq)
int
ret
;
if
(
ram
->
base
.
next
==
NULL
)
{
ret
=
gk104_ram_calc_data
(
ram
,
clk
->
read
(
clk
,
nv_clk_src_mem
),
ret
=
gk104_ram_calc_data
(
ram
,
nvkm_clk_read
(
clk
,
nv_clk_src_mem
),
&
ram
->
base
.
former
);
if
(
ret
)
return
ret
;
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c
浏览文件 @
6625f55c
...
...
@@ -186,7 +186,7 @@ gt215_link_train(struct gt215_ram *ram)
return
-
ENOENT
;
}
clk_current
=
clk
->
read
(
clk
,
nv_clk_src_mem
);
clk_current
=
nvkm_clk_
read
(
clk
,
nv_clk_src_mem
);
ret
=
gt215_clk_pre
(
clk
,
f
);
if
(
ret
)
...
...
drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c
浏览文件 @
6625f55c
...
...
@@ -50,7 +50,7 @@ struct gk20a_pmu_dvfs_dev_status {
static
int
gk20a_pmu_dvfs_target
(
struct
gk20a_pmu
*
pmu
,
int
*
state
)
{
struct
nvkm_clk
*
clk
=
nvkm_clk
(
pmu
)
;
struct
nvkm_clk
*
clk
=
pmu
->
base
.
subdev
.
device
->
clk
;
return
nvkm_clk_astate
(
clk
,
*
state
,
0
,
false
);
}
...
...
@@ -58,7 +58,7 @@ gk20a_pmu_dvfs_target(struct gk20a_pmu *pmu, int *state)
static
int
gk20a_pmu_dvfs_get_cur_state
(
struct
gk20a_pmu
*
pmu
,
int
*
state
)
{
struct
nvkm_clk
*
clk
=
nvkm_clk
(
pmu
)
;
struct
nvkm_clk
*
clk
=
pmu
->
base
.
subdev
.
device
->
clk
;
*
state
=
clk
->
pstate
;
return
0
;
...
...
@@ -69,7 +69,7 @@ gk20a_pmu_dvfs_get_target_state(struct gk20a_pmu *pmu,
int
*
state
,
int
load
)
{
struct
gk20a_pmu_dvfs_data
*
data
=
pmu
->
data
;
struct
nvkm_clk
*
clk
=
nvkm_clk
(
pmu
)
;
struct
nvkm_clk
*
clk
=
pmu
->
base
.
subdev
.
device
->
clk
;
int
cur_level
,
level
;
/* For GK20A, the performance level is directly mapped to pstate */
...
...
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