common.c 29.9 KB
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#include <linux/bootmem.h>
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#include <linux/linkage.h>
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#include <linux/bitops.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/percpu.h>
#include <linux/string.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
#include <linux/init.h>
#include <linux/kgdb.h>
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#include <linux/smp.h>
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#include <linux/io.h>

#include <asm/stackprotector.h>
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#include <asm/perf_event.h>
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#include <asm/mmu_context.h>
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#include <asm/hypervisor.h>
#include <asm/processor.h>
#include <asm/sections.h>
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#include <linux/topology.h>
#include <linux/cpumask.h>
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#include <asm/pgtable.h>
#include <asm/atomic.h>
#include <asm/proto.h>
#include <asm/setup.h>
#include <asm/apic.h>
#include <asm/desc.h>
#include <asm/i387.h>
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#include <asm/mtrr.h>
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#include <linux/numa.h>
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#include <asm/asm.h>
#include <asm/cpu.h>
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#include <asm/mce.h>
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#include <asm/msr.h>
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#include <asm/pat.h>
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#ifdef CONFIG_X86_LOCAL_APIC
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#include <asm/uv/uv.h>
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#endif

#include "cpu.h"

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/* all of these masks are initialized in setup_cpu_local_masks() */
cpumask_var_t cpu_initialized_mask;
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cpumask_var_t cpu_callout_mask;
cpumask_var_t cpu_callin_mask;
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/* representing cpus for which sibling maps can be computed */
cpumask_var_t cpu_sibling_setup_mask;

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/* correctly size the local cpu masks */
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void __init setup_cpu_local_masks(void)
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{
	alloc_bootmem_cpumask_var(&cpu_initialized_mask);
	alloc_bootmem_cpumask_var(&cpu_callin_mask);
	alloc_bootmem_cpumask_var(&cpu_callout_mask);
	alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
}

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static void __cpuinit default_init(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_64
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	cpu_detect_cache_sizes(c);
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#else
	/* Not much we can do here... */
	/* Check if at least it has cpuid */
	if (c->cpuid_level == -1) {
		/* No cpuid. It must be an ancient CPU */
		if (c->x86 == 4)
			strcpy(c->x86_model_id, "486");
		else if (c->x86 == 3)
			strcpy(c->x86_model_id, "386");
	}
#endif
}

static const struct cpu_dev __cpuinitconst default_cpu = {
	.c_init		= default_init,
	.c_vendor	= "Unknown",
	.c_x86_vendor	= X86_VENDOR_UNKNOWN,
};

static const struct cpu_dev *this_cpu __cpuinitdata = &default_cpu;
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DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
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#ifdef CONFIG_X86_64
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	/*
	 * We need valid kernel segments for data and code in long mode too
	 * IRET will check the segment types  kkeil 2000/10/28
	 * Also sysret mandates a special GDT layout
	 *
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	 * TLS descriptors are currently at a different place compared to i386.
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	 * Hopefully nobody expects them at a fixed place (Wine?)
	 */
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	[GDT_ENTRY_KERNEL32_CS]		= GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
	[GDT_ENTRY_KERNEL_CS]		= GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
	[GDT_ENTRY_KERNEL_DS]		= GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
	[GDT_ENTRY_DEFAULT_USER32_CS]	= GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
	[GDT_ENTRY_DEFAULT_USER_DS]	= GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
	[GDT_ENTRY_DEFAULT_USER_CS]	= GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
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#else
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	[GDT_ENTRY_KERNEL_CS]		= GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
	[GDT_ENTRY_KERNEL_DS]		= GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
	[GDT_ENTRY_DEFAULT_USER_CS]	= GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
	[GDT_ENTRY_DEFAULT_USER_DS]	= GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
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	/*
	 * Segments used for calling PnP BIOS have byte granularity.
	 * They code segments and data segments have fixed 64k limits,
	 * the transfer segment sizes are set at run time.
	 */
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	/* 32-bit code */
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	[GDT_ENTRY_PNPBIOS_CS32]	= GDT_ENTRY_INIT(0x409a, 0, 0xffff),
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	/* 16-bit code */
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	[GDT_ENTRY_PNPBIOS_CS16]	= GDT_ENTRY_INIT(0x009a, 0, 0xffff),
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	/* 16-bit data */
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	[GDT_ENTRY_PNPBIOS_DS]		= GDT_ENTRY_INIT(0x0092, 0, 0xffff),
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	/* 16-bit data */
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	[GDT_ENTRY_PNPBIOS_TS1]		= GDT_ENTRY_INIT(0x0092, 0, 0),
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	/* 16-bit data */
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	[GDT_ENTRY_PNPBIOS_TS2]		= GDT_ENTRY_INIT(0x0092, 0, 0),
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	/*
	 * The APM segments have byte granularity and their bases
	 * are set at run time.  All have 64k limits.
	 */
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	/* 32-bit code */
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	[GDT_ENTRY_APMBIOS_BASE]	= GDT_ENTRY_INIT(0x409a, 0, 0xffff),
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	/* 16-bit code */
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	[GDT_ENTRY_APMBIOS_BASE+1]	= GDT_ENTRY_INIT(0x009a, 0, 0xffff),
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	/* data */
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	[GDT_ENTRY_APMBIOS_BASE+2]	= GDT_ENTRY_INIT(0x4092, 0, 0xffff),
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	[GDT_ENTRY_ESPFIX_SS]		= GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
	[GDT_ENTRY_PERCPU]		= GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
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	GDT_STACK_CANARY_INIT
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#endif
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} };
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EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
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static int __init x86_xsave_setup(char *s)
{
	setup_clear_cpu_cap(X86_FEATURE_XSAVE);
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	setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
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	return 1;
}
__setup("noxsave", x86_xsave_setup);

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static int __init x86_xsaveopt_setup(char *s)
{
	setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
	return 1;
}
__setup("noxsaveopt", x86_xsaveopt_setup);

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#ifdef CONFIG_X86_32
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static int cachesize_override __cpuinitdata = -1;
static int disable_x86_serial_nr __cpuinitdata = 1;
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static int __init cachesize_setup(char *str)
{
	get_option(&str, &cachesize_override);
	return 1;
}
__setup("cachesize=", cachesize_setup);

static int __init x86_fxsr_setup(char *s)
{
	setup_clear_cpu_cap(X86_FEATURE_FXSR);
	setup_clear_cpu_cap(X86_FEATURE_XMM);
	return 1;
}
__setup("nofxsr", x86_fxsr_setup);

static int __init x86_sep_setup(char *s)
{
	setup_clear_cpu_cap(X86_FEATURE_SEP);
	return 1;
}
__setup("nosep", x86_sep_setup);

/* Standard macro to see if a specific flag is changeable */
static inline int flag_is_changeable_p(u32 flag)
{
	u32 f1, f2;

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	/*
	 * Cyrix and IDT cpus allow disabling of CPUID
	 * so the code below may return different results
	 * when it is executed before and after enabling
	 * the CPUID. Add "volatile" to not allow gcc to
	 * optimize the subsequent calls to this function.
	 */
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	asm volatile ("pushfl		\n\t"
		      "pushfl		\n\t"
		      "popl %0		\n\t"
		      "movl %0, %1	\n\t"
		      "xorl %2, %0	\n\t"
		      "pushl %0		\n\t"
		      "popfl		\n\t"
		      "pushfl		\n\t"
		      "popl %0		\n\t"
		      "popfl		\n\t"

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		      : "=&r" (f1), "=&r" (f2)
		      : "ir" (flag));
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	return ((f1^f2) & flag) != 0;
}

/* Probe for the CPUID instruction */
static int __cpuinit have_cpuid_p(void)
{
	return flag_is_changeable_p(X86_EFLAGS_ID);
}

static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
{
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	unsigned long lo, hi;

	if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
		return;

	/* Disable processor serial number: */

	rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
	lo |= 0x200000;
	wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);

	printk(KERN_NOTICE "CPU serial number disabled.\n");
	clear_cpu_cap(c, X86_FEATURE_PN);

	/* Disabling the serial number may affect the cpuid level */
	c->cpuid_level = cpuid_eax(0);
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}

static int __init x86_serial_nr_setup(char *s)
{
	disable_x86_serial_nr = 0;
	return 1;
}
__setup("serialnumber", x86_serial_nr_setup);
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#else
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static inline int flag_is_changeable_p(u32 flag)
{
	return 1;
}
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/* Probe for the CPUID instruction */
static inline int have_cpuid_p(void)
{
	return 1;
}
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static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
{
}
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#endif
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/*
 * Some CPU features depend on higher CPUID levels, which may not always
 * be available due to CPUID level capping or broken virtualization
 * software.  Add those features to this table to auto-disable them.
 */
struct cpuid_dependent_feature {
	u32 feature;
	u32 level;
};
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static const struct cpuid_dependent_feature __cpuinitconst
cpuid_dependent_features[] = {
	{ X86_FEATURE_MWAIT,		0x00000005 },
	{ X86_FEATURE_DCA,		0x00000009 },
	{ X86_FEATURE_XSAVE,		0x0000000d },
	{ 0, 0 }
};

static void __cpuinit filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
{
	const struct cpuid_dependent_feature *df;
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	for (df = cpuid_dependent_features; df->feature; df++) {
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		if (!cpu_has(c, df->feature))
			continue;
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		/*
		 * Note: cpuid_level is set to -1 if unavailable, but
		 * extended_extended_level is set to 0 if unavailable
		 * and the legitimate extended levels are all negative
		 * when signed; hence the weird messing around with
		 * signs here...
		 */
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		if (!((s32)df->level < 0 ?
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		     (u32)df->level > (u32)c->extended_cpuid_level :
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		     (s32)df->level > (s32)c->cpuid_level))
			continue;

		clear_cpu_cap(c, df->feature);
		if (!warn)
			continue;

		printk(KERN_WARNING
		       "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
				x86_cap_flags[df->feature], df->level);
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	}
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}
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/*
 * Naming convention should be: <Name> [(<Codename>)]
 * This table only is used unless init_<vendor>() below doesn't set it;
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 * in particular, if CPUID levels 0x80000002..4 are supported, this
 * isn't used
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 */

/* Look up CPU names by table lookup. */
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static const char *__cpuinit table_lookup_model(struct cpuinfo_x86 *c)
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{
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	const struct cpu_model_info *info;
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	if (c->x86_model >= 16)
		return NULL;	/* Range check */

	if (!this_cpu)
		return NULL;

	info = this_cpu->c_models;

	while (info && info->family) {
		if (info->family == c->x86)
			return info->model_names[c->x86_model];
		info++;
	}
	return NULL;		/* Not found */
}

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__u32 cpu_caps_cleared[NCAPINTS] __cpuinitdata;
__u32 cpu_caps_set[NCAPINTS] __cpuinitdata;
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void load_percpu_segment(int cpu)
{
#ifdef CONFIG_X86_32
	loadsegment(fs, __KERNEL_PERCPU);
#else
	loadsegment(gs, 0);
	wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
#endif
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	load_stack_canary_segment();
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}

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/*
 * Current gdt points %fs at the "master" per-cpu area: after this,
 * it's on the real one.
 */
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void switch_to_new_gdt(int cpu)
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{
	struct desc_ptr gdt_descr;

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	gdt_descr.address = (long)get_cpu_gdt_table(cpu);
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	gdt_descr.size = GDT_SIZE - 1;
	load_gdt(&gdt_descr);
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	/* Reload the per-cpu base */
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	load_percpu_segment(cpu);
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}

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static const struct cpu_dev *__cpuinitdata cpu_devs[X86_VENDOR_NUM] = {};
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static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
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{
	unsigned int *v;
	char *p, *q;

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	if (c->extended_cpuid_level < 0x80000004)
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		return;
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	v = (unsigned int *)c->x86_model_id;
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	cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
	cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
	cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
	c->x86_model_id[48] = 0;

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	/*
	 * Intel chips right-justify this string for some dumb reason;
	 * undo that brain damage:
	 */
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	p = q = &c->x86_model_id[0];
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	while (*p == ' ')
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		p++;
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	if (p != q) {
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		while (*p)
			*q++ = *p++;
		while (q <= &c->x86_model_id[48])
			*q++ = '\0';	/* Zero-pad the rest */
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	}
}

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void __cpuinit cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
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{
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	unsigned int n, dummy, ebx, ecx, edx, l2size;
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	n = c->extended_cpuid_level;
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	if (n >= 0x80000005) {
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		cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
		c->x86_cache_size = (ecx>>24) + (edx>>24);
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#ifdef CONFIG_X86_64
		/* On K8 L1 TLB is inclusive, so don't count it */
		c->x86_tlbsize = 0;
#endif
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	}

	if (n < 0x80000006)	/* Some chips just has a large L1. */
		return;

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	cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
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	l2size = ecx >> 16;
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#ifdef CONFIG_X86_64
	c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
#else
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	/* do processor-specific cache resizing */
	if (this_cpu->c_size_cache)
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		l2size = this_cpu->c_size_cache(c, l2size);
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	/* Allow user to override all this if necessary. */
	if (cachesize_override != -1)
		l2size = cachesize_override;

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	if (l2size == 0)
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		return;		/* Again, no L2 cache is possible */
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#endif
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	c->x86_cache_size = l2size;
}

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void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_HT
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	u32 eax, ebx, ecx, edx;
	int index_msb, core_bits;
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	static bool printed;
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	if (!cpu_has(c, X86_FEATURE_HT))
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		return;
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	if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
		goto out;
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	if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
		return;
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	cpuid(1, &eax, &ebx, &ecx, &edx);
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	smp_num_siblings = (ebx & 0xff0000) >> 16;

	if (smp_num_siblings == 1) {
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		printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
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		goto out;
	}
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	if (smp_num_siblings <= 1)
		goto out;
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	if (smp_num_siblings > nr_cpu_ids) {
		pr_warning("CPU: Unsupported number of siblings %d",
			   smp_num_siblings);
		smp_num_siblings = 1;
		return;
	}
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	index_msb = get_count_order(smp_num_siblings);
	c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
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	smp_num_siblings = smp_num_siblings / c->x86_max_cores;
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	index_msb = get_count_order(smp_num_siblings);
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	core_bits = get_count_order(c->x86_max_cores);
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	c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
				       ((1 << core_bits) - 1);
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out:
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	if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
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		printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
		       c->phys_proc_id);
		printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
		       c->cpu_core_id);
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		printed = 1;
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	}
#endif
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}
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static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
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{
	char *v = c->x86_vendor_id;
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	int i;
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	for (i = 0; i < X86_VENDOR_NUM; i++) {
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		if (!cpu_devs[i])
			break;

		if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
		    (cpu_devs[i]->c_ident[1] &&
		     !strcmp(v, cpu_devs[i]->c_ident[1]))) {
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			this_cpu = cpu_devs[i];
			c->x86_vendor = this_cpu->c_x86_vendor;
			return;
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		}
	}
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	printk_once(KERN_ERR
			"CPU: vendor_id '%s' unknown, using generic init.\n" \
			"CPU: Your system may be unstable.\n", v);
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	c->x86_vendor = X86_VENDOR_UNKNOWN;
	this_cpu = &default_cpu;
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}

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void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
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{
	/* Get vendor name */
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	cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
	      (unsigned int *)&c->x86_vendor_id[0],
	      (unsigned int *)&c->x86_vendor_id[8],
	      (unsigned int *)&c->x86_vendor_id[4]);
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	c->x86 = 4;
527
	/* Intel-defined flags: level 0x00000001 */
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	if (c->cpuid_level >= 0x00000001) {
		u32 junk, tfms, cap0, misc;
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		cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
532 533 534
		c->x86 = (tfms >> 8) & 0xf;
		c->x86_model = (tfms >> 4) & 0xf;
		c->x86_mask = tfms & 0xf;
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536
		if (c->x86 == 0xf)
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			c->x86 += (tfms >> 20) & 0xff;
538
		if (c->x86 >= 0x6)
539
			c->x86_model += ((tfms >> 16) & 0xf) << 4;
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		if (cap0 & (1<<19)) {
			c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
543
			c->x86_cache_alignment = c->x86_clflush_size;
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		}
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	}
}
547 548

static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
549 550
{
	u32 tfms, xlvl;
551
	u32 ebx;
552

553 554 555
	/* Intel-defined flags: level 0x00000001 */
	if (c->cpuid_level >= 0x00000001) {
		u32 capability, excap;
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557 558 559 560
		cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
		c->x86_capability[0] = capability;
		c->x86_capability[4] = excap;
	}
561

562 563 564 565 566 567 568 569 570 571
	/* Additional Intel-defined flags: level 0x00000007 */
	if (c->cpuid_level >= 0x00000007) {
		u32 eax, ebx, ecx, edx;

		cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);

		if (eax > 0)
			c->x86_capability[9] = ebx;
	}

572 573 574
	/* AMD-defined flags: level 0x80000001 */
	xlvl = cpuid_eax(0x80000000);
	c->extended_cpuid_level = xlvl;
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576 577 578 579
	if ((xlvl & 0xffff0000) == 0x80000000) {
		if (xlvl >= 0x80000001) {
			c->x86_capability[1] = cpuid_edx(0x80000001);
			c->x86_capability[6] = cpuid_ecx(0x80000001);
580 581 582
		}
	}

583 584 585 586 587
	if (c->extended_cpuid_level >= 0x80000008) {
		u32 eax = cpuid_eax(0x80000008);

		c->x86_virt_bits = (eax >> 8) & 0xff;
		c->x86_phys_bits = eax & 0xff;
588
	}
589 590 591
#ifdef CONFIG_X86_32
	else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
		c->x86_phys_bits = 36;
592
#endif
593 594 595

	if (c->extended_cpuid_level >= 0x80000007)
		c->x86_power = cpuid_edx(0x80000007);
596

597
	init_scattered_cpuid_features(c);
598
}
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static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
	int i;

	/*
	 * First of all, decide if this is a 486 or higher
	 * It's a 486 if we can modify the AC flag
	 */
	if (flag_is_changeable_p(X86_EFLAGS_AC))
		c->x86 = 4;
	else
		c->x86 = 3;

	for (i = 0; i < X86_VENDOR_NUM; i++)
		if (cpu_devs[i] && cpu_devs[i]->c_identify) {
			c->x86_vendor_id[0] = 0;
			cpu_devs[i]->c_identify(c);
			if (c->x86_vendor_id[0]) {
				get_cpu_vendor(c);
				break;
			}
		}
#endif
}

626 627 628 629 630 631 632 633 634
/*
 * Do minimum CPU detection early.
 * Fields really needed: vendor, cpuid_level, family, model, mask,
 * cache alignment.
 * The others are not touched to avoid unwanted side effects.
 *
 * WARNING: this function is only called on the BP.  Don't add code here
 * that is supposed to run on all CPUs.
 */
635
static void __init early_identify_cpu(struct cpuinfo_x86 *c)
636
{
637 638
#ifdef CONFIG_X86_64
	c->x86_clflush_size = 64;
639 640
	c->x86_phys_bits = 36;
	c->x86_virt_bits = 48;
641
#else
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	c->x86_clflush_size = 32;
643 644
	c->x86_phys_bits = 32;
	c->x86_virt_bits = 32;
645
#endif
646
	c->x86_cache_alignment = c->x86_clflush_size;
647

648
	memset(&c->x86_capability, 0, sizeof c->x86_capability);
649
	c->extended_cpuid_level = 0;
650

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	if (!have_cpuid_p())
		identify_cpu_without_cpuid(c);

	/* cyrix could have cpuid enabled via c_identify()*/
655 656 657 658 659
	if (!have_cpuid_p())
		return;

	cpu_detect(c);

660
	get_cpu_vendor(c);
661

662
	get_cpu_cap(c);
663

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	if (this_cpu->c_early_init)
		this_cpu->c_early_init(c);
666

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667
#ifdef CONFIG_SMP
668
	c->cpu_index = boot_cpu_id;
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#endif
670
	filter_cpuid_features(c, false);
671 672
}

673 674
void __init early_cpu_init(void)
{
675
	const struct cpu_dev *const *cdev;
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	int count = 0;

678
#ifdef PROCESSOR_SELECT
679
	printk(KERN_INFO "KERNEL supported cpus:\n");
680 681
#endif

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	for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
683
		const struct cpu_dev *cpudev = *cdev;
684

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		if (count >= X86_VENDOR_NUM)
			break;
		cpu_devs[count] = cpudev;
		count++;

690 691 692 693 694 695 696 697 698 699
#ifdef PROCESSOR_SELECT
		{
			unsigned int j;

			for (j = 0; j < 2; j++) {
				if (!cpudev->c_ident[j])
					continue;
				printk(KERN_INFO "  %s %s\n", cpudev->c_vendor,
					cpudev->c_ident[j]);
			}
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		}
701
#endif
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	}
703
	early_identify_cpu(&boot_cpu_data);
704
}
705

706 707
/*
 * The NOPL instruction is supposed to exist on all CPUs with
708
 * family >= 6; unfortunately, that's not true in practice because
709
 * of early VIA chips and (more importantly) broken virtualizers that
710 711 712
 * are not easy to detect.  In the latter case it doesn't even *fail*
 * reliably, so probing for it doesn't even work.  Disable it completely
 * unless we can find a reliable way to detect all the broken cases.
713 714 715 716
 */
static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
{
	clear_cpu_cap(c, X86_FEATURE_NOPL);
717 718
}

719
static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
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{
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721
	c->extended_cpuid_level = 0;
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723
	if (!have_cpuid_p())
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724
		identify_cpu_without_cpuid(c);
725

Y
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	/* cyrix could have cpuid enabled via c_identify()*/
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727
	if (!have_cpuid_p())
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		return;
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729

730
	cpu_detect(c);
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731

732
	get_cpu_vendor(c);
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733

734
	get_cpu_cap(c);
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735

736 737
	if (c->cpuid_level >= 0x00000001) {
		c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
738 739
#ifdef CONFIG_X86_32
# ifdef CONFIG_X86_HT
740
		c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
741
# else
742
		c->apicid = c->initial_apicid;
743 744
# endif
#endif
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746 747
#ifdef CONFIG_X86_HT
		c->phys_proc_id = c->initial_apicid;
748
#endif
749
	}
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751
	get_model_name(c); /* Default name */
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753
	detect_nopl(c);
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}

/*
 * This does the hard work of actually picking apart the CPU stuff...
 */
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static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
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{
	int i;

	c->loops_per_jiffy = loops_per_jiffy;
	c->x86_cache_size = -1;
	c->x86_vendor = X86_VENDOR_UNKNOWN;
	c->x86_model = c->x86_mask = 0;	/* So far unknown... */
	c->x86_vendor_id[0] = '\0'; /* Unset */
	c->x86_model_id[0] = '\0';  /* Unset */
769
	c->x86_max_cores = 1;
770
	c->x86_coreid_bits = 0;
771
#ifdef CONFIG_X86_64
772
	c->x86_clflush_size = 64;
773 774
	c->x86_phys_bits = 36;
	c->x86_virt_bits = 48;
775 776
#else
	c->cpuid_level = -1;	/* CPUID not detected */
777
	c->x86_clflush_size = 32;
778 779
	c->x86_phys_bits = 32;
	c->x86_virt_bits = 32;
780 781
#endif
	c->x86_cache_alignment = c->x86_clflush_size;
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	memset(&c->x86_capability, 0, sizeof c->x86_capability);

	generic_identify(c);

786
	if (this_cpu->c_identify)
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		this_cpu->c_identify(c);

789 790 791 792 793 794
	/* Clear/Set all flags overriden by options, after probe */
	for (i = 0; i < NCAPINTS; i++) {
		c->x86_capability[i] &= ~cpu_caps_cleared[i];
		c->x86_capability[i] |= cpu_caps_set[i];
	}

795
#ifdef CONFIG_X86_64
796
	c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
797 798
#endif

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	/*
	 * Vendor-specific initialization.  In this section we
	 * canonicalize the feature flags, meaning if there are
	 * features a certain CPU supports which CPUID doesn't
	 * tell us, CPUID claiming incorrect flags, or other bugs,
	 * we handle them here.
	 *
	 * At the end of this section, c->x86_capability better
	 * indicate the features this CPU genuinely supports!
	 */
	if (this_cpu->c_init)
		this_cpu->c_init(c);

	/* Disable the PN if appropriate */
	squash_the_stupid_serial_number(c);

	/*
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	 * The vendor-specific functions might have changed features.
	 * Now we do "generic changes."
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	 */

820 821 822
	/* Filter out anything that depends on CPUID levels we don't have */
	filter_cpuid_features(c, true);

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	/* If the model name is still unset, do table lookup. */
824
	if (!c->x86_model_id[0]) {
825
		const char *p;
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826
		p = table_lookup_model(c);
827
		if (p)
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			strcpy(c->x86_model_id, p);
		else
			/* Last resort... */
			sprintf(c->x86_model_id, "%02x/%02x",
832
				c->x86, c->x86_model);
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	}

835 836 837 838
#ifdef CONFIG_X86_64
	detect_ht(c);
#endif

839
	init_hypervisor(c);
840 841 842 843 844 845 846 847 848 849

	/*
	 * Clear/Set all flags overriden by options, need do it
	 * before following smp all cpus cap AND.
	 */
	for (i = 0; i < NCAPINTS; i++) {
		c->x86_capability[i] &= ~cpu_caps_cleared[i];
		c->x86_capability[i] |= cpu_caps_set[i];
	}

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	/*
	 * On SMP, boot_cpu_data holds the common feature set between
	 * all CPUs; so make sure that we indicate which features are
	 * common between the CPUs.  The first time this routine gets
	 * executed, c == &boot_cpu_data.
	 */
856
	if (c != &boot_cpu_data) {
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		/* AND the already accumulated flags with these */
858
		for (i = 0; i < NCAPINTS; i++)
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			boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
	}

	/* Init Machine Check Exception if available. */
863
	mcheck_cpu_init(c);
864 865

	select_idle_routine(c);
866 867 868 869

#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
	numa_add_cpu(smp_processor_id());
#endif
870
}
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872 873 874 875 876 877 878 879 880 881
#ifdef CONFIG_X86_64
static void vgetcpu_set_mode(void)
{
	if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
		vgetcpu_mode = VGETCPU_RDTSCP;
	else
		vgetcpu_mode = VGETCPU_LSL;
}
#endif

882 883 884
void __init identify_boot_cpu(void)
{
	identify_cpu(&boot_cpu_data);
885
	init_c1e_mask();
886
#ifdef CONFIG_X86_32
887
	sysenter_setup();
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	enable_sep_cpu();
889 890
#else
	vgetcpu_set_mode();
891
#endif
892
	init_hw_perf_events();
893
}
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895 896 897 898
void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
{
	BUG_ON(c == &boot_cpu_data);
	identify_cpu(c);
899
#ifdef CONFIG_X86_32
900
	enable_sep_cpu();
901
#endif
902
	mtrr_ap_init();
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}

905
struct msr_range {
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906 907
	unsigned	min;
	unsigned	max;
908
};
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910
static const struct msr_range msr_range_array[] __cpuinitconst = {
911 912 913 914 915
	{ 0x00000000, 0x00000418},
	{ 0xc0000000, 0xc000040b},
	{ 0xc0010000, 0xc0010142},
	{ 0xc0011000, 0xc001103b},
};
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917 918
static void __cpuinit print_cpu_msr(void)
{
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919
	unsigned index_min, index_max;
920 921 922 923 924 925 926
	unsigned index;
	u64 val;
	int i;

	for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
		index_min = msr_range_array[i].min;
		index_max = msr_range_array[i].max;
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927

928 929 930 931
		for (index = index_min; index < index_max; index++) {
			if (rdmsrl_amd_safe(index, &val))
				continue;
			printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
L
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932
		}
933 934
	}
}
935

936
static int show_msr __cpuinitdata;
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937

938 939 940
static __init int setup_show_msr(char *arg)
{
	int num;
941

942
	get_option(&arg, &num);
943

944 945 946
	if (num > 0)
		show_msr = num;
	return 1;
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}
948
__setup("show_msr=", setup_show_msr);
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static __init int setup_noclflush(char *arg)
{
	setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
	return 1;
}
__setup("noclflush", setup_noclflush);

957
void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
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958
{
959
	const char *vendor = NULL;
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960

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	if (c->x86_vendor < X86_VENDOR_NUM) {
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		vendor = this_cpu->c_vendor;
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963 964 965 966
	} else {
		if (c->cpuid_level >= 0)
			vendor = c->x86_vendor_id;
	}
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968
	if (vendor && !strstr(c->x86_model_id, vendor))
969
		printk(KERN_CONT "%s ", vendor);
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970

971 972
	if (c->x86_model_id[0])
		printk(KERN_CONT "%s", c->x86_model_id);
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973
	else
974
		printk(KERN_CONT "%d86", c->x86);
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975

976
	if (c->x86_mask || c->cpuid_level >= 0)
977
		printk(KERN_CONT " stepping %02x\n", c->x86_mask);
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	else
979
		printk(KERN_CONT "\n");
980 981 982 983 984 985 986 987

#ifdef CONFIG_SMP
	if (c->cpu_index < show_msr)
		print_cpu_msr();
#else
	if (show_msr)
		print_cpu_msr();
#endif
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988 989
}

990 991 992
static __init int setup_disablecpuid(char *arg)
{
	int bit;
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994 995 996 997
	if (get_option(&arg, &bit) && bit < NCAPINTS*32)
		setup_clear_cpu_cap(bit);
	else
		return 0;
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999 1000 1001 1002
	return 1;
}
__setup("clearcpuid=", setup_disablecpuid);

1003
#ifdef CONFIG_X86_64
1004
struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1005

1006 1007
DEFINE_PER_CPU_FIRST(union irq_stack_union,
		     irq_stack_union) __aligned(PAGE_SIZE);
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1009 1010 1011 1012 1013 1014 1015
/*
 * The following four percpu variables are hot.  Align current_task to
 * cacheline size such that all four fall in the same cacheline.
 */
DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
	&init_task;
EXPORT_PER_CPU_SYMBOL(current_task);
1016

1017 1018 1019 1020
DEFINE_PER_CPU(unsigned long, kernel_stack) =
	(unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
EXPORT_PER_CPU_SYMBOL(kernel_stack);

1021 1022 1023
DEFINE_PER_CPU(char *, irq_stack_ptr) =
	init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;

1024
DEFINE_PER_CPU(unsigned int, irq_count) = -1;
1025

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1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036
/*
 * Special IST stacks which the CPU switches to when it calls
 * an IST-marked descriptor entry. Up to 7 stacks (hardware
 * limit), all of them are 4K, except the debug stack which
 * is 8K.
 */
static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
	  [0 ... N_EXCEPTION_STACKS - 1]	= EXCEPTION_STKSZ,
	  [DEBUG_STACK - 1]			= DEBUG_STKSZ
};

1037
static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1038
	[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1039 1040 1041

/* May not be marked __init: used by software suspend */
void syscall_init(void)
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{
1043 1044 1045 1046 1047 1048 1049 1050
	/*
	 * LSTAR and STAR live in a bit strange symbiosis.
	 * They both write to the same internal register. STAR allows to
	 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
	 */
	wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
	wrmsrl(MSR_LSTAR, system_call);
	wrmsrl(MSR_CSTAR, ignore_sysret);
1051

1052 1053 1054
#ifdef CONFIG_IA32_EMULATION
	syscall32_cpu_init();
#endif
1055

1056 1057 1058
	/* Flags to clear on syscall */
	wrmsrl(MSR_SYSCALL_MASK,
	       X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
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1059
}
1060

1061 1062 1063 1064 1065 1066 1067 1068
unsigned long kernel_eflags;

/*
 * Copies of the original ist values from the tss are only accessed during
 * debugging, no special alignment required.
 */
DEFINE_PER_CPU(struct orig_ist, orig_ist);

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#else	/* CONFIG_X86_64 */
1070

1071 1072 1073
DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
EXPORT_PER_CPU_SYMBOL(current_task);

1074
#ifdef CONFIG_CC_STACKPROTECTOR
1075
DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1076
#endif
1077

1078
/* Make sure %fs and %gs are initialized properly in idle threads */
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struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
1080 1081
{
	memset(regs, 0, sizeof(struct pt_regs));
1082
	regs->fs = __KERNEL_PERCPU;
1083
	regs->gs = __KERNEL_STACK_CANARY;
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1085 1086
	return regs;
}
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#endif	/* CONFIG_X86_64 */
1088

1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103
/*
 * Clear all 6 debug registers:
 */
static void clear_all_debug_regs(void)
{
	int i;

	for (i = 0; i < 8; i++) {
		/* Ignore db4, db5 */
		if ((i == 4) || (i == 5))
			continue;

		set_debugreg(0, i);
	}
}
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1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118
#ifdef CONFIG_KGDB
/*
 * Restore debug regs if using kgdbwait and you have a kernel debugger
 * connection established.
 */
static void dbg_restore_debug_regs(void)
{
	if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
		arch_kgdb_ops.correct_hw_break();
}
#else /* ! CONFIG_KGDB */
#define dbg_restore_debug_regs()
#endif /* ! CONFIG_KGDB */

1119 1120 1121 1122 1123
/*
 * cpu_init() initializes state that is per-CPU. Some data is already
 * initialized (naturally) in the bootstrap process, such as the GDT
 * and IDT. We reload them nevertheless, this function acts as a
 * 'CPU state barrier', nothing should get across.
1124
 * A lot of state is already set up in PDA init for 64 bit
1125
 */
1126
#ifdef CONFIG_X86_64
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1128 1129
void __cpuinit cpu_init(void)
{
1130
	struct orig_ist *oist;
1131
	struct task_struct *me;
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	struct tss_struct *t;
	unsigned long v;
	int cpu;
1135 1136
	int i;

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	cpu = stack_smp_processor_id();
	t = &per_cpu(init_tss, cpu);
1139
	oist = &per_cpu(orig_ist, cpu);
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1141
#ifdef CONFIG_NUMA
1142 1143 1144
	if (cpu != 0 && percpu_read(numa_node) == 0 &&
	    early_cpu_to_node(cpu) != NUMA_NO_NODE)
		set_numa_node(early_cpu_to_node(cpu));
1145
#endif
1146 1147 1148

	me = current;

1149
	if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1150 1151
		panic("CPU#%d already initialized!\n", cpu);

1152
	pr_debug("Initializing CPU#%d\n", cpu);
1153 1154 1155 1156 1157 1158 1159 1160

	clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);

	/*
	 * Initialize the per-CPU GDT with the boot GDT,
	 * and set up the GDT descriptor:
	 */

1161
	switch_to_new_gdt(cpu);
1162 1163
	loadsegment(fs, 0);

1164 1165 1166 1167 1168 1169 1170 1171 1172
	load_idt((const struct desc_ptr *)&idt_descr);

	memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
	syscall_init();

	wrmsrl(MSR_FS_BASE, 0);
	wrmsrl(MSR_KERNEL_GS_BASE, 0);
	barrier();

1173
	x86_configure_nx();
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	if (cpu != 0)
1175 1176 1177 1178 1179
		enable_x2apic();

	/*
	 * set up and load the per-CPU TSS
	 */
1180
	if (!oist->ist[0]) {
1181
		char *estacks = per_cpu(exception_stacks, cpu);
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1183
		for (v = 0; v < N_EXCEPTION_STACKS; v++) {
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			estacks += exception_stack_sizes[v];
1185
			oist->ist[v] = t->x86_tss.ist[v] =
1186 1187 1188 1189 1190
					(unsigned long)estacks;
		}
	}

	t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
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1192 1193 1194 1195 1196 1197 1198 1199 1200
	/*
	 * <= is required because the CPU will access up to
	 * 8 bits beyond the end of the IO permission bitmap.
	 */
	for (i = 0; i <= IO_BITMAP_LONGS; i++)
		t->io_bitmap[i] = ~0UL;

	atomic_inc(&init_mm.mm_count);
	me->active_mm = &init_mm;
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	BUG_ON(me->mm);
1202 1203 1204 1205 1206 1207 1208
	enter_lazy_tlb(&init_mm, me);

	load_sp0(t, &current->thread);
	set_tss_desc(cpu, t);
	load_TR_desc();
	load_LDT(&init_mm.context);

1209 1210
	clear_all_debug_regs();
	dbg_restore_debug_regs();
1211 1212

	fpu_init();
1213
	xsave_init();
1214 1215 1216 1217 1218 1219 1220 1221 1222

	raw_local_save_flags(kernel_eflags);

	if (is_uv_system())
		uv_cpu_init();
}

#else

1223
void __cpuinit cpu_init(void)
1224
{
1225 1226
	int cpu = smp_processor_id();
	struct task_struct *curr = current;
1227
	struct tss_struct *t = &per_cpu(init_tss, cpu);
1228
	struct thread_struct *thread = &curr->thread;
1229

1230
	if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1231
		printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1232 1233
		for (;;)
			local_irq_enable();
1234 1235 1236 1237 1238 1239 1240
	}

	printk(KERN_INFO "Initializing CPU#%d\n", cpu);

	if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
		clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);

1241
	load_idt(&idt_descr);
1242
	switch_to_new_gdt(cpu);
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	/*
	 * Set up and load the per-CPU TSS and LDT
	 */
	atomic_inc(&init_mm.mm_count);
1248
	curr->active_mm = &init_mm;
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	BUG_ON(curr->mm);
1250
	enter_lazy_tlb(&init_mm, curr);
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1252
	load_sp0(t, thread);
1253
	set_tss_desc(cpu, t);
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	load_TR_desc();
	load_LDT(&init_mm.context);

1257 1258
	t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);

1259
#ifdef CONFIG_DOUBLEFAULT
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	/* Set up doublefault TSS pointer in the GDT */
	__set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1262
#endif
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1264
	clear_all_debug_regs();
1265
	dbg_restore_debug_regs();
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	/*
	 * Force FPU initialization:
	 */
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	current_thread_info()->status = 0;
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	clear_used_math();
	mxcsr_feature_mask_init();
1273

1274
	fpu_init();
1275
	xsave_init();
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}
1277
#endif