common.c 26.7 KB
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#include <linux/init.h>
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#include <linux/kernel.h>
#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/bootmem.h>
#include <linux/bitops.h>
#include <linux/module.h>
#include <linux/kgdb.h>
#include <linux/topology.h>
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#include <linux/delay.h>
#include <linux/smp.h>
#include <linux/percpu.h>
#include <asm/i387.h>
#include <asm/msr.h>
#include <asm/io.h>
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#include <asm/linkage.h>
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#include <asm/mmu_context.h>
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#include <asm/mtrr.h>
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#include <asm/mce.h>
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#include <asm/pat.h>
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#include <asm/asm.h>
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#include <asm/numa.h>
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#ifdef CONFIG_X86_LOCAL_APIC
#include <asm/mpspec.h>
#include <asm/apic.h>
#include <mach_apic.h>
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#include <asm/genapic.h>
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#endif

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#include <asm/pda.h>
#include <asm/pgtable.h>
#include <asm/processor.h>
#include <asm/desc.h>
#include <asm/atomic.h>
#include <asm/proto.h>
#include <asm/sections.h>
#include <asm/setup.h>

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#include "cpu.h"

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static struct cpu_dev *this_cpu __cpuinitdata;

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#ifdef CONFIG_X86_64
/* We need valid kernel segments for data and code in long mode too
 * IRET will check the segment types  kkeil 2000/10/28
 * Also sysret mandates a special GDT layout
 */
/* The TLS descriptors are currently at a different place compared to i386.
   Hopefully nobody expects them at a fixed place (Wine?) */
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DEFINE_PER_CPU(struct gdt_page, gdt_page) = { .gdt = {
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	[GDT_ENTRY_KERNEL32_CS] = { { { 0x0000ffff, 0x00cf9b00 } } },
	[GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00af9b00 } } },
	[GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9300 } } },
	[GDT_ENTRY_DEFAULT_USER32_CS] = { { { 0x0000ffff, 0x00cffb00 } } },
	[GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff300 } } },
	[GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00affb00 } } },
} };
#else
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DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
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	[GDT_ENTRY_KERNEL_CS] = { { { 0x0000ffff, 0x00cf9a00 } } },
	[GDT_ENTRY_KERNEL_DS] = { { { 0x0000ffff, 0x00cf9200 } } },
	[GDT_ENTRY_DEFAULT_USER_CS] = { { { 0x0000ffff, 0x00cffa00 } } },
	[GDT_ENTRY_DEFAULT_USER_DS] = { { { 0x0000ffff, 0x00cff200 } } },
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	/*
	 * Segments used for calling PnP BIOS have byte granularity.
	 * They code segments and data segments have fixed 64k limits,
	 * the transfer segment sizes are set at run time.
	 */
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	/* 32-bit code */
	[GDT_ENTRY_PNPBIOS_CS32] = { { { 0x0000ffff, 0x00409a00 } } },
	/* 16-bit code */
	[GDT_ENTRY_PNPBIOS_CS16] = { { { 0x0000ffff, 0x00009a00 } } },
	/* 16-bit data */
	[GDT_ENTRY_PNPBIOS_DS] = { { { 0x0000ffff, 0x00009200 } } },
	/* 16-bit data */
	[GDT_ENTRY_PNPBIOS_TS1] = { { { 0x00000000, 0x00009200 } } },
	/* 16-bit data */
	[GDT_ENTRY_PNPBIOS_TS2] = { { { 0x00000000, 0x00009200 } } },
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	/*
	 * The APM segments have byte granularity and their bases
	 * are set at run time.  All have 64k limits.
	 */
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	/* 32-bit code */
	[GDT_ENTRY_APMBIOS_BASE] = { { { 0x0000ffff, 0x00409a00 } } },
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	/* 16-bit code */
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	[GDT_ENTRY_APMBIOS_BASE+1] = { { { 0x0000ffff, 0x00009a00 } } },
	/* data */
	[GDT_ENTRY_APMBIOS_BASE+2] = { { { 0x0000ffff, 0x00409200 } } },
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	[GDT_ENTRY_ESPFIX_SS] = { { { 0x00000000, 0x00c09200 } } },
	[GDT_ENTRY_PERCPU] = { { { 0x00000000, 0x00000000 } } },
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} };
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#endif
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EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
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#ifdef CONFIG_X86_32
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static int cachesize_override __cpuinitdata = -1;
static int disable_x86_serial_nr __cpuinitdata = 1;
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static int __init cachesize_setup(char *str)
{
	get_option(&str, &cachesize_override);
	return 1;
}
__setup("cachesize=", cachesize_setup);

static int __init x86_fxsr_setup(char *s)
{
	setup_clear_cpu_cap(X86_FEATURE_FXSR);
	setup_clear_cpu_cap(X86_FEATURE_XMM);
	return 1;
}
__setup("nofxsr", x86_fxsr_setup);

static int __init x86_sep_setup(char *s)
{
	setup_clear_cpu_cap(X86_FEATURE_SEP);
	return 1;
}
__setup("nosep", x86_sep_setup);

/* Standard macro to see if a specific flag is changeable */
static inline int flag_is_changeable_p(u32 flag)
{
	u32 f1, f2;

	asm("pushfl\n\t"
	    "pushfl\n\t"
	    "popl %0\n\t"
	    "movl %0,%1\n\t"
	    "xorl %2,%0\n\t"
	    "pushl %0\n\t"
	    "popfl\n\t"
	    "pushfl\n\t"
	    "popl %0\n\t"
	    "popfl\n\t"
	    : "=&r" (f1), "=&r" (f2)
	    : "ir" (flag));

	return ((f1^f2) & flag) != 0;
}

/* Probe for the CPUID instruction */
static int __cpuinit have_cpuid_p(void)
{
	return flag_is_changeable_p(X86_EFLAGS_ID);
}

static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
{
	if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr) {
		/* Disable processor serial number */
		unsigned long lo, hi;
		rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
		lo |= 0x200000;
		wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
		printk(KERN_NOTICE "CPU serial number disabled.\n");
		clear_cpu_cap(c, X86_FEATURE_PN);

		/* Disabling the serial number may affect the cpuid level */
		c->cpuid_level = cpuid_eax(0);
	}
}

static int __init x86_serial_nr_setup(char *s)
{
	disable_x86_serial_nr = 0;
	return 1;
}
__setup("serialnumber", x86_serial_nr_setup);
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#else
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static inline int flag_is_changeable_p(u32 flag)
{
	return 1;
}
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/* Probe for the CPUID instruction */
static inline int have_cpuid_p(void)
{
	return 1;
}
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static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
{
}
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#endif
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/*
 * Naming convention should be: <Name> [(<Codename>)]
 * This table only is used unless init_<vendor>() below doesn't set it;
 * in particular, if CPUID levels 0x80000002..4 are supported, this isn't used
 *
 */

/* Look up CPU names by table lookup. */
static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
{
	struct cpu_model_info *info;

	if (c->x86_model >= 16)
		return NULL;	/* Range check */

	if (!this_cpu)
		return NULL;

	info = this_cpu->c_models;

	while (info && info->family) {
		if (info->family == c->x86)
			return info->model_names[c->x86_model];
		info++;
	}
	return NULL;		/* Not found */
}

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__u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;

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/* Current gdt points %fs at the "master" per-cpu area: after this,
 * it's on the real one. */
void switch_to_new_gdt(void)
{
	struct desc_ptr gdt_descr;

	gdt_descr.address = (long)get_cpu_gdt_table(smp_processor_id());
	gdt_descr.size = GDT_SIZE - 1;
	load_gdt(&gdt_descr);
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#ifdef CONFIG_X86_32
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	asm("mov %0, %%fs" : : "r" (__KERNEL_PERCPU) : "memory");
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#endif
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}

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static struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
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static void __cpuinit default_init(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_64
	display_cacheinfo(c);
#else
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	/* Not much we can do here... */
	/* Check if at least it has cpuid */
	if (c->cpuid_level == -1) {
		/* No cpuid. It must be an ancient CPU */
		if (c->x86 == 4)
			strcpy(c->x86_model_id, "486");
		else if (c->x86 == 3)
			strcpy(c->x86_model_id, "386");
	}
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#endif
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}

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static struct cpu_dev __cpuinitdata default_cpu = {
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	.c_init	= default_init,
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	.c_vendor = "Unknown",
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	.c_x86_vendor = X86_VENDOR_UNKNOWN,
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};

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static void __cpuinit get_model_name(struct cpuinfo_x86 *c)
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{
	unsigned int *v;
	char *p, *q;

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	if (c->extended_cpuid_level < 0x80000004)
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		return;
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	v = (unsigned int *) c->x86_model_id;
	cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
	cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
	cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
	c->x86_model_id[48] = 0;

	/* Intel chips right-justify this string for some dumb reason;
	   undo that brain damage */
	p = q = &c->x86_model_id[0];
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	while (*p == ' ')
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	     p++;
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	if (p != q) {
	     while (*p)
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		  *q++ = *p++;
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	     while (q <= &c->x86_model_id[48])
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		  *q++ = '\0';	/* Zero-pad the rest */
	}
}

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void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
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{
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	unsigned int n, dummy, ebx, ecx, edx, l2size;
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	n = c->extended_cpuid_level;
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	if (n >= 0x80000005) {
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		cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
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		printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
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				edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
		c->x86_cache_size = (ecx>>24) + (edx>>24);
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#ifdef CONFIG_X86_64
		/* On K8 L1 TLB is inclusive, so don't count it */
		c->x86_tlbsize = 0;
#endif
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	}

	if (n < 0x80000006)	/* Some chips just has a large L1. */
		return;

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	cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
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	l2size = ecx >> 16;
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#ifdef CONFIG_X86_64
	c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
#else
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	/* do processor-specific cache resizing */
	if (this_cpu->c_size_cache)
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		l2size = this_cpu->c_size_cache(c, l2size);
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	/* Allow user to override all this if necessary. */
	if (cachesize_override != -1)
		l2size = cachesize_override;

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	if (l2size == 0)
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		return;		/* Again, no L2 cache is possible */
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#endif
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	c->x86_cache_size = l2size;

	printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
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			l2size, ecx & 0xFF);
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}

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void __cpuinit detect_ht(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_HT
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	u32 eax, ebx, ecx, edx;
	int index_msb, core_bits;
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	if (!cpu_has(c, X86_FEATURE_HT))
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		return;
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	if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
		goto out;
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	if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
		return;
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	cpuid(1, &eax, &ebx, &ecx, &edx);
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	smp_num_siblings = (ebx & 0xff0000) >> 16;

	if (smp_num_siblings == 1) {
		printk(KERN_INFO  "CPU: Hyper-Threading is disabled\n");
	} else if (smp_num_siblings > 1) {

		if (smp_num_siblings > NR_CPUS) {
			printk(KERN_WARNING "CPU: Unsupported number of siblings %d",
					smp_num_siblings);
			smp_num_siblings = 1;
			return;
		}

		index_msb = get_count_order(smp_num_siblings);
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#ifdef CONFIG_X86_64
		c->phys_proc_id = phys_pkg_id(index_msb);
#else
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		c->phys_proc_id = phys_pkg_id(c->initial_apicid, index_msb);
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#endif
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		smp_num_siblings = smp_num_siblings / c->x86_max_cores;

		index_msb = get_count_order(smp_num_siblings);

		core_bits = get_count_order(c->x86_max_cores);

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#ifdef CONFIG_X86_64
		c->cpu_core_id = phys_pkg_id(index_msb) &
					       ((1 << core_bits) - 1);
#else
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		c->cpu_core_id = phys_pkg_id(c->initial_apicid, index_msb) &
					       ((1 << core_bits) - 1);
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#endif
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	}

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out:
	if ((c->x86_max_cores * smp_num_siblings) > 1) {
		printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
		       c->phys_proc_id);
		printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
		       c->cpu_core_id);
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	}
#endif
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}
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static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
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{
	char *v = c->x86_vendor_id;
	int i;
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	static int printed;
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	for (i = 0; i < X86_VENDOR_NUM; i++) {
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		if (!cpu_devs[i])
			break;

		if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
		    (cpu_devs[i]->c_ident[1] &&
		     !strcmp(v, cpu_devs[i]->c_ident[1]))) {
			this_cpu = cpu_devs[i];
			c->x86_vendor = this_cpu->c_x86_vendor;
			return;
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		}
	}
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	if (!printed) {
		printed++;
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		printk(KERN_ERR "CPU: vendor_id '%s' unknown, using generic init.\n", v);
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		printk(KERN_ERR "CPU: Your system may be unstable.\n");
	}
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	c->x86_vendor = X86_VENDOR_UNKNOWN;
	this_cpu = &default_cpu;
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}

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void __cpuinit cpu_detect(struct cpuinfo_x86 *c)
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{
	/* Get vendor name */
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	cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
	      (unsigned int *)&c->x86_vendor_id[0],
	      (unsigned int *)&c->x86_vendor_id[8],
	      (unsigned int *)&c->x86_vendor_id[4]);
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	c->x86 = 4;
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	/* Intel-defined flags: level 0x00000001 */
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	if (c->cpuid_level >= 0x00000001) {
		u32 junk, tfms, cap0, misc;
		cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
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		c->x86 = (tfms >> 8) & 0xf;
		c->x86_model = (tfms >> 4) & 0xf;
		c->x86_mask = tfms & 0xf;
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		if (c->x86 == 0xf)
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			c->x86 += (tfms >> 20) & 0xff;
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		if (c->x86 >= 0x6)
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			c->x86_model += ((tfms >> 16) & 0xf) << 4;
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		if (cap0 & (1<<19)) {
			c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
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			c->x86_cache_alignment = c->x86_clflush_size;
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		}
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	}
}
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static void __cpuinit get_cpu_cap(struct cpuinfo_x86 *c)
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{
	u32 tfms, xlvl;
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	u32 ebx;
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	/* Intel-defined flags: level 0x00000001 */
	if (c->cpuid_level >= 0x00000001) {
		u32 capability, excap;
		cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
		c->x86_capability[0] = capability;
		c->x86_capability[4] = excap;
	}
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	/* AMD-defined flags: level 0x80000001 */
	xlvl = cpuid_eax(0x80000000);
	c->extended_cpuid_level = xlvl;
	if ((xlvl & 0xffff0000) == 0x80000000) {
		if (xlvl >= 0x80000001) {
			c->x86_capability[1] = cpuid_edx(0x80000001);
			c->x86_capability[6] = cpuid_ecx(0x80000001);
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		}
	}

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#ifdef CONFIG_X86_64
	if (c->extended_cpuid_level >= 0x80000008) {
		u32 eax = cpuid_eax(0x80000008);

		c->x86_virt_bits = (eax >> 8) & 0xff;
		c->x86_phys_bits = eax & 0xff;
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	}
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#endif
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	if (c->extended_cpuid_level >= 0x80000007)
		c->x86_power = cpuid_edx(0x80000007);
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}
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static void __cpuinit identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
{
#ifdef CONFIG_X86_32
	int i;

	/*
	 * First of all, decide if this is a 486 or higher
	 * It's a 486 if we can modify the AC flag
	 */
	if (flag_is_changeable_p(X86_EFLAGS_AC))
		c->x86 = 4;
	else
		c->x86 = 3;

	for (i = 0; i < X86_VENDOR_NUM; i++)
		if (cpu_devs[i] && cpu_devs[i]->c_identify) {
			c->x86_vendor_id[0] = 0;
			cpu_devs[i]->c_identify(c);
			if (c->x86_vendor_id[0]) {
				get_cpu_vendor(c);
				break;
			}
		}
#endif
}

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/*
 * Do minimum CPU detection early.
 * Fields really needed: vendor, cpuid_level, family, model, mask,
 * cache alignment.
 * The others are not touched to avoid unwanted side effects.
 *
 * WARNING: this function is only called on the BP.  Don't add code here
 * that is supposed to run on all CPUs.
 */
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static void __init early_identify_cpu(struct cpuinfo_x86 *c)
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{
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#ifdef CONFIG_X86_64
	c->x86_clflush_size = 64;
#else
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	c->x86_clflush_size = 32;
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#endif
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	c->x86_cache_alignment = c->x86_clflush_size;
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	memset(&c->x86_capability, 0, sizeof c->x86_capability);
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	c->extended_cpuid_level = 0;
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	if (!have_cpuid_p())
		identify_cpu_without_cpuid(c);

	/* cyrix could have cpuid enabled via c_identify()*/
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	if (!have_cpuid_p())
		return;

	cpu_detect(c);

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	get_cpu_vendor(c);
538

539
	get_cpu_cap(c);
540

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	if (this_cpu->c_early_init)
		this_cpu->c_early_init(c);
543

544
	validate_pat_support(c);
545 546
}

547 548
void __init early_cpu_init(void)
{
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	struct cpu_dev **cdev;
	int count = 0;

	printk("KERNEL supported cpus:\n");
	for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
		struct cpu_dev *cpudev = *cdev;
		unsigned int j;
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		if (count >= X86_VENDOR_NUM)
			break;
		cpu_devs[count] = cpudev;
		count++;

		for (j = 0; j < 2; j++) {
			if (!cpudev->c_ident[j])
				continue;
			printk("  %s %s\n", cpudev->c_vendor,
				cpudev->c_ident[j]);
		}
	}
569 570

	early_identify_cpu(&boot_cpu_data);
571
}
572

573 574
/*
 * The NOPL instruction is supposed to exist on all CPUs with
575
 * family >= 6; unfortunately, that's not true in practice because
576
 * of early VIA chips and (more importantly) broken virtualizers that
577 578 579
 * are not easy to detect.  In the latter case it doesn't even *fail*
 * reliably, so probing for it doesn't even work.  Disable it completely
 * unless we can find a reliable way to detect all the broken cases.
580 581 582 583
 */
static void __cpuinit detect_nopl(struct cpuinfo_x86 *c)
{
	clear_cpu_cap(c, X86_FEATURE_NOPL);
584 585
}

586
static void __cpuinit generic_identify(struct cpuinfo_x86 *c)
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{
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	c->extended_cpuid_level = 0;
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590
	if (!have_cpuid_p())
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		identify_cpu_without_cpuid(c);
592

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	/* cyrix could have cpuid enabled via c_identify()*/
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	if (!have_cpuid_p())
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		return;
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597
	cpu_detect(c);
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599
	get_cpu_vendor(c);
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601
	get_cpu_cap(c);
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603 604
	if (c->cpuid_level >= 0x00000001) {
		c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
605 606
#ifdef CONFIG_X86_32
# ifdef CONFIG_X86_HT
607
		c->apicid = phys_pkg_id(c->initial_apicid, 0);
608
# else
609
		c->apicid = c->initial_apicid;
610 611
# endif
#endif
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613 614
#ifdef CONFIG_X86_HT
		c->phys_proc_id = c->initial_apicid;
615
#endif
616
	}
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618
	get_model_name(c); /* Default name */
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620 621
	init_scattered_cpuid_features(c);
	detect_nopl(c);
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}

/*
 * This does the hard work of actually picking apart the CPU stuff...
 */
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static void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
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{
	int i;

	c->loops_per_jiffy = loops_per_jiffy;
	c->x86_cache_size = -1;
	c->x86_vendor = X86_VENDOR_UNKNOWN;
	c->x86_model = c->x86_mask = 0;	/* So far unknown... */
	c->x86_vendor_id[0] = '\0'; /* Unset */
	c->x86_model_id[0] = '\0';  /* Unset */
637
	c->x86_max_cores = 1;
638
	c->x86_coreid_bits = 0;
639
#ifdef CONFIG_X86_64
640 641 642
	c->x86_clflush_size = 64;
#else
	c->cpuid_level = -1;	/* CPUID not detected */
643
	c->x86_clflush_size = 32;
644 645
#endif
	c->x86_cache_alignment = c->x86_clflush_size;
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	memset(&c->x86_capability, 0, sizeof c->x86_capability);

	generic_identify(c);

650
	if (this_cpu->c_identify)
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		this_cpu->c_identify(c);

653 654 655 656
#ifdef CONFIG_X86_64
	c->apicid = phys_pkg_id(0);
#endif

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	/*
	 * Vendor-specific initialization.  In this section we
	 * canonicalize the feature flags, meaning if there are
	 * features a certain CPU supports which CPUID doesn't
	 * tell us, CPUID claiming incorrect flags, or other bugs,
	 * we handle them here.
	 *
	 * At the end of this section, c->x86_capability better
	 * indicate the features this CPU genuinely supports!
	 */
	if (this_cpu->c_init)
		this_cpu->c_init(c);

	/* Disable the PN if appropriate */
	squash_the_stupid_serial_number(c);

	/*
	 * The vendor-specific functions might have changed features.  Now
	 * we do "generic changes."
	 */

	/* If the model name is still unset, do table lookup. */
679
	if (!c->x86_model_id[0]) {
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		char *p;
		p = table_lookup_model(c);
682
		if (p)
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			strcpy(c->x86_model_id, p);
		else
			/* Last resort... */
			sprintf(c->x86_model_id, "%02x/%02x",
687
				c->x86, c->x86_model);
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	}

690 691 692 693
#ifdef CONFIG_X86_64
	detect_ht(c);
#endif

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	/*
	 * On SMP, boot_cpu_data holds the common feature set between
	 * all CPUs; so make sure that we indicate which features are
	 * common between the CPUs.  The first time this routine gets
	 * executed, c == &boot_cpu_data.
	 */
700
	if (c != &boot_cpu_data) {
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		/* AND the already accumulated flags with these */
702
		for (i = 0; i < NCAPINTS; i++)
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			boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
	}

706 707
	/* Clear all flags overriden by options */
	for (i = 0; i < NCAPINTS; i++)
708
		c->x86_capability[i] &= ~cleared_cpu_caps[i];
709

710
#ifdef CONFIG_X86_MCE
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	/* Init Machine Check Exception if available. */
	mcheck_init(c);
713
#endif
714 715

	select_idle_routine(c);
716 717 718 719

#if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
	numa_add_cpu(smp_processor_id());
#endif
720
}
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#ifdef CONFIG_X86_64
static void vgetcpu_set_mode(void)
{
	if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
		vgetcpu_mode = VGETCPU_RDTSCP;
	else
		vgetcpu_mode = VGETCPU_LSL;
}
#endif

732 733 734
void __init identify_boot_cpu(void)
{
	identify_cpu(&boot_cpu_data);
735
#ifdef CONFIG_X86_32
736
	sysenter_setup();
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	enable_sep_cpu();
738 739
#else
	vgetcpu_set_mode();
740
#endif
741
}
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743 744 745 746
void __cpuinit identify_secondary_cpu(struct cpuinfo_x86 *c)
{
	BUG_ON(c == &boot_cpu_data);
	identify_cpu(c);
747
#ifdef CONFIG_X86_32
748
	enable_sep_cpu();
749
#endif
750
	mtrr_ap_init();
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}

753 754 755 756
struct msr_range {
	unsigned min;
	unsigned max;
};
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758 759 760 761 762 763
static struct msr_range msr_range_array[] __cpuinitdata = {
	{ 0x00000000, 0x00000418},
	{ 0xc0000000, 0xc000040b},
	{ 0xc0010000, 0xc0010142},
	{ 0xc0011000, 0xc001103b},
};
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static void __cpuinit print_cpu_msr(void)
{
	unsigned index;
	u64 val;
	int i;
	unsigned index_min, index_max;

	for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
		index_min = msr_range_array[i].min;
		index_max = msr_range_array[i].max;
		for (index = index_min; index < index_max; index++) {
			if (rdmsrl_amd_safe(index, &val))
				continue;
			printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
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		}
780 781
	}
}
782

783 784 785 786
static int show_msr __cpuinitdata;
static __init int setup_show_msr(char *arg)
{
	int num;
787

788
	get_option(&arg, &num);
789

790 791 792
	if (num > 0)
		show_msr = num;
	return 1;
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}
794
__setup("show_msr=", setup_show_msr);
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static __init int setup_noclflush(char *arg)
{
	setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
	return 1;
}
__setup("noclflush", setup_noclflush);

803
void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
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{
	char *vendor = NULL;

	if (c->x86_vendor < X86_VENDOR_NUM)
		vendor = this_cpu->c_vendor;
	else if (c->cpuid_level >= 0)
		vendor = c->x86_vendor_id;

812
	if (vendor && !strstr(c->x86_model_id, vendor))
813
		printk(KERN_CONT "%s ", vendor);
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815 816
	if (c->x86_model_id[0])
		printk(KERN_CONT "%s", c->x86_model_id);
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	else
818
		printk(KERN_CONT "%d86", c->x86);
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820
	if (c->x86_mask || c->cpuid_level >= 0)
821
		printk(KERN_CONT " stepping %02x\n", c->x86_mask);
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	else
823
		printk(KERN_CONT "\n");
824 825 826 827 828 829 830 831

#ifdef CONFIG_SMP
	if (c->cpu_index < show_msr)
		print_cpu_msr();
#else
	if (show_msr)
		print_cpu_msr();
#endif
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}

834 835 836 837 838 839 840 841 842 843 844
static __init int setup_disablecpuid(char *arg)
{
	int bit;
	if (get_option(&arg, &bit) && bit < NCAPINTS*32)
		setup_clear_cpu_cap(bit);
	else
		return 0;
	return 1;
}
__setup("clearcpuid=", setup_disablecpuid);

845
cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
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847 848 849 850 851 852 853 854
#ifdef CONFIG_X86_64
struct x8664_pda **_cpu_pda __read_mostly;
EXPORT_SYMBOL(_cpu_pda);

struct desc_ptr idt_descr = { 256 * 16 - 1, (unsigned long) idt_table };

char boot_cpu_stack[IRQSTACKSIZE] __page_aligned_bss;

855
void __cpuinit pda_init(int cpu)
856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896 897 898 899 900
{
	struct x8664_pda *pda = cpu_pda(cpu);

	/* Setup up data that may be needed in __get_free_pages early */
	loadsegment(fs, 0);
	loadsegment(gs, 0);
	/* Memory clobbers used to order PDA accessed */
	mb();
	wrmsrl(MSR_GS_BASE, pda);
	mb();

	pda->cpunumber = cpu;
	pda->irqcount = -1;
	pda->kernelstack = (unsigned long)stack_thread_info() -
				 PDA_STACKOFFSET + THREAD_SIZE;
	pda->active_mm = &init_mm;
	pda->mmu_state = 0;

	if (cpu == 0) {
		/* others are initialized in smpboot.c */
		pda->pcurrent = &init_task;
		pda->irqstackptr = boot_cpu_stack;
		pda->irqstackptr += IRQSTACKSIZE - 64;
	} else {
		if (!pda->irqstackptr) {
			pda->irqstackptr = (char *)
				__get_free_pages(GFP_ATOMIC, IRQSTACK_ORDER);
			if (!pda->irqstackptr)
				panic("cannot allocate irqstack for cpu %d",
				      cpu);
			pda->irqstackptr += IRQSTACKSIZE - 64;
		}

		if (pda->nodenumber == 0 && cpu_to_node(cpu) != NUMA_NO_NODE)
			pda->nodenumber = cpu_to_node(cpu);
	}
}

char boot_exception_stacks[(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ +
			   DEBUG_STKSZ] __page_aligned_bss;

extern asmlinkage void ignore_sysret(void);

/* May not be marked __init: used by software suspend */
void syscall_init(void)
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{
902 903 904 905 906 907 908 909
	/*
	 * LSTAR and STAR live in a bit strange symbiosis.
	 * They both write to the same internal register. STAR allows to
	 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
	 */
	wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
	wrmsrl(MSR_LSTAR, system_call);
	wrmsrl(MSR_CSTAR, ignore_sysret);
910

911 912 913
#ifdef CONFIG_IA32_EMULATION
	syscall32_cpu_init();
#endif
914

915 916 917
	/* Flags to clear on syscall */
	wrmsrl(MSR_SYSCALL_MASK,
	       X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|X86_EFLAGS_IOPL);
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}
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920 921 922 923 924 925 926 927 928 929
unsigned long kernel_eflags;

/*
 * Copies of the original ist values from the tss are only accessed during
 * debugging, no special alignment required.
 */
DEFINE_PER_CPU(struct orig_ist, orig_ist);

#else

930
/* Make sure %fs is initialized properly in idle threads */
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struct pt_regs * __cpuinit idle_regs(struct pt_regs *regs)
932 933
{
	memset(regs, 0, sizeof(struct pt_regs));
934
	regs->fs = __KERNEL_PERCPU;
935 936
	return regs;
}
937
#endif
938

939 940 941 942 943
/*
 * cpu_init() initializes state that is per-CPU. Some data is already
 * initialized (naturally) in the bootstrap process, such as the GDT
 * and IDT. We reload them nevertheless, this function acts as a
 * 'CPU state barrier', nothing should get across.
944
 * A lot of state is already set up in PDA init for 64 bit
945
 */
946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066
#ifdef CONFIG_X86_64
void __cpuinit cpu_init(void)
{
	int cpu = stack_smp_processor_id();
	struct tss_struct *t = &per_cpu(init_tss, cpu);
	struct orig_ist *orig_ist = &per_cpu(orig_ist, cpu);
	unsigned long v;
	char *estacks = NULL;
	struct task_struct *me;
	int i;

	/* CPU 0 is initialised in head64.c */
	if (cpu != 0)
		pda_init(cpu);
	else
		estacks = boot_exception_stacks;

	me = current;

	if (cpu_test_and_set(cpu, cpu_initialized))
		panic("CPU#%d already initialized!\n", cpu);

	printk(KERN_INFO "Initializing CPU#%d\n", cpu);

	clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);

	/*
	 * Initialize the per-CPU GDT with the boot GDT,
	 * and set up the GDT descriptor:
	 */

	switch_to_new_gdt();
	load_idt((const struct desc_ptr *)&idt_descr);

	memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
	syscall_init();

	wrmsrl(MSR_FS_BASE, 0);
	wrmsrl(MSR_KERNEL_GS_BASE, 0);
	barrier();

	check_efer();
	if (cpu != 0 && x2apic)
		enable_x2apic();

	/*
	 * set up and load the per-CPU TSS
	 */
	if (!orig_ist->ist[0]) {
		static const unsigned int order[N_EXCEPTION_STACKS] = {
		  [0 ... N_EXCEPTION_STACKS - 1] = EXCEPTION_STACK_ORDER,
		  [DEBUG_STACK - 1] = DEBUG_STACK_ORDER
		};
		for (v = 0; v < N_EXCEPTION_STACKS; v++) {
			if (cpu) {
				estacks = (char *)__get_free_pages(GFP_ATOMIC, order[v]);
				if (!estacks)
					panic("Cannot allocate exception "
					      "stack %ld %d\n", v, cpu);
			}
			estacks += PAGE_SIZE << order[v];
			orig_ist->ist[v] = t->x86_tss.ist[v] =
					(unsigned long)estacks;
		}
	}

	t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
	/*
	 * <= is required because the CPU will access up to
	 * 8 bits beyond the end of the IO permission bitmap.
	 */
	for (i = 0; i <= IO_BITMAP_LONGS; i++)
		t->io_bitmap[i] = ~0UL;

	atomic_inc(&init_mm.mm_count);
	me->active_mm = &init_mm;
	if (me->mm)
		BUG();
	enter_lazy_tlb(&init_mm, me);

	load_sp0(t, &current->thread);
	set_tss_desc(cpu, t);
	load_TR_desc();
	load_LDT(&init_mm.context);

#ifdef CONFIG_KGDB
	/*
	 * If the kgdb is connected no debug regs should be altered.  This
	 * is only applicable when KGDB and a KGDB I/O module are built
	 * into the kernel and you are using early debugging with
	 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
	 */
	if (kgdb_connected && arch_kgdb_ops.correct_hw_break)
		arch_kgdb_ops.correct_hw_break();
	else {
#endif
	/*
	 * Clear all 6 debug registers:
	 */

	set_debugreg(0UL, 0);
	set_debugreg(0UL, 1);
	set_debugreg(0UL, 2);
	set_debugreg(0UL, 3);
	set_debugreg(0UL, 6);
	set_debugreg(0UL, 7);
#ifdef CONFIG_KGDB
	/* If the kgdb is connected no debug regs should be altered. */
	}
#endif

	fpu_init();

	raw_local_save_flags(kernel_eflags);

	if (is_uv_system())
		uv_cpu_init();
}

#else

1067
void __cpuinit cpu_init(void)
1068
{
1069 1070
	int cpu = smp_processor_id();
	struct task_struct *curr = current;
1071
	struct tss_struct *t = &per_cpu(init_tss, cpu);
1072
	struct thread_struct *thread = &curr->thread;
1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083

	if (cpu_test_and_set(cpu, cpu_initialized)) {
		printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
		for (;;) local_irq_enable();
	}

	printk(KERN_INFO "Initializing CPU#%d\n", cpu);

	if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
		clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);

1084
	load_idt(&idt_descr);
1085
	switch_to_new_gdt();
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	/*
	 * Set up and load the per-CPU TSS and LDT
	 */
	atomic_inc(&init_mm.mm_count);
1091 1092 1093 1094
	curr->active_mm = &init_mm;
	if (curr->mm)
		BUG();
	enter_lazy_tlb(&init_mm, curr);
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1096
	load_sp0(t, thread);
1097
	set_tss_desc(cpu, t);
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	load_TR_desc();
	load_LDT(&init_mm.context);

1101
#ifdef CONFIG_DOUBLEFAULT
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	/* Set up doublefault TSS pointer in the GDT */
	__set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1104
#endif
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1106 1107
	/* Clear %gs. */
	asm volatile ("mov %0, %%gs" : : "r" (0));
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	/* Clear all 6 debug registers: */
1110 1111 1112 1113 1114 1115
	set_debugreg(0, 0);
	set_debugreg(0, 1);
	set_debugreg(0, 2);
	set_debugreg(0, 3);
	set_debugreg(0, 6);
	set_debugreg(0, 7);
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	/*
	 * Force FPU initialization:
	 */
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	if (cpu_has_xsave)
		current_thread_info()->status = TS_XSAVE;
	else
		current_thread_info()->status = 0;
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	clear_used_math();
	mxcsr_feature_mask_init();
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	/*
	 * Boot processor to setup the FP and extended state context info.
	 */
	if (!smp_processor_id())
		init_thread_xstate();

	xsave_init();
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}
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#endif