hda_controller.c 31.2 KB
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/*
 *
 *  Implementation of primary alsa driver code base for Intel HD Audio.
 *
 *  Copyright(c) 2004 Intel Corporation. All rights reserved.
 *
 *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
 *                     PeiSen Hou <pshou@realtek.com.tw>
 *
 *  This program is free software; you can redistribute it and/or modify it
 *  under the terms of the GNU General Public License as published by the Free
 *  Software Foundation; either version 2 of the License, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful, but WITHOUT
 *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 *  more details.
 *
 *
 */

#include <linux/clocksource.h>
#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
#include <sound/core.h>
#include <sound/initval.h>
#include "hda_controller.h"

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#define CREATE_TRACE_POINTS
#include "hda_intel_trace.h"

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/* DSP lock helpers */
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#define dsp_lock(dev)		snd_hdac_dsp_lock(azx_stream(dev))
#define dsp_unlock(dev)		snd_hdac_dsp_unlock(azx_stream(dev))
#define dsp_is_locked(dev)	snd_hdac_stream_is_locked(azx_stream(dev))
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/* assign a stream for the PCM */
static inline struct azx_dev *
azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
{
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	struct hdac_stream *s;

	s = snd_hdac_stream_assign(azx_bus(chip), substream);
	if (!s)
		return NULL;
	return stream_to_azx_dev(s);
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}

/* release the assigned stream */
static inline void azx_release_device(struct azx_dev *azx_dev)
{
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	snd_hdac_stream_release(azx_stream(azx_dev));
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}

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static inline struct hda_pcm_stream *
to_hda_pcm_stream(struct snd_pcm_substream *substream)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	return &apcm->info->stream[substream->stream];
}

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static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
				u64 nsec)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
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	struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
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	u64 codec_frames, codec_nsecs;

	if (!hinfo->ops.get_delay)
		return nsec;

	codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
	codec_nsecs = div_u64(codec_frames * 1000000000LL,
			      substream->runtime->rate);

	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
		return nsec + codec_nsecs;

	return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
}

/*
 * PCM ops
 */

static int azx_pcm_close(struct snd_pcm_substream *substream)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
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	struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
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	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev = get_azx_dev(substream);

	mutex_lock(&chip->open_mutex);
	azx_release_device(azx_dev);
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	if (hinfo->ops.close)
		hinfo->ops.close(hinfo, apcm->codec, substream);
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	snd_hda_power_down(apcm->codec);
	mutex_unlock(&chip->open_mutex);
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	snd_hda_codec_pcm_put(apcm->info);
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	return 0;
}

static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
			     struct snd_pcm_hw_params *hw_params)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;
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	struct azx_dev *azx_dev = get_azx_dev(substream);
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	int ret;

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	dsp_lock(azx_dev);
	if (dsp_is_locked(azx_dev)) {
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		ret = -EBUSY;
		goto unlock;
	}

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	azx_dev->core.bufsize = 0;
	azx_dev->core.period_bytes = 0;
	azx_dev->core.format_val = 0;
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	ret = chip->ops->substream_alloc_pages(chip, substream,
					  params_buffer_bytes(hw_params));
unlock:
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	dsp_unlock(azx_dev);
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	return ret;
}

static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx_dev *azx_dev = get_azx_dev(substream);
	struct azx *chip = apcm->chip;
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	struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
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	int err;

	/* reset BDL address */
	dsp_lock(azx_dev);
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	if (!dsp_is_locked(azx_dev))
		snd_hdac_stream_cleanup(azx_stream(azx_dev));
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	snd_hda_codec_cleanup(apcm->codec, hinfo, substream);

	err = chip->ops->substream_free_pages(chip, substream);
	azx_dev->prepared = 0;
	dsp_unlock(azx_dev);
	return err;
}

static int azx_pcm_prepare(struct snd_pcm_substream *substream)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev = get_azx_dev(substream);
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	struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
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	struct snd_pcm_runtime *runtime = substream->runtime;
	unsigned int bufsize, period_bytes, format_val, stream_tag;
	int err;
	struct hda_spdif_out *spdif =
		snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
	unsigned short ctls = spdif ? spdif->ctls : 0;

	dsp_lock(azx_dev);
	if (dsp_is_locked(azx_dev)) {
		err = -EBUSY;
		goto unlock;
	}

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	snd_hdac_stream_reset(azx_stream(azx_dev));
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	format_val = snd_hdac_calc_stream_format(runtime->rate,
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						runtime->channels,
						runtime->format,
						hinfo->maxbps,
						ctls);
	if (!format_val) {
		dev_err(chip->card->dev,
			"invalid format_val, rate=%d, ch=%d, format=%d\n",
			runtime->rate, runtime->channels, runtime->format);
		err = -EINVAL;
		goto unlock;
	}

	bufsize = snd_pcm_lib_buffer_bytes(substream);
	period_bytes = snd_pcm_lib_period_bytes(substream);

	dev_dbg(chip->card->dev, "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
		bufsize, format_val);

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	if (bufsize != azx_dev->core.bufsize ||
	    period_bytes != azx_dev->core.period_bytes ||
	    format_val != azx_dev->core.format_val ||
	    runtime->no_period_wakeup != azx_dev->core.no_period_wakeup) {
		azx_dev->core.bufsize = bufsize;
		azx_dev->core.period_bytes = period_bytes;
		azx_dev->core.format_val = format_val;
		azx_dev->core.no_period_wakeup = runtime->no_period_wakeup;
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		err = snd_hdac_stream_setup_periods(azx_stream(azx_dev));
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		if (err < 0)
			goto unlock;
	}

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	snd_hdac_stream_setup(azx_stream(azx_dev));
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	stream_tag = azx_dev->core.stream_tag;
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	/* CA-IBG chips need the playback stream starting from 1 */
	if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
	    stream_tag > chip->capture_streams)
		stream_tag -= chip->capture_streams;
	err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
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				     azx_dev->core.format_val, substream);
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 unlock:
	if (!err)
		azx_dev->prepared = 1;
	dsp_unlock(azx_dev);
	return err;
}

static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;
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	struct hdac_bus *bus = azx_bus(chip);
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	struct azx_dev *azx_dev;
	struct snd_pcm_substream *s;
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	struct hdac_stream *hstr;
	bool start;
	int sbits = 0;
	int sync_reg;
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	azx_dev = get_azx_dev(substream);
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	trace_azx_pcm_trigger(chip, azx_dev, cmd);

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	hstr = azx_stream(azx_dev);
	if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
		sync_reg = AZX_REG_OLD_SSYNC;
	else
		sync_reg = AZX_REG_SSYNC;
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	if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
		return -EPIPE;

	switch (cmd) {
	case SNDRV_PCM_TRIGGER_START:
	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
	case SNDRV_PCM_TRIGGER_RESUME:
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		start = true;
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		break;
	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
	case SNDRV_PCM_TRIGGER_SUSPEND:
	case SNDRV_PCM_TRIGGER_STOP:
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		start = false;
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		break;
	default:
		return -EINVAL;
	}

	snd_pcm_group_for_each_entry(s, substream) {
		if (s->pcm->card != substream->pcm->card)
			continue;
		azx_dev = get_azx_dev(s);
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		sbits |= 1 << azx_dev->core.index;
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		snd_pcm_trigger_done(s, substream);
	}

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	spin_lock(&bus->reg_lock);
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	/* first, set SYNC bits of corresponding streams */
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	snd_hdac_stream_sync_trigger(hstr, true, sbits, sync_reg);
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	snd_pcm_group_for_each_entry(s, substream) {
		if (s->pcm->card != substream->pcm->card)
			continue;
		azx_dev = get_azx_dev(s);
		if (start) {
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			azx_dev->insufficient = 1;
			snd_hdac_stream_start(azx_stream(azx_dev), true);
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		} else {
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			snd_hdac_stream_stop(azx_stream(azx_dev));
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		}
	}
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	spin_unlock(&bus->reg_lock);
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	snd_hdac_stream_sync(hstr, start, sbits);

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	spin_lock(&bus->reg_lock);
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	/* reset SYNC bits */
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	snd_hdac_stream_sync_trigger(hstr, false, sbits, sync_reg);
	if (start)
		snd_hdac_stream_timecounter_init(hstr, sbits);
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	spin_unlock(&bus->reg_lock);
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	return 0;
}

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unsigned int azx_get_pos_lpib(struct azx *chip, struct azx_dev *azx_dev)
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{
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	return snd_hdac_stream_get_pos_lpib(azx_stream(azx_dev));
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}
EXPORT_SYMBOL_GPL(azx_get_pos_lpib);
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unsigned int azx_get_pos_posbuf(struct azx *chip, struct azx_dev *azx_dev)
{
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	return snd_hdac_stream_get_pos_posbuf(azx_stream(azx_dev));
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}
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EXPORT_SYMBOL_GPL(azx_get_pos_posbuf);
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unsigned int azx_get_position(struct azx *chip,
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			      struct azx_dev *azx_dev)
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{
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	struct snd_pcm_substream *substream = azx_dev->core.substream;
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	unsigned int pos;
	int stream = substream->stream;
	int delay = 0;

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	if (chip->get_position[stream])
		pos = chip->get_position[stream](chip, azx_dev);
	else /* use the position buffer as default */
		pos = azx_get_pos_posbuf(chip, azx_dev);
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	if (pos >= azx_dev->core.bufsize)
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		pos = 0;

	if (substream->runtime) {
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		struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
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		struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
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		if (chip->get_delay[stream])
			delay += chip->get_delay[stream](chip, azx_dev, pos);
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		if (hinfo->ops.get_delay)
			delay += hinfo->ops.get_delay(hinfo, apcm->codec,
						      substream);
		substream->runtime->delay = delay;
	}

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	trace_azx_get_position(chip, azx_dev, pos, delay);
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	return pos;
}
EXPORT_SYMBOL_GPL(azx_get_position);

static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev = get_azx_dev(substream);
	return bytes_to_frames(substream->runtime,
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			       azx_get_position(chip, azx_dev));
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}

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static int azx_get_time_info(struct snd_pcm_substream *substream,
			struct timespec *system_ts, struct timespec *audio_ts,
			struct snd_pcm_audio_tstamp_config *audio_tstamp_config,
			struct snd_pcm_audio_tstamp_report *audio_tstamp_report)
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{
	struct azx_dev *azx_dev = get_azx_dev(substream);
	u64 nsec;

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	if ((substream->runtime->hw.info & SNDRV_PCM_INFO_HAS_LINK_ATIME) &&
		(audio_tstamp_config->type_requested == SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK)) {
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		snd_pcm_gettime(substream->runtime, system_ts);

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		nsec = timecounter_read(&azx_dev->core.tc);
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		nsec = div_u64(nsec, 3); /* can be optimized */
		if (audio_tstamp_config->report_delay)
			nsec = azx_adjust_codec_delay(substream, nsec);

		*audio_ts = ns_to_timespec(nsec);

		audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_LINK;
		audio_tstamp_report->accuracy_report = 1; /* rest of structure is valid */
		audio_tstamp_report->accuracy = 42; /* 24 MHz WallClock == 42ns resolution */

	} else
		audio_tstamp_report->actual_type = SNDRV_PCM_AUDIO_TSTAMP_TYPE_DEFAULT;
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	return 0;
}

static struct snd_pcm_hardware azx_pcm_hw = {
	.info =			(SNDRV_PCM_INFO_MMAP |
				 SNDRV_PCM_INFO_INTERLEAVED |
				 SNDRV_PCM_INFO_BLOCK_TRANSFER |
				 SNDRV_PCM_INFO_MMAP_VALID |
				 /* No full-resume yet implemented */
				 /* SNDRV_PCM_INFO_RESUME |*/
				 SNDRV_PCM_INFO_PAUSE |
				 SNDRV_PCM_INFO_SYNC_START |
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				 SNDRV_PCM_INFO_HAS_WALL_CLOCK | /* legacy */
				 SNDRV_PCM_INFO_HAS_LINK_ATIME |
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				 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
	.formats =		SNDRV_PCM_FMTBIT_S16_LE,
	.rates =		SNDRV_PCM_RATE_48000,
	.rate_min =		48000,
	.rate_max =		48000,
	.channels_min =		2,
	.channels_max =		2,
	.buffer_bytes_max =	AZX_MAX_BUF_SIZE,
	.period_bytes_min =	128,
	.period_bytes_max =	AZX_MAX_BUF_SIZE / 2,
	.periods_min =		2,
	.periods_max =		AZX_MAX_FRAG,
	.fifo_size =		0,
};

static int azx_pcm_open(struct snd_pcm_substream *substream)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
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	struct hda_pcm_stream *hinfo = to_hda_pcm_stream(substream);
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	struct azx *chip = apcm->chip;
	struct azx_dev *azx_dev;
	struct snd_pcm_runtime *runtime = substream->runtime;
	int err;
	int buff_step;

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	snd_hda_codec_pcm_get(apcm->info);
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	mutex_lock(&chip->open_mutex);
	azx_dev = azx_assign_device(chip, substream);
	if (azx_dev == NULL) {
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		err = -EBUSY;
		goto unlock;
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	}
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	runtime->private_data = azx_dev;
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	runtime->hw = azx_pcm_hw;
	runtime->hw.channels_min = hinfo->channels_min;
	runtime->hw.channels_max = hinfo->channels_max;
	runtime->hw.formats = hinfo->formats;
	runtime->hw.rates = hinfo->rates;
	snd_pcm_limit_hw_rates(runtime);
	snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);

	/* avoid wrap-around with wall-clock */
	snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
				     20,
				     178000000);

	if (chip->align_buffer_size)
		/* constrain buffer sizes to be multiple of 128
		   bytes. This is more efficient in terms of memory
		   access but isn't required by the HDA spec and
		   prevents users from specifying exact period/buffer
		   sizes. For example for 44.1kHz, a period size set
		   to 20ms will be rounded to 19.59ms. */
		buff_step = 128;
	else
		/* Don't enforce steps on buffer sizes, still need to
		   be multiple of 4 bytes (HDA spec). Tested on Intel
		   HDA controllers, may not work on all devices where
		   option needs to be disabled */
		buff_step = 4;

	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
				   buff_step);
	snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
				   buff_step);
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	snd_hda_power_up(apcm->codec);
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	if (hinfo->ops.open)
		err = hinfo->ops.open(hinfo, apcm->codec, substream);
	else
		err = -ENODEV;
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	if (err < 0) {
		azx_release_device(azx_dev);
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		goto powerdown;
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	}
	snd_pcm_limit_hw_rates(runtime);
	/* sanity check */
	if (snd_BUG_ON(!runtime->hw.channels_min) ||
	    snd_BUG_ON(!runtime->hw.channels_max) ||
	    snd_BUG_ON(!runtime->hw.formats) ||
	    snd_BUG_ON(!runtime->hw.rates)) {
		azx_release_device(azx_dev);
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		if (hinfo->ops.close)
			hinfo->ops.close(hinfo, apcm->codec, substream);
		err = -EINVAL;
		goto powerdown;
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	}

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	/* disable LINK_ATIME timestamps for capture streams
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	   until we figure out how to handle digital inputs */
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	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
		runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK; /* legacy */
		runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_LINK_ATIME;
	}
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	snd_pcm_set_sync(substream);
	mutex_unlock(&chip->open_mutex);
	return 0;
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 powerdown:
	snd_hda_power_down(apcm->codec);
 unlock:
	mutex_unlock(&chip->open_mutex);
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	snd_hda_codec_pcm_put(apcm->info);
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	return err;
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}

static int azx_pcm_mmap(struct snd_pcm_substream *substream,
			struct vm_area_struct *area)
{
	struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
	struct azx *chip = apcm->chip;
	if (chip->ops->pcm_mmap_prepare)
		chip->ops->pcm_mmap_prepare(substream, area);
	return snd_pcm_lib_default_mmap(substream, area);
}

static struct snd_pcm_ops azx_pcm_ops = {
	.open = azx_pcm_open,
	.close = azx_pcm_close,
	.ioctl = snd_pcm_lib_ioctl,
	.hw_params = azx_pcm_hw_params,
	.hw_free = azx_pcm_hw_free,
	.prepare = azx_pcm_prepare,
	.trigger = azx_pcm_trigger,
	.pointer = azx_pcm_pointer,
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	.get_time_info =  azx_get_time_info,
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	.mmap = azx_pcm_mmap,
	.page = snd_pcm_sgbuf_ops_page,
};

static void azx_pcm_free(struct snd_pcm *pcm)
{
	struct azx_pcm *apcm = pcm->private_data;
	if (apcm) {
		list_del(&apcm->list);
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		apcm->info->pcm = NULL;
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		kfree(apcm);
	}
}

#define MAX_PREALLOC_SIZE	(32 * 1024 * 1024)

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int snd_hda_attach_pcm_stream(struct hda_bus *_bus, struct hda_codec *codec,
			      struct hda_pcm *cpcm)
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{
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	struct hdac_bus *bus = &_bus->core;
	struct azx *chip = bus_to_azx(bus);
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	struct snd_pcm *pcm;
	struct azx_pcm *apcm;
	int pcm_dev = cpcm->device;
	unsigned int size;
	int s, err;

	list_for_each_entry(apcm, &chip->pcm_list, list) {
		if (apcm->pcm->device == pcm_dev) {
			dev_err(chip->card->dev, "PCM %d already exists\n",
				pcm_dev);
			return -EBUSY;
		}
	}
	err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
			  cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
			  cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
			  &pcm);
	if (err < 0)
		return err;
	strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
	apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
	if (apcm == NULL)
		return -ENOMEM;
	apcm->chip = chip;
	apcm->pcm = pcm;
	apcm->codec = codec;
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	apcm->info = cpcm;
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	pcm->private_data = apcm;
	pcm->private_free = azx_pcm_free;
	if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
		pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
	list_add_tail(&apcm->list, &chip->pcm_list);
	cpcm->pcm = pcm;
	for (s = 0; s < 2; s++) {
		if (cpcm->stream[s].substreams)
			snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
	}
	/* buffer pre-allocation */
	size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
	if (size > MAX_PREALLOC_SIZE)
		size = MAX_PREALLOC_SIZE;
	snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
					      chip->card->dev,
					      size, MAX_PREALLOC_SIZE);
	return 0;
}

587 588 589 590 591 592 593 594 595 596 597 598 599
static unsigned int azx_command_addr(u32 cmd)
{
	unsigned int addr = cmd >> 28;

	if (addr >= AZX_MAX_CODECS) {
		snd_BUG();
		addr = 0;
	}

	return addr;
}

/* receive a response */
600
static int azx_rirb_get_response(struct hdac_bus *bus, unsigned int addr,
601
				 unsigned int *res)
602
{
603 604
	struct azx *chip = bus_to_azx(bus);
	struct hda_bus *hbus = &chip->bus;
605 606 607 608 609 610 611 612
	unsigned long timeout;
	unsigned long loopcounter;
	int do_poll = 0;

 again:
	timeout = jiffies + msecs_to_jiffies(1000);

	for (loopcounter = 0;; loopcounter++) {
613 614 615 616
		spin_lock_irq(&bus->reg_lock);
		if (chip->polling_mode || do_poll)
			snd_hdac_bus_update_rirb(bus);
		if (!bus->rirb.cmds[addr]) {
617 618
			if (!do_poll)
				chip->poll_count = 0;
619
			if (res)
620 621
				*res = bus->rirb.res[addr]; /* the last value */
			spin_unlock_irq(&bus->reg_lock);
622
			return 0;
623
		}
624
		spin_unlock_irq(&bus->reg_lock);
625 626
		if (time_after(jiffies, timeout))
			break;
627
		if (hbus->needs_damn_long_delay || loopcounter > 3000)
628 629 630 631 632 633 634
			msleep(2); /* temporary workaround */
		else {
			udelay(10);
			cond_resched();
		}
	}

635
	if (hbus->no_response_fallback)
636
		return -EIO;
637 638 639 640

	if (!chip->polling_mode && chip->poll_count < 2) {
		dev_dbg(chip->card->dev,
			"azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
641
			bus->last_cmd[addr]);
642 643 644 645 646 647 648 649 650
		do_poll = 1;
		chip->poll_count++;
		goto again;
	}


	if (!chip->polling_mode) {
		dev_warn(chip->card->dev,
			 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
651
			 bus->last_cmd[addr]);
652 653 654 655 656 657 658
		chip->polling_mode = 1;
		goto again;
	}

	if (chip->msi) {
		dev_warn(chip->card->dev,
			 "No response from codec, disabling MSI: last cmd=0x%08x\n",
659 660
			 bus->last_cmd[addr]);
		if (chip->ops->disable_msi_reset_irq &&
661 662
		    chip->ops->disable_msi_reset_irq(chip) < 0)
			return -EIO;
663 664 665 666 667 668 669 670
		goto again;
	}

	if (chip->probing) {
		/* If this critical timeout happens during the codec probing
		 * phase, this is likely an access to a non-existing codec
		 * slot.  Better to return an error and reset the system.
		 */
671
		return -EIO;
672 673 674 675 676
	}

	/* a fatal communication error; need either to reset or to fallback
	 * to the single_cmd mode
	 */
677 678
	if (hbus->allow_bus_reset && !hbus->response_reset && !hbus->in_reset) {
		hbus->response_reset = 1;
679
		return -EAGAIN; /* give a chance to retry */
680 681 682 683
	}

	dev_err(chip->card->dev,
		"azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
684
		bus->last_cmd[addr]);
685
	chip->single_cmd = 1;
686 687
	hbus->response_reset = 0;
	snd_hdac_bus_stop_cmd_io(bus);
688
	return -EIO;
689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707
}

/*
 * Use the single immediate command instead of CORB/RIRB for simplicity
 *
 * Note: according to Intel, this is not preferred use.  The command was
 *       intended for the BIOS only, and may get confused with unsolicited
 *       responses.  So, we shouldn't use it for normal operation from the
 *       driver.
 *       I left the codes, however, for debugging/testing purposes.
 */

/* receive a response */
static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
{
	int timeout = 50;

	while (timeout--) {
		/* check IRV busy bit */
T
Takashi Iwai 已提交
708
		if (azx_readw(chip, IRS) & AZX_IRS_VALID) {
709
			/* reuse rirb.res as the response return value */
710
			azx_bus(chip)->rirb.res[addr] = azx_readl(chip, IR);
711 712 713 714 715 716 717
			return 0;
		}
		udelay(1);
	}
	if (printk_ratelimit())
		dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
			azx_readw(chip, IRS));
718
	azx_bus(chip)->rirb.res[addr] = -1;
719 720 721 722
	return -EIO;
}

/* send a command */
723
static int azx_single_send_cmd(struct hdac_bus *bus, u32 val)
724
{
725
	struct azx *chip = bus_to_azx(bus);
726 727 728
	unsigned int addr = azx_command_addr(val);
	int timeout = 50;

729
	bus->last_cmd[azx_command_addr(val)] = val;
730 731
	while (timeout--) {
		/* check ICB busy bit */
T
Takashi Iwai 已提交
732
		if (!((azx_readw(chip, IRS) & AZX_IRS_BUSY))) {
733 734
			/* Clear IRV valid bit */
			azx_writew(chip, IRS, azx_readw(chip, IRS) |
T
Takashi Iwai 已提交
735
				   AZX_IRS_VALID);
736 737
			azx_writel(chip, IC, val);
			azx_writew(chip, IRS, azx_readw(chip, IRS) |
T
Takashi Iwai 已提交
738
				   AZX_IRS_BUSY);
739 740 741 742 743 744 745 746 747 748 749 750
			return azx_single_wait_for_response(chip, addr);
		}
		udelay(1);
	}
	if (printk_ratelimit())
		dev_dbg(chip->card->dev,
			"send_cmd timeout: IRS=0x%x, val=0x%x\n",
			azx_readw(chip, IRS), val);
	return -EIO;
}

/* receive a response */
751
static int azx_single_get_response(struct hdac_bus *bus, unsigned int addr,
752
				   unsigned int *res)
753
{
754
	if (res)
755
		*res = bus->rirb.res[addr];
756
	return 0;
757 758 759 760 761 762 763 764 765 766
}

/*
 * The below are the main callbacks from hda_codec.
 *
 * They are just the skeleton to call sub-callbacks according to the
 * current setting of chip->single_cmd.
 */

/* send a command */
767
static int azx_send_cmd(struct hdac_bus *bus, unsigned int val)
768
{
769
	struct azx *chip = bus_to_azx(bus);
770 771 772 773 774 775

	if (chip->disabled)
		return 0;
	if (chip->single_cmd)
		return azx_single_send_cmd(bus, val);
	else
776
		return snd_hdac_bus_send_cmd(bus, val);
777 778 779
}

/* get a response */
780
static int azx_get_response(struct hdac_bus *bus, unsigned int addr,
781
			    unsigned int *res)
782
{
783 784
	struct azx *chip = bus_to_azx(bus);

785 786 787
	if (chip->disabled)
		return 0;
	if (chip->single_cmd)
788
		return azx_single_get_response(bus, addr, res);
789
	else
790
		return azx_rirb_get_response(bus, addr, res);
791 792
}

793 794 795 796 797
static const struct hdac_bus_ops bus_core_ops = {
	.command = azx_send_cmd,
	.get_response = azx_get_response,
};

798 799 800 801 802 803 804 805 806
#ifdef CONFIG_SND_HDA_DSP_LOADER
/*
 * DSP loading code (e.g. for CA0132)
 */

/* use the first stream for loading DSP */
static struct azx_dev *
azx_get_dsp_loader_dev(struct azx *chip)
{
807 808 809 810 811 812 813 814
	struct hdac_bus *bus = azx_bus(chip);
	struct hdac_stream *s;

	list_for_each_entry(s, &bus->stream_list, list)
		if (s->index == chip->playback_index_offset)
			return stream_to_azx_dev(s);

	return NULL;
815 816
}

817 818 819
int snd_hda_codec_load_dsp_prepare(struct hda_codec *codec, unsigned int format,
				   unsigned int byte_size,
				   struct snd_dma_buffer *bufp)
820
{
821
	struct hdac_bus *bus = &codec->bus->core;
822
	struct azx *chip = bus_to_azx(bus);
823
	struct azx_dev *azx_dev;
824 825
	struct hdac_stream *hstr;
	bool saved = false;
826 827 828
	int err;

	azx_dev = azx_get_dsp_loader_dev(chip);
829
	hstr = azx_stream(azx_dev);
830
	spin_lock_irq(&bus->reg_lock);
831 832 833
	if (hstr->opened) {
		chip->saved_azx_dev = *azx_dev;
		saved = true;
834
	}
835
	spin_unlock_irq(&bus->reg_lock);
836

837 838
	err = snd_hdac_dsp_prepare(hstr, format, byte_size, bufp);
	if (err < 0) {
839
		spin_lock_irq(&bus->reg_lock);
840 841
		if (saved)
			*azx_dev = chip->saved_azx_dev;
842
		spin_unlock_irq(&bus->reg_lock);
843 844
		return err;
	}
845

846
	azx_dev->prepared = 0;
847 848
	return err;
}
849
EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_prepare);
850

851
void snd_hda_codec_load_dsp_trigger(struct hda_codec *codec, bool start)
852
{
853
	struct hdac_bus *bus = &codec->bus->core;
854
	struct azx *chip = bus_to_azx(bus);
855 856
	struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);

857
	snd_hdac_dsp_trigger(azx_stream(azx_dev), start);
858
}
859
EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_trigger);
860

861 862
void snd_hda_codec_load_dsp_cleanup(struct hda_codec *codec,
				    struct snd_dma_buffer *dmab)
863
{
864
	struct hdac_bus *bus = &codec->bus->core;
865
	struct azx *chip = bus_to_azx(bus);
866
	struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
867
	struct hdac_stream *hstr = azx_stream(azx_dev);
868

869
	if (!dmab->area || !hstr->locked)
870 871
		return;

872
	snd_hdac_dsp_cleanup(hstr, dmab);
873
	spin_lock_irq(&bus->reg_lock);
874
	if (hstr->opened)
875
		*azx_dev = chip->saved_azx_dev;
876
	hstr->locked = false;
877
	spin_unlock_irq(&bus->reg_lock);
878
}
879
EXPORT_SYMBOL_GPL(snd_hda_codec_load_dsp_cleanup);
880 881
#endif /* CONFIG_SND_HDA_DSP_LOADER */

882 883 884
/*
 * reset and start the controller registers
 */
885
void azx_init_chip(struct azx *chip, bool full_reset)
886
{
887 888 889 890 891
	if (snd_hdac_bus_init_chip(azx_bus(chip), full_reset)) {
		/* correct RINTCNT for CXT */
		if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
			azx_writew(chip, RINTCNT, 0xc0);
	}
892 893 894
}
EXPORT_SYMBOL_GPL(azx_init_chip);

895 896 897 898 899 900 901 902 903 904
void azx_stop_all_streams(struct azx *chip)
{
	struct hdac_bus *bus = azx_bus(chip);
	struct hdac_stream *s;

	list_for_each_entry(s, &bus->stream_list, list)
		snd_hdac_stream_stop(s);
}
EXPORT_SYMBOL_GPL(azx_stop_all_streams);

905 906
void azx_stop_chip(struct azx *chip)
{
907
	snd_hdac_bus_stop_chip(azx_bus(chip));
908
}
909
EXPORT_SYMBOL_GPL(azx_stop_chip);
910

911 912 913
/*
 * interrupt handler
 */
914 915
static void stream_update(struct hdac_bus *bus, struct hdac_stream *s)
{
916
	struct azx *chip = bus_to_azx(bus);
917 918 919 920 921
	struct azx_dev *azx_dev = stream_to_azx_dev(s);

	/* check whether this IRQ is really acceptable */
	if (!chip->ops->position_check ||
	    chip->ops->position_check(chip, azx_dev)) {
922 923 924
		spin_unlock(&bus->reg_lock);
		snd_pcm_period_elapsed(azx_stream(azx_dev)->substream);
		spin_lock(&bus->reg_lock);
925 926 927
	}
}

928 929 930
irqreturn_t azx_interrupt(int irq, void *dev_id)
{
	struct azx *chip = dev_id;
931
	struct hdac_bus *bus = azx_bus(chip);
932 933
	u32 status;

934
#ifdef CONFIG_PM
935
	if (azx_has_pm_runtime(chip))
936
		if (!pm_runtime_active(chip->card->dev))
937 938 939
			return IRQ_NONE;
#endif

940
	spin_lock(&bus->reg_lock);
941 942

	if (chip->disabled) {
943
		spin_unlock(&bus->reg_lock);
944 945 946 947 948
		return IRQ_NONE;
	}

	status = azx_readl(chip, INTSTS);
	if (status == 0 || status == 0xffffffff) {
949
		spin_unlock(&bus->reg_lock);
950 951 952
		return IRQ_NONE;
	}

953
	snd_hdac_bus_handle_stream_irq(bus, status, stream_update);
954 955 956 957 958 959 960

	/* clear rirb int */
	status = azx_readb(chip, RIRBSTS);
	if (status & RIRB_INT_MASK) {
		if (status & RIRB_INT_RESPONSE) {
			if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
				udelay(80);
961
			snd_hdac_bus_update_rirb(bus);
962 963 964 965
		}
		azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
	}

966
	spin_unlock(&bus->reg_lock);
967 968 969 970 971

	return IRQ_HANDLED;
}
EXPORT_SYMBOL_GPL(azx_interrupt);

972 973 974 975 976 977 978 979 980 981 982
/*
 * Codec initerface
 */

/*
 * Probe the given codec address
 */
static int probe_codec(struct azx *chip, int addr)
{
	unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
		(AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
983
	struct hdac_bus *bus = azx_bus(chip);
984
	int err;
985
	unsigned int res = -1;
986

987
	mutex_lock(&bus->cmd_mutex);
988
	chip->probing = 1;
989 990
	azx_send_cmd(bus, cmd);
	err = azx_get_response(bus, addr, &res);
991
	chip->probing = 0;
992
	mutex_unlock(&bus->cmd_mutex);
993
	if (err < 0 || res == -1)
994 995 996 997 998
		return -EIO;
	dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
	return 0;
}

999
void snd_hda_bus_reset(struct hda_bus *bus)
1000
{
1001
	struct azx *chip = bus_to_azx(&bus->core);
1002 1003 1004

	bus->in_reset = 1;
	azx_stop_chip(chip);
1005
	azx_init_chip(chip, true);
1006
	if (bus->core.chip_init)
1007
		snd_hda_bus_reset_codecs(bus);
1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031
	bus->in_reset = 0;
}

static int get_jackpoll_interval(struct azx *chip)
{
	int i;
	unsigned int j;

	if (!chip->jackpoll_ms)
		return 0;

	i = chip->jackpoll_ms[chip->dev_index];
	if (i == 0)
		return 0;
	if (i < 50 || i > 60000)
		j = 0;
	else
		j = msecs_to_jiffies(i);
	if (j == 0)
		dev_warn(chip->card->dev,
			 "jackpoll_ms value out of range: %d\n", i);
	return j;
}

1032
/* HD-audio bus initialization */
1033 1034
int azx_bus_init(struct azx *chip, const char *model,
		 const struct hdac_io_ops *io_ops)
1035
{
1036
	struct hda_bus *bus = &chip->bus;
1037
	int err;
1038

1039 1040
	err = snd_hdac_bus_init(&bus->core, chip->card->dev, &bus_core_ops,
				io_ops);
1041 1042 1043
	if (err < 0)
		return err;

1044 1045
	bus->card = chip->card;
	mutex_init(&bus->prepare_mutex);
1046 1047
	bus->pci = chip->pci;
	bus->modelname = model;
1048 1049 1050 1051 1052 1053
	bus->core.snoop = azx_snoop(chip);
	if (chip->get_position[0] != azx_get_pos_lpib ||
	    chip->get_position[1] != azx_get_pos_lpib)
		bus->core.use_posbuf = true;
	if (chip->bdl_pos_adj)
		bus->core.bdl_pos_adj = chip->bdl_pos_adj[chip->dev_index];
1054 1055
	if (chip->driver_caps & AZX_DCAPS_CORBRP_SELF_CLEAR)
		bus->core.corbrp_self_clear = true;
1056

1057 1058
	if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
		dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1059
		bus->needs_damn_long_delay = 1;
1060 1061
	}

1062 1063 1064 1065 1066 1067
	/* AMD chipsets often cause the communication stalls upon certain
	 * sequence like the pin-detection.  It seems that forcing the synced
	 * access works around the stall.  Grrr...
	 */
	if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
		dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1068
		bus->core.sync_write = 1;
1069 1070 1071 1072 1073
		bus->allow_bus_reset = 1;
	}

	return 0;
}
1074
EXPORT_SYMBOL_GPL(azx_bus_init);
1075 1076 1077 1078

/* Probe codecs */
int azx_probe_codecs(struct azx *chip, unsigned int max_slots)
{
1079
	struct hdac_bus *bus = azx_bus(chip);
1080 1081
	int c, codecs, err;

1082 1083 1084 1085 1086 1087
	codecs = 0;
	if (!max_slots)
		max_slots = AZX_DEFAULT_CODECS;

	/* First try to probe all given codec slots */
	for (c = 0; c < max_slots; c++) {
1088
		if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1089 1090 1091 1092 1093 1094
			if (probe_codec(chip, c) < 0) {
				/* Some BIOSen give you wrong codec addresses
				 * that don't exist
				 */
				dev_warn(chip->card->dev,
					 "Codec #%d probe error; disabling it...\n", c);
1095
				bus->codec_mask &= ~(1 << c);
1096 1097 1098 1099 1100 1101 1102 1103
				/* More badly, accessing to a non-existing
				 * codec often screws up the controller chip,
				 * and disturbs the further communications.
				 * Thus if an error occurs during probing,
				 * better to reset the controller chip to
				 * get back to the sanity state.
				 */
				azx_stop_chip(chip);
1104
				azx_init_chip(chip, true);
1105 1106 1107 1108 1109 1110
			}
		}
	}

	/* Then create codec instances */
	for (c = 0; c < max_slots; c++) {
1111
		if ((bus->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1112
			struct hda_codec *codec;
1113
			err = snd_hda_codec_new(&chip->bus, chip->card, c, &codec);
1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126
			if (err < 0)
				continue;
			codec->jackpoll_interval = get_jackpoll_interval(chip);
			codec->beep_mode = chip->beep_mode;
			codecs++;
		}
	}
	if (!codecs) {
		dev_err(chip->card->dev, "no codecs initialized\n");
		return -ENXIO;
	}
	return 0;
}
1127
EXPORT_SYMBOL_GPL(azx_probe_codecs);
1128 1129 1130 1131 1132

/* configure each codec instance */
int azx_codec_configure(struct azx *chip)
{
	struct hda_codec *codec;
1133
	list_for_each_codec(codec, &chip->bus) {
1134 1135 1136 1137 1138 1139
		snd_hda_codec_configure(codec);
	}
	return 0;
}
EXPORT_SYMBOL_GPL(azx_codec_configure);

1140
static int stream_direction(struct azx *chip, unsigned char index)
1141
{
1142 1143 1144 1145
	if (index >= chip->capture_index_offset &&
	    index < chip->capture_index_offset + chip->capture_streams)
		return SNDRV_PCM_STREAM_CAPTURE;
	return SNDRV_PCM_STREAM_PLAYBACK;
1146 1147
}

1148
/* initialize SD streams */
1149
int azx_init_streams(struct azx *chip)
1150 1151
{
	int i;
1152
	int stream_tags[2] = { 0, 0 };
1153 1154 1155 1156 1157 1158

	/* initialize each stream (aka device)
	 * assign the starting bdl address to each stream (device)
	 * and initialize
	 */
	for (i = 0; i < chip->num_streams; i++) {
1159 1160 1161 1162 1163
		struct azx_dev *azx_dev = kzalloc(sizeof(*azx_dev), GFP_KERNEL);
		int dir, tag;

		if (!azx_dev)
			return -ENOMEM;
1164

1165
		dir = stream_direction(chip, i);
1166 1167 1168 1169 1170 1171 1172
		/* stream tag must be unique throughout
		 * the stream direction group,
		 * valid values 1...15
		 * use separate stream tag if the flag
		 * AZX_DCAPS_SEPARATE_STREAM_TAG is used
		 */
		if (chip->driver_caps & AZX_DCAPS_SEPARATE_STREAM_TAG)
1173
			tag = ++stream_tags[dir];
1174
		else
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			tag = i + 1;
		snd_hdac_stream_init(azx_bus(chip), azx_stream(azx_dev),
				     i, dir, tag);
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	}

	return 0;
}
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EXPORT_SYMBOL_GPL(azx_init_streams);

void azx_free_streams(struct azx *chip)
{
	struct hdac_bus *bus = azx_bus(chip);
	struct hdac_stream *s;

	while (!list_empty(&bus->stream_list)) {
		s = list_first_entry(&bus->stream_list, struct hdac_stream, list);
		list_del(&s->list);
		kfree(stream_to_azx_dev(s));
	}
}
EXPORT_SYMBOL_GPL(azx_free_streams);