irq-gic-v3-its.c 94.9 KB
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/*
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 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
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 * Author: Marc Zyngier <marc.zyngier@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

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#include <linux/acpi.h>
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#include <linux/acpi_iort.h>
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#include <linux/bitmap.h>
#include <linux/cpu.h>
#include <linux/delay.h>
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#include <linux/dma-iommu.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/list.h>
#include <linux/list_sort.h>
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#include <linux/log2.h>
#include <linux/mm.h>
#include <linux/msi.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/of_pci.h>
#include <linux/of_platform.h>
#include <linux/percpu.h>
#include <linux/slab.h>
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#include <linux/syscore_ops.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/arm-gic-v3.h>
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#include <linux/irqchip/arm-gic-v4.h>
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#include <asm/cputype.h>
#include <asm/exception.h>

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#include "irq-gic-common.h"

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#define ITS_FLAGS_CMDQ_NEEDS_FLUSHING		(1ULL << 0)
#define ITS_FLAGS_WORKAROUND_CAVIUM_22375	(1ULL << 1)
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#define ITS_FLAGS_WORKAROUND_CAVIUM_23144	(1ULL << 2)
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#define ITS_FLAGS_SAVE_SUSPEND_STATE		(1ULL << 3)
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#define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING	(1 << 0)

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static u32 lpi_id_bits;

/*
 * We allocate memory for PROPBASE to cover 2 ^ lpi_id_bits LPIs to
 * deal with (one configuration byte per interrupt). PENDBASE has to
 * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
 */
#define LPI_NRBITS		lpi_id_bits
#define LPI_PROPBASE_SZ		ALIGN(BIT(LPI_NRBITS), SZ_64K)
#define LPI_PENDBASE_SZ		ALIGN(BIT(LPI_NRBITS) / 8, SZ_64K)

#define LPI_PROP_DEFAULT_PRIO	0xa0

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/*
 * Collection structure - just an ID, and a redistributor address to
 * ping. We use one per CPU as a bag of interrupts assigned to this
 * CPU.
 */
struct its_collection {
	u64			target_address;
	u16			col_id;
};

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/*
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 * The ITS_BASER structure - contains memory information, cached
 * value of BASER register configuration and ITS page size.
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 */
struct its_baser {
	void		*base;
	u64		val;
	u32		order;
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	u32		psz;
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};

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struct its_device;

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/*
 * The ITS structure - contains most of the infrastructure, with the
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 * top-level MSI domain, the command queue, the collections, and the
 * list of devices writing to it.
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 *
 * dev_alloc_lock has to be taken for device allocations, while the
 * spinlock must be taken to parse data structures such as the device
 * list.
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 */
struct its_node {
	raw_spinlock_t		lock;
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	struct mutex		dev_alloc_lock;
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	struct list_head	entry;
	void __iomem		*base;
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	phys_addr_t		phys_base;
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	struct its_cmd_block	*cmd_base;
	struct its_cmd_block	*cmd_write;
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	struct its_baser	tables[GITS_BASER_NR_REGS];
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	struct its_collection	*collections;
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	struct fwnode_handle	*fwnode_handle;
	u64			(*get_msi_base)(struct its_device *its_dev);
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	u64			cbaser_save;
	u32			ctlr_save;
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	struct list_head	its_device_list;
	u64			flags;
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	unsigned long		list_nr;
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	u32			ite_size;
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	u32			device_ids;
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	int			numa_node;
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	unsigned int		msi_domain_flags;
	u32			pre_its_base; /* for Socionext Synquacer */
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	bool			is_v4;
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	int			vlpi_redist_offset;
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};

#define ITS_ITT_ALIGN		SZ_256

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/* The maximum number of VPEID bits supported by VLPI commands */
#define ITS_MAX_VPEID_BITS	(16)
#define ITS_MAX_VPEID		(1 << (ITS_MAX_VPEID_BITS))

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/* Convert page order to size in bytes */
#define PAGE_ORDER_TO_SIZE(o)	(PAGE_SIZE << (o))

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struct event_lpi_map {
	unsigned long		*lpi_map;
	u16			*col_map;
	irq_hw_number_t		lpi_base;
	int			nr_lpis;
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	struct mutex		vlpi_lock;
	struct its_vm		*vm;
	struct its_vlpi_map	*vlpi_maps;
	int			nr_vlpis;
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};

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/*
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 * The ITS view of a device - belongs to an ITS, owns an interrupt
 * translation table, and a list of interrupts.  If it some of its
 * LPIs are injected into a guest (GICv4), the event_map.vm field
 * indicates which one.
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 */
struct its_device {
	struct list_head	entry;
	struct its_node		*its;
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	struct event_lpi_map	event_map;
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	void			*itt;
	u32			nr_ites;
	u32			device_id;
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	bool			shared;
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};

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static struct {
	raw_spinlock_t		lock;
	struct its_device	*dev;
	struct its_vpe		**vpes;
	int			next_victim;
} vpe_proxy;

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static LIST_HEAD(its_nodes);
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static DEFINE_RAW_SPINLOCK(its_lock);
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static struct rdists *gic_rdists;
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static struct irq_domain *its_parent;
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static unsigned long its_list_map;
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static u16 vmovp_seq_num;
static DEFINE_RAW_SPINLOCK(vmovp_lock);

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static DEFINE_IDA(its_vpeid_ida);
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#define gic_data_rdist()		(raw_cpu_ptr(gic_rdists->rdist))
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#define gic_data_rdist_cpu(cpu)		(per_cpu_ptr(gic_rdists->rdist, cpu))
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#define gic_data_rdist_rd_base()	(gic_data_rdist()->rd_base)
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#define gic_data_rdist_vlpi_base()	(gic_data_rdist_rd_base() + SZ_128K)
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static struct its_collection *dev_event_to_col(struct its_device *its_dev,
					       u32 event)
{
	struct its_node *its = its_dev->its;

	return its->collections + its_dev->event_map.col_map[event];
}

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static struct its_collection *valid_col(struct its_collection *col)
{
	if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(0, 15)))
		return NULL;

	return col;
}

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static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe)
{
	if (valid_col(its->collections + vpe->col_idx))
		return vpe;

	return NULL;
}

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/*
 * ITS command descriptors - parameters to be encoded in a command
 * block.
 */
struct its_cmd_desc {
	union {
		struct {
			struct its_device *dev;
			u32 event_id;
		} its_inv_cmd;

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		struct {
			struct its_device *dev;
			u32 event_id;
		} its_clear_cmd;

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		struct {
			struct its_device *dev;
			u32 event_id;
		} its_int_cmd;

		struct {
			struct its_device *dev;
			int valid;
		} its_mapd_cmd;

		struct {
			struct its_collection *col;
			int valid;
		} its_mapc_cmd;

		struct {
			struct its_device *dev;
			u32 phys_id;
			u32 event_id;
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		} its_mapti_cmd;
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		struct {
			struct its_device *dev;
			struct its_collection *col;
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			u32 event_id;
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		} its_movi_cmd;

		struct {
			struct its_device *dev;
			u32 event_id;
		} its_discard_cmd;

		struct {
			struct its_collection *col;
		} its_invall_cmd;
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		struct {
			struct its_vpe *vpe;
		} its_vinvall_cmd;

		struct {
			struct its_vpe *vpe;
			struct its_collection *col;
			bool valid;
		} its_vmapp_cmd;

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		struct {
			struct its_vpe *vpe;
			struct its_device *dev;
			u32 virt_id;
			u32 event_id;
			bool db_enabled;
		} its_vmapti_cmd;

		struct {
			struct its_vpe *vpe;
			struct its_device *dev;
			u32 event_id;
			bool db_enabled;
		} its_vmovi_cmd;
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		struct {
			struct its_vpe *vpe;
			struct its_collection *col;
			u16 seq_num;
			u16 its_list;
		} its_vmovp_cmd;
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	};
};

/*
 * The ITS command block, which is what the ITS actually parses.
 */
struct its_cmd_block {
	u64	raw_cmd[4];
};

#define ITS_CMD_QUEUE_SZ		SZ_64K
#define ITS_CMD_QUEUE_NR_ENTRIES	(ITS_CMD_QUEUE_SZ / sizeof(struct its_cmd_block))

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typedef struct its_collection *(*its_cmd_builder_t)(struct its_node *,
						    struct its_cmd_block *,
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						    struct its_cmd_desc *);

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typedef struct its_vpe *(*its_cmd_vbuilder_t)(struct its_node *,
					      struct its_cmd_block *,
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					      struct its_cmd_desc *);

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static void its_mask_encode(u64 *raw_cmd, u64 val, int h, int l)
{
	u64 mask = GENMASK_ULL(h, l);
	*raw_cmd &= ~mask;
	*raw_cmd |= (val << l) & mask;
}

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static void its_encode_cmd(struct its_cmd_block *cmd, u8 cmd_nr)
{
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	its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0);
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}

static void its_encode_devid(struct its_cmd_block *cmd, u32 devid)
{
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	its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32);
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}

static void its_encode_event_id(struct its_cmd_block *cmd, u32 id)
{
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	its_mask_encode(&cmd->raw_cmd[1], id, 31, 0);
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}

static void its_encode_phys_id(struct its_cmd_block *cmd, u32 phys_id)
{
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	its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32);
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}

static void its_encode_size(struct its_cmd_block *cmd, u8 size)
{
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	its_mask_encode(&cmd->raw_cmd[1], size, 4, 0);
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}

static void its_encode_itt(struct its_cmd_block *cmd, u64 itt_addr)
{
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	its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8);
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}

static void its_encode_valid(struct its_cmd_block *cmd, int valid)
{
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	its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63);
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}

static void its_encode_target(struct its_cmd_block *cmd, u64 target_addr)
{
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	its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16);
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}

static void its_encode_collection(struct its_cmd_block *cmd, u16 col)
{
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	its_mask_encode(&cmd->raw_cmd[2], col, 15, 0);
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}

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static void its_encode_vpeid(struct its_cmd_block *cmd, u16 vpeid)
{
	its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32);
}

static void its_encode_virt_id(struct its_cmd_block *cmd, u32 virt_id)
{
	its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0);
}

static void its_encode_db_phys_id(struct its_cmd_block *cmd, u32 db_phys_id)
{
	its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32);
}

static void its_encode_db_valid(struct its_cmd_block *cmd, bool db_valid)
{
	its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0);
}

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static void its_encode_seq_num(struct its_cmd_block *cmd, u16 seq_num)
{
	its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32);
}

static void its_encode_its_list(struct its_cmd_block *cmd, u16 its_list)
{
	its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0);
}

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static void its_encode_vpt_addr(struct its_cmd_block *cmd, u64 vpt_pa)
{
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	its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16);
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}

static void its_encode_vpt_size(struct its_cmd_block *cmd, u8 vpt_size)
{
	its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0);
}

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static inline void its_fixup_cmd(struct its_cmd_block *cmd)
{
	/* Let's fixup BE commands */
	cmd->raw_cmd[0] = cpu_to_le64(cmd->raw_cmd[0]);
	cmd->raw_cmd[1] = cpu_to_le64(cmd->raw_cmd[1]);
	cmd->raw_cmd[2] = cpu_to_le64(cmd->raw_cmd[2]);
	cmd->raw_cmd[3] = cpu_to_le64(cmd->raw_cmd[3]);
}

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static struct its_collection *its_build_mapd_cmd(struct its_node *its,
						 struct its_cmd_block *cmd,
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						 struct its_cmd_desc *desc)
{
	unsigned long itt_addr;
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	u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites);
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	itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt);
	itt_addr = ALIGN(itt_addr, ITS_ITT_ALIGN);

	its_encode_cmd(cmd, GITS_CMD_MAPD);
	its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id);
	its_encode_size(cmd, size - 1);
	its_encode_itt(cmd, itt_addr);
	its_encode_valid(cmd, desc->its_mapd_cmd.valid);

	its_fixup_cmd(cmd);

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	return NULL;
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}

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static struct its_collection *its_build_mapc_cmd(struct its_node *its,
						 struct its_cmd_block *cmd,
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						 struct its_cmd_desc *desc)
{
	its_encode_cmd(cmd, GITS_CMD_MAPC);
	its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);
	its_encode_target(cmd, desc->its_mapc_cmd.col->target_address);
	its_encode_valid(cmd, desc->its_mapc_cmd.valid);

	its_fixup_cmd(cmd);

	return desc->its_mapc_cmd.col;
}

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static struct its_collection *its_build_mapti_cmd(struct its_node *its,
						  struct its_cmd_block *cmd,
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						  struct its_cmd_desc *desc)
{
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	struct its_collection *col;

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	col = dev_event_to_col(desc->its_mapti_cmd.dev,
			       desc->its_mapti_cmd.event_id);
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	its_encode_cmd(cmd, GITS_CMD_MAPTI);
	its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_mapti_cmd.event_id);
	its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id);
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	its_encode_collection(cmd, col->col_id);
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	its_fixup_cmd(cmd);

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	return valid_col(col);
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}

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static struct its_collection *its_build_movi_cmd(struct its_node *its,
						 struct its_cmd_block *cmd,
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						 struct its_cmd_desc *desc)
{
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	struct its_collection *col;

	col = dev_event_to_col(desc->its_movi_cmd.dev,
			       desc->its_movi_cmd.event_id);

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	its_encode_cmd(cmd, GITS_CMD_MOVI);
	its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id);
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	its_encode_event_id(cmd, desc->its_movi_cmd.event_id);
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	its_encode_collection(cmd, desc->its_movi_cmd.col->col_id);

	its_fixup_cmd(cmd);

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	return valid_col(col);
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}

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static struct its_collection *its_build_discard_cmd(struct its_node *its,
						    struct its_cmd_block *cmd,
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						    struct its_cmd_desc *desc)
{
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	struct its_collection *col;

	col = dev_event_to_col(desc->its_discard_cmd.dev,
			       desc->its_discard_cmd.event_id);

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	its_encode_cmd(cmd, GITS_CMD_DISCARD);
	its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_discard_cmd.event_id);

	its_fixup_cmd(cmd);

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	return valid_col(col);
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}

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static struct its_collection *its_build_inv_cmd(struct its_node *its,
						struct its_cmd_block *cmd,
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						struct its_cmd_desc *desc)
{
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	struct its_collection *col;

	col = dev_event_to_col(desc->its_inv_cmd.dev,
			       desc->its_inv_cmd.event_id);

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	its_encode_cmd(cmd, GITS_CMD_INV);
	its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_inv_cmd.event_id);

	its_fixup_cmd(cmd);

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	return valid_col(col);
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}

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static struct its_collection *its_build_int_cmd(struct its_node *its,
						struct its_cmd_block *cmd,
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						struct its_cmd_desc *desc)
{
	struct its_collection *col;

	col = dev_event_to_col(desc->its_int_cmd.dev,
			       desc->its_int_cmd.event_id);

	its_encode_cmd(cmd, GITS_CMD_INT);
	its_encode_devid(cmd, desc->its_int_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_int_cmd.event_id);

	its_fixup_cmd(cmd);

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	return valid_col(col);
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}

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static struct its_collection *its_build_clear_cmd(struct its_node *its,
						  struct its_cmd_block *cmd,
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						  struct its_cmd_desc *desc)
{
	struct its_collection *col;

	col = dev_event_to_col(desc->its_clear_cmd.dev,
			       desc->its_clear_cmd.event_id);

	its_encode_cmd(cmd, GITS_CMD_CLEAR);
	its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id);
	its_encode_event_id(cmd, desc->its_clear_cmd.event_id);

	its_fixup_cmd(cmd);

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	return valid_col(col);
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}

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static struct its_collection *its_build_invall_cmd(struct its_node *its,
						   struct its_cmd_block *cmd,
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						   struct its_cmd_desc *desc)
{
	its_encode_cmd(cmd, GITS_CMD_INVALL);
	its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id);

	its_fixup_cmd(cmd);

	return NULL;
}

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static struct its_vpe *its_build_vinvall_cmd(struct its_node *its,
					     struct its_cmd_block *cmd,
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					     struct its_cmd_desc *desc)
{
	its_encode_cmd(cmd, GITS_CMD_VINVALL);
	its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id);

	its_fixup_cmd(cmd);

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	return valid_vpe(its, desc->its_vinvall_cmd.vpe);
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}

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static struct its_vpe *its_build_vmapp_cmd(struct its_node *its,
					   struct its_cmd_block *cmd,
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					   struct its_cmd_desc *desc)
{
	unsigned long vpt_addr;
590
	u64 target;
591 592

	vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page));
593
	target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset;
594 595 596 597

	its_encode_cmd(cmd, GITS_CMD_VMAPP);
	its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id);
	its_encode_valid(cmd, desc->its_vmapp_cmd.valid);
598
	its_encode_target(cmd, target);
599 600 601 602 603
	its_encode_vpt_addr(cmd, vpt_addr);
	its_encode_vpt_size(cmd, LPI_NRBITS - 1);

	its_fixup_cmd(cmd);

604
	return valid_vpe(its, desc->its_vmapp_cmd.vpe);
605 606
}

607 608
static struct its_vpe *its_build_vmapti_cmd(struct its_node *its,
					    struct its_cmd_block *cmd,
609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626
					    struct its_cmd_desc *desc)
{
	u32 db;

	if (desc->its_vmapti_cmd.db_enabled)
		db = desc->its_vmapti_cmd.vpe->vpe_db_lpi;
	else
		db = 1023;

	its_encode_cmd(cmd, GITS_CMD_VMAPTI);
	its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id);
	its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id);
	its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id);
	its_encode_db_phys_id(cmd, db);
	its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id);

	its_fixup_cmd(cmd);

627
	return valid_vpe(its, desc->its_vmapti_cmd.vpe);
628 629
}

630 631
static struct its_vpe *its_build_vmovi_cmd(struct its_node *its,
					   struct its_cmd_block *cmd,
632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649
					   struct its_cmd_desc *desc)
{
	u32 db;

	if (desc->its_vmovi_cmd.db_enabled)
		db = desc->its_vmovi_cmd.vpe->vpe_db_lpi;
	else
		db = 1023;

	its_encode_cmd(cmd, GITS_CMD_VMOVI);
	its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id);
	its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id);
	its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id);
	its_encode_db_phys_id(cmd, db);
	its_encode_db_valid(cmd, true);

	its_fixup_cmd(cmd);

650
	return valid_vpe(its, desc->its_vmovi_cmd.vpe);
651 652
}

653 654
static struct its_vpe *its_build_vmovp_cmd(struct its_node *its,
					   struct its_cmd_block *cmd,
655 656
					   struct its_cmd_desc *desc)
{
657 658 659
	u64 target;

	target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset;
660 661 662 663
	its_encode_cmd(cmd, GITS_CMD_VMOVP);
	its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num);
	its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list);
	its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id);
664
	its_encode_target(cmd, target);
665 666 667

	its_fixup_cmd(cmd);

668
	return valid_vpe(its, desc->its_vmovp_cmd.vpe);
669 670
}

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static u64 its_cmd_ptr_to_offset(struct its_node *its,
				 struct its_cmd_block *ptr)
{
	return (ptr - its->cmd_base) * sizeof(*ptr);
}

static int its_queue_full(struct its_node *its)
{
	int widx;
	int ridx;

	widx = its->cmd_write - its->cmd_base;
	ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block);

	/* This is incredibly unlikely to happen, unless the ITS locks up. */
	if (((widx + 1) % ITS_CMD_QUEUE_NR_ENTRIES) == ridx)
		return 1;

	return 0;
}

static struct its_cmd_block *its_allocate_entry(struct its_node *its)
{
	struct its_cmd_block *cmd;
	u32 count = 1000000;	/* 1s! */

	while (its_queue_full(its)) {
		count--;
		if (!count) {
			pr_err_ratelimited("ITS queue not draining\n");
			return NULL;
		}
		cpu_relax();
		udelay(1);
	}

	cmd = its->cmd_write++;

	/* Handle queue wrapping */
	if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES))
		its->cmd_write = its->cmd_base;

713 714 715 716 717 718
	/* Clear command  */
	cmd->raw_cmd[0] = 0;
	cmd->raw_cmd[1] = 0;
	cmd->raw_cmd[2] = 0;
	cmd->raw_cmd[3] = 0;

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	return cmd;
}

static struct its_cmd_block *its_post_commands(struct its_node *its)
{
	u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write);

	writel_relaxed(wr, its->base + GITS_CWRITER);

	return its->cmd_write;
}

static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd)
{
	/*
	 * Make sure the commands written to memory are observable by
	 * the ITS.
	 */
	if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING)
738
		gic_flush_dcache_to_poc(cmd, sizeof(*cmd));
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	else
		dsb(ishst);
}

743
static int its_wait_for_range_completion(struct its_node *its,
744
					 u64	prev_idx,
745
					 struct its_cmd_block *to)
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{
747
	u64 rd_idx, to_idx, linear_idx;
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	u32 count = 1000000;	/* 1s! */

750
	/* Linearize to_idx if the command set has wrapped around */
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	to_idx = its_cmd_ptr_to_offset(its, to);
752 753 754 755
	if (to_idx < prev_idx)
		to_idx += ITS_CMD_QUEUE_SZ;

	linear_idx = prev_idx;
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	while (1) {
758 759
		s64 delta;

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		rd_idx = readl_relaxed(its->base + GITS_CREADR);
761

762 763 764 765 766 767 768
		/*
		 * Compute the read pointer progress, taking the
		 * potential wrap-around into account.
		 */
		delta = rd_idx - prev_idx;
		if (rd_idx < prev_idx)
			delta += ITS_CMD_QUEUE_SZ;
769

770 771
		linear_idx += delta;
		if (linear_idx >= to_idx)
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			break;

		count--;
		if (!count) {
776 777
			pr_err_ratelimited("ITS queue timeout (%llu %llu)\n",
					   to_idx, linear_idx);
778
			return -1;
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		}
780
		prev_idx = rd_idx;
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		cpu_relax();
		udelay(1);
	}
784 785

	return 0;
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}

788 789 790 791 792 793 794 795 796
/* Warning, macro hell follows */
#define BUILD_SINGLE_CMD_FUNC(name, buildtype, synctype, buildfn)	\
void name(struct its_node *its,						\
	  buildtype builder,						\
	  struct its_cmd_desc *desc)					\
{									\
	struct its_cmd_block *cmd, *sync_cmd, *next_cmd;		\
	synctype *sync_obj;						\
	unsigned long flags;						\
797
	u64 rd_idx;							\
798 799 800 801 802 803 804 805
									\
	raw_spin_lock_irqsave(&its->lock, flags);			\
									\
	cmd = its_allocate_entry(its);					\
	if (!cmd) {		/* We're soooooo screewed... */		\
		raw_spin_unlock_irqrestore(&its->lock, flags);		\
		return;							\
	}								\
806
	sync_obj = builder(its, cmd, desc);				\
807 808 809 810 811 812 813
	its_flush_cmd(its, cmd);					\
									\
	if (sync_obj) {							\
		sync_cmd = its_allocate_entry(its);			\
		if (!sync_cmd)						\
			goto post;					\
									\
814
		buildfn(its, sync_cmd, sync_obj);			\
815 816 817 818
		its_flush_cmd(its, sync_cmd);				\
	}								\
									\
post:									\
819
	rd_idx = readl_relaxed(its->base + GITS_CREADR);		\
820 821 822
	next_cmd = its_post_commands(its);				\
	raw_spin_unlock_irqrestore(&its->lock, flags);			\
									\
823
	if (its_wait_for_range_completion(its, rd_idx, next_cmd))	\
824
		pr_err_ratelimited("ITS cmd %ps failed\n", builder);	\
825
}
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827 828
static void its_build_sync_cmd(struct its_node *its,
			       struct its_cmd_block *sync_cmd,
829 830 831 832
			       struct its_collection *sync_col)
{
	its_encode_cmd(sync_cmd, GITS_CMD_SYNC);
	its_encode_target(sync_cmd, sync_col->target_address);
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834
	its_fixup_cmd(sync_cmd);
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}

837 838 839
static BUILD_SINGLE_CMD_FUNC(its_send_single_command, its_cmd_builder_t,
			     struct its_collection, its_build_sync_cmd)

840 841
static void its_build_vsync_cmd(struct its_node *its,
				struct its_cmd_block *sync_cmd,
842 843 844 845 846 847 848 849 850 851 852
				struct its_vpe *sync_vpe)
{
	its_encode_cmd(sync_cmd, GITS_CMD_VSYNC);
	its_encode_vpeid(sync_cmd, sync_vpe->vpe_id);

	its_fixup_cmd(sync_cmd);
}

static BUILD_SINGLE_CMD_FUNC(its_send_single_vcommand, its_cmd_vbuilder_t,
			     struct its_vpe, its_build_vsync_cmd)

853
static void its_send_int(struct its_device *dev, u32 event_id)
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{
855
	struct its_cmd_desc desc;
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857 858
	desc.its_int_cmd.dev = dev;
	desc.its_int_cmd.event_id = event_id;
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860 861
	its_send_single_command(dev->its, its_build_int_cmd, &desc);
}
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863 864 865
static void its_send_clear(struct its_device *dev, u32 event_id)
{
	struct its_cmd_desc desc;
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867 868
	desc.its_clear_cmd.dev = dev;
	desc.its_clear_cmd.event_id = event_id;
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870
	its_send_single_command(dev->its, its_build_clear_cmd, &desc);
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}

static void its_send_inv(struct its_device *dev, u32 event_id)
{
	struct its_cmd_desc desc;

	desc.its_inv_cmd.dev = dev;
	desc.its_inv_cmd.event_id = event_id;

	its_send_single_command(dev->its, its_build_inv_cmd, &desc);
}

static void its_send_mapd(struct its_device *dev, int valid)
{
	struct its_cmd_desc desc;

	desc.its_mapd_cmd.dev = dev;
	desc.its_mapd_cmd.valid = !!valid;

	its_send_single_command(dev->its, its_build_mapd_cmd, &desc);
}

static void its_send_mapc(struct its_node *its, struct its_collection *col,
			  int valid)
{
	struct its_cmd_desc desc;

	desc.its_mapc_cmd.col = col;
	desc.its_mapc_cmd.valid = !!valid;

	its_send_single_command(its, its_build_mapc_cmd, &desc);
}

904
static void its_send_mapti(struct its_device *dev, u32 irq_id, u32 id)
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{
	struct its_cmd_desc desc;

908 909 910
	desc.its_mapti_cmd.dev = dev;
	desc.its_mapti_cmd.phys_id = irq_id;
	desc.its_mapti_cmd.event_id = id;
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912
	its_send_single_command(dev->its, its_build_mapti_cmd, &desc);
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}

static void its_send_movi(struct its_device *dev,
			  struct its_collection *col, u32 id)
{
	struct its_cmd_desc desc;

	desc.its_movi_cmd.dev = dev;
	desc.its_movi_cmd.col = col;
922
	desc.its_movi_cmd.event_id = id;
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	its_send_single_command(dev->its, its_build_movi_cmd, &desc);
}

static void its_send_discard(struct its_device *dev, u32 id)
{
	struct its_cmd_desc desc;

	desc.its_discard_cmd.dev = dev;
	desc.its_discard_cmd.event_id = id;

	its_send_single_command(dev->its, its_build_discard_cmd, &desc);
}

static void its_send_invall(struct its_node *its, struct its_collection *col)
{
	struct its_cmd_desc desc;

	desc.its_invall_cmd.col = col;

	its_send_single_command(its, its_build_invall_cmd, &desc);
}
945

946 947 948 949 950 951 952 953 954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972
static void its_send_vmapti(struct its_device *dev, u32 id)
{
	struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
	struct its_cmd_desc desc;

	desc.its_vmapti_cmd.vpe = map->vpe;
	desc.its_vmapti_cmd.dev = dev;
	desc.its_vmapti_cmd.virt_id = map->vintid;
	desc.its_vmapti_cmd.event_id = id;
	desc.its_vmapti_cmd.db_enabled = map->db_enabled;

	its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc);
}

static void its_send_vmovi(struct its_device *dev, u32 id)
{
	struct its_vlpi_map *map = &dev->event_map.vlpi_maps[id];
	struct its_cmd_desc desc;

	desc.its_vmovi_cmd.vpe = map->vpe;
	desc.its_vmovi_cmd.dev = dev;
	desc.its_vmovi_cmd.event_id = id;
	desc.its_vmovi_cmd.db_enabled = map->db_enabled;

	its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc);
}

973 974
static void its_send_vmapp(struct its_node *its,
			   struct its_vpe *vpe, bool valid)
975 976 977 978 979
{
	struct its_cmd_desc desc;

	desc.its_vmapp_cmd.vpe = vpe;
	desc.its_vmapp_cmd.valid = valid;
980
	desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx];
981

982
	its_send_single_vcommand(its, its_build_vmapp_cmd, &desc);
983 984
}

985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019
static void its_send_vmovp(struct its_vpe *vpe)
{
	struct its_cmd_desc desc;
	struct its_node *its;
	unsigned long flags;
	int col_id = vpe->col_idx;

	desc.its_vmovp_cmd.vpe = vpe;
	desc.its_vmovp_cmd.its_list = (u16)its_list_map;

	if (!its_list_map) {
		its = list_first_entry(&its_nodes, struct its_node, entry);
		desc.its_vmovp_cmd.seq_num = 0;
		desc.its_vmovp_cmd.col = &its->collections[col_id];
		its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
		return;
	}

	/*
	 * Yet another marvel of the architecture. If using the
	 * its_list "feature", we need to make sure that all ITSs
	 * receive all VMOVP commands in the same order. The only way
	 * to guarantee this is to make vmovp a serialization point.
	 *
	 * Wall <-- Head.
	 */
	raw_spin_lock_irqsave(&vmovp_lock, flags);

	desc.its_vmovp_cmd.seq_num = vmovp_seq_num++;

	/* Emit VMOVPs */
	list_for_each_entry(its, &its_nodes, entry) {
		if (!its->is_v4)
			continue;

1020 1021 1022
		if (!vpe->its_vm->vlpi_count[its->list_nr])
			continue;

1023 1024 1025 1026 1027 1028 1029
		desc.its_vmovp_cmd.col = &its->collections[col_id];
		its_send_single_vcommand(its, its_build_vmovp_cmd, &desc);
	}

	raw_spin_unlock_irqrestore(&vmovp_lock, flags);
}

1030
static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe)
1031 1032 1033 1034
{
	struct its_cmd_desc desc;

	desc.its_vinvall_cmd.vpe = vpe;
1035
	its_send_single_vcommand(its, its_build_vinvall_cmd, &desc);
1036 1037
}

1038 1039 1040 1041 1042 1043 1044
/*
 * irqchip functions - assumes MSI, mostly.
 */

static inline u32 its_get_event_id(struct irq_data *d)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
1045
	return d->hwirq - its_dev->event_map.lpi_base;
1046 1047
}

1048
static void lpi_write_config(struct irq_data *d, u8 clr, u8 set)
1049
{
1050
	irq_hw_number_t hwirq;
1051
	void *va;
1052
	u8 *cfg;
1053

1054 1055 1056
	if (irqd_is_forwarded_to_vcpu(d)) {
		struct its_device *its_dev = irq_data_get_irq_chip_data(d);
		u32 event = its_get_event_id(d);
1057
		struct its_vlpi_map *map;
1058

1059
		va = page_address(its_dev->event_map.vm->vprop_page);
1060 1061 1062 1063 1064 1065
		map = &its_dev->event_map.vlpi_maps[event];
		hwirq = map->vintid;

		/* Remember the updated property */
		map->properties &= ~clr;
		map->properties |= set | LPI_PROP_GROUP1;
1066
	} else {
1067
		va = gic_rdists->prop_table_va;
1068 1069
		hwirq = d->hwirq;
	}
1070

1071
	cfg = va + hwirq - 8192;
1072
	*cfg &= ~clr;
1073
	*cfg |= set | LPI_PROP_GROUP1;
1074 1075 1076 1077 1078 1079 1080

	/*
	 * Make the above write visible to the redistributors.
	 * And yes, we're flushing exactly: One. Single. Byte.
	 * Humpf...
	 */
	if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING)
1081
		gic_flush_dcache_to_poc(cfg, sizeof(*cfg));
1082 1083
	else
		dsb(ishst);
1084 1085 1086 1087 1088 1089 1090
}

static void lpi_update_config(struct irq_data *d, u8 clr, u8 set)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);

	lpi_write_config(d, clr, set);
1091
	its_send_inv(its_dev, its_get_event_id(d));
1092 1093
}

1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114
static void its_vlpi_set_doorbell(struct irq_data *d, bool enable)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);

	if (its_dev->event_map.vlpi_maps[event].db_enabled == enable)
		return;

	its_dev->event_map.vlpi_maps[event].db_enabled = enable;

	/*
	 * More fun with the architecture:
	 *
	 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI
	 * value or to 1023, depending on the enable bit. But that
	 * would be issueing a mapping for an /existing/ DevID+EventID
	 * pair, which is UNPREDICTABLE. Instead, let's issue a VMOVI
	 * to the /same/ vPE, using this opportunity to adjust the
	 * doorbell. Mouahahahaha. We loves it, Precious.
	 */
	its_send_vmovi(its_dev, event);
1115 1116 1117 1118
}

static void its_mask_irq(struct irq_data *d)
{
1119 1120 1121
	if (irqd_is_forwarded_to_vcpu(d))
		its_vlpi_set_doorbell(d, false);

1122
	lpi_update_config(d, LPI_PROP_ENABLED, 0);
1123 1124 1125 1126
}

static void its_unmask_irq(struct irq_data *d)
{
1127 1128 1129
	if (irqd_is_forwarded_to_vcpu(d))
		its_vlpi_set_doorbell(d, true);

1130
	lpi_update_config(d, 0, LPI_PROP_ENABLED);
1131 1132 1133 1134 1135
}

static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
			    bool force)
{
1136 1137
	unsigned int cpu;
	const struct cpumask *cpu_mask = cpu_online_mask;
1138 1139 1140 1141
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	struct its_collection *target_col;
	u32 id = its_get_event_id(d);

1142 1143 1144 1145
	/* A forwarded interrupt should use irq_set_vcpu_affinity */
	if (irqd_is_forwarded_to_vcpu(d))
		return -EINVAL;

1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156
       /* lpi cannot be routed to a redistributor that is on a foreign node */
	if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
		if (its_dev->its->numa_node >= 0) {
			cpu_mask = cpumask_of_node(its_dev->its->numa_node);
			if (!cpumask_intersects(mask_val, cpu_mask))
				return -EINVAL;
		}
	}

	cpu = cpumask_any_and(mask_val, cpu_mask);

1157 1158 1159
	if (cpu >= nr_cpu_ids)
		return -EINVAL;

1160 1161 1162 1163 1164
	/* don't set the affinity when the target cpu is same as current one */
	if (cpu != its_dev->event_map.col_map[id]) {
		target_col = &its_dev->its->collections[cpu];
		its_send_movi(its_dev, target_col, id);
		its_dev->event_map.col_map[id] = cpu;
1165
		irq_data_update_effective_affinity(d, cpumask_of(cpu));
1166
	}
1167 1168 1169 1170

	return IRQ_SET_MASK_OK_DONE;
}

1171 1172 1173 1174 1175 1176 1177
static u64 its_irq_get_msi_base(struct its_device *its_dev)
{
	struct its_node *its = its_dev->its;

	return its->phys_base + GITS_TRANSLATER;
}

M
Marc Zyngier 已提交
1178 1179 1180 1181 1182 1183 1184
static void its_irq_compose_msi_msg(struct irq_data *d, struct msi_msg *msg)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	struct its_node *its;
	u64 addr;

	its = its_dev->its;
1185
	addr = its->get_msi_base(its_dev);
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Marc Zyngier 已提交
1186

1187 1188
	msg->address_lo		= lower_32_bits(addr);
	msg->address_hi		= upper_32_bits(addr);
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1189
	msg->data		= its_get_event_id(d);
1190 1191

	iommu_dma_map_msi_msg(d->irq, msg);
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1192 1193
}

1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211
static int its_irq_set_irqchip_state(struct irq_data *d,
				     enum irqchip_irq_state which,
				     bool state)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);

	if (which != IRQCHIP_STATE_PENDING)
		return -EINVAL;

	if (state)
		its_send_int(its_dev, event);
	else
		its_send_clear(its_dev, event);

	return 0;
}

1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232
static void its_map_vm(struct its_node *its, struct its_vm *vm)
{
	unsigned long flags;

	/* Not using the ITS list? Everything is always mapped. */
	if (!its_list_map)
		return;

	raw_spin_lock_irqsave(&vmovp_lock, flags);

	/*
	 * If the VM wasn't mapped yet, iterate over the vpes and get
	 * them mapped now.
	 */
	vm->vlpi_count[its->list_nr]++;

	if (vm->vlpi_count[its->list_nr] == 1) {
		int i;

		for (i = 0; i < vm->nr_vpes; i++) {
			struct its_vpe *vpe = vm->vpes[i];
1233
			struct irq_data *d = irq_get_irq_data(vpe->irq);
1234 1235 1236 1237 1238

			/* Map the VPE to the first possible CPU */
			vpe->col_idx = cpumask_first(cpu_online_mask);
			its_send_vmapp(its, vpe, true);
			its_send_vinvall(its, vpe);
1239
			irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));
1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265
		}
	}

	raw_spin_unlock_irqrestore(&vmovp_lock, flags);
}

static void its_unmap_vm(struct its_node *its, struct its_vm *vm)
{
	unsigned long flags;

	/* Not using the ITS list? Everything is always mapped. */
	if (!its_list_map)
		return;

	raw_spin_lock_irqsave(&vmovp_lock, flags);

	if (!--vm->vlpi_count[its->list_nr]) {
		int i;

		for (i = 0; i < vm->nr_vpes; i++)
			its_send_vmapp(its, vm->vpes[i], false);
	}

	raw_spin_unlock_irqrestore(&vmovp_lock, flags);
}

1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279
static int its_vlpi_map(struct irq_data *d, struct its_cmd_info *info)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);
	int ret = 0;

	if (!info->map)
		return -EINVAL;

	mutex_lock(&its_dev->event_map.vlpi_lock);

	if (!its_dev->event_map.vm) {
		struct its_vlpi_map *maps;

K
Kees Cook 已提交
1280
		maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps),
1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300
			       GFP_KERNEL);
		if (!maps) {
			ret = -ENOMEM;
			goto out;
		}

		its_dev->event_map.vm = info->map->vm;
		its_dev->event_map.vlpi_maps = maps;
	} else if (its_dev->event_map.vm != info->map->vm) {
		ret = -EINVAL;
		goto out;
	}

	/* Get our private copy of the mapping information */
	its_dev->event_map.vlpi_maps[event] = *info->map;

	if (irqd_is_forwarded_to_vcpu(d)) {
		/* Already mapped, move it around */
		its_send_vmovi(its_dev, event);
	} else {
1301 1302 1303
		/* Ensure all the VPEs are mapped on this ITS */
		its_map_vm(its_dev->its, info->map->vm);

1304 1305 1306 1307 1308 1309 1310 1311 1312
		/*
		 * Flag the interrupt as forwarded so that we can
		 * start poking the virtual property table.
		 */
		irqd_set_forwarded_to_vcpu(d);

		/* Write out the property to the prop table */
		lpi_write_config(d, 0xff, info->map->properties);

1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372
		/* Drop the physical mapping */
		its_send_discard(its_dev, event);

		/* and install the virtual one */
		its_send_vmapti(its_dev, event);

		/* Increment the number of VLPIs */
		its_dev->event_map.nr_vlpis++;
	}

out:
	mutex_unlock(&its_dev->event_map.vlpi_lock);
	return ret;
}

static int its_vlpi_get(struct irq_data *d, struct its_cmd_info *info)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);
	int ret = 0;

	mutex_lock(&its_dev->event_map.vlpi_lock);

	if (!its_dev->event_map.vm ||
	    !its_dev->event_map.vlpi_maps[event].vm) {
		ret = -EINVAL;
		goto out;
	}

	/* Copy our mapping information to the incoming request */
	*info->map = its_dev->event_map.vlpi_maps[event];

out:
	mutex_unlock(&its_dev->event_map.vlpi_lock);
	return ret;
}

static int its_vlpi_unmap(struct irq_data *d)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);
	int ret = 0;

	mutex_lock(&its_dev->event_map.vlpi_lock);

	if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) {
		ret = -EINVAL;
		goto out;
	}

	/* Drop the virtual mapping */
	its_send_discard(its_dev, event);

	/* and restore the physical one */
	irqd_clr_forwarded_to_vcpu(d);
	its_send_mapti(its_dev, d->hwirq, event);
	lpi_update_config(d, 0xff, (LPI_PROP_DEFAULT_PRIO |
				    LPI_PROP_ENABLED |
				    LPI_PROP_GROUP1));

1373 1374 1375
	/* Potentially unmap the VM from this ITS */
	its_unmap_vm(its_dev->its, its_dev->event_map.vm);

1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389
	/*
	 * Drop the refcount and make the device available again if
	 * this was the last VLPI.
	 */
	if (!--its_dev->event_map.nr_vlpis) {
		its_dev->event_map.vm = NULL;
		kfree(its_dev->event_map.vlpi_maps);
	}

out:
	mutex_unlock(&its_dev->event_map.vlpi_lock);
	return ret;
}

1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405
static int its_vlpi_prop_update(struct irq_data *d, struct its_cmd_info *info)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);

	if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d))
		return -EINVAL;

	if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI)
		lpi_update_config(d, 0xff, info->config);
	else
		lpi_write_config(d, 0xff, info->config);
	its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED));

	return 0;
}

1406 1407 1408 1409 1410 1411
static int its_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	struct its_cmd_info *info = vcpu_info;

	/* Need a v4 ITS */
1412
	if (!its_dev->its->is_v4)
1413 1414
		return -EINVAL;

1415 1416 1417 1418
	/* Unmap request? */
	if (!info)
		return its_vlpi_unmap(d);

1419 1420
	switch (info->cmd_type) {
	case MAP_VLPI:
1421
		return its_vlpi_map(d, info);
1422 1423

	case GET_VLPI:
1424
		return its_vlpi_get(d, info);
1425 1426 1427

	case PROP_UPDATE_VLPI:
	case PROP_UPDATE_AND_INV_VLPI:
1428
		return its_vlpi_prop_update(d, info);
1429 1430 1431 1432 1433 1434

	default:
		return -EINVAL;
	}
}

1435 1436 1437 1438
static struct irq_chip its_irq_chip = {
	.name			= "ITS",
	.irq_mask		= its_mask_irq,
	.irq_unmask		= its_unmask_irq,
1439
	.irq_eoi		= irq_chip_eoi_parent,
1440
	.irq_set_affinity	= its_set_affinity,
M
Marc Zyngier 已提交
1441
	.irq_compose_msi_msg	= its_irq_compose_msi_msg,
1442
	.irq_set_irqchip_state	= its_irq_set_irqchip_state,
1443
	.irq_set_vcpu_affinity	= its_irq_set_vcpu_affinity,
M
Marc Zyngier 已提交
1444 1445
};

1446

M
Marc Zyngier 已提交
1447 1448 1449
/*
 * How we allocate LPIs:
 *
1450 1451 1452 1453 1454 1455 1456 1457
 * lpi_range_list contains ranges of LPIs that are to available to
 * allocate from. To allocate LPIs, just pick the first range that
 * fits the required allocation, and reduce it by the required
 * amount. Once empty, remove the range from the list.
 *
 * To free a range of LPIs, add a free range to the list, sort it and
 * merge the result if the new range happens to be adjacent to an
 * already free block.
M
Marc Zyngier 已提交
1458
 *
1459 1460 1461
 * The consequence of the above is that allocation is cost is low, but
 * freeing is expensive. We assumes that freeing rarely occurs.
 */
1462
#define ITS_MAX_LPI_NRBITS	16 /* 64K LPIs */
1463 1464 1465 1466 1467 1468 1469 1470 1471

static DEFINE_MUTEX(lpi_range_lock);
static LIST_HEAD(lpi_range_list);

struct lpi_range {
	struct list_head	entry;
	u32			base_id;
	u32			span;
};
M
Marc Zyngier 已提交
1472

1473
static struct lpi_range *mk_lpi_range(u32 base, u32 span)
M
Marc Zyngier 已提交
1474
{
1475 1476 1477 1478 1479 1480 1481 1482 1483 1484
	struct lpi_range *range;

	range = kzalloc(sizeof(*range), GFP_KERNEL);
	if (range) {
		INIT_LIST_HEAD(&range->entry);
		range->base_id = base;
		range->span = span;
	}

	return range;
M
Marc Zyngier 已提交
1485 1486
}

1487
static int lpi_range_cmp(void *priv, struct list_head *a, struct list_head *b)
M
Marc Zyngier 已提交
1488
{
1489 1490 1491 1492 1493
	struct lpi_range *ra, *rb;

	ra = container_of(a, struct lpi_range, entry);
	rb = container_of(b, struct lpi_range, entry);

1494
	return ra->base_id - rb->base_id;
M
Marc Zyngier 已提交
1495 1496
}

1497
static void merge_lpi_ranges(void)
M
Marc Zyngier 已提交
1498
{
1499
	struct lpi_range *range, *tmp;
M
Marc Zyngier 已提交
1500

1501 1502 1503 1504 1505 1506 1507 1508
	list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
		if (!list_is_last(&range->entry, &lpi_range_list) &&
		    (tmp->base_id == (range->base_id + range->span))) {
			tmp->base_id = range->base_id;
			tmp->span += range->span;
			list_del(&range->entry);
			kfree(range);
		}
M
Marc Zyngier 已提交
1509
	}
1510
}
M
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1511

1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538
static int alloc_lpi_range(u32 nr_lpis, u32 *base)
{
	struct lpi_range *range, *tmp;
	int err = -ENOSPC;

	mutex_lock(&lpi_range_lock);

	list_for_each_entry_safe(range, tmp, &lpi_range_list, entry) {
		if (range->span >= nr_lpis) {
			*base = range->base_id;
			range->base_id += nr_lpis;
			range->span -= nr_lpis;

			if (range->span == 0) {
				list_del(&range->entry);
				kfree(range);
			}

			err = 0;
			break;
		}
	}

	mutex_unlock(&lpi_range_lock);

	pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis);
	return err;
M
Marc Zyngier 已提交
1539 1540
}

1541
static int free_lpi_range(u32 base, u32 nr_lpis)
M
Marc Zyngier 已提交
1542
{
1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564
	struct lpi_range *new;
	int err = 0;

	mutex_lock(&lpi_range_lock);

	new = mk_lpi_range(base, nr_lpis);
	if (!new) {
		err = -ENOMEM;
		goto out;
	}

	list_add(&new->entry, &lpi_range_list);
	list_sort(NULL, &lpi_range_list, lpi_range_cmp);
	merge_lpi_ranges();
out:
	mutex_unlock(&lpi_range_lock);
	return err;
}

static int __init its_lpi_init(u32 id_bits)
{
	u32 lpis = (1UL << id_bits) - 8192;
1565
	u32 numlpis;
1566 1567
	int err;

1568 1569 1570 1571 1572 1573 1574 1575
	numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer);

	if (numlpis > 2 && !WARN_ON(numlpis > lpis)) {
		lpis = numlpis;
		pr_info("ITS: Using hypervisor restricted LPI range [%u]\n",
			lpis);
	}

1576 1577 1578 1579 1580 1581 1582 1583
	/*
	 * Initializing the allocator is just the same as freeing the
	 * full range of LPIs.
	 */
	err = free_lpi_range(8192, lpis);
	pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis);
	return err;
}
M
Marc Zyngier 已提交
1584

1585
static unsigned long *its_lpi_alloc(int nr_irqs, u32 *base, int *nr_ids)
1586 1587 1588
{
	unsigned long *bitmap = NULL;
	int err = 0;
M
Marc Zyngier 已提交
1589 1590

	do {
1591
		err = alloc_lpi_range(nr_irqs, base);
1592
		if (!err)
M
Marc Zyngier 已提交
1593 1594
			break;

1595 1596
		nr_irqs /= 2;
	} while (nr_irqs > 0);
M
Marc Zyngier 已提交
1597

1598 1599 1600
	if (!nr_irqs)
		err = -ENOSPC;

1601
	if (err)
M
Marc Zyngier 已提交
1602 1603
		goto out;

1604
	bitmap = kcalloc(BITS_TO_LONGS(nr_irqs), sizeof (long), GFP_ATOMIC);
M
Marc Zyngier 已提交
1605 1606 1607
	if (!bitmap)
		goto out;

1608
	*nr_ids = nr_irqs;
M
Marc Zyngier 已提交
1609 1610

out:
1611 1612 1613
	if (!bitmap)
		*base = *nr_ids = 0;

M
Marc Zyngier 已提交
1614 1615 1616
	return bitmap;
}

1617
static void its_lpi_free(unsigned long *bitmap, u32 base, u32 nr_ids)
M
Marc Zyngier 已提交
1618
{
1619
	WARN_ON(free_lpi_range(base, nr_ids));
1620
	kfree(bitmap);
M
Marc Zyngier 已提交
1621
}
1622

1623 1624 1625 1626 1627 1628 1629 1630 1631
static void gic_reset_prop_table(void *va)
{
	/* Priority 0xa0, Group-1, disabled */
	memset(va, LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1, LPI_PROPBASE_SZ);

	/* Make sure the GIC will observe the written configuration */
	gic_flush_dcache_to_poc(va, LPI_PROPBASE_SZ);
}

1632 1633 1634
static struct page *its_allocate_prop_table(gfp_t gfp_flags)
{
	struct page *prop_page;
1635

1636 1637 1638 1639
	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
	if (!prop_page)
		return NULL;

1640
	gic_reset_prop_table(page_address(prop_page));
1641 1642 1643 1644

	return prop_page;
}

1645 1646 1647 1648 1649
static void its_free_prop_table(struct page *prop_page)
{
	free_pages((unsigned long)page_address(prop_page),
		   get_order(LPI_PROPBASE_SZ));
}
1650

1651
static int __init its_setup_lpi_prop_table(void)
1652
{
1653
	struct page *page;
1654

1655 1656
	lpi_id_bits = min_t(u32, GICD_TYPER_ID_BITS(gic_rdists->gicd_typer),
				ITS_MAX_LPI_NRBITS);
1657 1658
	page = its_allocate_prop_table(GFP_NOWAIT);
	if (!page) {
1659 1660 1661 1662
		pr_err("Failed to allocate PROPBASE\n");
		return -ENOMEM;
	}

1663 1664 1665 1666 1667
	gic_rdists->prop_table_pa = page_to_phys(page);
	gic_rdists->prop_table_va = page_address(page);

	pr_info("GICv3: using LPI property table @%pa\n",
		&gic_rdists->prop_table_pa);
1668

1669
	return its_lpi_init(lpi_id_bits);
1670 1671 1672 1673 1674
}

static const char *its_base_type_string[] = {
	[GITS_BASER_TYPE_DEVICE]	= "Devices",
	[GITS_BASER_TYPE_VCPU]		= "Virtual CPUs",
1675
	[GITS_BASER_TYPE_RESERVED3]	= "Reserved (3)",
1676 1677 1678 1679 1680 1681
	[GITS_BASER_TYPE_COLLECTION]	= "Interrupt Collections",
	[GITS_BASER_TYPE_RESERVED5] 	= "Reserved (5)",
	[GITS_BASER_TYPE_RESERVED6] 	= "Reserved (6)",
	[GITS_BASER_TYPE_RESERVED7] 	= "Reserved (7)",
};

1682 1683 1684 1685
static u64 its_read_baser(struct its_node *its, struct its_baser *baser)
{
	u32 idx = baser - its->tables;

1686
	return gits_read_baser(its->base + GITS_BASER + (idx << 3));
1687 1688 1689 1690 1691 1692 1693
}

static void its_write_baser(struct its_node *its, struct its_baser *baser,
			    u64 val)
{
	u32 idx = baser - its->tables;

1694
	gits_write_baser(val, its->base + GITS_BASER + (idx << 3));
1695 1696 1697
	baser->val = its_read_baser(its, baser);
}

1698
static int its_setup_baser(struct its_node *its, struct its_baser *baser,
1699 1700
			   u64 cache, u64 shr, u32 psz, u32 order,
			   bool indirect)
1701 1702 1703 1704
{
	u64 val = its_read_baser(its, baser);
	u64 esz = GITS_BASER_ENTRY_SIZE(val);
	u64 type = GITS_BASER_TYPE(val);
1705
	u64 baser_phys, tmp;
1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722
	u32 alloc_pages;
	void *base;

retry_alloc_baser:
	alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
	if (alloc_pages > GITS_BASER_PAGES_MAX) {
		pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n",
			&its->phys_base, its_base_type_string[type],
			alloc_pages, GITS_BASER_PAGES_MAX);
		alloc_pages = GITS_BASER_PAGES_MAX;
		order = get_order(GITS_BASER_PAGES_MAX * psz);
	}

	base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, order);
	if (!base)
		return -ENOMEM;

1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738
	baser_phys = virt_to_phys(base);

	/* Check if the physical address of the memory is above 48bits */
	if (IS_ENABLED(CONFIG_ARM64_64K_PAGES) && (baser_phys >> 48)) {

		/* 52bit PA is supported only when PageSize=64K */
		if (psz != SZ_64K) {
			pr_err("ITS: no 52bit PA support when psz=%d\n", psz);
			free_pages((unsigned long)base, order);
			return -ENXIO;
		}

		/* Convert 52bit PA to 48bit field */
		baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
	}

1739
retry_baser:
1740
	val = (baser_phys					 |
1741 1742 1743 1744 1745 1746 1747
		(type << GITS_BASER_TYPE_SHIFT)			 |
		((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT)	 |
		((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT)	 |
		cache						 |
		shr						 |
		GITS_BASER_VALID);

1748 1749
	val |=	indirect ? GITS_BASER_INDIRECT : 0x0;

1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775
	switch (psz) {
	case SZ_4K:
		val |= GITS_BASER_PAGE_SIZE_4K;
		break;
	case SZ_16K:
		val |= GITS_BASER_PAGE_SIZE_16K;
		break;
	case SZ_64K:
		val |= GITS_BASER_PAGE_SIZE_64K;
		break;
	}

	its_write_baser(its, baser, val);
	tmp = baser->val;

	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
		/*
		 * Shareability didn't stick. Just use
		 * whatever the read reported, which is likely
		 * to be the only thing this redistributor
		 * supports. If that's zero, make it
		 * non-cacheable as well.
		 */
		shr = tmp & GITS_BASER_SHAREABILITY_MASK;
		if (!shr) {
			cache = GITS_BASER_nC;
1776
			gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793 1794 1795 1796 1797 1798 1799 1800
		}
		goto retry_baser;
	}

	if ((val ^ tmp) & GITS_BASER_PAGE_SIZE_MASK) {
		/*
		 * Page size didn't stick. Let's try a smaller
		 * size and retry. If we reach 4K, then
		 * something is horribly wrong...
		 */
		free_pages((unsigned long)base, order);
		baser->base = NULL;

		switch (psz) {
		case SZ_16K:
			psz = SZ_4K;
			goto retry_alloc_baser;
		case SZ_64K:
			psz = SZ_16K;
			goto retry_alloc_baser;
		}
	}

	if (val != tmp) {
1801
		pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n",
1802
		       &its->phys_base, its_base_type_string[type],
1803
		       val, tmp);
1804 1805 1806 1807 1808 1809 1810
		free_pages((unsigned long)base, order);
		return -ENXIO;
	}

	baser->order = order;
	baser->base = base;
	baser->psz = psz;
1811
	tmp = indirect ? GITS_LVL1_ENTRY_SIZE : esz;
1812

1813
	pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n",
1814
		&its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp),
1815 1816
		its_base_type_string[type],
		(unsigned long)virt_to_phys(base),
1817
		indirect ? "indirect" : "flat", (int)esz,
1818 1819 1820 1821 1822
		psz / SZ_1K, (int)shr >> GITS_BASER_SHAREABILITY_SHIFT);

	return 0;
}

1823 1824
static bool its_parse_indirect_baser(struct its_node *its,
				     struct its_baser *baser,
1825
				     u32 psz, u32 *order, u32 ids)
1826
{
1827 1828 1829
	u64 tmp = its_read_baser(its, baser);
	u64 type = GITS_BASER_TYPE(tmp);
	u64 esz = GITS_BASER_ENTRY_SIZE(tmp);
1830
	u64 val = GITS_BASER_InnerShareable | GITS_BASER_RaWaWb;
1831
	u32 new_order = *order;
1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850
	bool indirect = false;

	/* No need to enable Indirection if memory requirement < (psz*2)bytes */
	if ((esz << ids) > (psz * 2)) {
		/*
		 * Find out whether hw supports a single or two-level table by
		 * table by reading bit at offset '62' after writing '1' to it.
		 */
		its_write_baser(its, baser, val | GITS_BASER_INDIRECT);
		indirect = !!(baser->val & GITS_BASER_INDIRECT);

		if (indirect) {
			/*
			 * The size of the lvl2 table is equal to ITS page size
			 * which is 'psz'. For computing lvl1 table size,
			 * subtract ID bits that sparse lvl2 table from 'ids'
			 * which is reported by ITS hardware times lvl1 table
			 * entry size.
			 */
1851
			ids -= ilog2(psz / (int)esz);
1852 1853 1854
			esz = GITS_LVL1_ENTRY_SIZE;
		}
	}
1855 1856 1857 1858 1859

	/*
	 * Allocate as many entries as required to fit the
	 * range of device IDs that the ITS can grok... The ID
	 * space being incredibly sparse, this results in a
1860 1861
	 * massive waste of memory if two-level device table
	 * feature is not supported by hardware.
1862 1863 1864 1865
	 */
	new_order = max_t(u32, get_order(esz << ids), new_order);
	if (new_order >= MAX_ORDER) {
		new_order = MAX_ORDER - 1;
1866
		ids = ilog2(PAGE_ORDER_TO_SIZE(new_order) / (int)esz);
1867 1868 1869
		pr_warn("ITS@%pa: %s Table too large, reduce ids %u->%u\n",
			&its->phys_base, its_base_type_string[type],
			its->device_ids, ids);
1870 1871 1872
	}

	*order = new_order;
1873 1874

	return indirect;
1875 1876
}

1877 1878 1879 1880 1881
static void its_free_tables(struct its_node *its)
{
	int i;

	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1882 1883 1884 1885
		if (its->tables[i].base) {
			free_pages((unsigned long)its->tables[i].base,
				   its->tables[i].order);
			its->tables[i].base = NULL;
1886 1887 1888 1889
		}
	}
}

1890
static int its_alloc_tables(struct its_node *its)
1891 1892
{
	u64 shr = GITS_BASER_InnerShareable;
1893
	u64 cache = GITS_BASER_RaWaWb;
1894 1895
	u32 psz = SZ_64K;
	int err, i;
1896

1897 1898 1899
	if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375)
		/* erratum 24313: ignore memory access type */
		cache = GITS_BASER_nCnB;
1900

1901
	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
1902 1903
		struct its_baser *baser = its->tables + i;
		u64 val = its_read_baser(its, baser);
1904
		u64 type = GITS_BASER_TYPE(val);
1905
		u32 order = get_order(psz);
1906
		bool indirect = false;
1907

1908 1909
		switch (type) {
		case GITS_BASER_TYPE_NONE:
1910 1911
			continue;

1912
		case GITS_BASER_TYPE_DEVICE:
1913 1914 1915
			indirect = its_parse_indirect_baser(its, baser,
							    psz, &order,
							    its->device_ids);
1916 1917
			break;

1918 1919
		case GITS_BASER_TYPE_VCPU:
			indirect = its_parse_indirect_baser(its, baser,
1920 1921
							    psz, &order,
							    ITS_MAX_VPEID_BITS);
1922 1923
			break;
		}
1924

1925
		err = its_setup_baser(its, baser, cache, shr, psz, order, indirect);
1926 1927 1928
		if (err < 0) {
			its_free_tables(its);
			return err;
1929 1930
		}

1931 1932 1933 1934
		/* Update settings which will be used for next BASERn */
		psz = baser->psz;
		cache = baser->val & GITS_BASER_CACHEABILITY_MASK;
		shr = baser->val & GITS_BASER_SHAREABILITY_MASK;
1935 1936 1937 1938 1939 1940 1941
	}

	return 0;
}

static int its_alloc_collections(struct its_node *its)
{
1942 1943
	int i;

K
Kees Cook 已提交
1944
	its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections),
1945 1946 1947 1948
				   GFP_KERNEL);
	if (!its->collections)
		return -ENOMEM;

1949 1950 1951
	for (i = 0; i < nr_cpu_ids; i++)
		its->collections[i].target_address = ~0ULL;

1952 1953 1954
	return 0;
}

1955 1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970 1971 1972
static struct page *its_allocate_pending_table(gfp_t gfp_flags)
{
	struct page *pend_page;
	/*
	 * The pending pages have to be at least 64kB aligned,
	 * hence the 'max(LPI_PENDBASE_SZ, SZ_64K)' below.
	 */
	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
				get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K)));
	if (!pend_page)
		return NULL;

	/* Make sure the GIC will observe the zero-ed page */
	gic_flush_dcache_to_poc(page_address(pend_page), LPI_PENDBASE_SZ);

	return pend_page;
}

1973 1974 1975 1976 1977 1978
static void its_free_pending_table(struct page *pt)
{
	free_pages((unsigned long)page_address(pt),
		   get_order(max_t(u32, LPI_PENDBASE_SZ, SZ_64K)));
}

1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001
static u64 its_clear_vpend_valid(void __iomem *vlpi_base)
{
	u32 count = 1000000;	/* 1s! */
	bool clean;
	u64 val;

	val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
	val &= ~GICR_VPENDBASER_Valid;
	gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);

	do {
		val = gits_read_vpendbaser(vlpi_base + GICR_VPENDBASER);
		clean = !(val & GICR_VPENDBASER_Dirty);
		if (!clean) {
			count--;
			cpu_relax();
			udelay(1);
		}
	} while (!clean && count);

	return val;
}

2002
static int __init allocate_lpi_tables(void)
2003
{
2004
	int err, cpu;
2005

2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016
	err = its_setup_lpi_prop_table();
	if (err)
		return err;

	/*
	 * We allocate all the pending tables anyway, as we may have a
	 * mix of RDs that have had LPIs enabled, and some that
	 * don't. We'll free the unused ones as each CPU comes online.
	 */
	for_each_possible_cpu(cpu) {
		struct page *pend_page;
2017 2018

		pend_page = its_allocate_pending_table(GFP_NOWAIT);
2019
		if (!pend_page) {
2020 2021
			pr_err("Failed to allocate PENDBASE for CPU%d\n", cpu);
			return -ENOMEM;
2022 2023
		}

2024
		gic_data_rdist_cpu(cpu)->pend_page = pend_page;
2025 2026
	}

2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042
	return 0;
}

static void its_cpu_init_lpis(void)
{
	void __iomem *rbase = gic_data_rdist_rd_base();
	struct page *pend_page;
	phys_addr_t paddr;
	u64 val, tmp;

	if (gic_data_rdist()->lpi_enabled)
		return;

	pend_page = gic_data_rdist()->pend_page;
	paddr = page_to_phys(pend_page);

2043
	/* set PROPBASE */
2044
	val = (gic_rdists->prop_table_pa |
2045
	       GICR_PROPBASER_InnerShareable |
2046
	       GICR_PROPBASER_RaWaWb |
2047 2048
	       ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK));

2049 2050
	gicr_write_propbaser(val, rbase + GICR_PROPBASER);
	tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
2051 2052

	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
2053 2054 2055 2056 2057 2058 2059 2060 2061
		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
			/*
			 * The HW reports non-shareable, we must
			 * remove the cacheability attributes as
			 * well.
			 */
			val &= ~(GICR_PROPBASER_SHAREABILITY_MASK |
				 GICR_PROPBASER_CACHEABILITY_MASK);
			val |= GICR_PROPBASER_nC;
2062
			gicr_write_propbaser(val, rbase + GICR_PROPBASER);
2063
		}
2064 2065 2066 2067 2068 2069
		pr_info_once("GIC: using cache flushing for LPI property table\n");
		gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING;
	}

	/* set PENDBASE */
	val = (page_to_phys(pend_page) |
2070
	       GICR_PENDBASER_InnerShareable |
2071
	       GICR_PENDBASER_RaWaWb);
2072

2073 2074
	gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
	tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
2075 2076 2077 2078 2079 2080 2081 2082 2083

	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
		/*
		 * The HW reports non-shareable, we must remove the
		 * cacheability attributes as well.
		 */
		val &= ~(GICR_PENDBASER_SHAREABILITY_MASK |
			 GICR_PENDBASER_CACHEABILITY_MASK);
		val |= GICR_PENDBASER_nC;
2084
		gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
2085
	}
2086 2087 2088 2089 2090 2091

	/* Enable LPIs */
	val = readl_relaxed(rbase + GICR_CTLR);
	val |= GICR_CTLR_ENABLE_LPIS;
	writel_relaxed(val, rbase + GICR_CTLR);

2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115
	if (gic_rdists->has_vlpis) {
		void __iomem *vlpi_base = gic_data_rdist_vlpi_base();

		/*
		 * It's possible for CPU to receive VLPIs before it is
		 * sheduled as a vPE, especially for the first CPU, and the
		 * VLPI with INTID larger than 2^(IDbits+1) will be considered
		 * as out of range and dropped by GIC.
		 * So we initialize IDbits to known value to avoid VLPI drop.
		 */
		val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
		pr_debug("GICv4: CPU%d: Init IDbits to 0x%llx for GICR_VPROPBASER\n",
			smp_processor_id(), val);
		gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);

		/*
		 * Also clear Valid bit of GICR_VPENDBASER, in case some
		 * ancient programming gets left in and has possibility of
		 * corrupting memory.
		 */
		val = its_clear_vpend_valid(vlpi_base);
		WARN_ON(val & GICR_VPENDBASER_Dirty);
	}

2116 2117
	/* Make sure the GIC has seen the above */
	dsb(sy);
2118 2119 2120 2121
	gic_data_rdist()->lpi_enabled = true;
	pr_info("GICv3: CPU%d: using LPI pending table @%pa\n",
		smp_processor_id(),
		&paddr);
2122 2123
}

2124
static void its_cpu_init_collection(struct its_node *its)
2125
{
2126 2127
	int cpu = smp_processor_id();
	u64 target;
2128

2129 2130 2131
	/* avoid cross node collections and its mapping */
	if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) {
		struct device_node *cpu_node;
2132

2133 2134 2135 2136 2137
		cpu_node = of_get_cpu_node(cpu, NULL);
		if (its->numa_node != NUMA_NO_NODE &&
			its->numa_node != of_node_to_nid(cpu_node))
			return;
	}
2138

2139 2140 2141 2142 2143
	/*
	 * We now have to bind each collection to its target
	 * redistributor.
	 */
	if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) {
2144
		/*
2145
		 * This ITS wants the physical address of the
2146 2147
		 * redistributor.
		 */
2148 2149 2150 2151 2152 2153
		target = gic_data_rdist()->phys_base;
	} else {
		/* This ITS wants a linear CPU number. */
		target = gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER);
		target = GICR_TYPER_CPU_NUMBER(target) << 16;
	}
2154

2155 2156 2157
	/* Perform collection mapping */
	its->collections[cpu].target_address = target;
	its->collections[cpu].col_id = cpu;
2158

2159 2160 2161 2162 2163 2164 2165 2166
	its_send_mapc(its, &its->collections[cpu], 1);
	its_send_invall(its, &its->collections[cpu]);
}

static void its_cpu_init_collections(void)
{
	struct its_node *its;

2167
	raw_spin_lock(&its_lock);
2168 2169 2170

	list_for_each_entry(its, &its_nodes, entry)
		its_cpu_init_collection(its);
2171

2172
	raw_spin_unlock(&its_lock);
2173
}
2174 2175 2176 2177

static struct its_device *its_find_device(struct its_node *its, u32 dev_id)
{
	struct its_device *its_dev = NULL, *tmp;
2178
	unsigned long flags;
2179

2180
	raw_spin_lock_irqsave(&its->lock, flags);
2181 2182 2183 2184 2185 2186 2187 2188

	list_for_each_entry(tmp, &its->its_device_list, entry) {
		if (tmp->device_id == dev_id) {
			its_dev = tmp;
			break;
		}
	}

2189
	raw_spin_unlock_irqrestore(&its->lock, flags);
2190 2191 2192 2193

	return its_dev;
}

2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205
static struct its_baser *its_get_baser(struct its_node *its, u32 type)
{
	int i;

	for (i = 0; i < GITS_BASER_NR_REGS; i++) {
		if (GITS_BASER_TYPE(its->tables[i].val) == type)
			return &its->tables[i];
	}

	return NULL;
}

2206
static bool its_alloc_table_entry(struct its_baser *baser, u32 id)
2207 2208 2209 2210 2211 2212 2213 2214
{
	struct page *page;
	u32 esz, idx;
	__le64 *table;

	/* Don't allow device id that exceeds single, flat table limit */
	esz = GITS_BASER_ENTRY_SIZE(baser->val);
	if (!(baser->val & GITS_BASER_INDIRECT))
2215
		return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz));
2216 2217

	/* Compute 1st level table index & check if that exceeds table limit */
2218
	idx = id >> ilog2(baser->psz / esz);
2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231
	if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE))
		return false;

	table = baser->base;

	/* Allocate memory for 2nd level table */
	if (!table[idx]) {
		page = alloc_pages(GFP_KERNEL | __GFP_ZERO, get_order(baser->psz));
		if (!page)
			return false;

		/* Flush Lvl2 table to PoC if hw doesn't support coherency */
		if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2232
			gic_flush_dcache_to_poc(page_address(page), baser->psz);
2233 2234 2235 2236 2237

		table[idx] = cpu_to_le64(page_to_phys(page) | GITS_BASER_VALID);

		/* Flush Lvl1 entry to PoC if hw doesn't support coherency */
		if (!(baser->val & GITS_BASER_SHAREABILITY_MASK))
2238
			gic_flush_dcache_to_poc(table + idx, GITS_LVL1_ENTRY_SIZE);
2239 2240 2241 2242 2243 2244 2245 2246

		/* Ensure updated table contents are visible to ITS hardware */
		dsb(sy);
	}

	return true;
}

2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259
static bool its_alloc_device_table(struct its_node *its, u32 dev_id)
{
	struct its_baser *baser;

	baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE);

	/* Don't allow device id that exceeds ITS hardware limit */
	if (!baser)
		return (ilog2(dev_id) < its->device_ids);

	return its_alloc_table_entry(baser, dev_id);
}

2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275
static bool its_alloc_vpe_table(u32 vpe_id)
{
	struct its_node *its;

	/*
	 * Make sure the L2 tables are allocated on *all* v4 ITSs. We
	 * could try and only do it on ITSs corresponding to devices
	 * that have interrupts targeted at this VPE, but the
	 * complexity becomes crazy (and you have tons of memory
	 * anyway, right?).
	 */
	list_for_each_entry(its, &its_nodes, entry) {
		struct its_baser *baser;

		if (!its->is_v4)
			continue;
2276

2277 2278 2279
		baser = its_get_baser(its, GITS_BASER_TYPE_VCPU);
		if (!baser)
			return false;
2280

2281 2282
		if (!its_alloc_table_entry(baser, vpe_id))
			return false;
2283 2284 2285 2286 2287
	}

	return true;
}

2288
static struct its_device *its_create_device(struct its_node *its, u32 dev_id,
2289
					    int nvecs, bool alloc_lpis)
2290 2291
{
	struct its_device *dev;
2292
	unsigned long *lpi_map = NULL;
2293
	unsigned long flags;
2294
	u16 *col_map = NULL;
2295 2296 2297
	void *itt;
	int lpi_base;
	int nr_lpis;
2298
	int nr_ites;
2299 2300
	int sz;

2301
	if (!its_alloc_device_table(its, dev_id))
2302 2303
		return NULL;

2304 2305 2306
	if (WARN_ON(!is_power_of_2(nvecs)))
		nvecs = roundup_pow_of_two(nvecs);

2307
	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2308
	/*
2309 2310
	 * Even if the device wants a single LPI, the ITT must be
	 * sized as a power of two (and you need at least one bit...).
2311
	 */
2312
	nr_ites = max(2, nvecs);
2313
	sz = nr_ites * its->ite_size;
2314
	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
2315
	itt = kzalloc(sz, GFP_KERNEL);
2316
	if (alloc_lpis) {
2317
		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
2318
		if (lpi_map)
K
Kees Cook 已提交
2319
			col_map = kcalloc(nr_lpis, sizeof(*col_map),
2320 2321
					  GFP_KERNEL);
	} else {
K
Kees Cook 已提交
2322
		col_map = kcalloc(nr_ites, sizeof(*col_map), GFP_KERNEL);
2323 2324 2325
		nr_lpis = 0;
		lpi_base = 0;
	}
2326

2327
	if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
2328 2329 2330
		kfree(dev);
		kfree(itt);
		kfree(lpi_map);
2331
		kfree(col_map);
2332 2333 2334
		return NULL;
	}

2335
	gic_flush_dcache_to_poc(itt, sz);
2336

2337 2338
	dev->its = its;
	dev->itt = itt;
2339
	dev->nr_ites = nr_ites;
2340 2341 2342 2343
	dev->event_map.lpi_map = lpi_map;
	dev->event_map.col_map = col_map;
	dev->event_map.lpi_base = lpi_base;
	dev->event_map.nr_lpis = nr_lpis;
2344
	mutex_init(&dev->event_map.vlpi_lock);
2345 2346 2347
	dev->device_id = dev_id;
	INIT_LIST_HEAD(&dev->entry);

2348
	raw_spin_lock_irqsave(&its->lock, flags);
2349
	list_add(&dev->entry, &its->its_device_list);
2350
	raw_spin_unlock_irqrestore(&its->lock, flags);
2351 2352 2353 2354 2355 2356 2357 2358 2359

	/* Map device to its ITT */
	its_send_mapd(dev, 1);

	return dev;
}

static void its_free_device(struct its_device *its_dev)
{
2360 2361 2362
	unsigned long flags;

	raw_spin_lock_irqsave(&its_dev->its->lock, flags);
2363
	list_del(&its_dev->entry);
2364
	raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
2365 2366 2367
	kfree(its_dev->itt);
	kfree(its_dev);
}
M
Marc Zyngier 已提交
2368

2369
static int its_alloc_device_irq(struct its_device *dev, int nvecs, irq_hw_number_t *hwirq)
M
Marc Zyngier 已提交
2370 2371 2372
{
	int idx;

2373 2374 2375 2376
	idx = bitmap_find_free_region(dev->event_map.lpi_map,
				      dev->event_map.nr_lpis,
				      get_count_order(nvecs));
	if (idx < 0)
M
Marc Zyngier 已提交
2377 2378
		return -ENOSPC;

2379 2380
	*hwirq = dev->event_map.lpi_base + idx;
	set_bit(idx, dev->event_map.lpi_map);
M
Marc Zyngier 已提交
2381 2382 2383 2384

	return 0;
}

2385 2386
static int its_msi_prepare(struct irq_domain *domain, struct device *dev,
			   int nvec, msi_alloc_info_t *info)
2387
{
M
Marc Zyngier 已提交
2388 2389
	struct its_node *its;
	struct its_device *its_dev;
2390 2391
	struct msi_domain_info *msi_info;
	u32 dev_id;
2392
	int err = 0;
2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403

	/*
	 * We ignore "dev" entierely, and rely on the dev_id that has
	 * been passed via the scratchpad. This limits this domain's
	 * usefulness to upper layers that definitely know that they
	 * are built on top of the ITS.
	 */
	dev_id = info->scratchpad[0].ul;

	msi_info = msi_get_domain_info(domain);
	its = msi_info->data;
2404

2405 2406 2407 2408 2409 2410 2411 2412 2413 2414
	if (!gic_rdists->has_direct_lpi &&
	    vpe_proxy.dev &&
	    vpe_proxy.dev->its == its &&
	    dev_id == vpe_proxy.dev->device_id) {
		/* Bad luck. Get yourself a better implementation */
		WARN_ONCE(1, "DevId %x clashes with GICv4 VPE proxy device\n",
			  dev_id);
		return -EINVAL;
	}

2415
	mutex_lock(&its->dev_alloc_lock);
2416
	its_dev = its_find_device(its, dev_id);
2417 2418 2419 2420 2421 2422
	if (its_dev) {
		/*
		 * We already have seen this ID, probably through
		 * another alias (PCI bridge of some sort). No need to
		 * create the device.
		 */
2423
		its_dev->shared = true;
2424
		pr_debug("Reusing ITT for devID %x\n", dev_id);
2425 2426
		goto out;
	}
M
Marc Zyngier 已提交
2427

2428
	its_dev = its_create_device(its, dev_id, nvec, true);
2429 2430 2431 2432
	if (!its_dev) {
		err = -ENOMEM;
		goto out;
	}
M
Marc Zyngier 已提交
2433

2434
	pr_debug("ITT %d entries, %d bits\n", nvec, ilog2(nvec));
2435
out:
2436
	mutex_unlock(&its->dev_alloc_lock);
M
Marc Zyngier 已提交
2437
	info->scratchpad[0].ptr = its_dev;
2438
	return err;
M
Marc Zyngier 已提交
2439 2440
}

2441 2442 2443 2444
static struct msi_domain_ops its_msi_domain_ops = {
	.msi_prepare	= its_msi_prepare,
};

M
Marc Zyngier 已提交
2445 2446 2447 2448
static int its_irq_gic_domain_alloc(struct irq_domain *domain,
				    unsigned int virq,
				    irq_hw_number_t hwirq)
{
2449 2450 2451 2452 2453 2454 2455 2456
	struct irq_fwspec fwspec;

	if (irq_domain_get_of_node(domain->parent)) {
		fwspec.fwnode = domain->parent->fwnode;
		fwspec.param_count = 3;
		fwspec.param[0] = GIC_IRQ_TYPE_LPI;
		fwspec.param[1] = hwirq;
		fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
2457 2458 2459 2460 2461
	} else if (is_fwnode_irqchip(domain->parent->fwnode)) {
		fwspec.fwnode = domain->parent->fwnode;
		fwspec.param_count = 2;
		fwspec.param[0] = hwirq;
		fwspec.param[1] = IRQ_TYPE_EDGE_RISING;
2462 2463 2464
	} else {
		return -EINVAL;
	}
M
Marc Zyngier 已提交
2465

2466
	return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
M
Marc Zyngier 已提交
2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477
}

static int its_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				unsigned int nr_irqs, void *args)
{
	msi_alloc_info_t *info = args;
	struct its_device *its_dev = info->scratchpad[0].ptr;
	irq_hw_number_t hwirq;
	int err;
	int i;

2478 2479 2480
	err = its_alloc_device_irq(its_dev, nr_irqs, &hwirq);
	if (err)
		return err;
M
Marc Zyngier 已提交
2481

2482 2483
	for (i = 0; i < nr_irqs; i++) {
		err = its_irq_gic_domain_alloc(domain, virq + i, hwirq + i);
M
Marc Zyngier 已提交
2484 2485 2486 2487
		if (err)
			return err;

		irq_domain_set_hwirq_and_chip(domain, virq + i,
2488
					      hwirq + i, &its_irq_chip, its_dev);
2489
		irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq + i)));
2490
		pr_debug("ID:%d pID:%d vID:%d\n",
2491 2492
			 (int)(hwirq + i - its_dev->event_map.lpi_base),
			 (int)(hwirq + i), virq + i);
M
Marc Zyngier 已提交
2493 2494 2495 2496 2497
	}

	return 0;
}

2498
static int its_irq_domain_activate(struct irq_domain *domain,
2499
				   struct irq_data *d, bool reserve)
2500 2501 2502
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);
2503
	const struct cpumask *cpu_mask = cpu_online_mask;
2504
	int cpu;
2505 2506 2507 2508

	/* get the cpu_mask of local node */
	if (its_dev->its->numa_node >= 0)
		cpu_mask = cpumask_of_node(its_dev->its->numa_node);
2509

2510
	/* Bind the LPI to the first possible CPU */
2511 2512 2513 2514 2515 2516 2517 2518
	cpu = cpumask_first_and(cpu_mask, cpu_online_mask);
	if (cpu >= nr_cpu_ids) {
		if (its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)
			return -EINVAL;

		cpu = cpumask_first(cpu_online_mask);
	}

2519 2520
	its_dev->event_map.col_map[event] = cpu;
	irq_data_update_effective_affinity(d, cpumask_of(cpu));
2521

2522
	/* Map the GIC IRQ and event to the device */
2523
	its_send_mapti(its_dev, d->hwirq, event);
2524
	return 0;
2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536
}

static void its_irq_domain_deactivate(struct irq_domain *domain,
				      struct irq_data *d)
{
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
	u32 event = its_get_event_id(d);

	/* Stop the delivery of interrupts */
	its_send_discard(its_dev, event);
}

M
Marc Zyngier 已提交
2537 2538 2539 2540 2541
static void its_irq_domain_free(struct irq_domain *domain, unsigned int virq,
				unsigned int nr_irqs)
{
	struct irq_data *d = irq_domain_get_irq_data(domain, virq);
	struct its_device *its_dev = irq_data_get_irq_chip_data(d);
2542
	struct its_node *its = its_dev->its;
M
Marc Zyngier 已提交
2543 2544 2545 2546 2547
	int i;

	for (i = 0; i < nr_irqs; i++) {
		struct irq_data *data = irq_domain_get_irq_data(domain,
								virq + i);
2548
		u32 event = its_get_event_id(data);
M
Marc Zyngier 已提交
2549 2550

		/* Mark interrupt index as unused */
2551
		clear_bit(event, its_dev->event_map.lpi_map);
M
Marc Zyngier 已提交
2552 2553

		/* Nuke the entry in the domain */
2554
		irq_domain_reset_irq_data(data);
M
Marc Zyngier 已提交
2555 2556
	}

2557 2558 2559 2560 2561 2562 2563 2564
	mutex_lock(&its->dev_alloc_lock);

	/*
	 * If all interrupts have been freed, start mopping the
	 * floor. This is conditionned on the device not being shared.
	 */
	if (!its_dev->shared &&
	    bitmap_empty(its_dev->event_map.lpi_map,
2565
			 its_dev->event_map.nr_lpis)) {
2566 2567 2568
		its_lpi_free(its_dev->event_map.lpi_map,
			     its_dev->event_map.lpi_base,
			     its_dev->event_map.nr_lpis);
2569
		kfree(its_dev->event_map.col_map);
M
Marc Zyngier 已提交
2570 2571 2572 2573 2574 2575

		/* Unmap device/itt */
		its_send_mapd(its_dev, 0);
		its_free_device(its_dev);
	}

2576 2577
	mutex_unlock(&its->dev_alloc_lock);

M
Marc Zyngier 已提交
2578 2579 2580 2581 2582 2583
	irq_domain_free_irqs_parent(domain, virq, nr_irqs);
}

static const struct irq_domain_ops its_domain_ops = {
	.alloc			= its_irq_domain_alloc,
	.free			= its_irq_domain_free,
2584 2585
	.activate		= its_irq_domain_activate,
	.deactivate		= its_irq_domain_deactivate,
M
Marc Zyngier 已提交
2586
};
2587

2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651
/*
 * This is insane.
 *
 * If a GICv4 doesn't implement Direct LPIs (which is extremely
 * likely), the only way to perform an invalidate is to use a fake
 * device to issue an INV command, implying that the LPI has first
 * been mapped to some event on that device. Since this is not exactly
 * cheap, we try to keep that mapping around as long as possible, and
 * only issue an UNMAP if we're short on available slots.
 *
 * Broken by design(tm).
 */
static void its_vpe_db_proxy_unmap_locked(struct its_vpe *vpe)
{
	/* Already unmapped? */
	if (vpe->vpe_proxy_event == -1)
		return;

	its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event);
	vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL;

	/*
	 * We don't track empty slots at all, so let's move the
	 * next_victim pointer if we can quickly reuse that slot
	 * instead of nuking an existing entry. Not clear that this is
	 * always a win though, and this might just generate a ripple
	 * effect... Let's just hope VPEs don't migrate too often.
	 */
	if (vpe_proxy.vpes[vpe_proxy.next_victim])
		vpe_proxy.next_victim = vpe->vpe_proxy_event;

	vpe->vpe_proxy_event = -1;
}

static void its_vpe_db_proxy_unmap(struct its_vpe *vpe)
{
	if (!gic_rdists->has_direct_lpi) {
		unsigned long flags;

		raw_spin_lock_irqsave(&vpe_proxy.lock, flags);
		its_vpe_db_proxy_unmap_locked(vpe);
		raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
	}
}

static void its_vpe_db_proxy_map_locked(struct its_vpe *vpe)
{
	/* Already mapped? */
	if (vpe->vpe_proxy_event != -1)
		return;

	/* This slot was already allocated. Kick the other VPE out. */
	if (vpe_proxy.vpes[vpe_proxy.next_victim])
		its_vpe_db_proxy_unmap_locked(vpe_proxy.vpes[vpe_proxy.next_victim]);

	/* Map the new VPE instead */
	vpe_proxy.vpes[vpe_proxy.next_victim] = vpe;
	vpe->vpe_proxy_event = vpe_proxy.next_victim;
	vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites;

	vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx;
	its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event);
}

2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678
static void its_vpe_db_proxy_move(struct its_vpe *vpe, int from, int to)
{
	unsigned long flags;
	struct its_collection *target_col;

	if (gic_rdists->has_direct_lpi) {
		void __iomem *rdbase;

		rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base;
		gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
		while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
			cpu_relax();

		return;
	}

	raw_spin_lock_irqsave(&vpe_proxy.lock, flags);

	its_vpe_db_proxy_map_locked(vpe);

	target_col = &vpe_proxy.dev->its->collections[to];
	its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event);
	vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to;

	raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
}

2679 2680 2681 2682 2683 2684 2685 2686 2687
static int its_vpe_set_affinity(struct irq_data *d,
				const struct cpumask *mask_val,
				bool force)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
	int cpu = cpumask_first(mask_val);

	/*
	 * Changing affinity is mega expensive, so let's be as lazy as
2688
	 * we can and only do it if we really have to. Also, if mapped
2689 2690
	 * into the proxy device, we need to move the doorbell
	 * interrupt to its new location.
2691 2692
	 */
	if (vpe->col_idx != cpu) {
2693 2694
		int from = vpe->col_idx;

2695 2696
		vpe->col_idx = cpu;
		its_send_vmovp(vpe);
2697
		its_vpe_db_proxy_move(vpe, from, cpu);
2698 2699
	}

2700 2701
	irq_data_update_effective_affinity(d, cpumask_of(cpu));

2702 2703 2704
	return IRQ_SET_MASK_OK_DONE;
}

2705 2706
static void its_vpe_schedule(struct its_vpe *vpe)
{
2707
	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738
	u64 val;

	/* Schedule the VPE */
	val  = virt_to_phys(page_address(vpe->its_vm->vprop_page)) &
		GENMASK_ULL(51, 12);
	val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK;
	val |= GICR_VPROPBASER_RaWb;
	val |= GICR_VPROPBASER_InnerShareable;
	gits_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER);

	val  = virt_to_phys(page_address(vpe->vpt_page)) &
		GENMASK_ULL(51, 16);
	val |= GICR_VPENDBASER_RaWaWb;
	val |= GICR_VPENDBASER_NonShareable;
	/*
	 * There is no good way of finding out if the pending table is
	 * empty as we can race against the doorbell interrupt very
	 * easily. So in the end, vpe->pending_last is only an
	 * indication that the vcpu has something pending, not one
	 * that the pending table is empty. A good implementation
	 * would be able to read its coarse map pretty quickly anyway,
	 * making this a tolerable issue.
	 */
	val |= GICR_VPENDBASER_PendingLast;
	val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0;
	val |= GICR_VPENDBASER_Valid;
	gits_write_vpendbaser(val, vlpi_base + GICR_VPENDBASER);
}

static void its_vpe_deschedule(struct its_vpe *vpe)
{
2739
	void __iomem *vlpi_base = gic_data_rdist_vlpi_base();
2740 2741
	u64 val;

2742
	val = its_clear_vpend_valid(vlpi_base);
2743

2744
	if (unlikely(val & GICR_VPENDBASER_Dirty)) {
2745 2746 2747 2748 2749 2750 2751 2752 2753
		pr_err_ratelimited("ITS virtual pending table not cleaning\n");
		vpe->idai = false;
		vpe->pending_last = true;
	} else {
		vpe->idai = !!(val & GICR_VPENDBASER_IDAI);
		vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast);
	}
}

2754 2755 2756 2757 2758 2759 2760 2761
static void its_vpe_invall(struct its_vpe *vpe)
{
	struct its_node *its;

	list_for_each_entry(its, &its_nodes, entry) {
		if (!its->is_v4)
			continue;

2762 2763 2764
		if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr])
			continue;

2765 2766 2767 2768
		/*
		 * Sending a VINVALL to a single ITS is enough, as all
		 * we need is to reach the redistributors.
		 */
2769
		its_send_vinvall(its, vpe);
2770
		return;
2771 2772 2773
	}
}

2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787
static int its_vpe_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
	struct its_cmd_info *info = vcpu_info;

	switch (info->cmd_type) {
	case SCHEDULE_VPE:
		its_vpe_schedule(vpe);
		return 0;

	case DESCHEDULE_VPE:
		its_vpe_deschedule(vpe);
		return 0;

2788
	case INVALL_VPE:
2789
		its_vpe_invall(vpe);
2790 2791
		return 0;

2792 2793 2794 2795 2796
	default:
		return -EINVAL;
	}
}

2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809
static void its_vpe_send_cmd(struct its_vpe *vpe,
			     void (*cmd)(struct its_device *, u32))
{
	unsigned long flags;

	raw_spin_lock_irqsave(&vpe_proxy.lock, flags);

	its_vpe_db_proxy_map_locked(vpe);
	cmd(vpe_proxy.dev, vpe->vpe_proxy_event);

	raw_spin_unlock_irqrestore(&vpe_proxy.lock, flags);
}

2810 2811 2812 2813
static void its_vpe_send_inv(struct irq_data *d)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

2814 2815 2816 2817 2818 2819 2820 2821 2822 2823
	if (gic_rdists->has_direct_lpi) {
		void __iomem *rdbase;

		rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
		gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_INVLPIR);
		while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
			cpu_relax();
	} else {
		its_vpe_send_cmd(vpe, its_send_inv);
	}
2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844
}

static void its_vpe_mask_irq(struct irq_data *d)
{
	/*
	 * We need to unmask the LPI, which is described by the parent
	 * irq_data. Instead of calling into the parent (which won't
	 * exactly do the right thing, let's simply use the
	 * parent_data pointer. Yes, I'm naughty.
	 */
	lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0);
	its_vpe_send_inv(d);
}

static void its_vpe_unmask_irq(struct irq_data *d)
{
	/* Same hack as above... */
	lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED);
	its_vpe_send_inv(d);
}

2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872 2873 2874
static int its_vpe_set_irqchip_state(struct irq_data *d,
				     enum irqchip_irq_state which,
				     bool state)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);

	if (which != IRQCHIP_STATE_PENDING)
		return -EINVAL;

	if (gic_rdists->has_direct_lpi) {
		void __iomem *rdbase;

		rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base;
		if (state) {
			gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR);
		} else {
			gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR);
			while (gic_read_lpir(rdbase + GICR_SYNCR) & 1)
				cpu_relax();
		}
	} else {
		if (state)
			its_vpe_send_cmd(vpe, its_send_int);
		else
			its_vpe_send_cmd(vpe, its_send_clear);
	}

	return 0;
}

2875 2876
static struct irq_chip its_vpe_irq_chip = {
	.name			= "GICv4-vpe",
2877 2878 2879
	.irq_mask		= its_vpe_mask_irq,
	.irq_unmask		= its_vpe_unmask_irq,
	.irq_eoi		= irq_chip_eoi_parent,
2880
	.irq_set_affinity	= its_vpe_set_affinity,
2881
	.irq_set_irqchip_state	= its_vpe_set_irqchip_state,
2882
	.irq_set_vcpu_affinity	= its_vpe_set_vcpu_affinity,
2883 2884
};

2885 2886
static int its_vpe_id_alloc(void)
{
2887
	return ida_simple_get(&its_vpeid_ida, 0, ITS_MAX_VPEID, GFP_KERNEL);
2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919
}

static void its_vpe_id_free(u16 id)
{
	ida_simple_remove(&its_vpeid_ida, id);
}

static int its_vpe_init(struct its_vpe *vpe)
{
	struct page *vpt_page;
	int vpe_id;

	/* Allocate vpe_id */
	vpe_id = its_vpe_id_alloc();
	if (vpe_id < 0)
		return vpe_id;

	/* Allocate VPT */
	vpt_page = its_allocate_pending_table(GFP_KERNEL);
	if (!vpt_page) {
		its_vpe_id_free(vpe_id);
		return -ENOMEM;
	}

	if (!its_alloc_vpe_table(vpe_id)) {
		its_vpe_id_free(vpe_id);
		its_free_pending_table(vpe->vpt_page);
		return -ENOMEM;
	}

	vpe->vpe_id = vpe_id;
	vpe->vpt_page = vpt_page;
2920
	vpe->vpe_proxy_event = -1;
2921 2922 2923 2924 2925 2926

	return 0;
}

static void its_vpe_teardown(struct its_vpe *vpe)
{
2927
	its_vpe_db_proxy_unmap(vpe);
2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953
	its_vpe_id_free(vpe->vpe_id);
	its_free_pending_table(vpe->vpt_page);
}

static void its_vpe_irq_domain_free(struct irq_domain *domain,
				    unsigned int virq,
				    unsigned int nr_irqs)
{
	struct its_vm *vm = domain->host_data;
	int i;

	irq_domain_free_irqs_parent(domain, virq, nr_irqs);

	for (i = 0; i < nr_irqs; i++) {
		struct irq_data *data = irq_domain_get_irq_data(domain,
								virq + i);
		struct its_vpe *vpe = irq_data_get_irq_chip_data(data);

		BUG_ON(vm != vpe->its_vm);

		clear_bit(data->hwirq, vm->db_bitmap);
		its_vpe_teardown(vpe);
		irq_domain_reset_irq_data(data);
	}

	if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) {
2954
		its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis);
2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968
		its_free_prop_table(vm->vprop_page);
	}
}

static int its_vpe_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
				    unsigned int nr_irqs, void *args)
{
	struct its_vm *vm = args;
	unsigned long *bitmap;
	struct page *vprop_page;
	int base, nr_ids, i, err = 0;

	BUG_ON(!vm);

2969
	bitmap = its_lpi_alloc(roundup_pow_of_two(nr_irqs), &base, &nr_ids);
2970 2971 2972 2973
	if (!bitmap)
		return -ENOMEM;

	if (nr_ids < nr_irqs) {
2974
		its_lpi_free(bitmap, base, nr_ids);
2975 2976 2977 2978 2979
		return -ENOMEM;
	}

	vprop_page = its_allocate_prop_table(GFP_KERNEL);
	if (!vprop_page) {
2980
		its_lpi_free(bitmap, base, nr_ids);
2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006
		return -ENOMEM;
	}

	vm->db_bitmap = bitmap;
	vm->db_lpi_base = base;
	vm->nr_db_lpis = nr_ids;
	vm->vprop_page = vprop_page;

	for (i = 0; i < nr_irqs; i++) {
		vm->vpes[i]->vpe_db_lpi = base + i;
		err = its_vpe_init(vm->vpes[i]);
		if (err)
			break;
		err = its_irq_gic_domain_alloc(domain, virq + i,
					       vm->vpes[i]->vpe_db_lpi);
		if (err)
			break;
		irq_domain_set_hwirq_and_chip(domain, virq + i, i,
					      &its_vpe_irq_chip, vm->vpes[i]);
		set_bit(i, bitmap);
	}

	if (err) {
		if (i > 0)
			its_vpe_irq_domain_free(domain, virq, i - 1);

3007
		its_lpi_free(bitmap, base, nr_ids);
3008 3009 3010 3011 3012 3013
		its_free_prop_table(vprop_page);
	}

	return err;
}

3014
static int its_vpe_irq_domain_activate(struct irq_domain *domain,
3015
				       struct irq_data *d, bool reserve)
3016 3017
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3018
	struct its_node *its;
3019

3020 3021
	/* If we use the list map, we issue VMAPP on demand... */
	if (its_list_map)
3022
		return 0;
3023 3024 3025

	/* Map the VPE to the first possible CPU */
	vpe->col_idx = cpumask_first(cpu_online_mask);
3026 3027 3028 3029 3030

	list_for_each_entry(its, &its_nodes, entry) {
		if (!its->is_v4)
			continue;

3031
		its_send_vmapp(its, vpe, true);
3032 3033 3034
		its_send_vinvall(its, vpe);
	}

3035 3036
	irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx));

3037
	return 0;
3038 3039 3040 3041 3042 3043
}

static void its_vpe_irq_domain_deactivate(struct irq_domain *domain,
					  struct irq_data *d)
{
	struct its_vpe *vpe = irq_data_get_irq_chip_data(d);
3044 3045
	struct its_node *its;

3046 3047 3048 3049 3050 3051
	/*
	 * If we use the list map, we unmap the VPE once no VLPIs are
	 * associated with the VM.
	 */
	if (its_list_map)
		return;
3052

3053 3054 3055
	list_for_each_entry(its, &its_nodes, entry) {
		if (!its->is_v4)
			continue;
3056

3057 3058
		its_send_vmapp(its, vpe, false);
	}
3059 3060
}

3061
static const struct irq_domain_ops its_vpe_domain_ops = {
3062 3063
	.alloc			= its_vpe_irq_domain_alloc,
	.free			= its_vpe_irq_domain_free,
3064 3065
	.activate		= its_vpe_irq_domain_activate,
	.deactivate		= its_vpe_irq_domain_deactivate,
3066 3067
};

3068 3069 3070 3071 3072 3073
static int its_force_quiescent(void __iomem *base)
{
	u32 count = 1000000;	/* 1s */
	u32 val;

	val = readl_relaxed(base + GITS_CTLR);
3074 3075 3076 3077 3078 3079
	/*
	 * GIC architecture specification requires the ITS to be both
	 * disabled and quiescent for writes to GITS_BASER<n> or
	 * GITS_CBASER to not have UNPREDICTABLE results.
	 */
	if ((val & GITS_CTLR_QUIESCENT) && !(val & GITS_CTLR_ENABLE))
3080 3081 3082
		return 0;

	/* Disable the generation of all interrupts to this ITS */
3083
	val &= ~(GITS_CTLR_ENABLE | GITS_CTLR_ImDe);
3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100
	writel_relaxed(val, base + GITS_CTLR);

	/* Poll GITS_CTLR and wait until ITS becomes quiescent */
	while (1) {
		val = readl_relaxed(base + GITS_CTLR);
		if (val & GITS_CTLR_QUIESCENT)
			return 0;

		count--;
		if (!count)
			return -EBUSY;

		cpu_relax();
		udelay(1);
	}
}

3101
static bool __maybe_unused its_enable_quirk_cavium_22375(void *data)
3102 3103 3104
{
	struct its_node *its = data;

3105 3106
	/* erratum 22375: only alloc 8MB table size */
	its->device_ids = 0x14;		/* 20 bits, 8MB */
3107
	its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375;
3108 3109

	return true;
3110 3111
}

3112
static bool __maybe_unused its_enable_quirk_cavium_23144(void *data)
3113 3114 3115 3116
{
	struct its_node *its = data;

	its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144;
3117 3118

	return true;
3119 3120
}

3121
static bool __maybe_unused its_enable_quirk_qdf2400_e0065(void *data)
3122 3123 3124 3125 3126
{
	struct its_node *its = data;

	/* On QDF2400, the size of the ITE is 16Bytes */
	its->ite_size = 16;
3127 3128

	return true;
3129 3130
}

3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169
static u64 its_irq_get_msi_base_pre_its(struct its_device *its_dev)
{
	struct its_node *its = its_dev->its;

	/*
	 * The Socionext Synquacer SoC has a so-called 'pre-ITS',
	 * which maps 32-bit writes targeted at a separate window of
	 * size '4 << device_id_bits' onto writes to GITS_TRANSLATER
	 * with device ID taken from bits [device_id_bits + 1:2] of
	 * the window offset.
	 */
	return its->pre_its_base + (its_dev->device_id << 2);
}

static bool __maybe_unused its_enable_quirk_socionext_synquacer(void *data)
{
	struct its_node *its = data;
	u32 pre_its_window[2];
	u32 ids;

	if (!fwnode_property_read_u32_array(its->fwnode_handle,
					   "socionext,synquacer-pre-its",
					   pre_its_window,
					   ARRAY_SIZE(pre_its_window))) {

		its->pre_its_base = pre_its_window[0];
		its->get_msi_base = its_irq_get_msi_base_pre_its;

		ids = ilog2(pre_its_window[1]) - 2;
		if (its->device_ids > ids)
			its->device_ids = ids;

		/* the pre-ITS breaks isolation, so disable MSI remapping */
		its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_MSI_REMAP;
		return true;
	}
	return false;
}

3170 3171 3172 3173 3174 3175 3176 3177 3178 3179
static bool __maybe_unused its_enable_quirk_hip07_161600802(void *data)
{
	struct its_node *its = data;

	/*
	 * Hip07 insists on using the wrong address for the VLPI
	 * page. Trick it into doing the right thing...
	 */
	its->vlpi_redist_offset = SZ_128K;
	return true;
3180 3181
}

3182
static const struct gic_quirk its_quirks[] = {
3183 3184 3185 3186 3187 3188 3189
#ifdef CONFIG_CAVIUM_ERRATUM_22375
	{
		.desc	= "ITS: Cavium errata 22375, 24313",
		.iidr	= 0xa100034c,	/* ThunderX pass 1.x */
		.mask	= 0xffff0fff,
		.init	= its_enable_quirk_cavium_22375,
	},
3190 3191 3192 3193 3194 3195 3196 3197
#endif
#ifdef CONFIG_CAVIUM_ERRATUM_23144
	{
		.desc	= "ITS: Cavium erratum 23144",
		.iidr	= 0xa100034c,	/* ThunderX pass 1.x */
		.mask	= 0xffff0fff,
		.init	= its_enable_quirk_cavium_23144,
	},
3198 3199 3200 3201 3202 3203 3204 3205
#endif
#ifdef CONFIG_QCOM_QDF2400_ERRATUM_0065
	{
		.desc	= "ITS: QDF2400 erratum 0065",
		.iidr	= 0x00001070, /* QDF2400 ITS rev 1.x */
		.mask	= 0xffffffff,
		.init	= its_enable_quirk_qdf2400_e0065,
	},
3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216 3217 3218
#endif
#ifdef CONFIG_SOCIONEXT_SYNQUACER_PREITS
	{
		/*
		 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
		 * implementation, but with a 'pre-ITS' added that requires
		 * special handling in software.
		 */
		.desc	= "ITS: Socionext Synquacer pre-ITS",
		.iidr	= 0x0001143b,
		.mask	= 0xffffffff,
		.init	= its_enable_quirk_socionext_synquacer,
	},
3219 3220 3221 3222 3223 3224 3225 3226
#endif
#ifdef CONFIG_HISILICON_ERRATUM_161600802
	{
		.desc	= "ITS: Hip07 erratum 161600802",
		.iidr	= 0x00000004,
		.mask	= 0xffffffff,
		.init	= its_enable_quirk_hip07_161600802,
	},
3227
#endif
3228 3229 3230 3231 3232 3233 3234 3235 3236 3237 3238
	{
	}
};

static void its_enable_quirks(struct its_node *its)
{
	u32 iidr = readl_relaxed(its->base + GITS_IIDR);

	gic_enable_quirks(iidr, its_quirks, its);
}

3239 3240 3241 3242 3243
static int its_save_disable(void)
{
	struct its_node *its;
	int err = 0;

3244
	raw_spin_lock(&its_lock);
3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275
	list_for_each_entry(its, &its_nodes, entry) {
		void __iomem *base;

		if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
			continue;

		base = its->base;
		its->ctlr_save = readl_relaxed(base + GITS_CTLR);
		err = its_force_quiescent(base);
		if (err) {
			pr_err("ITS@%pa: failed to quiesce: %d\n",
			       &its->phys_base, err);
			writel_relaxed(its->ctlr_save, base + GITS_CTLR);
			goto err;
		}

		its->cbaser_save = gits_read_cbaser(base + GITS_CBASER);
	}

err:
	if (err) {
		list_for_each_entry_continue_reverse(its, &its_nodes, entry) {
			void __iomem *base;

			if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
				continue;

			base = its->base;
			writel_relaxed(its->ctlr_save, base + GITS_CTLR);
		}
	}
3276
	raw_spin_unlock(&its_lock);
3277 3278 3279 3280 3281 3282 3283 3284 3285

	return err;
}

static void its_restore_enable(void)
{
	struct its_node *its;
	int ret;

3286
	raw_spin_lock(&its_lock);
3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327
	list_for_each_entry(its, &its_nodes, entry) {
		void __iomem *base;
		int i;

		if (!(its->flags & ITS_FLAGS_SAVE_SUSPEND_STATE))
			continue;

		base = its->base;

		/*
		 * Make sure that the ITS is disabled. If it fails to quiesce,
		 * don't restore it since writing to CBASER or BASER<n>
		 * registers is undefined according to the GIC v3 ITS
		 * Specification.
		 */
		ret = its_force_quiescent(base);
		if (ret) {
			pr_err("ITS@%pa: failed to quiesce on resume: %d\n",
			       &its->phys_base, ret);
			continue;
		}

		gits_write_cbaser(its->cbaser_save, base + GITS_CBASER);

		/*
		 * Writing CBASER resets CREADR to 0, so make CWRITER and
		 * cmd_write line up with it.
		 */
		its->cmd_write = its->cmd_base;
		gits_write_cwriter(0, base + GITS_CWRITER);

		/* Restore GITS_BASER from the value cache. */
		for (i = 0; i < GITS_BASER_NR_REGS; i++) {
			struct its_baser *baser = &its->tables[i];

			if (!(baser->val & GITS_BASER_VALID))
				continue;

			its_write_baser(its, baser, baser->val);
		}
		writel_relaxed(its->ctlr_save, base + GITS_CTLR);
3328 3329 3330 3331 3332 3333 3334 3335 3336

		/*
		 * Reinit the collection if it's stored in the ITS. This is
		 * indicated by the col_id being less than the HCC field.
		 * CID < HCC as specified in the GIC v3 Documentation.
		 */
		if (its->collections[smp_processor_id()].col_id <
		    GITS_TYPER_HCC(gic_read_typer(base + GITS_TYPER)))
			its_cpu_init_collection(its);
3337
	}
3338
	raw_spin_unlock(&its_lock);
3339 3340 3341 3342 3343 3344 3345
}

static struct syscore_ops its_syscore_ops = {
	.suspend = its_save_disable,
	.resume = its_restore_enable,
};

3346
static int its_init_domain(struct fwnode_handle *handle, struct its_node *its)
3347 3348 3349 3350 3351 3352 3353 3354
{
	struct irq_domain *inner_domain;
	struct msi_domain_info *info;

	info = kzalloc(sizeof(*info), GFP_KERNEL);
	if (!info)
		return -ENOMEM;

3355
	inner_domain = irq_domain_create_tree(handle, &its_domain_ops, its);
3356 3357 3358 3359 3360
	if (!inner_domain) {
		kfree(info);
		return -ENOMEM;
	}

3361
	inner_domain->parent = its_parent;
3362
	irq_domain_update_bus_token(inner_domain, DOMAIN_BUS_NEXUS);
3363
	inner_domain->flags |= its->msi_domain_flags;
3364 3365 3366 3367 3368 3369 3370
	info->ops = &its_msi_domain_ops;
	info->data = its;
	inner_domain->host_data = info;

	return 0;
}

3371 3372
static int its_init_vpe_domain(void)
{
3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385
	struct its_node *its;
	u32 devid;
	int entries;

	if (gic_rdists->has_direct_lpi) {
		pr_info("ITS: Using DirectLPI for VPE invalidation\n");
		return 0;
	}

	/* Any ITS will do, even if not v4 */
	its = list_first_entry(&its_nodes, struct its_node, entry);

	entries = roundup_pow_of_two(nr_cpu_ids);
K
Kees Cook 已提交
3386
	vpe_proxy.vpes = kcalloc(entries, sizeof(*vpe_proxy.vpes),
3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401
				 GFP_KERNEL);
	if (!vpe_proxy.vpes) {
		pr_err("ITS: Can't allocate GICv4 proxy device array\n");
		return -ENOMEM;
	}

	/* Use the last possible DevID */
	devid = GENMASK(its->device_ids - 1, 0);
	vpe_proxy.dev = its_create_device(its, devid, entries, false);
	if (!vpe_proxy.dev) {
		kfree(vpe_proxy.vpes);
		pr_err("ITS: Can't allocate GICv4 proxy device\n");
		return -ENOMEM;
	}

3402
	BUG_ON(entries > vpe_proxy.dev->nr_ites);
3403 3404 3405 3406 3407 3408

	raw_spin_lock_init(&vpe_proxy.lock);
	vpe_proxy.next_victim = 0;
	pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n",
		devid, vpe_proxy.dev->nr_ites);

3409 3410 3411
	return 0;
}

3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423
static int __init its_compute_its_list_map(struct resource *res,
					   void __iomem *its_base)
{
	int its_number;
	u32 ctlr;

	/*
	 * This is assumed to be done early enough that we're
	 * guaranteed to be single-threaded, hence no
	 * locking. Should this change, we should address
	 * this.
	 */
3424 3425
	its_number = find_first_zero_bit(&its_list_map, GICv4_ITS_LIST_MAX);
	if (its_number >= GICv4_ITS_LIST_MAX) {
3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449
		pr_err("ITS@%pa: No ITSList entry available!\n",
		       &res->start);
		return -EINVAL;
	}

	ctlr = readl_relaxed(its_base + GITS_CTLR);
	ctlr &= ~GITS_CTLR_ITS_NUMBER;
	ctlr |= its_number << GITS_CTLR_ITS_NUMBER_SHIFT;
	writel_relaxed(ctlr, its_base + GITS_CTLR);
	ctlr = readl_relaxed(its_base + GITS_CTLR);
	if ((ctlr & GITS_CTLR_ITS_NUMBER) != (its_number << GITS_CTLR_ITS_NUMBER_SHIFT)) {
		its_number = ctlr & GITS_CTLR_ITS_NUMBER;
		its_number >>= GITS_CTLR_ITS_NUMBER_SHIFT;
	}

	if (test_and_set_bit(its_number, &its_list_map)) {
		pr_err("ITS@%pa: Duplicate ITSList entry %d\n",
		       &res->start, its_number);
		return -EINVAL;
	}

	return its_number;
}

3450 3451
static int __init its_probe_one(struct resource *res,
				struct fwnode_handle *handle, int numa_node)
3452 3453 3454
{
	struct its_node *its;
	void __iomem *its_base;
3455 3456
	u32 val, ctlr;
	u64 baser, tmp, typer;
3457 3458
	int err;

3459
	its_base = ioremap(res->start, resource_size(res));
3460
	if (!its_base) {
3461
		pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start);
3462 3463 3464 3465 3466
		return -ENOMEM;
	}

	val = readl_relaxed(its_base + GITS_PIDR2) & GIC_PIDR2_ARCH_MASK;
	if (val != 0x30 && val != 0x40) {
3467
		pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start);
3468 3469 3470 3471
		err = -ENODEV;
		goto out_unmap;
	}

3472 3473
	err = its_force_quiescent(its_base);
	if (err) {
3474
		pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start);
3475 3476 3477
		goto out_unmap;
	}

3478
	pr_info("ITS %pR\n", res);
3479 3480 3481 3482 3483 3484 3485 3486

	its = kzalloc(sizeof(*its), GFP_KERNEL);
	if (!its) {
		err = -ENOMEM;
		goto out_unmap;
	}

	raw_spin_lock_init(&its->lock);
3487
	mutex_init(&its->dev_alloc_lock);
3488 3489
	INIT_LIST_HEAD(&its->entry);
	INIT_LIST_HEAD(&its->its_device_list);
3490
	typer = gic_read_typer(its_base + GITS_TYPER);
3491
	its->base = its_base;
3492
	its->phys_base = res->start;
3493
	its->ite_size = GITS_TYPER_ITT_ENTRY_SIZE(typer);
3494
	its->device_ids = GITS_TYPER_DEVBITS(typer);
3495 3496 3497 3498 3499 3500 3501
	its->is_v4 = !!(typer & GITS_TYPER_VLPIS);
	if (its->is_v4) {
		if (!(typer & GITS_TYPER_VMOVP)) {
			err = its_compute_its_list_map(res, its_base);
			if (err < 0)
				goto out_free_its;

3502 3503
			its->list_nr = err;

3504 3505 3506 3507 3508 3509 3510
			pr_info("ITS@%pa: Using ITS number %d\n",
				&res->start, err);
		} else {
			pr_info("ITS@%pa: Single VMOVP capable\n", &res->start);
		}
	}

3511
	its->numa_node = numa_node;
3512

3513 3514
	its->cmd_base = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
						get_order(ITS_CMD_QUEUE_SZ));
3515 3516 3517 3518 3519
	if (!its->cmd_base) {
		err = -ENOMEM;
		goto out_free_its;
	}
	its->cmd_write = its->cmd_base;
3520 3521 3522
	its->fwnode_handle = handle;
	its->get_msi_base = its_irq_get_msi_base;
	its->msi_domain_flags = IRQ_DOMAIN_FLAG_MSI_REMAP;
3523

3524 3525
	its_enable_quirks(its);

3526
	err = its_alloc_tables(its);
3527 3528 3529 3530 3531 3532 3533 3534
	if (err)
		goto out_free_cmd;

	err = its_alloc_collections(its);
	if (err)
		goto out_free_tables;

	baser = (virt_to_phys(its->cmd_base)	|
3535
		 GITS_CBASER_RaWaWb		|
3536 3537 3538 3539
		 GITS_CBASER_InnerShareable	|
		 (ITS_CMD_QUEUE_SZ / SZ_4K - 1)	|
		 GITS_CBASER_VALID);

3540 3541
	gits_write_cbaser(baser, its->base + GITS_CBASER);
	tmp = gits_read_cbaser(its->base + GITS_CBASER);
3542

3543
	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
3544 3545 3546 3547 3548 3549 3550 3551 3552
		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
			/*
			 * The HW reports non-shareable, we must
			 * remove the cacheability attributes as
			 * well.
			 */
			baser &= ~(GITS_CBASER_SHAREABILITY_MASK |
				   GITS_CBASER_CACHEABILITY_MASK);
			baser |= GITS_CBASER_nC;
3553
			gits_write_cbaser(baser, its->base + GITS_CBASER);
3554
		}
3555 3556 3557 3558
		pr_info("ITS: using cache flushing for cmd queue\n");
		its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING;
	}

3559
	gits_write_cwriter(0, its->base + GITS_CWRITER);
3560
	ctlr = readl_relaxed(its->base + GITS_CTLR);
3561 3562 3563 3564
	ctlr |= GITS_CTLR_ENABLE;
	if (its->is_v4)
		ctlr |= GITS_CTLR_ImDe;
	writel_relaxed(ctlr, its->base + GITS_CTLR);
3565

3566 3567 3568
	if (GITS_TYPER_HCC(typer))
		its->flags |= ITS_FLAGS_SAVE_SUSPEND_STATE;

3569
	err = its_init_domain(handle, its);
3570 3571
	if (err)
		goto out_free_tables;
3572

3573
	raw_spin_lock(&its_lock);
3574
	list_add(&its->entry, &its_nodes);
3575
	raw_spin_unlock(&its_lock);
3576 3577 3578 3579 3580 3581

	return 0;

out_free_tables:
	its_free_tables(its);
out_free_cmd:
3582
	free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ));
3583 3584 3585 3586
out_free_its:
	kfree(its);
out_unmap:
	iounmap(its_base);
3587
	pr_err("ITS@%pa: failed probing (%d)\n", &res->start, err);
3588 3589 3590 3591 3592
	return err;
}

static bool gic_rdists_supports_plpis(void)
{
3593
	return !!(gic_read_typer(gic_data_rdist_rd_base() + GICR_TYPER) & GICR_TYPER_PLPIS);
3594 3595
}

3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610
static int redist_disable_lpis(void)
{
	void __iomem *rbase = gic_data_rdist_rd_base();
	u64 timeout = USEC_PER_SEC;
	u64 val;

	if (!gic_rdists_supports_plpis()) {
		pr_info("CPU%d: LPIs not supported\n", smp_processor_id());
		return -ENXIO;
	}

	val = readl_relaxed(rbase + GICR_CTLR);
	if (!(val & GICR_CTLR_ENABLE_LPIS))
		return 0;

3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622
	/*
	 * If coming via a CPU hotplug event, we don't need to disable
	 * LPIs before trying to re-enable them. They are already
	 * configured and all is well in the world.
	 */
	if (gic_data_rdist()->lpi_enabled)
		return 0;

	/*
	 * From that point on, we only try to do some damage control.
	 */
	pr_warn("GICv3: CPU%d: Booted with LPIs enabled, memory probably corrupted\n",
3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652 3653 3654 3655 3656 3657 3658 3659 3660
		smp_processor_id());
	add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);

	/* Disable LPIs */
	val &= ~GICR_CTLR_ENABLE_LPIS;
	writel_relaxed(val, rbase + GICR_CTLR);

	/* Make sure any change to GICR_CTLR is observable by the GIC */
	dsb(sy);

	/*
	 * Software must observe RWP==0 after clearing GICR_CTLR.EnableLPIs
	 * from 1 to 0 before programming GICR_PEND{PROP}BASER registers.
	 * Error out if we time out waiting for RWP to clear.
	 */
	while (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_RWP) {
		if (!timeout) {
			pr_err("CPU%d: Timeout while disabling LPIs\n",
			       smp_processor_id());
			return -ETIMEDOUT;
		}
		udelay(1);
		timeout--;
	}

	/*
	 * After it has been written to 1, it is IMPLEMENTATION
	 * DEFINED whether GICR_CTLR.EnableLPI becomes RES1 or can be
	 * cleared to 0. Error out if clearing the bit failed.
	 */
	if (readl_relaxed(rbase + GICR_CTLR) & GICR_CTLR_ENABLE_LPIS) {
		pr_err("CPU%d: Failed to disable LPIs\n", smp_processor_id());
		return -EBUSY;
	}

	return 0;
}

3661 3662 3663
int its_cpu_init(void)
{
	if (!list_empty(&its_nodes)) {
3664 3665 3666 3667 3668 3669
		int ret;

		ret = redist_disable_lpis();
		if (ret)
			return ret;

3670
		its_cpu_init_lpis();
3671
		its_cpu_init_collections();
3672 3673 3674 3675 3676
	}

	return 0;
}

3677
static const struct of_device_id its_device_id[] = {
3678 3679 3680 3681
	{	.compatible	= "arm,gic-v3-its",	},
	{},
};

3682
static int __init its_of_probe(struct device_node *node)
3683 3684
{
	struct device_node *np;
3685
	struct resource res;
3686 3687 3688

	for (np = of_find_matching_node(node, its_device_id); np;
	     np = of_find_matching_node(np, its_device_id)) {
3689 3690
		if (!of_device_is_available(np))
			continue;
3691
		if (!of_property_read_bool(np, "msi-controller")) {
3692 3693
			pr_warn("%pOF: no msi-controller property, ITS ignored\n",
				np);
3694 3695 3696
			continue;
		}

3697
		if (of_address_to_resource(np, 0, &res)) {
3698
			pr_warn("%pOF: no regs?\n", np);
3699 3700 3701 3702
			continue;
		}

		its_probe_one(&res, &np->fwnode, of_node_to_nid(np));
3703
	}
3704 3705 3706
	return 0;
}

3707 3708 3709 3710
#ifdef CONFIG_ACPI

#define ACPI_GICV3_ITS_MEM_SIZE (SZ_128K)

3711
#ifdef CONFIG_ACPI_NUMA
3712 3713 3714 3715 3716 3717 3718
struct its_srat_map {
	/* numa node id */
	u32	numa_node;
	/* GIC ITS ID */
	u32	its_id;
};

3719
static struct its_srat_map *its_srat_maps __initdata;
3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732
static int its_in_srat __initdata;

static int __init acpi_get_its_numa_node(u32 its_id)
{
	int i;

	for (i = 0; i < its_in_srat; i++) {
		if (its_id == its_srat_maps[i].its_id)
			return its_srat_maps[i].numa_node;
	}
	return NUMA_NO_NODE;
}

3733 3734 3735 3736 3737 3738
static int __init gic_acpi_match_srat_its(struct acpi_subtable_header *header,
					  const unsigned long end)
{
	return 0;
}

3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772
static int __init gic_acpi_parse_srat_its(struct acpi_subtable_header *header,
			 const unsigned long end)
{
	int node;
	struct acpi_srat_gic_its_affinity *its_affinity;

	its_affinity = (struct acpi_srat_gic_its_affinity *)header;
	if (!its_affinity)
		return -EINVAL;

	if (its_affinity->header.length < sizeof(*its_affinity)) {
		pr_err("SRAT: Invalid header length %d in ITS affinity\n",
			its_affinity->header.length);
		return -EINVAL;
	}

	node = acpi_map_pxm_to_node(its_affinity->proximity_domain);

	if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
		pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node);
		return 0;
	}

	its_srat_maps[its_in_srat].numa_node = node;
	its_srat_maps[its_in_srat].its_id = its_affinity->its_id;
	its_in_srat++;
	pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n",
		its_affinity->proximity_domain, its_affinity->its_id, node);

	return 0;
}

static void __init acpi_table_parse_srat_its(void)
{
3773 3774 3775 3776 3777 3778 3779 3780 3781
	int count;

	count = acpi_table_parse_entries(ACPI_SIG_SRAT,
			sizeof(struct acpi_table_srat),
			ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
			gic_acpi_match_srat_its, 0);
	if (count <= 0)
		return;

3782 3783
	its_srat_maps = kmalloc_array(count, sizeof(struct its_srat_map),
				      GFP_KERNEL);
3784 3785 3786 3787 3788
	if (!its_srat_maps) {
		pr_warn("SRAT: Failed to allocate memory for its_srat_maps!\n");
		return;
	}

3789 3790 3791 3792 3793
	acpi_table_parse_entries(ACPI_SIG_SRAT,
			sizeof(struct acpi_table_srat),
			ACPI_SRAT_TYPE_GIC_ITS_AFFINITY,
			gic_acpi_parse_srat_its, 0);
}
3794 3795 3796 3797 3798 3799

/* free the its_srat_maps after ITS probing */
static void __init acpi_its_srat_maps_free(void)
{
	kfree(its_srat_maps);
}
3800 3801 3802
#else
static void __init acpi_table_parse_srat_its(void)	{ }
static int __init acpi_get_its_numa_node(u32 its_id) { return NUMA_NO_NODE; }
3803
static void __init acpi_its_srat_maps_free(void) { }
3804 3805
#endif

3806 3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825 3826
static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header,
					  const unsigned long end)
{
	struct acpi_madt_generic_translator *its_entry;
	struct fwnode_handle *dom_handle;
	struct resource res;
	int err;

	its_entry = (struct acpi_madt_generic_translator *)header;
	memset(&res, 0, sizeof(res));
	res.start = its_entry->base_address;
	res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1;
	res.flags = IORESOURCE_MEM;

	dom_handle = irq_domain_alloc_fwnode((void *)its_entry->base_address);
	if (!dom_handle) {
		pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n",
		       &res.start);
		return -ENOMEM;
	}

3827 3828
	err = iort_register_domain_token(its_entry->translation_id, res.start,
					 dom_handle);
3829 3830 3831 3832 3833 3834
	if (err) {
		pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
		       &res.start, its_entry->translation_id);
		goto dom_err;
	}

3835 3836
	err = its_probe_one(&res, dom_handle,
			acpi_get_its_numa_node(its_entry->translation_id));
3837 3838 3839 3840 3841 3842 3843 3844 3845 3846 3847
	if (!err)
		return 0;

	iort_deregister_domain_token(its_entry->translation_id);
dom_err:
	irq_domain_free_fwnode(dom_handle);
	return err;
}

static void __init its_acpi_probe(void)
{
3848
	acpi_table_parse_srat_its();
3849 3850
	acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
			      gic_acpi_parse_madt_its, 0);
3851
	acpi_its_srat_maps_free();
3852 3853 3854 3855 3856
}
#else
static void __init its_acpi_probe(void) { }
#endif

3857 3858 3859 3860
int __init its_init(struct fwnode_handle *handle, struct rdists *rdists,
		    struct irq_domain *parent_domain)
{
	struct device_node *of_node;
3861 3862 3863
	struct its_node *its;
	bool has_v4 = false;
	int err;
3864 3865 3866 3867 3868 3869

	its_parent = parent_domain;
	of_node = to_of_node(handle);
	if (of_node)
		its_of_probe(of_node);
	else
3870
		its_acpi_probe();
3871 3872 3873 3874 3875 3876 3877

	if (list_empty(&its_nodes)) {
		pr_warn("ITS: No ITS available, not enabling LPIs\n");
		return -ENXIO;
	}

	gic_rdists = rdists;
3878 3879

	err = allocate_lpi_tables();
3880 3881 3882 3883 3884 3885 3886
	if (err)
		return err;

	list_for_each_entry(its, &its_nodes, entry)
		has_v4 |= its->is_v4;

	if (has_v4 & rdists->has_vlpis) {
3887 3888
		if (its_init_vpe_domain() ||
		    its_init_v4(parent_domain, &its_vpe_domain_ops)) {
3889 3890 3891 3892 3893
			rdists->has_vlpis = false;
			pr_err("ITS: Disabling GICv4 support\n");
		}
	}

3894 3895
	register_syscore_ops(&its_syscore_ops);

3896
	return 0;
3897
}