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提交 18dfb50e 编写于 作者: armink_ztl's avatar armink_ztl
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[bsp] Remove the at91sam9g45 bsp.

上级 56075ce8
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bsp/at91sam9g45/.config 已删除 100644 → 0
浏览文件 @ 56075ce8
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=16
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=1000
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_IDEL_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
CONFIG_RT_USING_INTERRUPT_INFO=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="dbgu"
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
CONFIG_RT_USING_CPLUSPLUS=y
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=2
CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_WIFI is not set
# CONFIG_RT_USING_AUDIO is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
CONFIG_RT_USING_PTHREADS=y
# CONFIG_RT_USING_MODULE is not set
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# Modbus master and slave stack
#
# CONFIG_RT_USING_MODBUS is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_STM32F4_HAL is not set
# CONFIG_PKG_USING_STM32F4_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AHT10 is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
#
# sample package
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# example package: hello
#
# CONFIG_PKG_USING_HELLO is not set
CONFIG_RT_USING_DBGU=y
# CONFIG_RT_USING_UART0 is not set
# CONFIG_RT_USING_UART1 is not set
# CONFIG_RT_USING_UART2 is not set
# CONFIG_RT_USING_UART3 is not set
CONFIG_RT_USING_LED=y
bsp/at91sam9g45/SConscript 已删除 100644 → 0
浏览文件 @ 56075ce8
# for module compiling
import os
Import('RTT_ROOT')
cwd = str(Dir('#'))
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
bsp/at91sam9g45/SConstruct 已删除 100644 → 0
浏览文件 @ 56075ce8
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-at91sam9g45.' + rtconfig.TARGET_EXT
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
if GetDepend('RT_USING_WEBSERVER'):
objs = objs + SConscript(RTT_ROOT + '/components/net/webserver/SConscript', variant_dir='build/net/webserver', duplicate=0)
if GetDepend('RT_USING_RTGUI'):
objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
# libc testsuite
objs = objs + SConscript(RTT_ROOT + '/examples/libc/SConscript', variant_dir='build/examples/libc', duplicate=0)
# make a building
DoBuilding(TARGET, objs)
bsp/at91sam9g45/applications/SConscript 已删除 100644 → 0
浏览文件 @ 56075ce8
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/at91sam9g45/applications/application.c 已删除 100644 → 0
浏览文件 @ 56075ce8
/*
* File : application.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
/**
* @addtogroup at91sam9260
*/
/*@{*/
#include <rtthread.h>
#include <rtdevice.h>
#ifdef RT_USING_DFS
/* dfs Filesystem APIs */
#include <dfs_fs.h>
#endif
#ifdef RT_USING_SDIO
#include <drivers/mmcsd_core.h>
#include "at91_mci.h"
#endif
#ifdef RT_USING_LED
#include "led.h"
#endif
static int rt_led_app_init(void);
RT_WEAK int main(void)
{
#ifdef RT_USING_SDIO
int timeout = 0;
#endif
/* Filesystem Initialization */
#ifdef RT_USING_DFS
{
#if defined(RT_USING_DFS_ROMFS)
if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0)
{
rt_kprintf("ROM File System initialized!\n");
}
else
rt_kprintf("ROM File System initialzation failed!\n");
#endif
#if defined(RT_USING_DFS_UFFS)
{
/* mount flash device as flash directory */
if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0)
rt_kprintf("UFFS File System initialized!\n");
else
rt_kprintf("UFFS File System initialzation failed!\n");
}
#endif
#ifdef RT_USING_SDIO
timeout = 0;
while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2))
{
rt_thread_delay(1);
}
if (timeout < RT_TICK_PER_SECOND*2)
{
/* mount sd card fat partition 1 as root directory */
if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
{
rt_kprintf("File System initialized!\n");
}
else
rt_kprintf("File System initialzation failed!%d\n", rt_get_errno());
}
else
{
rt_kprintf("No SD card found.\n");
}
#endif
}
#endif
rt_led_app_init();
}
#ifdef RT_USING_LED
void rt_led_thread_entry(void* parameter)
{
rt_uint8_t cnt = 0;
led_init();
while(1)
{
/* light on leds for one second */
rt_thread_delay(40);
cnt++;
if (cnt&0x01)
led_on(1);
else
led_off(1);
if (cnt&0x02)
led_on(2);
else
led_off(2);
if (cnt&0x04)
led_on(3);
else
led_off(3);
}
}
#endif
static int rt_led_app_init(void)
{
#ifdef RT_USING_LED
rt_thread_t led_thread;
#if (RT_THREAD_PRIORITY_MAX == 32)
led_thread = rt_thread_create("led",
rt_led_thread_entry, RT_NULL,
512, 20, 20);
#else
led_thread = rt_thread_create("led",
rt_led_thread_entry, RT_NULL,
512, 200, 20);
#endif
if(led_thread != RT_NULL)
rt_thread_startup(led_thread);
#endif
return 0;
}
/* NFSv3 Initialization */
#if defined(RT_USING_DFS) && defined(RT_USING_LWIP) && defined(RT_USING_DFS_NFS)
#include <dfs_nfs.h>
void nfs_start(void)
{
nfs_init();
if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0)
{
rt_kprintf("NFSv3 File System initialized!\n");
}
else
rt_kprintf("NFSv3 File System initialzation failed!\n");
}
#include "finsh.h"
FINSH_FUNCTION_EXPORT(nfs_start, start net filesystem);
#endif
/*@}*/
bsp/at91sam9g45/drivers/SConscript 已删除 100644 → 0
浏览文件 @ 56075ce8
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'drivers')
# add the general drvers.
src = Split("""
board.c
usart.c
""")
# add Ethernet drvers.
if GetDepend('RT_USING_LED'):
src += ['led.c']
if GetDepend('RT_USING_SDIO'):
src += ['at91_mci.c']
if GetDepend('RT_USING_LWIP'):
src += ['macb.c']
if GetDepend('RT_USING_I2C') and GetDepend('RT_USING_I2C_BITOPS'):
src += ['at91_i2c_gpio.c']
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/at91sam9g45/drivers/at91_i2c_gpio.c 已删除 100644 → 0
浏览文件 @ 56075ce8
/*
* File : at91_i2c_gpio.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2012-04-25 weety first version
*/
#include <rtdevice.h>
#include <rthw.h>
#include <at91sam9g45.h>
static void at91_i2c_gpio_init()
{
AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA; //enable PIOA clock
AT91C_BASE_PIOA->PIO_PUER = (1 << 23);
AT91C_BASE_PIOA->PIO_PER = (1 << 23);
AT91C_BASE_PIOA->PIO_MDER = (1 << 23);
AT91C_BASE_PIOA->PIO_PUER = (1 << 24);
AT91C_BASE_PIOA->PIO_PER = (1 << 24);
AT91C_BASE_PIOA->PIO_MDER = (1 << 24);
AT91C_BASE_PIOA->PIO_OER = (1 << 23);
AT91C_BASE_PIOA->PIO_OER = (1 << 24);
AT91C_BASE_PIOA->PIO_SODR = (1 << 23);
AT91C_BASE_PIOA->PIO_SODR = (1 << 24);
}
static void at91_set_sda(void *data, rt_int32_t state)
{
if (state)
{
AT91C_BASE_PIOA->PIO_SODR = (1 << 23);
}
else
{
AT91C_BASE_PIOA->PIO_CODR = (1 << 23);
}
}
static void at91_set_scl(void *data, rt_int32_t state)
{
if (state)
{
AT91C_BASE_PIOA->PIO_SODR = (1 << 24);
}
else
{
AT91C_BASE_PIOA->PIO_CODR = (1 << 24);
}
}
static rt_int32_t at91_get_sda(void *data)
{
return AT91C_BASE_PIOA->PIO_PDSR & (1 << 23);
}
static rt_int32_t at91_get_scl(void *data)
{
return AT91C_BASE_PIOA->PIO_PDSR & (1 << 24);
}
static void at91_udelay (rt_uint32_t us)
{
rt_int32_t i;
for (; us > 0; us--)
{
i = 50000;
while(i > 0)
{
i--;
}
}
}
static const struct rt_i2c_bit_ops bit_ops = {
RT_NULL,
at91_set_sda,
at91_set_scl,
at91_get_sda,
at91_get_scl,
at91_udelay,
5,
100
};
int at91_i2c_init(void)
{
struct rt_i2c_bus_device *bus;
bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
if (bus == RT_NULL)
{
rt_kprintf("rt_malloc failed\n");
return -RT_ENOMEM;
}
rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
bus->priv = (void *)&bit_ops;
at91_i2c_gpio_init();
rt_i2c_bit_add_bus(bus, "i2c0");
return 0;
}
INIT_DEVICE_EXPORT(at91_i2c_init);
bsp/at91sam9g45/drivers/at91_mci.c 已删除 100644 → 0
浏览文件 @ 56075ce8
此差异已折叠。
bsp/at91sam9g45/drivers/at91_mci.h 已删除 100644 → 0
浏览文件 @ 56075ce8
/*
* File : at91_mci.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-06-09 weety first version
*/
#ifndef __AT91C_MCI_H__
#define __AT91C_MCI_H__
#define AT91C_MCI_CR 0x00 /* Control Register */
#define AT91C_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
#define AT91C_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */
#define AT91C_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */
#define AT91C_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */
#define AT91C_MCI_SWRST (1 << 7) /* Software Reset */
#define AT91C_MCI_MR 0x04 /* Mode Register */
#define AT91C_MCI_CLKDIV (0xff << 0) /* Clock Divider */
#define AT91C_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
#define AT91C_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */
#define AT91C_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */
#define AT91C_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */
#define AT91C_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
#define AT91C_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
#define AT91C_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
#define AT91C_MCI_DTOR 0x08 /* Data Timeout Register */
#define AT91C_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
#define AT91C_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */
#define AT91C_MCI_DTOMUL_1 (0 << 4)
#define AT91C_MCI_DTOMUL_16 (1 << 4)
#define AT91C_MCI_DTOMUL_128 (2 << 4)
#define AT91C_MCI_DTOMUL_256 (3 << 4)
#define AT91C_MCI_DTOMUL_1K (4 << 4)
#define AT91C_MCI_DTOMUL_4K (5 << 4)
#define AT91C_MCI_DTOMUL_64K (6 << 4)
#define AT91C_MCI_DTOMUL_1M (7 << 4)
#define AT91C_MCI_SDCR 0x0c /* SD Card Register */
#define AT91C_MCI_SDCSEL (3 << 0) /* SD Card Selector */
#define AT91C_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
#define AT91C_MCI_ARGR 0x10 /* Argument Register */
#define AT91C_MCI_CMDR 0x14 /* Command Register */
#define AT91C_MCI_CMDNB (0x3f << 0) /* Command Number */
#define AT91C_MCI_RSPTYP (3 << 6) /* Response Type */
#define AT91C_MCI_RSPTYP_NONE (0 << 6)
#define AT91C_MCI_RSPTYP_48 (1 << 6)
#define AT91C_MCI_RSPTYP_136 (2 << 6)
#define AT91C_MCI_SPCMD (7 << 8) /* Special Command */
#define AT91C_MCI_SPCMD_NONE (0 << 8)
#define AT91C_MCI_SPCMD_INIT (1 << 8)
#define AT91C_MCI_SPCMD_SYNC (2 << 8)
#define AT91C_MCI_SPCMD_ICMD (4 << 8)
#define AT91C_MCI_SPCMD_IRESP (5 << 8)
#define AT91C_MCI_OPDCMD (1 << 11) /* Open Drain Command */
#define AT91C_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */
#define AT91C_MCI_TRCMD (3 << 16) /* Transfer Command */
#define AT91C_MCI_TRCMD_NONE (0 << 16)
#define AT91C_MCI_TRCMD_START (1 << 16)
#define AT91C_MCI_TRCMD_STOP (2 << 16)
#define AT91C_MCI_TRDIR (1 << 18) /* Transfer Direction */
#define AT91C_MCI_TRTYP (3 << 19) /* Transfer Type */
#define AT91C_MCI_TRTYP_BLOCK (0 << 19)
#define AT91C_MCI_TRTYP_MULTIPLE (1 << 19)
#define AT91C_MCI_TRTYP_STREAM (2 << 19)
#define AT91C_MCI_BLKR 0x18 /* Block Register */
#define AT91C_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */
#define AT91C_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */
#define AT91C_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */
#define AT91C_MCR_RDR 0x30 /* Receive Data Register */
#define AT91C_MCR_TDR 0x34 /* Transmit Data Register */
#define AT91C_MCI_SR 0x40 /* Status Register */
#define AT91C_MCI_CMDRDY (1U << 0) /* Command Ready */
#define AT91C_MCI_RXRDY (1U << 1) /* Receiver Ready */
#define AT91C_MCI_TXRDY (1U << 2) /* Transmit Ready */
#define AT91C_MCI_BLKE (1U << 3) /* Data Block Ended */
#define AT91C_MCI_DTIP (1U << 4) /* Data Transfer in Progress */
#define AT91C_MCI_NOTBUSY (1U << 5) /* Data Not Busy */
#define AT91C_MCI_ENDRX (1U << 6) /* End of RX Buffer */
#define AT91C_MCI_ENDTX (1U << 7) /* End fo TX Buffer */
#define AT91C_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */
#define AT91C_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */
#define AT91C_MCI_RXBUFF (1U << 14) /* RX Buffer Full */
#define AT91C_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */
#define AT91C_MCI_RINDE (1U << 16) /* Response Index Error */
#define AT91C_MCI_RDIRE (1U << 17) /* Response Direction Error */
#define AT91C_MCI_RCRCE (1U << 18) /* Response CRC Error */
#define AT91C_MCI_RENDE (1U << 19) /* Response End Bit Error */
#define AT91C_MCI_RTOE (1U << 20) /* Reponse Time-out Error */
#define AT91C_MCI_DCRCE (1U << 21) /* Data CRC Error */
#define AT91C_MCI_DTOE (1U << 22) /* Data Time-out Error */
#define AT91C_MCI_OVRE (1U << 30) /* Overrun */
#define AT91C_MCI_UNRE (1U << 31) /* Underrun */
#define AT91C_MCI_IER 0x44 /* Interrupt Enable Register */
#define AT91C_MCI_IDR 0x48 /* Interrupt Disable Register */
#define AT91C_MCI_IMR 0x4c /* Interrupt Mask Register */
extern int at91_mci_init(void);
#endif
bsp/at91sam9g45/drivers/board.c 已删除 100644 → 0
浏览文件 @ 56075ce8
/*
* File : board.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#include <rtthread.h>
#include <rthw.h>
#include "board.h"
#include <mmu.h>
/**
* @addtogroup at91sam9g45
*/
/*@{*/
#if defined(__CC_ARM)
extern int Image$$ER_ZI$$ZI$$Limit;
#define HEAP_BEGIN (&Image$$ER_ZI$$ZI$$Limit)
#elif (defined (__GNUC__))
extern unsigned char __bss_end__;
#define HEAP_BEGIN (&__bss_end__)
#elif (defined (__ICCARM__))
#pragma section=".noinit"
#define HEAP_BEGIN (__section_end(".noinit"))
#endif
#define HEAP_END (((rt_uint32_t)HEAP_BEGIN & 0xF0000000) + 0x04000000)
extern void rt_hw_interrupt_init(void);
extern void rt_hw_clock_init(void);
extern void rt_hw_get_clock(void);
extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn);
extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv);
extern void rt_dbgu_isr(void);
#define SAM9G45_BLOCK_SIZE 0x10000000 // 256M
#define MMU_SECTION_SIZE 0x100000 // 1M
#define PERIPHERALS_ADDR // 1M
#define SECTION_END(sa) ((sa) + MMU_SECTION_SIZE - 1) // sa: start address
#define BLOCK_END(ba) ((ba) + SAM9G45_BLOCK_SIZE - 1) // ba: block address
static struct mem_desc at91_mem_desc[] = { /* FIXME, hornby, to confirm MMU and memory */
{ 0x00000000, 0xFFFFFFFF , 0x00000000, RW_NCNB }, /* None cached for 4G memory */
//{ 0x00000000, SECTION_END(0x00000000), 0x00000000, RW_CNB }, /* TLB for ITCM, ITCM map to address zero, 32KB */
//{ 0x00200000, SECTION_END(0x00200000), 0x00200000, RW_CNB }, /* TLB for DTCM, 32KB */
//{ 0x00300000, SECTION_END(0x00300000), 0x00300000, RW_CNB }, /* TLB for internal RAM, 64KB, we use it as global variable area */
//{ 0x00600000, SECTION_END(0x00600000), 0x00600000, RW_NCNB }, /* TLB for UDPHS(DMA) */
//{ 0x00700000, SECTION_END(0x00700000), 0x00700000, RW_NCNB }, /* TLB for UHP OHCI */
//{ 0x00800000, SECTION_END(0x00800000), 0x00800000, RW_NCNB }, /* TLB for UHP EHCI */
//{ 0x30000000, 0x30000000+0x00100000-1, 0x30000000, RW_CB }, /* 1M external SRAM for program code and stack */
//{ 0x40000000, BLOCK_END(0x40000000), 0x40000000, RW_NCNB }, /* 256M for nand-flash controller */
//{ 0x60000000, BLOCK_END(0x60000000), 0x60000000, RW_NCNB }, /* 256M for FPGA */
//{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_NCNB }, /* 128M for main DDR-SDRAM for print data */
{ 0x00000000, SECTION_END(0x00000000), 0x70000000, RW_CB }, /* isr */
{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_CB }, /* 128M for main DDR-SDRAM for print data */
//{ 0xFFF00000, SECTION_END(0xFFF00000), 0xFFF00000, RW_NCNB }, /* Internal Peripherals, 1MB */
};
#define PIT_CPIV(x) ((x) & AT91C_PITC_CPIV)
#define PIT_PICNT(x) (((x) & AT91C_PITC_PICNT) >> 20)
static rt_uint32_t pit_cycle; /* write-once */
static rt_uint32_t pit_cnt; /* access only w/system irq blocked */
/**
* This function will handle rtos timer
*/
void rt_timer_handler(int vector, void *param)
{
#ifdef RT_USING_DBGU
if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY)
{
rt_dbgu_isr();
}
#endif
if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS)
{
unsigned nr_ticks;
/* Get number of ticks performed before irq, and ack it */
nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR));
while (nr_ticks--)
rt_tick_increase();
}
}
static void at91sam9g45_pit_reset(void)
{
/* Disable timer and irqs */
AT91C_BASE_PITC->PITC_PIMR = 0;
/* Clear any pending interrupts, wait for PIT to stop counting */
while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0)
;
/* Start PIT but don't enable IRQ */
//AT91C_BASE_PITC->PITC_PIMR = (pit_cycle - 1) | AT91C_PITC_PITEN;
pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR));
AT91C_BASE_PITC->PITC_PIMR =
(pit_cycle - 1) | AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR));
}
/*
* Set up both clocksource and clockevent support.
*/
static void at91sam9g45_pit_init(void)
{
rt_uint32_t pit_rate;
//rt_uint32_t bits;
/*
* Use our actual MCK to figure out how many MCK/16 ticks per
* 1/HZ period (instead of a compile-time constant LATCH).
*/
pit_rate = clk_get_rate(clk_get("mck")) / 16;
rt_kprintf("pit_rate=%dHZ\n", pit_rate);
pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND;
/* Initialize and enable the timer */
at91sam9g45_pit_reset();
}
/**
* This function will init pit for system ticks
*/
void rt_hw_timer_init()
{
at91sam9g45_pit_init();
/* install interrupt handler */
rt_hw_interrupt_install(AT91C_ID_SYS, rt_timer_handler,
RT_NULL, "system");
rt_hw_interrupt_umask(AT91C_ID_SYS);
}
void at91_tc1_init()
{
AT91C_BASE_PMC->PMC_PCER = 1<<AT91C_ID_TC;
writel(AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE, AT91C_TCB0_BMR);
writel(AT91C_TC_CLKDIS, AT91C_TC0_CCR);
writel(AT91C_TC_CLKS_TIMER_DIV4_CLOCK, AT91C_TC0_CMR);
writel(0xffff, AT91C_TC0_CV);
}
#define BPS 115200 /* serial console port baudrate */
static void at91_usart_putc(char c)
{
while (!(AT91C_BASE_DBGU->DBGU_CSR & AT91C_US_TXRDY))
;
AT91C_BASE_DBGU->DBGU_THR = c;
}
/**
* This function is used to display a string on console, normally, it's
* invoked by rt_kprintf
*
* @param str the displayed string
*/
void rt_hw_console_output(const char* str)
{
while (*str)
{
if (*str=='\n')
{
at91_usart_putc('\r');
}
at91_usart_putc(*str++);
}
}
static void rt_hw_console_init(void)
{
int div;
int mode = 0;
AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTTX | AT91C_US_RSTRX |
AT91C_US_RXDIS | AT91C_US_TXDIS;
mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
AT91C_US_CHMODE_NORMAL;
mode |= AT91C_US_CHRL_8_BITS;
mode |= AT91C_US_NBSTOP_1_BIT;
mode |= AT91C_US_PAR_NONE;
AT91C_BASE_DBGU->DBGU_MR = mode;
div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS;
AT91C_BASE_DBGU->DBGU_BRGR = div;
AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN;
}
/**
* This function will init at91sam9g45 board
*/
void rt_hw_board_init()
{
/* initialize the system clock */
rt_hw_clock_init();
/* initialize console */
rt_hw_console_init();
/* initialize mmu */
rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0]));
/* initialize hardware interrupt */
rt_hw_interrupt_init();
/* initialize early device */
#ifdef RT_USING_COMPONENTS_INIT
rt_components_board_init();
#endif
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
/* initialize timer0 */
rt_hw_timer_init();
/* initialize board */
#ifdef RT_USING_HEAP
rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END);
#endif
}
/*@}*/
bsp/at91sam9g45/drivers/board.h 已删除 100644 → 0
浏览文件 @ 56075ce8
/*
* File : board.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety add board.h to this bsp
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include <at91sam9g45.h>
void rt_hw_board_init(void);
#endif
bsp/at91sam9g45/drivers/led.c 已删除 100644 → 0
浏览文件 @ 56075ce8
/*
* File : led.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#include <rtthread.h>
#include <at91sam9g45.h>
#include "led.h"
// BYHX A-Plus Board
#define LED0 (1UL << 30)
#define LED1 (1UL << 31)
#define LED2 (1UL << 29)
#define LED3 (1UL << 28)
#define LED_ALL (LED0 | LED1 | LED2 | LED3)
void led_init(void)
{
AT91C_BASE_PIOC->PIO_PER = LED_ALL;
AT91C_BASE_PIOC->PIO_OER = LED_ALL;
AT91C_BASE_PIOC->PIO_PPUER = LED_ALL;
AT91C_BASE_PIOC->PIO_SODR = LED_ALL;
}
const static rt_uint32_t m_leds[] = { LED0, LED1, LED2, LED3 };
void led_on(int num)
{
if (num < 4) AT91C_BASE_PIOC->PIO_CODR = m_leds[num];
}
void led_off(int num)
{
if (num < 4) AT91C_BASE_PIOC->PIO_SODR = m_leds[num];
}
bsp/at91sam9g45/drivers/led.h 已删除 100644 → 0
浏览文件 @ 56075ce8
/*
* File : led.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#ifndef __LED_H__
#define __LED_H__
void led_init(void);
void led_on(int num);
void led_off(int num);
#endif
bsp/at91sam9g45/drivers/macb.c 已删除 100644 → 0
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此差异已折叠。
bsp/at91sam9g45/drivers/macb.h 已删除 100644 → 0
浏览文件 @ 56075ce8
/*
* File : macb.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-03-18 weety first version
*/
#ifndef _MACB_H
#define _MACB_H
#include <mii.h>
/* MACB register offsets */
#define MACB_NCR 0x0000
#define MACB_NCFGR 0x0004
#define MACB_NSR 0x0008
#define MACB_TSR 0x0014
#define MACB_RBQP 0x0018
#define MACB_TBQP 0x001c
#define MACB_RSR 0x0020
#define MACB_ISR 0x0024
#define MACB_IER 0x0028
#define MACB_IDR 0x002c
#define MACB_IMR 0x0030
#define MACB_MAN 0x0034
#define MACB_PTR 0x0038
#define MACB_PFR 0x003c
#define MACB_FTO 0x0040
#define MACB_SCF 0x0044
#define MACB_MCF 0x0048
#define MACB_FRO 0x004c
#define MACB_FCSE 0x0050
#define MACB_ALE 0x0054
#define MACB_DTF 0x0058
#define MACB_LCOL 0x005c
#define MACB_EXCOL 0x0060
#define MACB_TUND 0x0064
#define MACB_CSE 0x0068
#define MACB_RRE 0x006c
#define MACB_ROVR 0x0070
#define MACB_RSE 0x0074
#define MACB_ELE 0x0078
#define MACB_RJA 0x007c
#define MACB_USF 0x0080
#define MACB_STE 0x0084
#define MACB_RLE 0x0088
#define MACB_TPF 0x008c
#define MACB_HRB 0x0090
#define MACB_HRT 0x0094
#define MACB_SA1B 0x0098
#define MACB_SA1T 0x009c
#define MACB_SA2B 0x00a0
#define MACB_SA2T 0x00a4
#define MACB_SA3B 0x00a8
#define MACB_SA3T 0x00ac
#define MACB_SA4B 0x00b0
#define MACB_SA4T 0x00b4
#define MACB_TID 0x00b8
#define MACB_TPQ 0x00bc
#define MACB_USRIO 0x00c0
#define MACB_WOL 0x00c4
/* Bitfields in NCR */
#define MACB_LB_OFFSET 0
#define MACB_LB_SIZE 1
#define MACB_LLB_OFFSET 1
#define MACB_LLB_SIZE 1
#define MACB_RE_OFFSET 2
#define MACB_RE_SIZE 1
#define MACB_TE_OFFSET 3
#define MACB_TE_SIZE 1
#define MACB_MPE_OFFSET 4
#define MACB_MPE_SIZE 1
#define MACB_CLRSTAT_OFFSET 5
#define MACB_CLRSTAT_SIZE 1
#define MACB_INCSTAT_OFFSET 6
#define MACB_INCSTAT_SIZE 1
#define MACB_WESTAT_OFFSET 7
#define MACB_WESTAT_SIZE 1
#define MACB_BP_OFFSET 8
#define MACB_BP_SIZE 1
#define MACB_TSTART_OFFSET 9
#define MACB_TSTART_SIZE 1
#define MACB_THALT_OFFSET 10
#define MACB_THALT_SIZE 1
#define MACB_NCR_TPF_OFFSET 11
#define MACB_NCR_TPF_SIZE 1
#define MACB_TZQ_OFFSET 12
#define MACB_TZQ_SIZE 1
/* Bitfields in NCFGR */
#define MACB_SPD_OFFSET 0
#define MACB_SPD_SIZE 1
#define MACB_FD_OFFSET 1
#define MACB_FD_SIZE 1
#define MACB_BIT_RATE_OFFSET 2
#define MACB_BIT_RATE_SIZE 1
#define MACB_JFRAME_OFFSET 3
#define MACB_JFRAME_SIZE 1
#define MACB_CAF_OFFSET 4
#define MACB_CAF_SIZE 1
#define MACB_NBC_OFFSET 5
#define MACB_NBC_SIZE 1
#define MACB_NCFGR_MTI_OFFSET 6
#define MACB_NCFGR_MTI_SIZE 1
#define MACB_UNI_OFFSET 7
#define MACB_UNI_SIZE 1
#define MACB_BIG_OFFSET 8
#define MACB_BIG_SIZE 1
#define MACB_EAE_OFFSET 9
#define MACB_EAE_SIZE 1
#define MACB_CLK_OFFSET 10
#define MACB_CLK_SIZE 2
#define MACB_RTY_OFFSET 12
#define MACB_RTY_SIZE 1
#define MACB_PAE_OFFSET 13
#define MACB_PAE_SIZE 1
#define MACB_RBOF_OFFSET 14
#define MACB_RBOF_SIZE 2
#define MACB_RLCE_OFFSET 16
#define MACB_RLCE_SIZE 1
#define MACB_DRFCS_OFFSET 17
#define MACB_DRFCS_SIZE 1
#define MACB_EFRHD_OFFSET 18
#define MACB_EFRHD_SIZE 1
#define MACB_IRXFCS_OFFSET 19
#define MACB_IRXFCS_SIZE 1
/* Bitfields in NSR */
#define MACB_NSR_LINK_OFFSET 0
#define MACB_NSR_LINK_SIZE 1
#define MACB_MDIO_OFFSET 1
#define MACB_MDIO_SIZE 1
#define MACB_IDLE_OFFSET 2
#define MACB_IDLE_SIZE 1
/* Bitfields in TSR */
#define MACB_UBR_OFFSET 0
#define MACB_UBR_SIZE 1
#define MACB_COL_OFFSET 1
#define MACB_COL_SIZE 1
#define MACB_TSR_RLE_OFFSET 2
#define MACB_TSR_RLE_SIZE 1
#define MACB_TGO_OFFSET 3
#define MACB_TGO_SIZE 1
#define MACB_BEX_OFFSET 4
#define MACB_BEX_SIZE 1
#define MACB_COMP_OFFSET 5
#define MACB_COMP_SIZE 1
#define MACB_UND_OFFSET 6
#define MACB_UND_SIZE 1
/* Bitfields in RSR */
#define MACB_BNA_OFFSET 0
#define MACB_BNA_SIZE 1
#define MACB_REC_OFFSET 1
#define MACB_REC_SIZE 1
#define MACB_OVR_OFFSET 2
#define MACB_OVR_SIZE 1
/* Bitfields in ISR/IER/IDR/IMR */
#define MACB_MFD_OFFSET 0
#define MACB_MFD_SIZE 1
#define MACB_RCOMP_OFFSET 1
#define MACB_RCOMP_SIZE 1
#define MACB_RXUBR_OFFSET 2
#define MACB_RXUBR_SIZE 1
#define MACB_TXUBR_OFFSET 3
#define MACB_TXUBR_SIZE 1
#define MACB_ISR_TUND_OFFSET 4
#define MACB_ISR_TUND_SIZE 1
#define MACB_ISR_RLE_OFFSET 5
#define MACB_ISR_RLE_SIZE 1
#define MACB_TXERR_OFFSET 6
#define MACB_TXERR_SIZE 1
#define MACB_TCOMP_OFFSET 7
#define MACB_TCOMP_SIZE 1
#define MACB_ISR_LINK_OFFSET 9
#define MACB_ISR_LINK_SIZE 1
#define MACB_ISR_ROVR_OFFSET 10
#define MACB_ISR_ROVR_SIZE 1
#define MACB_HRESP_OFFSET 11
#define MACB_HRESP_SIZE 1
#define MACB_PFR_OFFSET 12
#define MACB_PFR_SIZE 1
#define MACB_PTZ_OFFSET 13
#define MACB_PTZ_SIZE 1
/* Bitfields in MAN */
#define MACB_DATA_OFFSET 0
#define MACB_DATA_SIZE 16
#define MACB_CODE_OFFSET 16
#define MACB_CODE_SIZE 2
#define MACB_REGA_OFFSET 18
#define MACB_REGA_SIZE 5
#define MACB_PHYA_OFFSET 23
#define MACB_PHYA_SIZE 5
#define MACB_RW_OFFSET 28
#define MACB_RW_SIZE 2
#define MACB_SOF_OFFSET 30
#define MACB_SOF_SIZE 2
/* Bitfields in USRIO (AVR32) */
#define MACB_MII_OFFSET 0
#define MACB_MII_SIZE 1
#define MACB_EAM_OFFSET 1
#define MACB_EAM_SIZE 1
#define MACB_TX_PAUSE_OFFSET 2
#define MACB_TX_PAUSE_SIZE 1
#define MACB_TX_PAUSE_ZERO_OFFSET 3
#define MACB_TX_PAUSE_ZERO_SIZE 1
/* Bitfields in USRIO (AT91) */
#define MACB_RMII_OFFSET 0
#define MACB_RMII_SIZE 1
#define MACB_CLKEN_OFFSET 1
#define MACB_CLKEN_SIZE 1
/* Bitfields in WOL */
#define MACB_IP_OFFSET 0
#define MACB_IP_SIZE 16
#define MACB_MAG_OFFSET 16
#define MACB_MAG_SIZE 1
#define MACB_ARP_OFFSET 17
#define MACB_ARP_SIZE 1
#define MACB_SA1_OFFSET 18
#define MACB_SA1_SIZE 1
#define MACB_WOL_MTI_OFFSET 19
#define MACB_WOL_MTI_SIZE 1
/* Constants for CLK */
#define MACB_CLK_DIV8 0
#define MACB_CLK_DIV16 1
#define MACB_CLK_DIV32 2
#define MACB_CLK_DIV64 3
/* Constants for MAN register */
#define MACB_MAN_SOF 1
#define MACB_MAN_WRITE 1
#define MACB_MAN_READ 2
#define MACB_MAN_CODE 2
/* Bit manipulation macros */
#define MACB_BIT(name) \
(1 << MACB_##name##_OFFSET)
#define MACB_BF(name,value) \
(((value) & ((1 << MACB_##name##_SIZE) - 1)) \
<< MACB_##name##_OFFSET)
#define MACB_BFEXT(name,value)\
(((value) >> MACB_##name##_OFFSET) \
& ((1 << MACB_##name##_SIZE) - 1))
#define MACB_BFINS(name,value,old) \
(((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
<< MACB_##name##_OFFSET)) \
| MACB_BF(name,value))
/* Register access macros */
#define macb_readl(port,reg) \
readl((port)->regs + MACB_##reg)
#define macb_writel(port,reg,value) \
writel((value), (port)->regs + MACB_##reg)
struct dma_desc {
rt_uint32_t addr;
rt_uint32_t ctrl;
};
/* DMA descriptor bitfields */
#define MACB_RX_USED_OFFSET 0
#define MACB_RX_USED_SIZE 1
#define MACB_RX_WRAP_OFFSET 1
#define MACB_RX_WRAP_SIZE 1
#define MACB_RX_WADDR_OFFSET 2
#define MACB_RX_WADDR_SIZE 30
#define MACB_RX_FRMLEN_OFFSET 0
#define MACB_RX_FRMLEN_SIZE 12
#define MACB_RX_OFFSET_OFFSET 12
#define MACB_RX_OFFSET_SIZE 2
#define MACB_RX_SOF_OFFSET 14
#define MACB_RX_SOF_SIZE 1
#define MACB_RX_EOF_OFFSET 15
#define MACB_RX_EOF_SIZE 1
#define MACB_RX_CFI_OFFSET 16
#define MACB_RX_CFI_SIZE 1
#define MACB_RX_VLAN_PRI_OFFSET 17
#define MACB_RX_VLAN_PRI_SIZE 3
#define MACB_RX_PRI_TAG_OFFSET 20
#define MACB_RX_PRI_TAG_SIZE 1
#define MACB_RX_VLAN_TAG_OFFSET 21
#define MACB_RX_VLAN_TAG_SIZE 1
#define MACB_RX_TYPEID_MATCH_OFFSET 22
#define MACB_RX_TYPEID_MATCH_SIZE 1
#define MACB_RX_SA4_MATCH_OFFSET 23
#define MACB_RX_SA4_MATCH_SIZE 1
#define MACB_RX_SA3_MATCH_OFFSET 24
#define MACB_RX_SA3_MATCH_SIZE 1
#define MACB_RX_SA2_MATCH_OFFSET 25
#define MACB_RX_SA2_MATCH_SIZE 1
#define MACB_RX_SA1_MATCH_OFFSET 26
#define MACB_RX_SA1_MATCH_SIZE 1
#define MACB_RX_EXT_MATCH_OFFSET 28
#define MACB_RX_EXT_MATCH_SIZE 1
#define MACB_RX_UHASH_MATCH_OFFSET 29
#define MACB_RX_UHASH_MATCH_SIZE 1
#define MACB_RX_MHASH_MATCH_OFFSET 30
#define MACB_RX_MHASH_MATCH_SIZE 1
#define MACB_RX_BROADCAST_OFFSET 31
#define MACB_RX_BROADCAST_SIZE 1
#define MACB_TX_FRMLEN_OFFSET 0
#define MACB_TX_FRMLEN_SIZE 11
#define MACB_TX_LAST_OFFSET 15
#define MACB_TX_LAST_SIZE 1
#define MACB_TX_NOCRC_OFFSET 16
#define MACB_TX_NOCRC_SIZE 1
#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
#define MACB_TX_BUF_EXHAUSTED_SIZE 1
#define MACB_TX_UNDERRUN_OFFSET 28
#define MACB_TX_UNDERRUN_SIZE 1
#define MACB_TX_ERROR_OFFSET 29
#define MACB_TX_ERROR_SIZE 1
#define MACB_TX_WRAP_OFFSET 30
#define MACB_TX_WRAP_SIZE 1
#define MACB_TX_USED_OFFSET 31
#define MACB_TX_USED_SIZE 1
extern int rt_hw_macb_init();
#endif /* _MACB_H */
bsp/at91sam9g45/drivers/mii.h 已删除 100644 → 0
浏览文件 @ 56075ce8
/*
* File : mii.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-03-18 weety first version
*/
#ifndef __MII_H__
#define __MII_H__
/* Generic MII registers. */
#define MII_BMCR 0x00 /* Basic mode control register */
#define MII_BMSR 0x01 /* Basic mode status register */
#define MII_PHYSID1 0x02 /* PHYS ID 1 */
#define MII_PHYSID2 0x03 /* PHYS ID 2 */
#define MII_ADVERTISE 0x04 /* Advertisement control reg */
#define MII_LPA 0x05 /* Link partner ability reg */
#define MII_EXPANSION 0x06 /* Expansion register */
#define MII_CTRL1000 0x09 /* 1000BASE-T control */
#define MII_STAT1000 0x0a /* 1000BASE-T status */
#define MII_ESTATUS 0x0f /* Extended Status */
#define MII_DCOUNTER 0x12 /* Disconnect counter */
#define MII_FCSCOUNTER 0x13 /* False carrier counter */
#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */
#define MII_RERRCOUNTER 0x15 /* Receive error counter */
#define MII_SREVISION 0x16 /* Silicon revision */
#define MII_RESV1 0x17 /* Reserved... */
#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */
#define MII_PHYADDR 0x19 /* PHY address */
#define MII_RESV2 0x1a /* Reserved... */
#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */
#define MII_NCONFIG 0x1c /* Network interface config */
/* Basic mode control register. */
#define BMCR_RESV 0x003f /* Unused... */
#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */
#define BMCR_CTST 0x0080 /* Collision test */
#define BMCR_FULLDPLX 0x0100 /* Full duplex */
#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */
#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
#define BMCR_RESET 0x8000 /* Reset the DP83840 */
/* Basic mode status register. */
#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
#define BMSR_JCD 0x0002 /* Jabber detected */
#define BMSR_LSTATUS 0x0004 /* Link status */
#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */
#define BMSR_RFAULT 0x0010 /* Remote fault detected */
#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */
#define BMSR_RESV 0x00c0 /* Unused... */
#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */
#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */
#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */
#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */
#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */
#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */
/* Advertisement control register. */
#define ADVERTISE_SLCT 0x001f /* Selector bits */
#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */
#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */
#define ADVERTISE_RESV 0x1000 /* Unused... */
#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
ADVERTISE_CSMA)
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
ADVERTISE_100HALF | ADVERTISE_100FULL)
/* Link partner ability register. */
#define LPA_SLCT 0x001f /* Same as advertise selector */
#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */
#define LPA_PAUSE_CAP 0x0400 /* Can pause */
#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */
#define LPA_RESV 0x1000 /* Unused... */
#define LPA_RFAULT 0x2000 /* Link partner faulted */
#define LPA_LPACK 0x4000 /* Link partner acked us */
#define LPA_NPAGE 0x8000 /* Next page bit */
#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL)
#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
/* Expansion register for auto-negotiation. */
#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */
#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */
#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */
#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */
#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */
#define EXPANSION_RESV 0xffe0 /* Unused... */
#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */
#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */
/* N-way test register. */
#define NWAYTEST_RESV1 0x00ff /* Unused... */
#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */
#define NWAYTEST_RESV2 0xfe00 /* Unused... */
/* 1000BASE-T Control register */
#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
/* 1000BASE-T Status register */
#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */
#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */
#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
/* Flow control flags */
#define FLOW_CTRL_TX 0x01
#define FLOW_CTRL_RX 0x02
/**
* mii_nway_result
* @negotiated: value of MII ANAR and'd with ANLPAR
*
* Given a set of MII abilities, check each bit and returns the
* currently supported media, in the priority order defined by
* IEEE 802.3u. We use LPA_xxx constants but note this is not the
* value of LPA solely, as described above.
*
* The one exception to IEEE 802.3u is that 100baseT4 is placed
* between 100T-full and 100T-half. If your phy does not support
* 100T4 this is fine. If your phy places 100T4 elsewhere in the
* priority order, you will need to roll your own function.
*/
rt_inline unsigned int mii_nway_result (unsigned int negotiated)
{
unsigned int ret;
if (negotiated & LPA_100FULL)
ret = LPA_100FULL;
else if (negotiated & LPA_100BASE4)
ret = LPA_100BASE4;
else if (negotiated & LPA_100HALF)
ret = LPA_100HALF;
else if (negotiated & LPA_10FULL)
ret = LPA_10FULL;
else
ret = LPA_10HALF;
return ret;
}
#endif /* __MII_H__ */
bsp/at91sam9g45/drivers/usart.c 已删除 100644 → 0
浏览文件 @ 56075ce8
/*
* File : usart.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
* 2013-07-21 weety using serial component
*/
#include <rtthread.h>
#include <rthw.h>
#include <at91sam9g45.h>
#include <rtdevice.h>
struct at91_uart {
AT91S_USART *port;
int irq;
};
/**
* This function will handle serial port interrupt
*/
void rt_at91_usart_handler(int vector, void *param)
{
int status;
struct at91_uart *uart;
rt_device_t dev = (rt_device_t)param;
uart = (struct at91_uart *)dev->user_data;
status = uart->port->US_CSR;
if (!(status & uart->port->US_IMR)) /* check actived and enabled interrupt */
{
return;
}
rt_interrupt_enter();
rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND);
rt_interrupt_leave();
}
/**
* UART device in RT-Thread
*/
static rt_err_t at91_usart_configure(struct rt_serial_device *serial,
struct serial_configure *cfg)
{
int div;
int mode = 0;
struct at91_uart *uart;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
uart = (struct at91_uart *)serial->parent.user_data;
uart->port->US_CR = AT91C_US_RSTTX | AT91C_US_RSTRX |
AT91C_US_RXDIS | AT91C_US_TXDIS;
mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK |
AT91C_US_CHMODE_NORMAL;
switch (cfg->data_bits)
{
case DATA_BITS_8:
mode |= AT91C_US_CHRL_8_BITS;
break;
case DATA_BITS_7:
mode |= AT91C_US_CHRL_7_BITS;
break;
case DATA_BITS_6:
mode |= AT91C_US_CHRL_6_BITS;
break;
case DATA_BITS_5:
mode |= AT91C_US_CHRL_5_BITS;
break;
default:
mode |= AT91C_US_CHRL_8_BITS;
break;
}
switch (cfg->stop_bits)
{
case STOP_BITS_2:
mode |= AT91C_US_NBSTOP_2_BIT;
break;
case STOP_BITS_1:
default:
mode |= AT91C_US_NBSTOP_1_BIT;
break;
}
switch (cfg->parity)
{
case PARITY_ODD:
mode |= AT91C_US_PAR_ODD;
break;
case PARITY_EVEN:
mode |= AT91C_US_PAR_EVEN;
break;
case PARITY_NONE:
default:
mode |= AT91C_US_PAR_NONE;
break;
}
uart->port->US_MR = mode;
/* Assume OVER is cleared and fractional baudrate generator is disabled */
div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate;
uart->port->US_BRGR = div;
uart->port->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
uart->port->US_IER = AT91C_US_RXRDY;
return RT_EOK;
}
static rt_err_t at91_usart_control(struct rt_serial_device *serial,
int cmd, void *arg)
{
struct at91_uart* uart;
RT_ASSERT(serial != RT_NULL);
uart = (struct at91_uart *)serial->parent.user_data;
switch (cmd)
{
case RT_DEVICE_CTRL_CLR_INT:
/* disable rx irq */
rt_hw_interrupt_mask(uart->irq);
break;
case RT_DEVICE_CTRL_SET_INT:
/* enable rx irq */
rt_hw_interrupt_umask(uart->irq);
break;
}
return RT_EOK;
}
static int at91_usart_putc(struct rt_serial_device *serial, char c)
{
//rt_uint32_t level;
struct at91_uart *uart = serial->parent.user_data;
while (!(uart->port->US_CSR & AT91C_US_TXRDY));
uart->port->US_THR = c;
return 1;
}
static int at91_usart_getc(struct rt_serial_device *serial)
{
int result;
struct at91_uart *uart = serial->parent.user_data;
if (uart->port->US_CSR & AT91C_US_RXRDY)
{
result = uart->port->US_RHR & 0xff;
}
else
{
result = -1;
}
return result;
}
static const struct rt_uart_ops at91_usart_ops =
{
at91_usart_configure,
at91_usart_control,
at91_usart_putc,
at91_usart_getc,
};
#if defined(RT_USING_DBGU)
static struct rt_serial_device serial_dbgu;
struct at91_uart dbgu = {
(AT91PS_USART)AT91C_BASE_DBGU,
AT91C_ID_SYS
};
#endif
#if defined(RT_USING_UART0)
static struct rt_serial_device serial0;
struct at91_uart uart0 = {
AT91C_BASE_US0,
AT91C_ID_US0
};
#endif
#if defined(RT_USING_UART1)
static struct rt_serial_device serial1;
struct at91_uart uart1 = {
AT91C_BASE_US1,
AT91C_ID_US1
};
#endif
#if defined(RT_USING_UART2)
static struct rt_serial_device serial2;
struct at91_uart uart2 = {
AT91C_BASE_US2,
AT91C_ID_US2
};
#endif
#if defined(RT_USING_UART3)
static struct rt_serial_device serial3;
struct at91_uart uart3 = {
AT91C_BASE_US3,
AT91C_ID_US3
};
#endif
void at91_usart_gpio_init(void)
{
#ifdef RT_USING_DBGU
#define DRXD 12 // DBGU rx as Peripheral A on PB12
#define DTXD 13 // DBGU tx as Peripheral A on PB13
AT91C_BASE_PIOB->PIO_IDR, (1<<DRXD)|(1<<DTXD); // Disables the Input Change Interrupt on the I/O line
AT91C_BASE_PIOB->PIO_PPUDR, (1<<DRXD)|(1<<DTXD); // Disables the pull up resistor on the I/O line
AT91C_BASE_PIOB->PIO_ASR, (1<<DRXD)|(1<<DTXD); // Assigns the I/O line to the Peripheral A function
AT91C_BASE_PIOB->PIO_PDR, (1<<DRXD)|(1<<DTXD); // enables peripheral control of the pin
AT91C_BASE_PMC->PMC_PCER, 1 << AT91C_ID_SYS;
#endif
#ifdef RT_USING_UART0
#define RXD0 18 // UART0 rx as Peripheral A on PB18
#define TXD0 19 // UART0 tx as Peripheral A on PB19
AT91C_BASE_PMC->PMC_PCER, 1 << AT91C_ID_US0;
AT91C_BASE_PIOB->PIO_IDR, (1<<RXD0)|(1<<TXD0);
AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD0);
AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD0);
AT91C_BASE_PIOB->PIO_ASR, (1<<RXD0)|(1<<TXD0);
AT91C_BASE_PIOB->PIO_PDR, (1<<RXD0)|(1<<TXD0);
#endif
#ifdef RT_USING_UART1
#define TXD1 4 // UART1 tx as Peripheral A on PB4
#define RXD1 5 // UART1 rx as Peripheral A on PB5
AT91C_BASE_PMC->PMC_PCER, 1 << AT91C_ID_US1;
AT91C_BASE_PIOB->PIO_IDR, (1<<RXD1)|(1<<TXD1);
AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD1);
AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD1);
AT91C_BASE_PIOB->PIO_ASR, (1<<RXD1)|(1<<TXD1);
AT91C_BASE_PIOB->PIO_PDR, (1<<RXD1)|(1<<TXD1);
#endif
#ifdef RT_USING_UART2
#define TXD2 6 // UART2 tx as Peripheral A on PB6
#define RXD2 7 // UART2 rx as Peripheral A on PB7
AT91C_BASE_PMC->PMC_PCER, 1 << AT91C_ID_US2;
AT91C_BASE_PIOB->PIO_IDR, (1<<RXD2)|(1<<TXD2);
AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD2);
AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD2);
AT91C_BASE_PIOB->PIO_ASR, (1<<RXD2)|(1<<TXD2);
AT91C_BASE_PIOB->PIO_PDR, (1<<RXD2)|(1<<TXD2);
#endif
#ifdef RT_USING_UART3
#define TXD3 8 // UART3 tx as Peripheral A on PB8
#define RXD3 9 // UART3 rx as Peripheral A on PB9
AT91C_BASE_PMC->PMC_PCER, 1<<AT91C_ID_US3;
AT91C_BASE_PIOB->PIO_IDR, (1<<RXD3)|(1<<TXD3);
AT91C_BASE_PIOB->PIO_PPUER, (1<<RXD3);
AT91C_BASE_PIOB->PIO_PPUDR, (1<<TXD3);
AT91C_BASE_PIOB->PIO_ASR, (1<<RXD3)|(1<<TXD3);
AT91C_BASE_PIOB->PIO_PDR, (1<<RXD3)|(1<<TXD3);
#endif
}
/**
* This function will handle init uart
*/
int rt_hw_uart_init(void)
{
at91_usart_gpio_init();
#if defined(RT_USING_DBGU)
serial_dbgu.ops = &at91_usart_ops;
serial_dbgu.config.baud_rate = BAUD_RATE_115200;
serial_dbgu.config.bit_order = BIT_ORDER_LSB;
serial_dbgu.config.data_bits = DATA_BITS_8;
serial_dbgu.config.parity = PARITY_NONE;
serial_dbgu.config.stop_bits = STOP_BITS_1;
serial_dbgu.config.invert = NRZ_NORMAL;
serial_dbgu.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial_dbgu, "dbgu",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&dbgu);
#endif
#if defined(RT_USING_UART0)
serial0.ops = &at91_usart_ops;
serial0.config.baud_rate = BAUD_RATE_115200;
serial0.config.bit_order = BIT_ORDER_LSB;
serial0.config.data_bits = DATA_BITS_8;
serial0.config.parity = PARITY_NONE;
serial0.config.stop_bits = STOP_BITS_1;
serial0.config.invert = NRZ_NORMAL;
serial0.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial0, "uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
&uart0);
rt_hw_interrupt_install(uart0.irq, rt_at91_usart_handler,
(void *)&(serial0.parent), "UART0");
rt_hw_interrupt_umask(uart0.irq);
#endif
#if defined(RT_USING_UART1)
serial1.ops = &at91_usart_ops;
serial1.config.baud_rate = BAUD_RATE_115200;
serial1.config.bit_order = BIT_ORDER_LSB;
serial1.config.data_bits = DATA_BITS_8;
serial1.config.parity = PARITY_NONE;
serial1.config.stop_bits = STOP_BITS_1;
serial1.config.invert = NRZ_NORMAL;
serial1.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial1, "uart1",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart1);
rt_hw_interrupt_install(uart1.irq, rt_at91_usart_handler,
(void *)&(serial1.parent), "UART1");
rt_hw_interrupt_umask(uart1.irq);
#endif
#if defined(RT_USING_UART2)
serial2.ops = &at91_usart_ops;
serial2.config.baud_rate = BAUD_RATE_115200;
serial2.config.bit_order = BIT_ORDER_LSB;
serial2.config.data_bits = DATA_BITS_8;
serial2.config.parity = PARITY_NONE;
serial2.config.stop_bits = STOP_BITS_1;
serial2.config.invert = NRZ_NORMAL;
serial2.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial2, "uart2",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart2);
rt_hw_interrupt_install(uart2.irq, rt_at91_usart_handler,
(void *)&(serial2.parent), "UART2");
rt_hw_interrupt_umask(uart2.irq);
#endif
#if defined(RT_USING_UART3)
serial3.ops = &at91_usart_ops;
serial3.config.baud_rate = BAUD_RATE_115200;
serial3.config.bit_order = BIT_ORDER_LSB;
serial3.config.data_bits = DATA_BITS_8;
serial3.config.parity = PARITY_NONE;
serial3.config.stop_bits = STOP_BITS_1;
serial3.config.invert = NRZ_NORMAL;
serial3.config.bufsz = RT_SERIAL_RB_BUFSZ;
/* register vcom device */
rt_hw_serial_register(&serial3, "uart3",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart3);
rt_hw_interrupt_install(uart3.irq, rt_at91_usart_handler,
(void *)&(serial3.parent), "UART3");
rt_hw_interrupt_umask(uart3.irq);
#endif
return 0;
}
INIT_BOARD_EXPORT(rt_hw_uart_init);
#ifdef RT_USING_DBGU
void rt_dbgu_isr(void)
{
rt_at91_usart_handler(dbgu.irq, &(serial_dbgu.parent));
}
#endif
bsp/at91sam9g45/link_scripts/at91sam9g45_ram.icf 已删除 100644 → 0
浏览文件 @ 56075ce8
//------------------------------------------------------------------------------
// Linker scatter for running in external SDRAM on the AT91SAM9260
//------------------------------------------------------------------------------
//
// Define a memory region that covers the entire 4 GB addressible space of the
// processor.
//
define memory mem with size = 4G;
//
// Define a region for the on-chip flash.
//
define region FLASH = mem:[from 0x70000000 to 0x707FFFFF];
//
// Define a region for the on-chip SRAM.
//
define region SRAM = mem:[from 0x70800000 to 0x73FFFFFF];
//
// Indicate that the read/write values should be initialized by copying from
// flash.
//
initialize by copy { readwrite };
//
// Indicate that the noinit values should be left alone. This includes the
// stack, which if initialized will destroy the return address from the
// initialization code, causing the processor to branch to zero and fault.
//
do not initialize { section .noinit };
//
// Place the interrupt vectors at the start of flash.
//
place at start of FLASH { readonly section .intvec };
//
// Place the remainder of the read-only items into flash.
//
place in FLASH { readonly };
//
// Place the RAM vector table at the start of SRAM.
//
place at start of SRAM { section VTABLE };
//
// Place all read/write items into SRAM.
//
place in SRAM { readwrite};
keep { section FSymTab };
keep { section VSymTab };
keep { section .rti_fn* };
bsp/at91sam9g45/link_scripts/at91sam9g45_ram.ld 已删除 100644 → 0
浏览文件 @ 56075ce8
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(start)
SECTIONS
{
. = 0x70000000;
. = ALIGN(4);
.text :
{
*(.init)
*(.text)
*(.gnu.linkonce.t*)
/* section information for finsh shell */
. = ALIGN(4);
__fsymtab_start = .;
KEEP(*(FSymTab))
__fsymtab_end = .;
. = ALIGN(4);
__vsymtab_start = .;
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(4);
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
/* section information for modules */
. = ALIGN(4);
__rtmsymtab_start = .;
KEEP(*(RTMSymTab))
__rtmsymtab_end = .;
. = ALIGN(4);
/* section information for initial. */
. = ALIGN(4);
__rt_init_start = .;
KEEP(*(SORT(.rti_fn*)))
__rt_init_end = .;
. = ALIGN(4);
}
. = ALIGN(4);
.rodata : { *(.rodata) *(.rodata.*) *(.gnu.linkonce.r*) *(.eh_frame) }
. = ALIGN(4);
.ctors :
{
PROVIDE(__ctors_start__ = .);
KEEP(*(SORT(.ctors.*)))
KEEP(*(.ctors))
PROVIDE(__ctors_end__ = .);
}
.dtors :
{
PROVIDE(__dtors_start__ = .);
KEEP(*(SORT(.dtors.*)))
KEEP(*(.dtors))
PROVIDE(__dtors_end__ = .);
}
. = ALIGN(4);
.data :
{
*(.data)
*(.data.*)
*(.gnu.linkonce.d*)
}
. = ALIGN(4);
.nobss : { *(.nobss) }
. = ALIGN(4);
__bss_start__ = .;
.bss : { *(.bss)}
__bss_end__ = .;
/* stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_info 0 : { *(.debug_info) }
.debug_line 0 : { *(.debug_line) }
.debug_pubnames 0 : { *(.debug_pubnames) }
.debug_aranges 0 : { *(.debug_aranges) }
_end = .;
}
bsp/at91sam9g45/link_scripts/at91sam9g45_ram.scat 已删除 100644 → 0
浏览文件 @ 56075ce8
;*------------------------------------------------------------------------------
;* Linker scatter for running in external SDRAM on the AT91SAM9260
;*----------------------------------------------------------------------------*/
Load_region 0x70000000 0x00800000
{
Fixed_region 0x70000000
{
* (RESET +First)
.ANY (+RO +RW)
}
ARM_LIB_HEAP +0 EMPTY 0x1000
{
}
ARM_LIB_STACK +0 EMPTY 0x1000
{
}
; Application ZI data (.bss)
ER_ZI +0
{
* (+ZI)
}
;Relocate_region 0x200000 0x1000
;{
; *.o (VECTOR, +First)
;}
;ARM_LIB_HEAP 0x21FFE000 EMPTY 0x1000
;{
;}
;ARM_LIB_STACK 0x22000000 EMPTY -0x1000
;{
;}
}
bsp/at91sam9g45/platform/SConscript 已删除 100644 → 0
浏览文件 @ 56075ce8
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = GetCurrentDir()
CPPPATH = [cwd]
# The set of source files associated with this SConscript file.
if rtconfig.PLATFORM == 'armcc':
src = Glob('*.c') + Glob('*_rvds.S')
if rtconfig.PLATFORM == 'gcc':
src = Glob('*.c') + Glob('*_gcc.S') + Glob('*_init.S')
if rtconfig.PLATFORM == 'iar':
src = Glob('*.c') + Glob('*_iar.S')
if rtconfig.PLATFORM == 'cl':
src = Glob('*.c')
if rtconfig.PLATFORM == 'mingw':
src = Glob('*.c')
group = DefineGroup('platform', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/at91sam9g45/platform/at91sam9g45.h 已删除 100644 → 0
浏览文件 @ 56075ce8
此差异已折叠。
bsp/at91sam9g45/platform/gpio.h 已删除 100644 → 0
浏览文件 @ 56075ce8
/*
* File : gpio.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#ifndef __GPIO_H__
#define __GPIO_H__
#include <rtthread.h>
#define PIN_BASE AIC_IRQS
#define MAX_GPIO_BANKS 5
#define PIN_IRQS (MAX_GPIO_BANKS*32)
/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
#define AT91C_PIN_PA0 (PIN_BASE + 0x00 + 0)
#define AT91C_PIN_PA1 (PIN_BASE + 0x00 + 1)
#define AT91C_PIN_PA2 (PIN_BASE + 0x00 + 2)
#define AT91C_PIN_PA3 (PIN_BASE + 0x00 + 3)
#define AT91C_PIN_PA4 (PIN_BASE + 0x00 + 4)
#define AT91C_PIN_PA5 (PIN_BASE + 0x00 + 5)
#define AT91C_PIN_PA6 (PIN_BASE + 0x00 + 6)
#define AT91C_PIN_PA7 (PIN_BASE + 0x00 + 7)
#define AT91C_PIN_PA8 (PIN_BASE + 0x00 + 8)
#define AT91C_PIN_PA9 (PIN_BASE + 0x00 + 9)
#define AT91C_PIN_PA10 (PIN_BASE + 0x00 + 10)
#define AT91C_PIN_PA11 (PIN_BASE + 0x00 + 11)
#define AT91C_PIN_PA12 (PIN_BASE + 0x00 + 12)
#define AT91C_PIN_PA13 (PIN_BASE + 0x00 + 13)
#define AT91C_PIN_PA14 (PIN_BASE + 0x00 + 14)
#define AT91C_PIN_PA15 (PIN_BASE + 0x00 + 15)
#define AT91C_PIN_PA16 (PIN_BASE + 0x00 + 16)
#define AT91C_PIN_PA17 (PIN_BASE + 0x00 + 17)
#define AT91C_PIN_PA18 (PIN_BASE + 0x00 + 18)
#define AT91C_PIN_PA19 (PIN_BASE + 0x00 + 19)
#define AT91C_PIN_PA20 (PIN_BASE + 0x00 + 20)
#define AT91C_PIN_PA21 (PIN_BASE + 0x00 + 21)
#define AT91C_PIN_PA22 (PIN_BASE + 0x00 + 22)
#define AT91C_PIN_PA23 (PIN_BASE + 0x00 + 23)
#define AT91C_PIN_PA24 (PIN_BASE + 0x00 + 24)
#define AT91C_PIN_PA25 (PIN_BASE + 0x00 + 25)
#define AT91C_PIN_PA26 (PIN_BASE + 0x00 + 26)
#define AT91C_PIN_PA27 (PIN_BASE + 0x00 + 27)
#define AT91C_PIN_PA28 (PIN_BASE + 0x00 + 28)
#define AT91C_PIN_PA29 (PIN_BASE + 0x00 + 29)
#define AT91C_PIN_PA30 (PIN_BASE + 0x00 + 30)
#define AT91C_PIN_PA31 (PIN_BASE + 0x00 + 31)
#define AT91C_PIN_PB0 (PIN_BASE + 0x20 + 0)
#define AT91C_PIN_PB1 (PIN_BASE + 0x20 + 1)
#define AT91C_PIN_PB2 (PIN_BASE + 0x20 + 2)
#define AT91C_PIN_PB3 (PIN_BASE + 0x20 + 3)
#define AT91C_PIN_PB4 (PIN_BASE + 0x20 + 4)
#define AT91C_PIN_PB5 (PIN_BASE + 0x20 + 5)
#define AT91C_PIN_PB6 (PIN_BASE + 0x20 + 6)
#define AT91C_PIN_PB7 (PIN_BASE + 0x20 + 7)
#define AT91C_PIN_PB8 (PIN_BASE + 0x20 + 8)
#define AT91C_PIN_PB9 (PIN_BASE + 0x20 + 9)
#define AT91C_PIN_PB10 (PIN_BASE + 0x20 + 10)
#define AT91C_PIN_PB11 (PIN_BASE + 0x20 + 11)
#define AT91C_PIN_PB12 (PIN_BASE + 0x20 + 12)
#define AT91C_PIN_PB13 (PIN_BASE + 0x20 + 13)
#define AT91C_PIN_PB14 (PIN_BASE + 0x20 + 14)
#define AT91C_PIN_PB15 (PIN_BASE + 0x20 + 15)
#define AT91C_PIN_PB16 (PIN_BASE + 0x20 + 16)
#define AT91C_PIN_PB17 (PIN_BASE + 0x20 + 17)
#define AT91C_PIN_PB18 (PIN_BASE + 0x20 + 18)
#define AT91C_PIN_PB19 (PIN_BASE + 0x20 + 19)
#define AT91C_PIN_PB20 (PIN_BASE + 0x20 + 20)
#define AT91C_PIN_PB21 (PIN_BASE + 0x20 + 21)
#define AT91C_PIN_PB22 (PIN_BASE + 0x20 + 22)
#define AT91C_PIN_PB23 (PIN_BASE + 0x20 + 23)
#define AT91C_PIN_PB24 (PIN_BASE + 0x20 + 24)
#define AT91C_PIN_PB25 (PIN_BASE + 0x20 + 25)
#define AT91C_PIN_PB26 (PIN_BASE + 0x20 + 26)
#define AT91C_PIN_PB27 (PIN_BASE + 0x20 + 27)
#define AT91C_PIN_PB28 (PIN_BASE + 0x20 + 28)
#define AT91C_PIN_PB29 (PIN_BASE + 0x20 + 29)
#define AT91C_PIN_PB30 (PIN_BASE + 0x20 + 30)
#define AT91C_PIN_PB31 (PIN_BASE + 0x20 + 31)
#define AT91C_PIN_PC0 (PIN_BASE + 0x40 + 0)
#define AT91C_PIN_PC1 (PIN_BASE + 0x40 + 1)
#define AT91C_PIN_PC2 (PIN_BASE + 0x40 + 2)
#define AT91C_PIN_PC3 (PIN_BASE + 0x40 + 3)
#define AT91C_PIN_PC4 (PIN_BASE + 0x40 + 4)
#define AT91C_PIN_PC5 (PIN_BASE + 0x40 + 5)
#define AT91C_PIN_PC6 (PIN_BASE + 0x40 + 6)
#define AT91C_PIN_PC7 (PIN_BASE + 0x40 + 7)
#define AT91C_PIN_PC8 (PIN_BASE + 0x40 + 8)
#define AT91C_PIN_PC9 (PIN_BASE + 0x40 + 9)
#define AT91C_PIN_PC10 (PIN_BASE + 0x40 + 10)
#define AT91C_PIN_PC11 (PIN_BASE + 0x40 + 11)
#define AT91C_PIN_PC12 (PIN_BASE + 0x40 + 12)
#define AT91C_PIN_PC13 (PIN_BASE + 0x40 + 13)
#define AT91C_PIN_PC14 (PIN_BASE + 0x40 + 14)
#define AT91C_PIN_PC15 (PIN_BASE + 0x40 + 15)
#define AT91C_PIN_PC16 (PIN_BASE + 0x40 + 16)
#define AT91C_PIN_PC17 (PIN_BASE + 0x40 + 17)
#define AT91C_PIN_PC18 (PIN_BASE + 0x40 + 18)
#define AT91C_PIN_PC19 (PIN_BASE + 0x40 + 19)
#define AT91C_PIN_PC20 (PIN_BASE + 0x40 + 20)
#define AT91C_PIN_PC21 (PIN_BASE + 0x40 + 21)
#define AT91C_PIN_PC22 (PIN_BASE + 0x40 + 22)
#define AT91C_PIN_PC23 (PIN_BASE + 0x40 + 23)
#define AT91C_PIN_PC24 (PIN_BASE + 0x40 + 24)
#define AT91C_PIN_PC25 (PIN_BASE + 0x40 + 25)
#define AT91C_PIN_PC26 (PIN_BASE + 0x40 + 26)
#define AT91C_PIN_PC27 (PIN_BASE + 0x40 + 27)
#define AT91C_PIN_PC28 (PIN_BASE + 0x40 + 28)
#define AT91C_PIN_PC29 (PIN_BASE + 0x40 + 29)
#define AT91C_PIN_PC30 (PIN_BASE + 0x40 + 30)
#define AT91C_PIN_PC31 (PIN_BASE + 0x40 + 31)
#define AT91C_PIN_PD0 (PIN_BASE + 0x60 + 0)
#define AT91C_PIN_PD1 (PIN_BASE + 0x60 + 1)
#define AT91C_PIN_PD2 (PIN_BASE + 0x60 + 2)
#define AT91C_PIN_PD3 (PIN_BASE + 0x60 + 3)
#define AT91C_PIN_PD4 (PIN_BASE + 0x60 + 4)
#define AT91C_PIN_PD5 (PIN_BASE + 0x60 + 5)
#define AT91C_PIN_PD6 (PIN_BASE + 0x60 + 6)
#define AT91C_PIN_PD7 (PIN_BASE + 0x60 + 7)
#define AT91C_PIN_PD8 (PIN_BASE + 0x60 + 8)
#define AT91C_PIN_PD9 (PIN_BASE + 0x60 + 9)
#define AT91C_PIN_PD10 (PIN_BASE + 0x60 + 10)
#define AT91C_PIN_PD11 (PIN_BASE + 0x60 + 11)
#define AT91C_PIN_PD12 (PIN_BASE + 0x60 + 12)
#define AT91C_PIN_PD13 (PIN_BASE + 0x60 + 13)
#define AT91C_PIN_PD14 (PIN_BASE + 0x60 + 14)
#define AT91C_PIN_PD15 (PIN_BASE + 0x60 + 15)
#define AT91C_PIN_PD16 (PIN_BASE + 0x60 + 16)
#define AT91C_PIN_PD17 (PIN_BASE + 0x60 + 17)
#define AT91C_PIN_PD18 (PIN_BASE + 0x60 + 18)
#define AT91C_PIN_PD19 (PIN_BASE + 0x60 + 19)
#define AT91C_PIN_PD20 (PIN_BASE + 0x60 + 20)
#define AT91C_PIN_PD21 (PIN_BASE + 0x60 + 21)
#define AT91C_PIN_PD22 (PIN_BASE + 0x60 + 22)
#define AT91C_PIN_PD23 (PIN_BASE + 0x60 + 23)
#define AT91C_PIN_PD24 (PIN_BASE + 0x60 + 24)
#define AT91C_PIN_PD25 (PIN_BASE + 0x60 + 25)
#define AT91C_PIN_PD26 (PIN_BASE + 0x60 + 26)
#define AT91C_PIN_PD27 (PIN_BASE + 0x60 + 27)
#define AT91C_PIN_PD28 (PIN_BASE + 0x60 + 28)
#define AT91C_PIN_PD29 (PIN_BASE + 0x60 + 29)
#define AT91C_PIN_PD30 (PIN_BASE + 0x60 + 30)
#define AT91C_PIN_PD31 (PIN_BASE + 0x60 + 31)
#define AT91C_PIN_PE0 (PIN_BASE + 0x80 + 0)
#define AT91C_PIN_PE1 (PIN_BASE + 0x80 + 1)
#define AT91C_PIN_PE2 (PIN_BASE + 0x80 + 2)
#define AT91C_PIN_PE3 (PIN_BASE + 0x80 + 3)
#define AT91C_PIN_PE4 (PIN_BASE + 0x80 + 4)
#define AT91C_PIN_PE5 (PIN_BASE + 0x80 + 5)
#define AT91C_PIN_PE6 (PIN_BASE + 0x80 + 6)
#define AT91C_PIN_PE7 (PIN_BASE + 0x80 + 7)
#define AT91C_PIN_PE8 (PIN_BASE + 0x80 + 8)
#define AT91C_PIN_PE9 (PIN_BASE + 0x80 + 9)
#define AT91C_PIN_PE10 (PIN_BASE + 0x80 + 10)
#define AT91C_PIN_PE11 (PIN_BASE + 0x80 + 11)
#define AT91C_PIN_PE12 (PIN_BASE + 0x80 + 12)
#define AT91C_PIN_PE13 (PIN_BASE + 0x80 + 13)
#define AT91C_PIN_PE14 (PIN_BASE + 0x80 + 14)
#define AT91C_PIN_PE15 (PIN_BASE + 0x80 + 15)
#define AT91C_PIN_PE16 (PIN_BASE + 0x80 + 16)
#define AT91C_PIN_PE17 (PIN_BASE + 0x80 + 17)
#define AT91C_PIN_PE18 (PIN_BASE + 0x80 + 18)
#define AT91C_PIN_PE19 (PIN_BASE + 0x80 + 19)
#define AT91C_PIN_PE20 (PIN_BASE + 0x80 + 20)
#define AT91C_PIN_PE21 (PIN_BASE + 0x80 + 21)
#define AT91C_PIN_PE22 (PIN_BASE + 0x80 + 22)
#define AT91C_PIN_PE23 (PIN_BASE + 0x80 + 23)
#define AT91C_PIN_PE24 (PIN_BASE + 0x80 + 24)
#define AT91C_PIN_PE25 (PIN_BASE + 0x80 + 25)
#define AT91C_PIN_PE26 (PIN_BASE + 0x80 + 26)
#define AT91C_PIN_PE27 (PIN_BASE + 0x80 + 27)
#define AT91C_PIN_PE28 (PIN_BASE + 0x80 + 28)
#define AT91C_PIN_PE29 (PIN_BASE + 0x80 + 29)
#define AT91C_PIN_PE30 (PIN_BASE + 0x80 + 30)
#define AT91C_PIN_PE31 (PIN_BASE + 0x80 + 31)
rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio)
{
return gpio;
}
#endif
bsp/at91sam9g45/platform/interrupt.c 已删除 100644 → 0
浏览文件 @ 56075ce8
/*
* File : interrupt.c
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#include <rthw.h>
#include "at91sam9g45.h"
#include "interrupt.h"
#define AIC_IRQS 32
#define MAX_HANDLERS (AIC_IRQS + PIN_IRQS)
extern rt_uint32_t rt_interrupt_nest;
/* exception and interrupt handler table */
struct rt_irq_desc irq_desc[MAX_HANDLERS];
rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
rt_uint32_t rt_thread_switch_interrupt_flag;
/* --------------------------------------------------------------------
* Interrupt initialization
* -------------------------------------------------------------------- */
rt_uint32_t at91_extern_irq;
#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq)
/*
* The default interrupt priority levels (0 = lowest, 7 = highest).
*/
static rt_uint32_t at91sam9g45_default_irq_priority[MAX_HANDLERS] = {
7, /* Advanced Interrupt Controller - FIQ */
7, /* System Controller Interrupt */
1, /* Parallel I/O Controller A, */
1, /* Parallel I/O Controller B */
1, /* Parallel I/O Controller C */
0, /* Parallel I/O Controller D/E */
5, /* True Random Number Generator */
5, /* USART 0 */
5, /* USART 1 */
0, /* USART 2 */
2, /* USART 3 */
6, /* High Speed Multimedia Card Interface 0 */
5, /* Two-Wire Interface 0 */
5, /* Two-Wire Interface 1 */
5, /* Serial Peripheral Interface */
0, /* Serial Peripheral Interface */
0, /* Synchronous Serial Controller 0 */
0, /* Synchronous Serial Controller 1 */
0, /* Timer Counter 0,1,2,3,4,5 */
0, /* Pulse Width Modulation Controller */
2, /* Touch Screen ADC Controller */
3, /* DMA Controller */
0, /* USB Host High Speed */
5, /* LCD Controller */
5, /* AC97 Controller */
5, /* Ethernet MAC */
0, /* Image Sensor Interface */
0, /* USB Device High Speed */
0, /* N/A */
0, /* High Speed Multimedia Card Interface 1 */
0, /* Reserved */
0, /* Advanced Interrupt Controller - IRQ */
};
/**
* @addtogroup AT91SAM9G45
*/
/*@{*/
void rt_hw_interrupt_mask(int irq);
void rt_hw_interrupt_umask(int irq);
rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param)
{
rt_kprintf("Unhandled interrupt %d occured!!!\n", vector);
return RT_NULL;
}
rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t bank, void *param)
{
rt_uint32_t isr, irq_n;
AT91PS_PIO pio;
void *parameter;
switch (bank)
{
case 0: pio = AT91C_BASE_PIOA; break;
case 1: pio = AT91C_BASE_PIOB; break;
case 2: pio = AT91C_BASE_PIOC; break;
case 3: pio = AT91C_BASE_PIOD; break;
case 4: pio = AT91C_BASE_PIOE; break;
default: return RT_NULL;
}
irq_n = AIC_IRQS + 32*bank;
isr = readl(pio->PIO_ISR);
isr &= readl(pio->PIO_IMR);
while (isr)
{
if (isr & 1)
{
parameter = irq_desc[irq_n].param;
irq_desc[irq_n].handler(irq_n, parameter);
}
isr >>= 1;
irq_n++;
}
return RT_NULL;
}
unsigned int SpuriousCount = 0;
static void DefaultSpuriousHandler( void )
{
SpuriousCount++;
rt_kprintf("Spurious interrupt %d occured!!!\n", SpuriousCount);
return ;
}
static void DefaultFiqHandler(void)
{
rt_kprintf("Unhandled FIQ occured!!!\n");
while (1);
}
static void DefaultIrqHandler(void)
{
rt_kprintf("Unhandled IRQ %d occured!!!\n", AT91C_BASE_AIC->AIC_ISR);
while (1);
}
/*
* Initialize the AIC interrupt controller.
*/
void at91_aic_init(rt_uint32_t *priority)
{
rt_uint32_t i;
/*
* The IVR is used by macro get_irqnr_and_base to read and verify.
* The irq number is NR_AIC_IRQS when a spurious interrupt has occurred.
*/
AT91C_BASE_AIC->AIC_SVR[0] = (rt_uint32_t)DefaultFiqHandler;
for (i = 1; i < AIC_IRQS; i++) {
/* Put irq number in Source Vector Register: */
AT91C_BASE_AIC->AIC_SVR[i] = (rt_uint32_t)DefaultIrqHandler; // no-used
/* Active Low interrupt, with the specified priority */
AT91C_BASE_AIC->AIC_SMR[i] = AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE | priority[i];
//AT91C_AIC_SRCTYPE_FALLING
}
/*
* Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS
* When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU
*/
AT91C_BASE_AIC->AIC_SPU = (rt_uint32_t)DefaultSpuriousHandler;
/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
for (i = 0; i < 8; i++)
AT91C_BASE_AIC->AIC_EOICR = 0;
/* No debugging in AIC: Debug (Protect) Control Register */
AT91C_BASE_AIC->AIC_DCR = 0;
/* Disable and clear all interrupts initially */
AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
}
static void at91_gpio_irq_init()
{
int i, idx;
char *name[] = {"PIOA", "PIOB", "PIOC", "PIODE"};
rt_uint32_t aic_pids[] = { AT91C_ID_PIOA, AT91C_ID_PIOB, AT91C_ID_PIOC, AT91C_ID_PIOD_E };
AT91C_BASE_PIOA->PIO_IDR = 0xffffffff;
AT91C_BASE_PIOB->PIO_IDR = 0xffffffff;
AT91C_BASE_PIOC->PIO_IDR = 0xffffffff;
AT91C_BASE_PIOD->PIO_IDR = 0xffffffff;
AT91C_BASE_PIOE->PIO_IDR = 0xffffffff;
for (i = 0; i < 4; i++)
{
idx = aic_pids[i];
irq_desc[idx].handler = (rt_isr_handler_t)at91_gpio_irq_handle;
irq_desc[idx].param = RT_NULL;
#ifdef RT_USING_INTERRUPT_INFO
rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]);
irq_desc[idx].counter = 0;
#endif
rt_hw_interrupt_umask(idx);
}
}
/**
* This function will initialize hardware interrupt
*/
void rt_hw_interrupt_init(void)
{
register rt_uint32_t idx;
rt_uint32_t *priority = at91sam9g45_default_irq_priority;
at91_extern_irq = (1UL << AT91C_ID_IRQ0);
/* Initialize the AIC interrupt controller */
at91_aic_init(priority);
/* init exceptions table */
for(idx=0; idx < MAX_HANDLERS; idx++)
{
irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle;
irq_desc[idx].param = RT_NULL;
#ifdef RT_USING_INTERRUPT_INFO
rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default");
irq_desc[idx].counter = 0;
#endif
}
at91_gpio_irq_init();
/* init interrupt nest, and context in thread sp */
rt_interrupt_nest = 0;
rt_interrupt_from_thread = 0;
rt_interrupt_to_thread = 0;
rt_thread_switch_interrupt_flag = 0;
}
static void at91_gpio_irq_mask(int irq)
{
rt_uint32_t pin, bank;
AT91PS_PIO pio;
bank = (irq - AIC_IRQS)>>5;
switch (bank)
{
case 0: pio = AT91C_BASE_PIOA; break;
case 1: pio = AT91C_BASE_PIOB; break;
case 2: pio = AT91C_BASE_PIOC; break;
case 3: pio = AT91C_BASE_PIOD; break;
case 4: pio = AT91C_BASE_PIOE; break;
default: return;
}
pin = 1 << ((irq - AIC_IRQS) & 31);
pio->PIO_IDR = pin;
}
/**
* This function will mask a interrupt.
* @param irq the interrupt number
*/
void rt_hw_interrupt_mask(int irq)
{
if (irq >= AIC_IRQS)
{
at91_gpio_irq_mask(irq);
}
else
{
/* Disable interrupt on AIC */
AT91C_BASE_AIC->AIC_IDCR = 1 << irq;
}
}
static void at91_gpio_irq_umask(int irq)
{
rt_uint32_t pin, bank;
AT91PS_PIO pio;
bank = (irq - AIC_IRQS)>>5;
switch (bank)
{
case 0: pio = AT91C_BASE_PIOA; break;
case 1: pio = AT91C_BASE_PIOB; break;
case 2: pio = AT91C_BASE_PIOC; break;
case 3: pio = AT91C_BASE_PIOD; break;
case 4: pio = AT91C_BASE_PIOE; break;
default: return;
}
pin = 1 << ((irq - AIC_IRQS) & 31);
pio->PIO_IER = pin;
}
/**
* This function will un-mask a interrupt.
* @param vector the interrupt number
*/
void rt_hw_interrupt_umask(int irq)
{
if (irq >= AIC_IRQS)
{
at91_gpio_irq_umask(irq);
}
else
{
/* Enable interrupt on AIC */
AT91C_BASE_AIC->AIC_IECR = 1 << irq;
}
}
/**
* This function will install a interrupt service routine to a interrupt.
* @param vector the interrupt number
* @param handler the interrupt service routine to be installed
* @param param the interrupt service function parameter
* @param name the interrupt name
* @return old handler
*/
rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
void *param, char *name)
{
rt_isr_handler_t old_handler = RT_NULL;
if (vector < MAX_HANDLERS)
{
old_handler = irq_desc[vector].handler;
if (handler != RT_NULL)
{
irq_desc[vector].handler = (rt_isr_handler_t)handler;
irq_desc[vector].param = param;
#ifdef RT_USING_INTERRUPT_INFO
rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
irq_desc[vector].counter = 0;
#endif
}
}
return old_handler;
}
/*@}*/
/*
static int at91_aic_set_type(unsigned irq, unsigned type)
{
unsigned int smr, srctype;
switch (type) {
case AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL:
srctype = AT91C_AIC_SRCTYPE_HIGH;
break;
case AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE:
srctype = AT91C_AIC_SRCTYPE_RISING;
break;
case AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE:
// only supported on external interrupts
if ((irq == AT91C_ID_FIQ) || is_extern_irq(irq))
srctype = AT91C_AIC_SRCTYPE_LOW;
else
return -1;
break;
case AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED:
// only supported on external interrupts
if ((irq == AT91C_ID_FIQ) || is_extern_irq(irq))
srctype = AT91C_AIC_SRCTYPE_FALLING;
else
return -1;
break;
default:
return -1;
}
smr = readl(AT91C_AIC_SMR(irq)) & ~AT91C_AIC_SRCTYPE;
AT91C_BASE_AIC->AIC_SMR[irq] = smr | srctype;
return 0;
}
*/
rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq)
{
//volatile rt_uint32_t irqstat;
rt_uint32_t id;
if (fiq_irq == INT_FIQ)
return 0;
//IRQ
/* AIC need this dummy read */
readl(AT91C_AIC_IVR);
/* clear pending register */
id = readl(AT91C_AIC_ISR);
return id;
}
void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id)
{
/* new FIQ generation */
if (fiq_irq == INT_FIQ)
return;
/* new IRQ generation */
// EIOCR must be write any value after interrupt,
// or else can't response next interrupt
AT91C_BASE_AIC->AIC_EOICR = 0x0;
}
#ifdef RT_USING_FINSH
#ifdef RT_USING_INTERRUPT_INFO
void list_irq(void)
{
int irq;
rt_kprintf("number\tcount\tname\n");
for (irq = 0; irq < MAX_HANDLERS; irq++)
{
if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default")))
{
rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name);
}
}
}
#include <finsh.h>
FINSH_FUNCTION_EXPORT(list_irq, list system irq);
#ifdef FINSH_USING_MSH
int cmd_list_irq(int argc, char** argv)
{
list_irq();
return 0;
}
FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.);
#endif
#endif
#endif
bsp/at91sam9g45/platform/interrupt.h 已删除 100644 → 0
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/*
* File : interrupt.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2015-04-14 ArdaFu first version
*/
#ifndef __INTERRUPT_H__
#define __INTERRUPT_H__
#define INT_IRQ 0x00
#define INT_FIQ 0x01
#endif
bsp/at91sam9g45/platform/io.h 已删除 100644 → 0
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/*
* File : io.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#ifndef __ASM_ARCH_IO_H
#define __ASM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xFFFFFFFF
#define readb(a) (*(volatile unsigned char *)(a))
#define readw(a) (*(volatile unsigned short *)(a))
#define readl(a) (*(volatile unsigned int *)(a))
#define writeb(v,a) (*(volatile unsigned char *)(a) = (v))
#define writew(v,a) (*(volatile unsigned short *)(a) = (v))
#define writel(v,a) (*(volatile unsigned int *)(a) = (v))
#endif
bsp/at91sam9g45/platform/irq.h 已删除 100644 → 0
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/*
* File : irq.h
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2006, RT-Thread Develop Team
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*
* Change Logs:
* Date Author Notes
* 2011-01-13 weety first version
*/
#ifndef __IRQ_H__
#define __IRQ_H__
#ifdef __cplusplus
extern "C" {
#endif
/*
* IRQ line status.
*
* Bits 0-7 are reserved
*
* IRQ types
*/
#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */
#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */
#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */
#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */
#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */
#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */
#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */
#ifdef __cplusplus
}
#endif
#endif
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\template.ewp</path>
</project>
<batchBuild/>
</workspace>
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