diff --git a/bsp/at91sam9g45/.config b/bsp/at91sam9g45/.config deleted file mode 100644 index 5f3ae786734ac4c1473d150e476c8f45be7a0ac4..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/.config +++ /dev/null @@ -1,311 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# - -# -# RT-Thread Kernel -# -CONFIG_RT_NAME_MAX=16 -CONFIG_RT_ALIGN_SIZE=4 -# CONFIG_RT_THREAD_PRIORITY_8 is not set -CONFIG_RT_THREAD_PRIORITY_32=y -# CONFIG_RT_THREAD_PRIORITY_256 is not set -CONFIG_RT_THREAD_PRIORITY_MAX=32 -CONFIG_RT_TICK_PER_SECOND=1000 -CONFIG_RT_USING_OVERFLOW_CHECK=y -CONFIG_RT_USING_HOOK=y -CONFIG_RT_IDEL_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 -# CONFIG_RT_USING_TIMER_SOFT is not set -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set - -# -# Inter-Thread communication -# -CONFIG_RT_USING_SEMAPHORE=y -CONFIG_RT_USING_MUTEX=y -CONFIG_RT_USING_EVENT=y -CONFIG_RT_USING_MAILBOX=y -CONFIG_RT_USING_MESSAGEQUEUE=y -# CONFIG_RT_USING_SIGNALS is not set - -# -# Memory Management -# -CONFIG_RT_USING_MEMPOOL=y -# CONFIG_RT_USING_MEMHEAP is not set -# CONFIG_RT_USING_NOHEAP is not set -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set -# CONFIG_RT_USING_MEMTRACE is not set -CONFIG_RT_USING_HEAP=y - -# -# Kernel Device Object -# -CONFIG_RT_USING_DEVICE=y -# CONFIG_RT_USING_DEVICE_OPS is not set -CONFIG_RT_USING_INTERRUPT_INFO=y -CONFIG_RT_USING_CONSOLE=y -CONFIG_RT_CONSOLEBUF_SIZE=128 -CONFIG_RT_CONSOLE_DEVICE_NAME="dbgu" - -# -# RT-Thread Components -# -CONFIG_RT_USING_COMPONENTS_INIT=y -CONFIG_RT_USING_USER_MAIN=y -CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 -CONFIG_RT_MAIN_THREAD_PRIORITY=10 - -# -# C++ features -# -CONFIG_RT_USING_CPLUSPLUS=y - -# -# Command shell -# -CONFIG_RT_USING_FINSH=y -CONFIG_FINSH_THREAD_NAME="tshell" -CONFIG_FINSH_USING_HISTORY=y -CONFIG_FINSH_HISTORY_LINES=5 -CONFIG_FINSH_USING_SYMTAB=y -CONFIG_FINSH_USING_DESCRIPTION=y -# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set -CONFIG_FINSH_THREAD_PRIORITY=20 -CONFIG_FINSH_THREAD_STACK_SIZE=4096 -CONFIG_FINSH_CMD_SIZE=80 -# CONFIG_FINSH_USING_AUTH is not set -CONFIG_FINSH_USING_MSH=y -CONFIG_FINSH_USING_MSH_DEFAULT=y -# CONFIG_FINSH_USING_MSH_ONLY is not set -CONFIG_FINSH_ARG_MAX=10 - -# -# Device virtual file system -# -CONFIG_RT_USING_DFS=y -CONFIG_DFS_USING_WORKDIR=y -CONFIG_DFS_FILESYSTEMS_MAX=2 -CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 -CONFIG_DFS_FD_MAX=16 -# CONFIG_RT_USING_DFS_MNTTABLE is not set -# CONFIG_RT_USING_DFS_ELMFAT is not set -CONFIG_RT_USING_DFS_DEVFS=y -# CONFIG_RT_USING_DFS_ROMFS is not set -# CONFIG_RT_USING_DFS_RAMFS is not set -# CONFIG_RT_USING_DFS_UFFS is not set -# CONFIG_RT_USING_DFS_JFFS2 is not set -# CONFIG_RT_USING_DFS_NFS is not set - -# -# Device Drivers -# -CONFIG_RT_USING_DEVICE_IPC=y -CONFIG_RT_PIPE_BUFSZ=512 -CONFIG_RT_USING_SERIAL=y -# CONFIG_RT_USING_CAN is not set -# CONFIG_RT_USING_HWTIMER is not set -# CONFIG_RT_USING_CPUTIME is not set -# CONFIG_RT_USING_I2C is not set -CONFIG_RT_USING_PIN=y -# CONFIG_RT_USING_PWM is not set -# CONFIG_RT_USING_MTD_NOR is not set -# CONFIG_RT_USING_MTD_NAND is not set -# CONFIG_RT_USING_RTC is not set -# CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set -# CONFIG_RT_USING_WDT is not set -# CONFIG_RT_USING_WIFI is not set -# CONFIG_RT_USING_AUDIO is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set - -# -# POSIX layer and C standard library -# -CONFIG_RT_USING_LIBC=y -CONFIG_RT_USING_PTHREADS=y -# CONFIG_RT_USING_MODULE is not set - -# -# Network -# - -# -# Socket abstraction layer -# -# CONFIG_RT_USING_SAL is not set - -# -# light weight TCP/IP stack -# -# CONFIG_RT_USING_LWIP is not set - -# -# Modbus master and slave stack -# -# CONFIG_RT_USING_MODBUS is not set - -# -# AT commands -# -# CONFIG_RT_USING_AT is not set - -# -# VBUS(Virtual Software BUS) -# -# CONFIG_RT_USING_VBUS is not set - -# -# Utilities -# -# CONFIG_RT_USING_LOGTRACE is not set -# CONFIG_RT_USING_RYM is not set - -# -# RT-Thread online packages -# - -# -# IoT - internet of things -# -# CONFIG_PKG_USING_PAHOMQTT is not set -# CONFIG_PKG_USING_WEBCLIENT is not set -# CONFIG_PKG_USING_MONGOOSE is not set -# CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_CJSON is not set -# CONFIG_PKG_USING_JSMN is not set -# CONFIG_PKG_USING_LJSON is not set -# CONFIG_PKG_USING_EZXML is not set -# CONFIG_PKG_USING_NANOPB is not set - -# -# Wi-Fi -# - -# -# Marvell WiFi -# -# CONFIG_PKG_USING_WLANMARVELL is not set - -# -# Wiced WiFi -# -# CONFIG_PKG_USING_WLAN_WICED is not set -# CONFIG_PKG_USING_COAP is not set -# CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set -# CONFIG_PKG_USING_AT_DEVICE is not set - -# -# IoT Cloud -# -# CONFIG_PKG_USING_ONENET is not set -# CONFIG_PKG_USING_GAGENT_CLOUD is not set -# CONFIG_PKG_USING_ALI_IOTKIT is not set -# CONFIG_PKG_USING_AZURE is not set - -# -# security packages -# -# CONFIG_PKG_USING_MBEDTLS is not set -# CONFIG_PKG_USING_libsodium is not set -# CONFIG_PKG_USING_TINYCRYPT is not set - -# -# language packages -# -# CONFIG_PKG_USING_LUA is not set -# CONFIG_PKG_USING_JERRYSCRIPT is not set -# CONFIG_PKG_USING_MICROPYTHON is not set - -# -# multimedia packages -# -# CONFIG_PKG_USING_OPENMV is not set -# CONFIG_PKG_USING_MUPDF is not set - -# -# tools packages -# -# CONFIG_PKG_USING_CMBACKTRACE is not set -# CONFIG_PKG_USING_EASYFLASH is not set -# CONFIG_PKG_USING_EASYLOGGER is not set -# CONFIG_PKG_USING_SYSTEMVIEW is not set - -# -# system packages -# -# CONFIG_PKG_USING_GUIENGINE is not set -# CONFIG_PKG_USING_CAIRO is not set -# CONFIG_PKG_USING_PIXMAN is not set -# CONFIG_PKG_USING_LWEXT4 is not set -# CONFIG_PKG_USING_PARTITION is not set -# CONFIG_PKG_USING_FAL is not set -# CONFIG_PKG_USING_SQLITE is not set -# CONFIG_PKG_USING_RTI is not set -# CONFIG_PKG_USING_LITTLEVGL2RTT is not set - -# -# peripheral libraries and drivers -# -# CONFIG_PKG_USING_STM32F4_HAL is not set -# CONFIG_PKG_USING_STM32F4_DRIVERS is not set -# CONFIG_PKG_USING_REALTEK_AMEBA is not set -# CONFIG_PKG_USING_SHT2X is not set -# CONFIG_PKG_USING_AHT10 is not set -# CONFIG_PKG_USING_AP3216C is not set -# CONFIG_PKG_USING_STM32_SDIO is not set - -# -# miscellaneous packages -# -# CONFIG_PKG_USING_LIBCSV is not set -# CONFIG_PKG_USING_OPTPARSE is not set -# CONFIG_PKG_USING_FASTLZ is not set -# CONFIG_PKG_USING_MINILZO is not set -# CONFIG_PKG_USING_QUICKLZ is not set -# CONFIG_PKG_USING_MULTIBUTTON is not set -# CONFIG_PKG_USING_CANFESTIVAL is not set -# CONFIG_PKG_USING_ZLIB is not set -# CONFIG_PKG_USING_DSTR is not set - -# -# sample package -# - -# -# samples: kernel and components samples -# -# CONFIG_PKG_USING_KERNEL_SAMPLES is not set -# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set -# CONFIG_PKG_USING_NETWORK_SAMPLES is not set -# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set - -# -# example package: hello -# -# CONFIG_PKG_USING_HELLO is not set -CONFIG_RT_USING_DBGU=y -# CONFIG_RT_USING_UART0 is not set -# CONFIG_RT_USING_UART1 is not set -# CONFIG_RT_USING_UART2 is not set -# CONFIG_RT_USING_UART3 is not set -CONFIG_RT_USING_LED=y diff --git a/bsp/at91sam9g45/SConscript b/bsp/at91sam9g45/SConscript deleted file mode 100644 index fe0ae941ae9a759ae478de901caec1c961e56af8..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/SConscript +++ /dev/null @@ -1,14 +0,0 @@ -# for module compiling -import os -Import('RTT_ROOT') - -cwd = str(Dir('#')) -objs = [] -list = os.listdir(cwd) - -for d in list: - path = os.path.join(cwd, d) - if os.path.isfile(os.path.join(path, 'SConscript')): - objs = objs + SConscript(os.path.join(d, 'SConscript')) - -Return('objs') diff --git a/bsp/at91sam9g45/SConstruct b/bsp/at91sam9g45/SConstruct deleted file mode 100644 index 41139a3377362a84276e7356082260e740ebf47e..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/SConstruct +++ /dev/null @@ -1,39 +0,0 @@ -import os -import sys -import rtconfig - -if os.getenv('RTT_ROOT'): - RTT_ROOT = os.getenv('RTT_ROOT') -else: - RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') - -sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] -from building import * - -TARGET = 'rtthread-at91sam9g45.' + rtconfig.TARGET_EXT - -env = Environment(tools = ['mingw'], - AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, - CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, - CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CFLAGS, - AR = rtconfig.AR, ARFLAGS = '-rc', - LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) -env.PrependENVPath('PATH', rtconfig.EXEC_PATH) - -Export('RTT_ROOT') -Export('rtconfig') - -# prepare building environment -objs = PrepareBuilding(env, RTT_ROOT) - -if GetDepend('RT_USING_WEBSERVER'): - objs = objs + SConscript(RTT_ROOT + '/components/net/webserver/SConscript', variant_dir='build/net/webserver', duplicate=0) - -if GetDepend('RT_USING_RTGUI'): - objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0) - -# libc testsuite -objs = objs + SConscript(RTT_ROOT + '/examples/libc/SConscript', variant_dir='build/examples/libc', duplicate=0) - -# make a building -DoBuilding(TARGET, objs) diff --git a/bsp/at91sam9g45/applications/SConscript b/bsp/at91sam9g45/applications/SConscript deleted file mode 100644 index 01eb940dfb35f92c503a78b0b49a4354590f9f3a..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/applications/SConscript +++ /dev/null @@ -1,11 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'applications') -src = Glob('*.c') -CPPPATH = [cwd, str(Dir('#'))] - -group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/at91sam9g45/applications/application.c b/bsp/at91sam9g45/applications/application.c deleted file mode 100644 index ec878faa858db7f75f0bf07370b7a37c018cbe8a..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/applications/application.c +++ /dev/null @@ -1,173 +0,0 @@ -/* - * File : application.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - */ - -/** - * @addtogroup at91sam9260 - */ -/*@{*/ - -#include -#include - -#ifdef RT_USING_DFS -/* dfs Filesystem APIs */ -#include -#endif - -#ifdef RT_USING_SDIO -#include -#include "at91_mci.h" -#endif - -#ifdef RT_USING_LED -#include "led.h" -#endif - -static int rt_led_app_init(void); - -RT_WEAK int main(void) -{ -#ifdef RT_USING_SDIO - int timeout = 0; -#endif - -/* Filesystem Initialization */ -#ifdef RT_USING_DFS - { -#if defined(RT_USING_DFS_ROMFS) - if (dfs_mount(RT_NULL, "/rom", "rom", 0, &romfs_root) == 0) - { - rt_kprintf("ROM File System initialized!\n"); - } - else - rt_kprintf("ROM File System initialzation failed!\n"); -#endif - -#if defined(RT_USING_DFS_UFFS) - { - /* mount flash device as flash directory */ - if(dfs_mount("nand0", "/nand0", "uffs", 0, 0) == 0) - rt_kprintf("UFFS File System initialized!\n"); - else - rt_kprintf("UFFS File System initialzation failed!\n"); - } -#endif - -#ifdef RT_USING_SDIO - timeout = 0; - while ((rt_device_find("sd0") == RT_NULL) && (timeout++ < RT_TICK_PER_SECOND*2)) - { - rt_thread_delay(1); - } - - if (timeout < RT_TICK_PER_SECOND*2) - { - /* mount sd card fat partition 1 as root directory */ - if (dfs_mount("sd0", "/", "elm", 0, 0) == 0) - { - rt_kprintf("File System initialized!\n"); - } - else - rt_kprintf("File System initialzation failed!%d\n", rt_get_errno()); - } - else - { - rt_kprintf("No SD card found.\n"); - } -#endif - } -#endif - - rt_led_app_init(); -} - -#ifdef RT_USING_LED -void rt_led_thread_entry(void* parameter) -{ - rt_uint8_t cnt = 0; - led_init(); - while(1) - { - /* light on leds for one second */ - rt_thread_delay(40); - cnt++; - if (cnt&0x01) - led_on(1); - else - led_off(1); - if (cnt&0x02) - led_on(2); - else - led_off(2); - if (cnt&0x04) - led_on(3); - else - led_off(3); - - } -} -#endif - -static int rt_led_app_init(void) -{ -#ifdef RT_USING_LED - rt_thread_t led_thread; - -#if (RT_THREAD_PRIORITY_MAX == 32) - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 20, 20); -#else - led_thread = rt_thread_create("led", - rt_led_thread_entry, RT_NULL, - 512, 200, 20); -#endif - - if(led_thread != RT_NULL) - rt_thread_startup(led_thread); -#endif - - return 0; -} - -/* NFSv3 Initialization */ -#if defined(RT_USING_DFS) && defined(RT_USING_LWIP) && defined(RT_USING_DFS_NFS) -#include -void nfs_start(void) -{ - nfs_init(); - - if (dfs_mount(RT_NULL, "/nfs", "nfs", 0, RT_NFS_HOST_EXPORT) == 0) - { - rt_kprintf("NFSv3 File System initialized!\n"); - } - else - rt_kprintf("NFSv3 File System initialzation failed!\n"); -} - -#include "finsh.h" -FINSH_FUNCTION_EXPORT(nfs_start, start net filesystem); -#endif - -/*@}*/ diff --git a/bsp/at91sam9g45/drivers/SConscript b/bsp/at91sam9g45/drivers/SConscript deleted file mode 100644 index d0470f904950ab1f18aebde4492e0d7fcbc6cbfb..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/drivers/SConscript +++ /dev/null @@ -1,31 +0,0 @@ -Import('RTT_ROOT') -Import('rtconfig') -from building import * - -cwd = os.path.join(str(Dir('#')), 'drivers') - -# add the general drvers. -src = Split(""" -board.c -usart.c -""") - -# add Ethernet drvers. -if GetDepend('RT_USING_LED'): - src += ['led.c'] - -if GetDepend('RT_USING_SDIO'): - src += ['at91_mci.c'] - -if GetDepend('RT_USING_LWIP'): - src += ['macb.c'] - -if GetDepend('RT_USING_I2C') and GetDepend('RT_USING_I2C_BITOPS'): - src += ['at91_i2c_gpio.c'] - - -CPPPATH = [cwd] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -Return('group') diff --git a/bsp/at91sam9g45/drivers/at91_i2c_gpio.c b/bsp/at91sam9g45/drivers/at91_i2c_gpio.c deleted file mode 100644 index 91ca646c7a95fdabf4613da20339a7168138aa0d..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/drivers/at91_i2c_gpio.c +++ /dev/null @@ -1,130 +0,0 @@ -/* - * File : at91_i2c_gpio.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2012-04-25 weety first version - */ - -#include -#include -#include - - -static void at91_i2c_gpio_init() -{ - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_PIOA; //enable PIOA clock - AT91C_BASE_PIOA->PIO_PUER = (1 << 23); - AT91C_BASE_PIOA->PIO_PER = (1 << 23); - AT91C_BASE_PIOA->PIO_MDER = (1 << 23); - AT91C_BASE_PIOA->PIO_PUER = (1 << 24); - AT91C_BASE_PIOA->PIO_PER = (1 << 24); - AT91C_BASE_PIOA->PIO_MDER = (1 << 24); - - AT91C_BASE_PIOA->PIO_OER = (1 << 23); - AT91C_BASE_PIOA->PIO_OER = (1 << 24); - - AT91C_BASE_PIOA->PIO_SODR = (1 << 23); - AT91C_BASE_PIOA->PIO_SODR = (1 << 24); -} - -static void at91_set_sda(void *data, rt_int32_t state) -{ - if (state) - { - AT91C_BASE_PIOA->PIO_SODR = (1 << 23); - } - else - { - AT91C_BASE_PIOA->PIO_CODR = (1 << 23); - } -} - -static void at91_set_scl(void *data, rt_int32_t state) -{ - if (state) - { - AT91C_BASE_PIOA->PIO_SODR = (1 << 24); - } - else - { - AT91C_BASE_PIOA->PIO_CODR = (1 << 24); - } -} - -static rt_int32_t at91_get_sda(void *data) -{ - return AT91C_BASE_PIOA->PIO_PDSR & (1 << 23); -} - -static rt_int32_t at91_get_scl(void *data) -{ - return AT91C_BASE_PIOA->PIO_PDSR & (1 << 24); -} - -static void at91_udelay (rt_uint32_t us) -{ - rt_int32_t i; - for (; us > 0; us--) - { - i = 50000; - while(i > 0) - { - i--; - } - } -} - -static const struct rt_i2c_bit_ops bit_ops = { - RT_NULL, - at91_set_sda, - at91_set_scl, - at91_get_sda, - at91_get_scl, - - at91_udelay, - - 5, - 100 -}; - -int at91_i2c_init(void) -{ - struct rt_i2c_bus_device *bus; - - bus = rt_malloc(sizeof(struct rt_i2c_bus_device)); - if (bus == RT_NULL) - { - rt_kprintf("rt_malloc failed\n"); - return -RT_ENOMEM; - } - - rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device)); - - bus->priv = (void *)&bit_ops; - - at91_i2c_gpio_init(); - - rt_i2c_bit_add_bus(bus, "i2c0"); - - return 0; -} - -INIT_DEVICE_EXPORT(at91_i2c_init); - diff --git a/bsp/at91sam9g45/drivers/at91_mci.c b/bsp/at91sam9g45/drivers/at91_mci.c deleted file mode 100644 index 0ad5590df672f2b066900c604fd140755ac26e82..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/drivers/at91_mci.c +++ /dev/null @@ -1,924 +0,0 @@ -/* - * File : at91_mci.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-07-25 weety first version - */ - -#include -#include -#include -#include -#include "at91_mci.h" - -#define USE_SLOT_B -//#define RT_MCI_DBG - -#ifdef RT_MCI_DBG -#define mci_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__) -#else -#define mci_dbg(fmt, ...) -#endif - -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) - -extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); -extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); - - -#define AT91C_MCI_ERRORS (AT91C_MCI_RINDE | AT91C_MCI_RDIRE | AT91C_MCI_RCRCE \ - | AT91C_MCI_RENDE | AT91C_MCI_RTOE | AT91C_MCI_DCRCE \ - | AT91C_MCI_DTOE | AT91C_MCI_OVRE | AT91C_MCI_UNRE) - -#define at91_mci_read(reg) readl(AT91C_BASE_MCI + (reg)) -#define at91_mci_write(reg, val) writel((val), AT91C_BASE_MCI + (reg)) - - -#define REQ_ST_INIT (1U << 0) -#define REQ_ST_CMD (1U << 1) -#define REQ_ST_STOP (1U << 2) - -struct at91_mci { - struct rt_mmcsd_host *host; - struct rt_mmcsd_req *req; - struct rt_mmcsd_cmd *cmd; - struct rt_timer timer; - //struct rt_semaphore sem_ack; - rt_uint32_t *buf; - rt_uint32_t current_status; -}; - -/* - * Reset the controller and restore most of the state - */ -static void at91_reset_host() -{ - rt_uint32_t mr; - rt_uint32_t sdcr; - rt_uint32_t dtor; - rt_uint32_t imr; - rt_uint32_t level; - - level = rt_hw_interrupt_disable(); - - imr = at91_mci_read(AT91C_MCI_IMR); - - at91_mci_write(AT91C_MCI_IDR, 0xffffffff); - - /* save current state */ - mr = at91_mci_read(AT91C_MCI_MR) & 0x7fff; - sdcr = at91_mci_read(AT91C_MCI_SDCR); - dtor = at91_mci_read(AT91C_MCI_DTOR); - - /* reset the controller */ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST); - - /* restore state */ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); - at91_mci_write(AT91C_MCI_MR, mr); - at91_mci_write(AT91C_MCI_SDCR, sdcr); - at91_mci_write(AT91C_MCI_DTOR, dtor); - at91_mci_write(AT91C_MCI_IER, imr); - - /* make sure sdio interrupts will fire */ - at91_mci_read(AT91C_MCI_SR); - rt_hw_interrupt_enable(level); - -} - - -/* - * Enable the controller - */ -static void at91_mci_enable() -{ - rt_uint32_t mr; - - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); - at91_mci_write(AT91C_MCI_IDR, 0xffffffff); - at91_mci_write(AT91C_MCI_DTOR, AT91C_MCI_DTOMUL_1M | AT91C_MCI_DTOCYC); - mr = AT91C_MCI_PDCMODE | 0x34a; - - mr |= AT91C_MCI_RDPROOF | AT91C_MCI_WRPROOF; - - at91_mci_write(AT91C_MCI_MR, mr); - - /* use Slot A or B (only one at same time) */ - at91_mci_write(AT91C_MCI_SDCR, 1); /* use slot b */ -} - -/* - * Disable the controller - */ -static void at91_mci_disable() -{ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS | AT91C_MCI_SWRST); -} - -static void at91_timeout_timer(void *data) -{ - struct at91_mci *mci; - - mci = (struct at91_mci *)data; - - if (mci->req) - { - rt_kprintf("Timeout waiting end of packet\n"); - - if (mci->current_status == REQ_ST_CMD) - { - if (mci->req->cmd && mci->req->data) - { - mci->req->data->err = -RT_ETIMEOUT; - } - else - { - if (mci->req->cmd) - mci->req->cmd->err = -RT_ETIMEOUT; - } - } - else if (mci->current_status == REQ_ST_STOP) - { - mci->req->stop->err = -RT_ETIMEOUT; - } - - at91_reset_host(); - mmcsd_req_complete(mci->host); - } -} - -/* - * Prepare a dma read - */ -static void at91_mci_init_dma_read(struct at91_mci *mci) -{ - rt_uint8_t i; - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; - rt_uint32_t length; - - mci_dbg("pre dma read\n"); - - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } - - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } - - for (i = 0; i < 1; i++) - { - /* Check to see if this needs filling */ - if (i == 0) - { - if (at91_mci_read(AT91C_PDC_RCR) != 0) - { - mci_dbg("Transfer active in current\n"); - continue; - } - } - else { - if (at91_mci_read(AT91C_PDC_RNCR) != 0) - { - mci_dbg("Transfer active in next\n"); - continue; - } - } - - length = data->blksize * data->blks; - mci_dbg("dma address = %08X, length = %d\n", data->buf, length); - - if (i == 0) - { - at91_mci_write(AT91C_PDC_RPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91C_PDC_RCR, (data->blksize & 0x3) ? length : length / 4); - } - else - { - at91_mci_write(AT91C_PDC_RNPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91C_PDC_RNCR, (data->blksize & 0x3) ? length : length / 4); - } - } - - mci_dbg("pre dma read done\n"); -} - -/* - * Send a command - */ -static void at91_mci_send_command(struct at91_mci *mci, struct rt_mmcsd_cmd *cmd) -{ - rt_uint32_t cmdr, mr; - rt_uint32_t block_length; - struct rt_mmcsd_data *data = cmd->data; - struct rt_mmcsd_host *host = mci->host; - - rt_uint32_t blocks; - rt_uint32_t ier = 0; - rt_uint32_t length; - - mci->cmd = cmd; - - /* Needed for leaving busy state before CMD1 */ - if ((at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_RTOE) && (cmd->cmd_code == 1)) - { - mci_dbg("Clearing timeout\n"); - at91_mci_write(AT91C_MCI_ARGR, 0); - at91_mci_write(AT91C_MCI_CMDR, AT91C_MCI_OPDCMD); - while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY)) - { - /* spin */ - mci_dbg("Clearing: SR = %08X\n", at91_mci_read(AT91C_MCI_SR)); - } - } - - cmdr = cmd->cmd_code; - - if (resp_type(cmd) == RESP_NONE) - cmdr |= AT91C_MCI_RSPTYP_NONE; - else - { - /* if a response is expected then allow maximum response latancy */ - cmdr |= AT91C_MCI_MAXLAT; - /* set 136 bit response for R2, 48 bit response otherwise */ - if (resp_type(cmd) == RESP_R2) - cmdr |= AT91C_MCI_RSPTYP_136; - else - cmdr |= AT91C_MCI_RSPTYP_48; - } - - if (data) - { - - block_length = data->blksize; - blocks = data->blks; - - /* always set data start - also set direction flag for read */ - if (data->flags & DATA_DIR_READ) - cmdr |= (AT91C_MCI_TRDIR | AT91C_MCI_TRCMD_START); - else if (data->flags & DATA_DIR_WRITE) - cmdr |= AT91C_MCI_TRCMD_START; - - if (data->flags & DATA_STREAM) - cmdr |= AT91C_MCI_TRTYP_STREAM; - if (data->blks > 1) - cmdr |= AT91C_MCI_TRTYP_MULTIPLE; - } - else - { - block_length = 0; - blocks = 0; - } - - /*if (cmd->cmd_code == GO_IDLE_STATE) - { - cmdr |= AT91C_MCI_SPCMD_INIT; - }*/ - - if (cmd->cmd_code == STOP_TRANSMISSION) - cmdr |= AT91C_MCI_TRCMD_STOP; - - if (host->io_cfg.bus_mode == MMCSD_BUSMODE_OPENDRAIN) - cmdr |= AT91C_MCI_OPDCMD; - - /* - * Set the arguments and send the command - */ - mci_dbg("Sending command %d as %08X, arg = %08X, blocks = %d, length = %d (MR = %08X)\n", - cmd->cmd_code, cmdr, cmd->arg, blocks, block_length, at91_mci_read(AT91C_MCI_MR)); - - if (!data) - { - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTDIS | AT91C_PDC_RXTDIS); - at91_mci_write(AT91C_PDC_RPR, 0); - at91_mci_write(AT91C_PDC_RCR, 0); - at91_mci_write(AT91C_PDC_RNPR, 0); - at91_mci_write(AT91C_PDC_RNCR, 0); - at91_mci_write(AT91C_PDC_TPR, 0); - at91_mci_write(AT91C_PDC_TCR, 0); - at91_mci_write(AT91C_PDC_TNPR, 0); - at91_mci_write(AT91C_PDC_TNCR, 0); - ier = AT91C_MCI_CMDRDY; - } - else - { - /* zero block length and PDC mode */ - mr = at91_mci_read(AT91C_MCI_MR) & 0x5fff; - mr |= (data->blksize & 0x3) ? AT91C_MCI_PDCFBYTE : 0; - mr |= (block_length << 16); - mr |= AT91C_MCI_PDCMODE; - at91_mci_write(AT91C_MCI_MR, mr); - - at91_mci_write(AT91C_MCI_BLKR, - AT91C_MCI_BLKR_BCNT(blocks) | - AT91C_MCI_BLKR_BLKLEN(block_length)); - - /* - * Disable the PDC controller - */ - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); - - if (cmdr & AT91C_MCI_TRCMD_START) - { - if (cmdr & AT91C_MCI_TRDIR) - { - /* - * Handle a read - */ - - mmu_invalidate_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_init_dma_read(mci); - ier = AT91C_MCI_ENDRX /* | AT91C_MCI_RXBUFF */; - } - else - { - /* - * Handle a write - */ - length = block_length * blocks; - /* - * at91mci MCI1 rev2xx Data Write Operation and - * number of bytes erratum - */ - if (length < 12) - { - length = 12; - mci->buf = rt_malloc(length); - if (!mci->buf) - { - rt_kprintf("rt alloc tx buffer failed\n"); - cmd->err = -RT_ENOMEM; - mmcsd_req_complete(mci->host); - return; - } - rt_memset(mci->buf, 0, 12); - rt_memcpy(mci->buf, data->buf, length); - mmu_clean_dcache((rt_uint32_t)mci->buf, length); - at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(mci->buf)); - at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - else - { - mmu_clean_dcache((rt_uint32_t)data->buf, data->blksize*data->blks); - at91_mci_write(AT91C_PDC_TPR, (rt_uint32_t)(data->buf)); - at91_mci_write(AT91C_PDC_TCR, (data->blksize & 0x3) ? - length : length / 4); - } - mci_dbg("Transmitting %d bytes\n", length); - ier = AT91C_MCI_CMDRDY; - } - } - } - - /* - * Send the command and then enable the PDC - not the other way round as - * the data sheet says - */ - - at91_mci_write(AT91C_MCI_ARGR, cmd->arg); - at91_mci_write(AT91C_MCI_CMDR, cmdr); - - if (cmdr & AT91C_MCI_TRCMD_START) - { - if (cmdr & AT91C_MCI_TRDIR) - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTEN); - } - - /* Enable selected interrupts */ - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_ERRORS | ier); -} - -/* - * Process the next step in the request - */ -static void at91_mci_process_next(struct at91_mci *mci) -{ - if (mci->current_status == REQ_ST_INIT) - { - mci->current_status = REQ_ST_CMD; - at91_mci_send_command(mci, mci->req->cmd); - } - else if ((mci->current_status == REQ_ST_CMD) && mci->req->stop) - { - mci->current_status = REQ_ST_STOP; - at91_mci_send_command(mci, mci->req->stop); - } - else - { - rt_timer_stop(&mci->timer); - /* the mci controller hangs after some transfers, - * and the workaround is to reset it after each transfer. - */ - at91_reset_host(); - mmcsd_req_complete(mci->host); - } -} - -/* - * Handle an MMC request - */ -static void at91_mci_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) -{ - rt_uint32_t timeout = RT_TICK_PER_SECOND; - struct at91_mci *mci = host->private_data; - mci->req = req; - mci->current_status = REQ_ST_INIT; - - rt_timer_control(&mci->timer, RT_TIMER_CTRL_SET_TIME, (void*)&timeout); - rt_timer_start(&mci->timer); - - at91_mci_process_next(mci); -} - -/* - * Handle transmitted data - */ -static void at91_mci_handle_transmitted(struct at91_mci *mci) -{ - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; - - mci_dbg("Handling the transmit\n"); - - /* Disable the transfer */ - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); - - /* Now wait for cmd ready */ - at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_TXBUFE); - - cmd = mci->cmd; - if (!cmd) return; - - data = cmd->data; - if (!data) return; - - if (data->blks > 1) - { - mci_dbg("multiple write : wait for BLKE...\n"); - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_BLKE); - } else - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); -} - - -/* - * Handle after a dma read - */ -static void at91_mci_post_dma_read(struct at91_mci *mci) -{ - struct rt_mmcsd_cmd *cmd; - struct rt_mmcsd_data *data; - - mci_dbg("post dma read\n"); - - cmd = mci->cmd; - if (!cmd) - { - mci_dbg("no command\n"); - return; - } - - data = cmd->data; - if (!data) - { - mci_dbg("no data\n"); - return; - } - - at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_ENDRX); - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_RXBUFF); - - mci_dbg("post dma read done\n"); -} - -/*Handle after command sent ready*/ -static int at91_mci_handle_cmdrdy(struct at91_mci *mci) -{ - if (!mci->cmd) - return 1; - else if (!mci->cmd->data) - { - if (mci->current_status == REQ_ST_STOP) - { - /*After multi block write, we must wait for NOTBUSY*/ - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); - } - else return 1; - } - else if (mci->cmd->data->flags & DATA_DIR_WRITE) - { - /*After sendding multi-block-write command, start DMA transfer*/ - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_TXBUFE | AT91C_MCI_BLKE); - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_TXTEN); - } - - /* command not completed, have to wait */ - return 0; -} - -/* - * Handle a command that has been completed - */ -static void at91_mci_completed_command(struct at91_mci *mci, rt_uint32_t status) -{ - struct rt_mmcsd_cmd *cmd = mci->cmd; - struct rt_mmcsd_data *data = cmd->data; - - at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); - - cmd->resp[0] = at91_mci_read(AT91C_MCI_RSPR(0)); - cmd->resp[1] = at91_mci_read(AT91C_MCI_RSPR(1)); - cmd->resp[2] = at91_mci_read(AT91C_MCI_RSPR(2)); - cmd->resp[3] = at91_mci_read(AT91C_MCI_RSPR(3)); - - if (mci->buf) - { - //rt_memcpy(data->buf, mci->buf, data->blksize*data->blks); - rt_free(mci->buf); - mci->buf = RT_NULL; - } - - mci_dbg("Status = %08X/%08x [%08X %08X %08X %08X]\n", - status, at91_mci_read(AT91C_MCI_SR), - cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]); - - if (status & AT91C_MCI_ERRORS) - { - if ((status & AT91C_MCI_RCRCE) && (resp_type(cmd) & (RESP_R3|RESP_R4))) - { - cmd->err = 0; - } - else - { - if (status & (AT91C_MCI_DTOE | AT91C_MCI_DCRCE)) - { - if (data) - { - if (status & AT91C_MCI_DTOE) - data->err = -RT_ETIMEOUT; - else if (status & AT91C_MCI_DCRCE) - data->err = -RT_ERROR; - } - } - else - { - if (status & AT91C_MCI_RTOE) - cmd->err = -RT_ETIMEOUT; - else if (status & AT91C_MCI_RCRCE) - cmd->err = -RT_ERROR; - else - cmd->err = -RT_ERROR; - } - - rt_kprintf("error detected and set to %d/%d (cmd = %d)\n", - cmd->err, data ? data->err : 0, - cmd->cmd_code); - } - } - else - cmd->err = 0; - - at91_mci_process_next(mci); -} - -/* - * Handle an interrupt - */ -static void at91_mci_irq(int irq, void *param) -{ - struct at91_mci *mci = (struct at91_mci *)param; - rt_int32_t completed = 0; - rt_uint32_t int_status, int_mask; - - int_status = at91_mci_read(AT91C_MCI_SR); - int_mask = at91_mci_read(AT91C_MCI_IMR); - - mci_dbg("MCI irq: status = %08X, %08X, %08X\n", int_status, int_mask, - int_status & int_mask); - - int_status = int_status & int_mask; - - if (int_status & AT91C_MCI_ERRORS) - { - completed = 1; - - if (int_status & AT91C_MCI_UNRE) - mci_dbg("MMC: Underrun error\n"); - if (int_status & AT91C_MCI_OVRE) - mci_dbg("MMC: Overrun error\n"); - if (int_status & AT91C_MCI_DTOE) - mci_dbg("MMC: Data timeout\n"); - if (int_status & AT91C_MCI_DCRCE) - mci_dbg("MMC: CRC error in data\n"); - if (int_status & AT91C_MCI_RTOE) - mci_dbg("MMC: Response timeout\n"); - if (int_status & AT91C_MCI_RENDE) - mci_dbg("MMC: Response end bit error\n"); - if (int_status & AT91C_MCI_RCRCE) - mci_dbg("MMC: Response CRC error\n"); - if (int_status & AT91C_MCI_RDIRE) - mci_dbg("MMC: Response direction error\n"); - if (int_status & AT91C_MCI_RINDE) - mci_dbg("MMC: Response index error\n"); - } - else - { - /* Only continue processing if no errors */ - - if (int_status & AT91C_MCI_TXBUFE) - { - mci_dbg("TX buffer empty\n"); - at91_mci_handle_transmitted(mci); - } - - if (int_status & AT91C_MCI_ENDRX) - { - mci_dbg("ENDRX\n"); - at91_mci_post_dma_read(mci); - } - - if (int_status & AT91C_MCI_RXBUFF) - { - mci_dbg("RX buffer full\n"); - at91_mci_write(AT91C_PDC_PTCR, AT91C_PDC_RXTDIS | AT91C_PDC_TXTDIS); - at91_mci_write(AT91C_MCI_IDR, AT91C_MCI_RXBUFF | AT91C_MCI_ENDRX); - completed = 1; - } - - if (int_status & AT91C_MCI_ENDTX) - mci_dbg("Transmit has ended\n"); - - if (int_status & AT91C_MCI_NOTBUSY) - { - mci_dbg("Card is ready\n"); - //at91_mci_update_bytes_xfered(host); - completed = 1; - } - - if (int_status & AT91C_MCI_DTIP) - mci_dbg("Data transfer in progress\n"); - - if (int_status & AT91C_MCI_BLKE) - { - mci_dbg("Block transfer has ended\n"); - if (mci->req->data && mci->req->data->blks > 1) - { - /* multi block write : complete multi write - * command and send stop */ - completed = 1; - } - else - { - at91_mci_write(AT91C_MCI_IER, AT91C_MCI_NOTBUSY); - } - } - - /*if (int_status & AT91C_MCI_SDIOIRQA) - rt_mmcsd_signal_sdio_irq(host->mmc);*/ - - if (int_status & AT91C_MCI_SDIOIRQB) - sdio_irq_wakeup(mci->host); - - if (int_status & AT91C_MCI_TXRDY) - mci_dbg("Ready to transmit\n"); - - if (int_status & AT91C_MCI_RXRDY) - mci_dbg("Ready to receive\n"); - - if (int_status & AT91C_MCI_CMDRDY) - { - mci_dbg("Command ready\n"); - completed = at91_mci_handle_cmdrdy(mci); - } - } - - if (completed) - { - mci_dbg("Completed command\n"); - at91_mci_write(AT91C_MCI_IDR, 0xffffffff & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); - at91_mci_completed_command(mci, int_status); - } - else - at91_mci_write(AT91C_MCI_IDR, int_status & ~(AT91C_MCI_SDIOIRQA | AT91C_MCI_SDIOIRQB)); - -} - - -/* - * Set the IOCFG - */ -static void at91_mci_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) -{ - rt_uint32_t clkdiv; - //struct at91_mci *mci = host->private_data; - rt_uint32_t at91_master_clock = clk_get_rate(clk_get("mck")); - - if (io_cfg->clock == 0) - { - /* Disable the MCI controller */ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIDIS); - clkdiv = 0; - } - else - { - /* Enable the MCI controller */ - at91_mci_write(AT91C_MCI_CR, AT91C_MCI_MCIEN); - - if ((at91_master_clock % (io_cfg->clock * 2)) == 0) - clkdiv = ((at91_master_clock / io_cfg->clock) / 2) - 1; - else - clkdiv = (at91_master_clock / io_cfg->clock) / 2; - - mci_dbg("clkdiv = %d. mcck = %ld\n", clkdiv, - at91_master_clock / (2 * (clkdiv + 1))); - } - if (io_cfg->bus_width == MMCSD_BUS_WIDTH_4) - { - mci_dbg("MMC: Setting controller bus width to 4\n"); - at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) | AT91C_MCI_SDCBUS); - } - else - { - mci_dbg("MMC: Setting controller bus width to 1\n"); - at91_mci_write(AT91C_MCI_SDCR, at91_mci_read(AT91C_MCI_SDCR) & ~AT91C_MCI_SDCBUS); - } - - /* Set the clock divider */ - at91_mci_write(AT91C_MCI_MR, (at91_mci_read(AT91C_MCI_MR) & ~AT91C_MCI_CLKDIV) | clkdiv); - - /* maybe switch power to the card */ - switch (io_cfg->power_mode) - { - case MMCSD_POWER_OFF: - break; - case MMCSD_POWER_UP: - break; - case MMCSD_POWER_ON: - /*at91_mci_write(AT91C_MCI_ARGR, 0); - at91_mci_write(AT91C_MCI_CMDR, 0|AT91C_MCI_SPCMD_INIT|AT91C_MCI_OPDCMD); - mci_dbg("MCI_SR=0x%08x\n", at91_mci_read(AT91C_MCI_SR)); - while (!(at91_mci_read(AT91C_MCI_SR) & AT91C_MCI_CMDRDY)) - { - - } - mci_dbg("at91 mci power on\n");*/ - break; - default: - rt_kprintf("unknown power_mode %d\n", io_cfg->power_mode); - break; - } - -} - - -static void at91_mci_enable_sdio_irq(struct rt_mmcsd_host *host, rt_int32_t enable) -{ - at91_mci_write(enable ? AT91C_MCI_IER : AT91C_MCI_IDR, AT91C_MCI_SDIOIRQB); -} - - -static const struct rt_mmcsd_host_ops ops = { - at91_mci_request, - at91_mci_set_iocfg, - RT_NULL, - at91_mci_enable_sdio_irq, -}; - -void at91_mci_detect(int irq, void *param) -{ - rt_kprintf("mmcsd gpio detected\n"); -} - -static void mci_gpio_init() -{ -#ifdef USE_SLOT_B - AT91C_BASE_PIOA->PIO_PUER = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5); - AT91C_BASE_PIOA->PIO_PUDR = (1 << 8); - AT91C_BASE_PIOA->PIO_BSR = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5); - AT91C_BASE_PIOA->PIO_ASR = (1 << 8); - AT91C_BASE_PIOA->PIO_PDR = (1 << 0)|(1 << 1)|(1 << 3)|(1 << 4)|(1 << 5)|(1 << 8); - - AT91C_BASE_PIOA->PIO_IDR = (1 << 6)|(1 << 7); - AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7); - AT91C_BASE_PIOA->PIO_ODR = (1 << 6)|(1 << 7); - AT91C_BASE_PIOA->PIO_PER = (1 << 6)|(1 << 7); -#else - AT91C_BASE_PIOA->PIO_PUER = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11); - AT91C_BASE_PIOA->PIO_ASR = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8); - AT91C_BASE_PIOA->PIO_PDR = (1 << 6)|(1 << 7)|(1 << 9)|(1 << 10)|(1 << 11)|(1 << 8); -#endif -} - -int at91_mci_init(void) -{ - struct rt_mmcsd_host *host; - struct at91_mci *mci; - - host = mmcsd_alloc_host(); - if (!host) - { - return -RT_ERROR; - } - - mci = rt_malloc(sizeof(struct at91_mci)); - if (!mci) - { - rt_kprintf("alloc mci failed\n"); - goto err; - } - - rt_memset(mci, 0, sizeof(struct at91_mci)); - - host->ops = &ops; - host->freq_min = 375000; - host->freq_max = 25000000; - host->valid_ocr = VDD_32_33 | VDD_33_34; - host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | \ - MMCSD_SUP_HIGHSPEED | MMCSD_SUP_SDIO_IRQ; - host->max_seg_size = 65535; - host->max_dma_segs = 2; - host->max_blk_size = 512; - host->max_blk_count = 4096; - - mci->host = host; - - mci_gpio_init(); - AT91C_BASE_PMC->AT91C_PMC_PCER = 1 << AT91C_ID_MCI; //enable MCI clock - - at91_mci_disable(); - at91_mci_enable(); - - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_MCI, at91_mci_irq, - (void *)mci, "MMC"); - rt_hw_interrupt_umask(AT91SAM9260_ID_MCI); - rt_hw_interrupt_install(gpio_to_irq(AT91C_PIN_PA7), - at91_mci_detect, RT_NULL, "MMC_DETECT"); - rt_hw_interrupt_umask(gpio_to_irq(AT91C_PIN_PA7)); - - rt_timer_init(&mci->timer, "mci_timer", - at91_timeout_timer, - mci, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); - - //rt_timer_start(&mci->timer); - - //rt_sem_init(&mci->sem_ack, "sd_ack", 0, RT_IPC_FLAG_FIFO); - - host->private_data = mci; - - mmcsd_change(host); - - return 0; - -err: - mmcsd_free_host(host); - - return -RT_ENOMEM; -} - -INIT_DEVICE_EXPORT(at91_mci_init); - -#include "finsh.h" -FINSH_FUNCTION_EXPORT(at91_mci_init, at91sam9260 sd init); - -void mci_dump(void) -{ - rt_uint32_t i; - - rt_kprintf("PIOA_PSR=0x%08x\n", readl(AT91C_PIOA+PIO_PSR)); - rt_kprintf("PIOA_ABSR=0x%08x\n", readl(AT91C_PIOA+PIO_ABSR)); - rt_kprintf("PIOA_PUSR=0x%08x\n", readl(AT91C_PIOA+PIO_PUSR)); - - for (i = 0; i <= 0x4c; i += 4) { - rt_kprintf("0x%08x:0x%08x\n", AT91SAM9260_BASE_MCI+i, at91_mci_read(i)); - } -} - -FINSH_FUNCTION_EXPORT(mci_dump, dump register for mci); diff --git a/bsp/at91sam9g45/drivers/at91_mci.h b/bsp/at91sam9g45/drivers/at91_mci.h deleted file mode 100644 index b3bfd289b1ee2313b1dacbeed324d85b664807ff..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/drivers/at91_mci.h +++ /dev/null @@ -1,124 +0,0 @@ -/* - * File : at91_mci.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-06-09 weety first version - */ - -#ifndef __AT91C_MCI_H__ -#define __AT91C_MCI_H__ - -#define AT91C_MCI_CR 0x00 /* Control Register */ -#define AT91C_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */ -#define AT91C_MCI_MCIDIS (1 << 1) /* Multi-Media Interface Disable */ -#define AT91C_MCI_PWSEN (1 << 2) /* Power Save Mode Enable */ -#define AT91C_MCI_PWSDIS (1 << 3) /* Power Save Mode Disable */ -#define AT91C_MCI_SWRST (1 << 7) /* Software Reset */ - -#define AT91C_MCI_MR 0x04 /* Mode Register */ -#define AT91C_MCI_CLKDIV (0xff << 0) /* Clock Divider */ -#define AT91C_MCI_PWSDIV (7 << 8) /* Power Saving Divider */ -#define AT91C_MCI_RDPROOF (1 << 11) /* Read Proof Enable [SAM926[03] only] */ -#define AT91C_MCI_WRPROOF (1 << 12) /* Write Proof Enable [SAM926[03] only] */ -#define AT91C_MCI_PDCFBYTE (1 << 13) /* PDC Force Byte Transfer [SAM926[03] only] */ -#define AT91C_MCI_PDCPADV (1 << 14) /* PDC Padding Value */ -#define AT91C_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */ -#define AT91C_MCI_BLKLEN (0xfff << 18) /* Data Block Length */ - -#define AT91C_MCI_DTOR 0x08 /* Data Timeout Register */ -#define AT91C_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */ -#define AT91C_MCI_DTOMUL (7 << 4) /* Data Timeout Multiplier */ -#define AT91C_MCI_DTOMUL_1 (0 << 4) -#define AT91C_MCI_DTOMUL_16 (1 << 4) -#define AT91C_MCI_DTOMUL_128 (2 << 4) -#define AT91C_MCI_DTOMUL_256 (3 << 4) -#define AT91C_MCI_DTOMUL_1K (4 << 4) -#define AT91C_MCI_DTOMUL_4K (5 << 4) -#define AT91C_MCI_DTOMUL_64K (6 << 4) -#define AT91C_MCI_DTOMUL_1M (7 << 4) - -#define AT91C_MCI_SDCR 0x0c /* SD Card Register */ -#define AT91C_MCI_SDCSEL (3 << 0) /* SD Card Selector */ -#define AT91C_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */ - -#define AT91C_MCI_ARGR 0x10 /* Argument Register */ - -#define AT91C_MCI_CMDR 0x14 /* Command Register */ -#define AT91C_MCI_CMDNB (0x3f << 0) /* Command Number */ -#define AT91C_MCI_RSPTYP (3 << 6) /* Response Type */ -#define AT91C_MCI_RSPTYP_NONE (0 << 6) -#define AT91C_MCI_RSPTYP_48 (1 << 6) -#define AT91C_MCI_RSPTYP_136 (2 << 6) -#define AT91C_MCI_SPCMD (7 << 8) /* Special Command */ -#define AT91C_MCI_SPCMD_NONE (0 << 8) -#define AT91C_MCI_SPCMD_INIT (1 << 8) -#define AT91C_MCI_SPCMD_SYNC (2 << 8) -#define AT91C_MCI_SPCMD_ICMD (4 << 8) -#define AT91C_MCI_SPCMD_IRESP (5 << 8) -#define AT91C_MCI_OPDCMD (1 << 11) /* Open Drain Command */ -#define AT91C_MCI_MAXLAT (1 << 12) /* Max Latency for Command to Response */ -#define AT91C_MCI_TRCMD (3 << 16) /* Transfer Command */ -#define AT91C_MCI_TRCMD_NONE (0 << 16) -#define AT91C_MCI_TRCMD_START (1 << 16) -#define AT91C_MCI_TRCMD_STOP (2 << 16) -#define AT91C_MCI_TRDIR (1 << 18) /* Transfer Direction */ -#define AT91C_MCI_TRTYP (3 << 19) /* Transfer Type */ -#define AT91C_MCI_TRTYP_BLOCK (0 << 19) -#define AT91C_MCI_TRTYP_MULTIPLE (1 << 19) -#define AT91C_MCI_TRTYP_STREAM (2 << 19) - -#define AT91C_MCI_BLKR 0x18 /* Block Register */ -#define AT91C_MCI_BLKR_BCNT(n) ((0xffff & (n)) << 0) /* Block count */ -#define AT91C_MCI_BLKR_BLKLEN(n) ((0xffff & (n)) << 16) /* Block lenght */ - -#define AT91C_MCI_RSPR(n) (0x20 + ((n) * 4)) /* Response Registers 0-3 */ -#define AT91C_MCR_RDR 0x30 /* Receive Data Register */ -#define AT91C_MCR_TDR 0x34 /* Transmit Data Register */ - -#define AT91C_MCI_SR 0x40 /* Status Register */ -#define AT91C_MCI_CMDRDY (1U << 0) /* Command Ready */ -#define AT91C_MCI_RXRDY (1U << 1) /* Receiver Ready */ -#define AT91C_MCI_TXRDY (1U << 2) /* Transmit Ready */ -#define AT91C_MCI_BLKE (1U << 3) /* Data Block Ended */ -#define AT91C_MCI_DTIP (1U << 4) /* Data Transfer in Progress */ -#define AT91C_MCI_NOTBUSY (1U << 5) /* Data Not Busy */ -#define AT91C_MCI_ENDRX (1U << 6) /* End of RX Buffer */ -#define AT91C_MCI_ENDTX (1U << 7) /* End fo TX Buffer */ -#define AT91C_MCI_SDIOIRQA (1U << 8) /* SDIO Interrupt for Slot A */ -#define AT91C_MCI_SDIOIRQB (1U << 9) /* SDIO Interrupt for Slot B */ -#define AT91C_MCI_RXBUFF (1U << 14) /* RX Buffer Full */ -#define AT91C_MCI_TXBUFE (1U << 15) /* TX Buffer Empty */ -#define AT91C_MCI_RINDE (1U << 16) /* Response Index Error */ -#define AT91C_MCI_RDIRE (1U << 17) /* Response Direction Error */ -#define AT91C_MCI_RCRCE (1U << 18) /* Response CRC Error */ -#define AT91C_MCI_RENDE (1U << 19) /* Response End Bit Error */ -#define AT91C_MCI_RTOE (1U << 20) /* Reponse Time-out Error */ -#define AT91C_MCI_DCRCE (1U << 21) /* Data CRC Error */ -#define AT91C_MCI_DTOE (1U << 22) /* Data Time-out Error */ -#define AT91C_MCI_OVRE (1U << 30) /* Overrun */ -#define AT91C_MCI_UNRE (1U << 31) /* Underrun */ - -#define AT91C_MCI_IER 0x44 /* Interrupt Enable Register */ -#define AT91C_MCI_IDR 0x48 /* Interrupt Disable Register */ -#define AT91C_MCI_IMR 0x4c /* Interrupt Mask Register */ - -extern int at91_mci_init(void); - -#endif diff --git a/bsp/at91sam9g45/drivers/board.c b/bsp/at91sam9g45/drivers/board.c deleted file mode 100644 index c14055f3103fc736a44d847b937998cb5c3018e3..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/drivers/board.c +++ /dev/null @@ -1,248 +0,0 @@ -/* - * File : board.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2009 RT-Thread Develop Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - */ - -#include -#include - -#include "board.h" -#include - -/** - * @addtogroup at91sam9g45 - */ -/*@{*/ -#if defined(__CC_ARM) -extern int Image$$ER_ZI$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$ER_ZI$$ZI$$Limit) -#elif (defined (__GNUC__)) -extern unsigned char __bss_end__; -#define HEAP_BEGIN (&__bss_end__) -#elif (defined (__ICCARM__)) -#pragma section=".noinit" -#define HEAP_BEGIN (__section_end(".noinit")) -#endif - -#define HEAP_END (((rt_uint32_t)HEAP_BEGIN & 0xF0000000) + 0x04000000) - -extern void rt_hw_interrupt_init(void); -extern void rt_hw_clock_init(void); - -extern void rt_hw_get_clock(void); -extern void rt_hw_set_dividor(rt_uint8_t hdivn, rt_uint8_t pdivn); -extern void rt_hw_set_clock(rt_uint8_t sdiv, rt_uint8_t pdiv, rt_uint8_t mdiv); -extern void rt_dbgu_isr(void); - -#define SAM9G45_BLOCK_SIZE 0x10000000 // 256M -#define MMU_SECTION_SIZE 0x100000 // 1M -#define PERIPHERALS_ADDR // 1M - -#define SECTION_END(sa) ((sa) + MMU_SECTION_SIZE - 1) // sa: start address -#define BLOCK_END(ba) ((ba) + SAM9G45_BLOCK_SIZE - 1) // ba: block address - -static struct mem_desc at91_mem_desc[] = { /* FIXME, hornby, to confirm MMU and memory */ - { 0x00000000, 0xFFFFFFFF , 0x00000000, RW_NCNB }, /* None cached for 4G memory */ - //{ 0x00000000, SECTION_END(0x00000000), 0x00000000, RW_CNB }, /* TLB for ITCM, ITCM map to address zero, 32KB */ - //{ 0x00200000, SECTION_END(0x00200000), 0x00200000, RW_CNB }, /* TLB for DTCM, 32KB */ - //{ 0x00300000, SECTION_END(0x00300000), 0x00300000, RW_CNB }, /* TLB for internal RAM, 64KB, we use it as global variable area */ - //{ 0x00600000, SECTION_END(0x00600000), 0x00600000, RW_NCNB }, /* TLB for UDPHS(DMA) */ - //{ 0x00700000, SECTION_END(0x00700000), 0x00700000, RW_NCNB }, /* TLB for UHP OHCI */ - //{ 0x00800000, SECTION_END(0x00800000), 0x00800000, RW_NCNB }, /* TLB for UHP EHCI */ - //{ 0x30000000, 0x30000000+0x00100000-1, 0x30000000, RW_CB }, /* 1M external SRAM for program code and stack */ - //{ 0x40000000, BLOCK_END(0x40000000), 0x40000000, RW_NCNB }, /* 256M for nand-flash controller */ - //{ 0x60000000, BLOCK_END(0x60000000), 0x60000000, RW_NCNB }, /* 256M for FPGA */ - //{ 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_NCNB }, /* 128M for main DDR-SDRAM for print data */ - { 0x00000000, SECTION_END(0x00000000), 0x70000000, RW_CB }, /* isr */ - { 0x70000000, 0x70000000+0x08000000-1, 0x70000000, RW_CB }, /* 128M for main DDR-SDRAM for print data */ - //{ 0xFFF00000, SECTION_END(0xFFF00000), 0xFFF00000, RW_NCNB }, /* Internal Peripherals, 1MB */ -}; - - -#define PIT_CPIV(x) ((x) & AT91C_PITC_CPIV) -#define PIT_PICNT(x) (((x) & AT91C_PITC_PICNT) >> 20) - -static rt_uint32_t pit_cycle; /* write-once */ -static rt_uint32_t pit_cnt; /* access only w/system irq blocked */ - -/** - * This function will handle rtos timer - */ -void rt_timer_handler(int vector, void *param) -{ -#ifdef RT_USING_DBGU - if (readl(AT91C_DBGU_CSR) & AT91C_US_RXRDY) - { - rt_dbgu_isr(); - } -#endif - if (readl(AT91C_PITC_PISR) & AT91C_PITC_PITS) - { - unsigned nr_ticks; - - /* Get number of ticks performed before irq, and ack it */ - nr_ticks = PIT_PICNT(readl(AT91C_PITC_PIVR)); - while (nr_ticks--) - rt_tick_increase(); - } -} - -static void at91sam9g45_pit_reset(void) -{ - /* Disable timer and irqs */ - AT91C_BASE_PITC->PITC_PIMR = 0; - - /* Clear any pending interrupts, wait for PIT to stop counting */ - while (PIT_CPIV(readl(AT91C_PITC_PIVR)) != 0) - ; - - /* Start PIT but don't enable IRQ */ - //AT91C_BASE_PITC->PITC_PIMR = (pit_cycle - 1) | AT91C_PITC_PITEN; - pit_cnt += pit_cycle * PIT_PICNT(readl(AT91C_PITC_PIVR)); - AT91C_BASE_PITC->PITC_PIMR = - (pit_cycle - 1) | AT91C_PITC_PITEN | AT91C_PITC_PITIEN; - rt_kprintf("PIT_MR=0x%08x\n", readl(AT91C_PITC_PIMR)); -} - -/* - * Set up both clocksource and clockevent support. - */ -static void at91sam9g45_pit_init(void) -{ - rt_uint32_t pit_rate; - //rt_uint32_t bits; - - /* - * Use our actual MCK to figure out how many MCK/16 ticks per - * 1/HZ period (instead of a compile-time constant LATCH). - */ - pit_rate = clk_get_rate(clk_get("mck")) / 16; - rt_kprintf("pit_rate=%dHZ\n", pit_rate); - pit_cycle = (pit_rate + RT_TICK_PER_SECOND/2) / RT_TICK_PER_SECOND; - - /* Initialize and enable the timer */ - at91sam9g45_pit_reset(); -} - -/** - * This function will init pit for system ticks - */ -void rt_hw_timer_init() -{ - at91sam9g45_pit_init(); - - /* install interrupt handler */ - rt_hw_interrupt_install(AT91C_ID_SYS, rt_timer_handler, - RT_NULL, "system"); - rt_hw_interrupt_umask(AT91C_ID_SYS); -} - -void at91_tc1_init() -{ - AT91C_BASE_PMC->PMC_PCER = 1<DBGU_CSR & AT91C_US_TXRDY)) - ; - AT91C_BASE_DBGU->DBGU_THR = c; -} - -/** - * This function is used to display a string on console, normally, it's - * invoked by rt_kprintf - * - * @param str the displayed string - */ -void rt_hw_console_output(const char* str) -{ - while (*str) - { - if (*str=='\n') - { - at91_usart_putc('\r'); - } - - at91_usart_putc(*str++); - } -} - -static void rt_hw_console_init(void) -{ - int div; - int mode = 0; - - AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RSTTX | AT91C_US_RSTRX | - AT91C_US_RXDIS | AT91C_US_TXDIS; - mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | - AT91C_US_CHMODE_NORMAL; - mode |= AT91C_US_CHRL_8_BITS; - mode |= AT91C_US_NBSTOP_1_BIT; - mode |= AT91C_US_PAR_NONE; - AT91C_BASE_DBGU->DBGU_MR = mode; - div = (clk_get_rate(clk_get("mck")) / 16 + BPS/2) / BPS; - AT91C_BASE_DBGU->DBGU_BRGR = div; - AT91C_BASE_DBGU->DBGU_CR = AT91C_US_RXEN | AT91C_US_TXEN; -} - - -/** - * This function will init at91sam9g45 board - */ -void rt_hw_board_init() -{ - /* initialize the system clock */ - rt_hw_clock_init(); - - /* initialize console */ - rt_hw_console_init(); - - /* initialize mmu */ - rt_hw_mmu_init(at91_mem_desc, sizeof(at91_mem_desc)/sizeof(at91_mem_desc[0])); - - /* initialize hardware interrupt */ - rt_hw_interrupt_init(); - - /* initialize early device */ -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif -#ifdef RT_USING_CONSOLE - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - /* initialize timer0 */ - rt_hw_timer_init(); - -/* initialize board */ -#ifdef RT_USING_HEAP - rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); -#endif -} - -/*@}*/ diff --git a/bsp/at91sam9g45/drivers/board.h b/bsp/at91sam9g45/drivers/board.h deleted file mode 100644 index a6ec4e0ef7d377f388870811b6044f3d21368d3e..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/drivers/board.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * File : board.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety add board.h to this bsp - */ - -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include - -void rt_hw_board_init(void); - -#endif diff --git a/bsp/at91sam9g45/drivers/led.c b/bsp/at91sam9g45/drivers/led.c deleted file mode 100644 index fb8b417033a5b63e7ed96e39dbb622f5d0ffed1f..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/drivers/led.c +++ /dev/null @@ -1,54 +0,0 @@ -/* - * File : led.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - */ - -#include -#include -#include "led.h" - -// BYHX A-Plus Board -#define LED0 (1UL << 30) -#define LED1 (1UL << 31) -#define LED2 (1UL << 29) -#define LED3 (1UL << 28) -#define LED_ALL (LED0 | LED1 | LED2 | LED3) - -void led_init(void) -{ - AT91C_BASE_PIOC->PIO_PER = LED_ALL; - AT91C_BASE_PIOC->PIO_OER = LED_ALL; - AT91C_BASE_PIOC->PIO_PPUER = LED_ALL; - AT91C_BASE_PIOC->PIO_SODR = LED_ALL; -} - -const static rt_uint32_t m_leds[] = { LED0, LED1, LED2, LED3 }; - -void led_on(int num) -{ - if (num < 4) AT91C_BASE_PIOC->PIO_CODR = m_leds[num]; -} - -void led_off(int num) -{ - if (num < 4) AT91C_BASE_PIOC->PIO_SODR = m_leds[num]; -} diff --git a/bsp/at91sam9g45/drivers/led.h b/bsp/at91sam9g45/drivers/led.h deleted file mode 100644 index f2967bc92d333f5a2c23af7dfc793c2993b5ad74..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/drivers/led.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * File : led.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - */ - -#ifndef __LED_H__ -#define __LED_H__ - -void led_init(void); -void led_on(int num); -void led_off(int num); - -#endif diff --git a/bsp/at91sam9g45/drivers/macb.c b/bsp/at91sam9g45/drivers/macb.c deleted file mode 100644 index b5cffaa1d2476db93aa58da8b5e5d5ff0c32d813..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/drivers/macb.c +++ /dev/null @@ -1,911 +0,0 @@ -/* - * File : macb.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-03-18 weety first version - */ - -#include -#include -#include "lwipopts.h" -#include -#include "macb.h" - -#define MMU_NOCACHE_ADDR(a) ((rt_uint32_t)a | (1UL<<31)) - -extern void mmu_clean_dcache(rt_uint32_t buffer, rt_uint32_t size); -extern void mmu_invalidate_dcache(rt_uint32_t buffer, rt_uint32_t size); - -/* Cache macros - Packet buffers would be from pbuf pool which is cached */ -#define EMAC_VIRT_NOCACHE(addr) (addr) -#define EMAC_CACHE_INVALIDATE(addr, size) \ - mmu_invalidate_dcache((rt_uint32_t)addr, size) -#define EMAC_CACHE_WRITEBACK(addr, size) \ - mmu_clean_dcache((rt_uint32_t)addr, size) -#define EMAC_CACHE_WRITEBACK_INVALIDATE(addr, size) \ - mmu_clean_invalidated_dcache((rt_uint32_t)addr, size) - -/* EMAC has BD's in cached memory - so need cache functions */ -#define BD_CACHE_INVALIDATE(addr, size) -#define BD_CACHE_WRITEBACK(addr, size) -#define BD_CACHE_WRITEBACK_INVALIDATE(addr, size) - -/* EMAC internal utility function */ -rt_inline unsigned long emac_virt_to_phys(unsigned long addr) -{ - return addr; -} - - -#define AT91SAM9260_SRAM0_VIRT_BASE (0x90000000) - -#define MACB_TX_SRAM - -#if defined(MACB_TX_SRAM) -#define MACB_TX_RING_SIZE 2 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) -#define TX_RING_BYTES (sizeof(struct macb_dma_desc) * MACB_TX_RING_SIZE) -#else -#define MACB_TX_RING_SIZE 16 -#define MACB_TX_BUFFER_SIZE (1536 * MACB_TX_RING_SIZE) -#endif - -#define MACB_RX_BUFFER_SIZE (4096*4) -#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128) - -#define DEF_TX_RING_PENDING (MACB_TX_RING_SIZE) - -#define TX_RING_GAP(macb) \ - (MACB_TX_RING_SIZE - (macb)->tx_pending) - -#define TX_BUFFS_AVAIL(macb) \ - (((macb)->tx_tail <= (macb)->tx_head) ? \ - (macb)->tx_tail + (macb)->tx_pending - (macb)->tx_head : \ - (macb)->tx_tail - (macb)->tx_head - TX_RING_GAP(macb)) - -#define NEXT_TX(n) (((n) + 1) & (MACB_TX_RING_SIZE - 1)) - -#define NEXT_RX(n) (((n) + 1) & (MACB_RX_RING_SIZE - 1)) - -/* minimum number of free TX descriptors before waking up TX process */ -#define MACB_TX_WAKEUP_THRESH (MACB_TX_RING_SIZE / 4) - -#define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \ - | MACB_BIT(ISR_ROVR)) - -#define MACB_TX_TIMEOUT 1000 -#define MACB_AUTONEG_TIMEOUT 5000000 -#define MACB_LINK_TIMEOUT 500000 - -#define CONFIG_RMII - -struct macb_dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; -}; - -#define RXADDR_USED 0x00000001 -#define RXADDR_WRAP 0x00000002 - -#define RXBUF_FRMLEN_MASK 0x00000fff -#define RXBUF_FRAME_START 0x00004000 -#define RXBUF_FRAME_END 0x00008000 -#define RXBUF_TYPEID_MATCH 0x00400000 -#define RXBUF_ADDR4_MATCH 0x00800000 -#define RXBUF_ADDR3_MATCH 0x01000000 -#define RXBUF_ADDR2_MATCH 0x02000000 -#define RXBUF_ADDR1_MATCH 0x04000000 -#define RXBUF_BROADCAST 0x80000000 - -#define TXBUF_FRMLEN_MASK 0x000007ff -#define TXBUF_FRAME_END 0x00008000 -#define TXBUF_NOCRC 0x00010000 -#define TXBUF_EXHAUSTED 0x08000000 -#define TXBUF_UNDERRUN 0x10000000 -#define TXBUF_MAXRETRY 0x20000000 -#define TXBUF_WRAP 0x40000000 -#define TXBUF_USED 0x80000000 - -/* Duplex, half or full. */ -#define DUPLEX_HALF 0x00 -#define DUPLEX_FULL 0x01 - -#define MAX_ADDR_LEN 6 -struct rt_macb_eth -{ - /* inherit from ethernet device */ - struct eth_device parent; - - unsigned int regs; - - unsigned int rx_tail; - unsigned int tx_head; - unsigned int tx_tail; - unsigned int rx_pending; - unsigned int tx_pending; - - void *rx_buffer; - void *tx_buffer; - struct macb_dma_desc *rx_ring; - struct macb_dma_desc *tx_ring; - - unsigned long rx_buffer_dma; - unsigned long tx_buffer_dma; - unsigned long rx_ring_dma; - unsigned long tx_ring_dma; - - unsigned int tx_stop; - - /* interface address info. */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* hw address */ - unsigned short phy_addr; - - struct rt_semaphore mdio_bus_lock; - struct rt_semaphore tx_lock; - struct rt_semaphore rx_lock; - struct rt_semaphore tx_ack; - rt_uint32_t speed; - rt_uint32_t duplex; - rt_uint32_t link; - struct rt_timer timer; -}; -static struct rt_macb_eth macb_device; - -static void macb_tx(struct rt_macb_eth *macb); - -static void udelay(rt_uint32_t us) -{ - rt_uint32_t len; - for (;us > 0; us --) - for (len = 0; len < 10; len++ ); -} - -static void rt_macb_isr(int irq, void *param) -{ - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &(macb->parent.parent); - rt_uint32_t status, rsr, tsr; - - status = macb_readl(macb, ISR); - - while (status) { - - if (status & MACB_RX_INT_FLAGS) - { - rsr = macb_readl(macb, RSR); - macb_writel(macb, RSR, rsr); - /* a frame has been received */ - eth_device_ready(&(macb_device.parent)); - - } - - if (status & (MACB_BIT(TCOMP) | MACB_BIT(ISR_TUND) | - MACB_BIT(ISR_RLE))) - { - macb_tx(macb); - } - - /* - * Link change detection isn't possible with RMII, so we'll - * add that if/when we get our hands on a full-blown MII PHY. - */ - - if (status & MACB_BIT(HRESP)) - { - /* - * TODO: Reset the hardware, and maybe move the printk - * to a lower-priority context as well (work queue?) - */ - rt_kprintf("%s: DMA bus error: HRESP not OK\n", - dev->parent.name); - } - - status = macb_readl(macb, ISR); - } - - -} - -static int macb_mdio_write(struct rt_macb_eth *macb, rt_uint8_t reg, rt_uint16_t value) -{ - unsigned long netctl; - unsigned long netstat; - unsigned long frame; - - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 1) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2) - | MACB_BF(DATA, value)); - macb_writel(macb, MAN, frame); - - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); - - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); -} - -static int macb_mdio_read(struct rt_macb_eth *macb, rt_uint8_t reg) -{ - unsigned long netctl; - unsigned long netstat; - unsigned long frame; - - rt_sem_take(&macb->mdio_bus_lock, RT_WAITING_FOREVER); - netctl = macb_readl(macb, NCR); - netctl |= MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - - frame = (MACB_BF(SOF, 1) - | MACB_BF(RW, 2) - | MACB_BF(PHYA, macb->phy_addr) - | MACB_BF(REGA, reg) - | MACB_BF(CODE, 2)); - macb_writel(macb, MAN, frame); - - do { - netstat = macb_readl(macb, NSR); - } while (!(netstat & MACB_BIT(IDLE))); - - frame = macb_readl(macb, MAN); - - netctl = macb_readl(macb, NCR); - netctl &= ~MACB_BIT(MPE); - macb_writel(macb, NCR, netctl); - rt_sem_release(&macb->mdio_bus_lock); - - return MACB_BFEXT(DATA, frame); -} - -static void macb_phy_reset(rt_device_t dev) -{ - int i; - rt_uint16_t status, adv; - struct rt_macb_eth *macb = dev->user_data;; - - adv = ADVERTISE_CSMA | ADVERTISE_ALL; - macb_mdio_write(macb, MII_ADVERTISE, adv); - rt_kprintf("%s: Starting autonegotiation...\n", dev->parent.name); - macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE - | BMCR_ANRESTART)); - - for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_ANEGCOMPLETE) - break; - udelay(100); - } - - if (status & BMSR_ANEGCOMPLETE) - rt_kprintf("%s: Autonegotiation complete\n", dev->parent.name); - else - rt_kprintf("%s: Autonegotiation timed out (status=0x%04x)\n", - dev->parent.name, status); -} - - -static int macb_phy_init(rt_device_t dev) -{ - struct rt_macb_eth *macb = dev->user_data; - rt_uint32_t ncfgr; - rt_uint16_t phy_id, status, adv, lpa; - int media, speed, duplex; - int i; - - /* Check if the PHY is up to snuff... */ - phy_id = macb_mdio_read(macb, MII_PHYSID1); - if (phy_id == 0xffff) - { - rt_kprintf("%s: No PHY present\n", dev->parent.name); - return 0; - } - - status = macb_mdio_read(macb, MII_BMSR); - if (!(status & BMSR_LSTATUS)) - { - /* Try to re-negotiate if we don't have link already. */ - macb_phy_reset(dev); - - for (i = 0; i < MACB_LINK_TIMEOUT / 100; i++) - { - status = macb_mdio_read(macb, MII_BMSR); - if (status & BMSR_LSTATUS) - break; - udelay(100); - } - } - - if (!(status & BMSR_LSTATUS)) - { - rt_kprintf("%s: link down (status: 0x%04x)\n", - dev->parent.name, status); - return 0; - } - else - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 1 : 0); - duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up, %sMbps %s-duplex (lpa: 0x%04x)\n", - dev->parent.name, - speed ? "100" : "10", - duplex ? "full" : "half", - lpa); - - ncfgr = macb_readl(macb, NCFGR); - ncfgr &= ~(MACB_BIT(SPD) | MACB_BIT(FD)); - if (speed) - ncfgr |= MACB_BIT(SPD); - if (duplex) - ncfgr |= MACB_BIT(FD); - macb_writel(macb, NCFGR, ncfgr); - return 1; - } -} - -void macb_update_link(void *param) -{ - struct rt_macb_eth *macb = (struct rt_macb_eth *)param; - rt_device_t dev = &macb->parent.parent; - int status, status_change = 0; - rt_uint32_t link; - rt_uint32_t media; - rt_uint16_t adv, lpa; - - /* Do a fake read */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; - - /* Read link and autonegotiation status */ - status = macb_mdio_read(macb, MII_BMSR); - if (status < 0) - return; - - if ((status & BMSR_LSTATUS) == 0) - link = 0; - else - link = 1; - - if (link != macb->link) - { - macb->link = link; - status_change = 1; - } - - if (status_change) - { - if (macb->link) - { - adv = macb_mdio_read(macb, MII_ADVERTISE); - lpa = macb_mdio_read(macb, MII_LPA); - media = mii_nway_result(lpa & adv); - macb->speed = (media & (ADVERTISE_100FULL | ADVERTISE_100HALF) - ? 100 : 10); - macb->duplex = (media & ADVERTISE_FULL) ? 1 : 0; - rt_kprintf("%s: link up (%dMbps/%s-duplex)\n", - dev->parent.name, macb->speed, - DUPLEX_FULL == macb->duplex ? "Full":"Half"); - eth_device_linkchange(&macb->parent, RT_TRUE); - } - else - { - rt_kprintf("%s: link down\n", dev->parent.name); - eth_device_linkchange(&macb->parent, RT_FALSE); - } - - } - -} - -/* RT-Thread Device Interface */ -/* initialize the interface */ - -static rt_err_t rt_macb_init(rt_device_t dev) -{ - struct rt_macb_eth *macb = dev->user_data; - unsigned long paddr; - rt_uint32_t hwaddr_bottom; - rt_uint16_t hwaddr_top; - int i; - - /* - * macb_halt should have been called at some point before now, - * so we'll assume the controller is idle. - */ - - /* initialize DMA descriptors */ - paddr = macb->rx_buffer_dma; - for (i = 0; i < MACB_RX_RING_SIZE; i++) - { - if (i == (MACB_RX_RING_SIZE - 1)) - paddr |= RXADDR_WRAP; - macb->rx_ring[i].addr = paddr; - macb->rx_ring[i].ctrl = 0; - paddr += 128; - } - paddr = macb->tx_buffer_dma; - for (i = 0; i < MACB_TX_RING_SIZE; i++) - { - macb->tx_ring[i].addr = paddr; - if (i == (MACB_TX_RING_SIZE - 1)) - macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP; - else - macb->tx_ring[i].ctrl = TXBUF_USED; - paddr += 1536; - } - macb->rx_tail = macb->tx_head = macb->tx_tail = 0; - - BD_CACHE_WRITEBACK_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - BD_CACHE_WRITEBACK_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb_writel(macb, RBQP, macb->rx_ring_dma); - macb_writel(macb, TBQP, macb->tx_ring_dma); - - /* set hardware address */ - hwaddr_bottom = (*((rt_uint32_t *)macb->dev_addr)); - macb_writel(macb, SA1B, hwaddr_bottom); - hwaddr_top = (*((rt_uint16_t *)(macb->dev_addr + 4))); - macb_writel(macb, SA1T, hwaddr_top); - - - /* choose RMII or MII mode. This depends on the board */ -#ifdef CONFIG_RMII - macb_writel(macb, USRIO, MACB_BIT(RMII) | MACB_BIT(CLKEN)); -#else - macb_writel(macb, USRIO, MACB_BIT(CLKEN)); -#endif /* CONFIG_RMII */ - - if (!macb_phy_init(dev)) - return -RT_ERROR; - - /* Enable TX and RX */ - macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(MPE)); - - /* Enable interrupts */ - macb_writel(macb, IER, (MACB_BIT(RCOMP) - | MACB_BIT(RXUBR) - | MACB_BIT(ISR_TUND) - | MACB_BIT(ISR_RLE) - | MACB_BIT(TXERR) - | MACB_BIT(TCOMP) - | MACB_BIT(ISR_ROVR) - | MACB_BIT(HRESP))); - - /* instal interrupt */ - rt_hw_interrupt_install(AT91SAM9260_ID_EMAC, rt_macb_isr, - (void *)macb, "emac"); - rt_hw_interrupt_umask(AT91SAM9260_ID_EMAC); - - rt_timer_init(&macb->timer, "link_timer", - macb_update_link, - (void *)macb, - RT_TICK_PER_SECOND, - RT_TIMER_FLAG_PERIODIC); - - rt_timer_start(&macb->timer); - - return RT_EOK; -} - -static rt_err_t rt_macb_open(rt_device_t dev, rt_uint16_t oflag) -{ - return RT_EOK; -} - -static rt_err_t rt_macb_close(rt_device_t dev) -{ - return RT_EOK; -} - -static rt_size_t rt_macb_read(rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -static rt_size_t rt_macb_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size) -{ - rt_set_errno(-RT_ENOSYS); - return 0; -} - -static rt_err_t rt_macb_control(rt_device_t dev, int cmd, void *args) -{ - switch(cmd) - { - case NIOCTL_GADDR: - /* get mac address */ - if(args) rt_memcpy(args, macb_device.dev_addr, 6); - else return -RT_ERROR; - break; - - default : - break; - } - - return RT_EOK; -} - -static void macb_tx(struct rt_macb_eth *macb) -{ - unsigned int tail; - unsigned int head; - rt_uint32_t status; - - status = macb_readl(macb, TSR); - macb_writel(macb, TSR, status); - - /*rt_kprintf("macb_tx status = %02lx\n", - (unsigned long)status);*/ - - if (status & (MACB_BIT(UND) | MACB_BIT(TSR_RLE))) - { - int i; - rt_kprintf("%s: TX %s, resetting buffers\n", - macb->parent.parent.parent.name, status & MACB_BIT(UND) ? - "underrun" : "retry limit exceeded"); - - /* Transfer ongoing, disable transmitter, to avoid confusion */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) & ~MACB_BIT(TE)); - - head = macb->tx_head; - - /*Mark all the buffer as used to avoid sending a lost buffer*/ - for (i = 0; i < MACB_TX_RING_SIZE; i++) - macb->tx_ring[i].ctrl = MACB_BIT(TX_USED); - - /* free transmit buffer in upper layer*/ - - macb->tx_head = macb->tx_tail = 0; - - /* Enable the transmitter again */ - if (status & MACB_BIT(TGO)) - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TE)); - } - - if (!(status & MACB_BIT(COMP))) - /* - * This may happen when a buffer becomes complete - * between reading the ISR and scanning the - * descriptors. Nothing to worry about. - */ - return; - - head = macb->tx_head; - for (tail = macb->tx_tail; tail != head; tail = NEXT_TX(tail)) - { - rt_uint32_t bufstat; - - bufstat = macb->tx_ring[tail].ctrl; - - if (!(bufstat & MACB_BIT(TX_USED))) - break; - } - - macb->tx_tail = tail; - if ((macb->tx_stop == 1) && - TX_BUFFS_AVAIL(macb) > MACB_TX_WAKEUP_THRESH) - rt_sem_release(&macb->tx_ack); -} - - -/* ethernet device interface */ -/* transmit packet. */ -rt_err_t rt_macb_tx( rt_device_t dev, struct pbuf* p) -{ - unsigned long ctrl; - struct pbuf* q; - rt_uint8_t* bufptr; - rt_uint32_t mapping; - struct rt_macb_eth *macb = dev->user_data; - unsigned int tx_head = macb->tx_head; - - rt_sem_take(&macb->tx_lock, RT_WAITING_FOREVER); - if (TX_BUFFS_AVAIL(macb) < 1) - { - rt_sem_release(&macb->tx_lock); - rt_kprintf("Tx Ring full!\n"); - rt_kprintf("tx_head = %u, tx_tail = %u\n", - macb->tx_head, macb->tx_tail); - return -RT_ERROR; - } - - macb->tx_stop = 0; - - ctrl = p->tot_len & TXBUF_FRMLEN_MASK; - ctrl |= TXBUF_FRAME_END; - if (tx_head == (MACB_TX_RING_SIZE - 1)) - { - ctrl |= TXBUF_WRAP; - } -#if defined(MACB_TX_SRAM) - bufptr = macb->tx_buffer + tx_head * 1536; -#else - mapping = (unsigned long)macb->tx_buffer + tx_head * 1536; - bufptr = (rt_uint8_t *)mapping; -#endif - - for (q = p; q != NULL; q = q->next) - { - memcpy(bufptr, q->payload, q->len); - bufptr += q->len; - } -#if !defined(MACB_TX_SRAM) - EMAC_CACHE_WRITEBACK(mapping, p->tot_len); -#endif - macb->tx_ring[tx_head].ctrl = ctrl; - BD_CACHE_WRITEBACK_INVALIDATE(&macb->tx_ring[tx_head], sizeof(struct macb_dma_desc)); - tx_head = NEXT_TX(tx_head); - macb->tx_head = tx_head; - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - macb_writel(macb, NCR, macb_readl(macb, NCR) | MACB_BIT(TSTART)); - - if (TX_BUFFS_AVAIL(macb) < 1) - { - macb->tx_stop = 1; - rt_sem_take(&macb->tx_ack, RT_WAITING_FOREVER); - } - rt_sem_release(&macb->tx_lock); - - return RT_EOK; -} - -static void reclaim_rx_buffers(struct rt_macb_eth *macb, - unsigned int new_tail) -{ - unsigned int i; - - i = macb->rx_tail; - while (i > new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - if (i > MACB_RX_RING_SIZE) - i = 0; - } - - while (i < new_tail) - { - macb->rx_ring[i].addr &= ~RXADDR_USED; - i++; - } - - macb->rx_tail = new_tail; -} - -/* reception packet. */ -struct pbuf *rt_macb_rx(rt_device_t dev) -{ - struct rt_macb_eth *macb = dev->user_data; - struct pbuf* p = RT_NULL; - rt_uint32_t len; - unsigned int rx_tail = macb->rx_tail; - void *buffer; - int wrapped = 0; - rt_uint32_t status; - - rt_sem_take(&macb->rx_lock, RT_WAITING_FOREVER); - for (;;) - { - if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED)) - break; - - status = macb->rx_ring[rx_tail].ctrl; - if (status & RXBUF_FRAME_START) - { - if (rx_tail != macb->rx_tail) - reclaim_rx_buffers(macb, rx_tail); - wrapped = 0; - } - - if (status & RXBUF_FRAME_END) - { - buffer = (void *)((unsigned int)macb->rx_buffer + 128 * macb->rx_tail); - len = status & RXBUF_FRMLEN_MASK; - p = pbuf_alloc(PBUF_LINK, len, PBUF_RAM); - if (!p) - { - rt_kprintf("alloc pbuf failed\n"); - break; - } - if (wrapped) - { - unsigned int headlen, taillen; - - headlen = 128 * (MACB_RX_RING_SIZE - - macb->rx_tail); - taillen = len - headlen; - EMAC_CACHE_INVALIDATE(buffer, headlen); - EMAC_CACHE_INVALIDATE(macb->rx_buffer, taillen); - memcpy((void *)p->payload, buffer, headlen); - memcpy((void *)((unsigned int)p->payload + headlen), - macb->rx_buffer, taillen); - } - else - { - EMAC_CACHE_INVALIDATE(buffer, len); - memcpy((void *)p->payload, buffer, p->len); - } - - if (++rx_tail >= MACB_RX_RING_SIZE) - rx_tail = 0; - reclaim_rx_buffers(macb, rx_tail); - break; - } - else - { - if (++rx_tail >= MACB_RX_RING_SIZE) - { - wrapped = 1; - rx_tail = 0; - } - } - } - - rt_sem_release(&macb->rx_lock); - - return p; -} - -void macb_gpio_init() -{ - /* Pins used for MII and RMII */ - AT91C_BASE_PIOA->PIO_PDR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20); - AT91C_BASE_PIOA->PIO_ASR, (1 << 19)|(1 << 17)|(1 << 14)|(1 << 15)|(1 << 18)|(1 << 16)|(1 << 12)|(1 << 13)|(1 << 21)|(1 << 20); - -#ifndef GONFIG_RMII - AT91C_BASE_PIOA->PIO_PDR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29); - AT91C_BASE_PIOA->PIO_ASR, (1 << 22)|(1 << 23)|(1 << 24)|(1 << 25)|(1 << 26)|(1 << 27)|(1 << 28)|(1 << 29); -#endif -} - -rt_err_t macb_initialize() -{ - struct rt_macb_eth *macb = &macb_device; - unsigned long macb_hz; - rt_uint32_t ncfgr; - -#if defined(MACB_TX_SRAM) - macb->tx_ring_dma = AT91SAM9260_SRAM0_BASE; - macb->tx_ring = (struct macb_dma_desc *)AT91SAM9260_SRAM0_VIRT_BASE; - macb->tx_buffer = (char *) macb->tx_ring + TX_RING_BYTES; - macb->tx_buffer_dma = macb->tx_ring_dma + TX_RING_BYTES; -#else - macb->tx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->tx_ring == RT_NULL) - goto err1; - EMAC_CACHE_INVALIDATE(macb->tx_ring, MACB_TX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->tx_ring_dma = emac_virt_to_phys((unsigned long)macb->tx_ring); - macb->tx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->tx_ring); - macb->tx_buffer = rt_malloc(MACB_TX_BUFFER_SIZE); - if (macb->tx_buffer == RT_NULL) - goto err2; - macb->tx_buffer_dma = emac_virt_to_phys((unsigned long)macb->tx_buffer); -#endif - - macb->rx_ring = rt_malloc(MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - if (macb->rx_ring == RT_NULL) - goto err3; - EMAC_CACHE_INVALIDATE(macb->rx_ring, MACB_RX_RING_SIZE * sizeof(struct macb_dma_desc)); - macb->rx_ring_dma = emac_virt_to_phys((unsigned long)macb->rx_ring); - macb->rx_ring = (struct macb_dma_desc *)MMU_NOCACHE_ADDR((unsigned long)macb->rx_ring); - macb->rx_buffer = rt_malloc(MACB_RX_BUFFER_SIZE); - if (macb->rx_buffer == RT_NULL) - goto err4; - macb->rx_buffer_dma = emac_virt_to_phys((unsigned long)macb->rx_buffer); - - macb->tx_pending = DEF_TX_RING_PENDING; - - macb->regs = AT91SAM9260_BASE_EMAC; - macb->phy_addr = 0x00; - - /* - * Do some basic initialization so that we at least can talk - * to the PHY - */ - macb_hz = clk_get_rate(clk_get("mck")); - if (macb_hz < 20000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV8); - else if (macb_hz < 40000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV16); - else if (macb_hz < 80000000) - ncfgr = MACB_BF(CLK, MACB_CLK_DIV32); - else - ncfgr = MACB_BF(CLK, MACB_CLK_DIV64); - - macb_writel(macb, NCFGR, ncfgr); - - macb->link = 0; - - return RT_EOK; - -err4: - rt_free(macb->rx_ring); - macb->rx_ring = RT_NULL; -err3: -#if !defined(MACB_TX_SRAM) - rt_free(macb->tx_buffer); - macb->tx_buffer = RT_NULL; -err2: - rt_free(macb->tx_ring); - macb->tx_ring = RT_NULL; -err1: -#endif - return -RT_ENOMEM; -} - -int rt_hw_macb_init(void) -{ - rt_err_t ret; - AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_EMAC; //enable macb clock - macb_gpio_init(); - rt_memset(&macb_device, 0, sizeof(macb_device)); - ret = macb_initialize(); - if (ret != RT_EOK) - { - rt_kprintf("AT91 EMAC initialized failed\n"); - return -1; - } - rt_sem_init(&macb_device.tx_ack, "tx_ack", 0, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.tx_lock, "tx_lock", 1, RT_IPC_FLAG_FIFO); - rt_sem_init(&macb_device.rx_lock, "rx_lock", 1, RT_IPC_FLAG_FIFO); - - macb_device.dev_addr[0] = 0x00; - macb_device.dev_addr[1] = 0x60; - macb_device.dev_addr[2] = 0x6E; - macb_device.dev_addr[3] = 0x11; - macb_device.dev_addr[4] = 0x22; - macb_device.dev_addr[5] = 0x33; - - macb_device.parent.parent.init = rt_macb_init; - macb_device.parent.parent.open = rt_macb_open; - macb_device.parent.parent.close = rt_macb_close; - macb_device.parent.parent.read = rt_macb_read; - macb_device.parent.parent.write = rt_macb_write; - macb_device.parent.parent.control = rt_macb_control; - macb_device.parent.parent.user_data = &macb_device; - - macb_device.parent.eth_rx = rt_macb_rx; - macb_device.parent.eth_tx = rt_macb_tx; - - rt_sem_init(&macb_device.mdio_bus_lock, "mdio_bus_lock", 1, RT_IPC_FLAG_FIFO); - - eth_device_init(&(macb_device.parent), "e0"); - - return 0; -} - -INIT_DEVICE_EXPORT(rt_hw_macb_init); - diff --git a/bsp/at91sam9g45/drivers/macb.h b/bsp/at91sam9g45/drivers/macb.h deleted file mode 100644 index 9df2883534a670f303ca7e2856044b32385a37e9..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/drivers/macb.h +++ /dev/null @@ -1,346 +0,0 @@ -/* - * File : macb.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-03-18 weety first version - */ -#ifndef _MACB_H -#define _MACB_H -#include - -/* MACB register offsets */ -#define MACB_NCR 0x0000 -#define MACB_NCFGR 0x0004 -#define MACB_NSR 0x0008 -#define MACB_TSR 0x0014 -#define MACB_RBQP 0x0018 -#define MACB_TBQP 0x001c -#define MACB_RSR 0x0020 -#define MACB_ISR 0x0024 -#define MACB_IER 0x0028 -#define MACB_IDR 0x002c -#define MACB_IMR 0x0030 -#define MACB_MAN 0x0034 -#define MACB_PTR 0x0038 -#define MACB_PFR 0x003c -#define MACB_FTO 0x0040 -#define MACB_SCF 0x0044 -#define MACB_MCF 0x0048 -#define MACB_FRO 0x004c -#define MACB_FCSE 0x0050 -#define MACB_ALE 0x0054 -#define MACB_DTF 0x0058 -#define MACB_LCOL 0x005c -#define MACB_EXCOL 0x0060 -#define MACB_TUND 0x0064 -#define MACB_CSE 0x0068 -#define MACB_RRE 0x006c -#define MACB_ROVR 0x0070 -#define MACB_RSE 0x0074 -#define MACB_ELE 0x0078 -#define MACB_RJA 0x007c -#define MACB_USF 0x0080 -#define MACB_STE 0x0084 -#define MACB_RLE 0x0088 -#define MACB_TPF 0x008c -#define MACB_HRB 0x0090 -#define MACB_HRT 0x0094 -#define MACB_SA1B 0x0098 -#define MACB_SA1T 0x009c -#define MACB_SA2B 0x00a0 -#define MACB_SA2T 0x00a4 -#define MACB_SA3B 0x00a8 -#define MACB_SA3T 0x00ac -#define MACB_SA4B 0x00b0 -#define MACB_SA4T 0x00b4 -#define MACB_TID 0x00b8 -#define MACB_TPQ 0x00bc -#define MACB_USRIO 0x00c0 -#define MACB_WOL 0x00c4 - -/* Bitfields in NCR */ -#define MACB_LB_OFFSET 0 -#define MACB_LB_SIZE 1 -#define MACB_LLB_OFFSET 1 -#define MACB_LLB_SIZE 1 -#define MACB_RE_OFFSET 2 -#define MACB_RE_SIZE 1 -#define MACB_TE_OFFSET 3 -#define MACB_TE_SIZE 1 -#define MACB_MPE_OFFSET 4 -#define MACB_MPE_SIZE 1 -#define MACB_CLRSTAT_OFFSET 5 -#define MACB_CLRSTAT_SIZE 1 -#define MACB_INCSTAT_OFFSET 6 -#define MACB_INCSTAT_SIZE 1 -#define MACB_WESTAT_OFFSET 7 -#define MACB_WESTAT_SIZE 1 -#define MACB_BP_OFFSET 8 -#define MACB_BP_SIZE 1 -#define MACB_TSTART_OFFSET 9 -#define MACB_TSTART_SIZE 1 -#define MACB_THALT_OFFSET 10 -#define MACB_THALT_SIZE 1 -#define MACB_NCR_TPF_OFFSET 11 -#define MACB_NCR_TPF_SIZE 1 -#define MACB_TZQ_OFFSET 12 -#define MACB_TZQ_SIZE 1 - -/* Bitfields in NCFGR */ -#define MACB_SPD_OFFSET 0 -#define MACB_SPD_SIZE 1 -#define MACB_FD_OFFSET 1 -#define MACB_FD_SIZE 1 -#define MACB_BIT_RATE_OFFSET 2 -#define MACB_BIT_RATE_SIZE 1 -#define MACB_JFRAME_OFFSET 3 -#define MACB_JFRAME_SIZE 1 -#define MACB_CAF_OFFSET 4 -#define MACB_CAF_SIZE 1 -#define MACB_NBC_OFFSET 5 -#define MACB_NBC_SIZE 1 -#define MACB_NCFGR_MTI_OFFSET 6 -#define MACB_NCFGR_MTI_SIZE 1 -#define MACB_UNI_OFFSET 7 -#define MACB_UNI_SIZE 1 -#define MACB_BIG_OFFSET 8 -#define MACB_BIG_SIZE 1 -#define MACB_EAE_OFFSET 9 -#define MACB_EAE_SIZE 1 -#define MACB_CLK_OFFSET 10 -#define MACB_CLK_SIZE 2 -#define MACB_RTY_OFFSET 12 -#define MACB_RTY_SIZE 1 -#define MACB_PAE_OFFSET 13 -#define MACB_PAE_SIZE 1 -#define MACB_RBOF_OFFSET 14 -#define MACB_RBOF_SIZE 2 -#define MACB_RLCE_OFFSET 16 -#define MACB_RLCE_SIZE 1 -#define MACB_DRFCS_OFFSET 17 -#define MACB_DRFCS_SIZE 1 -#define MACB_EFRHD_OFFSET 18 -#define MACB_EFRHD_SIZE 1 -#define MACB_IRXFCS_OFFSET 19 -#define MACB_IRXFCS_SIZE 1 - -/* Bitfields in NSR */ -#define MACB_NSR_LINK_OFFSET 0 -#define MACB_NSR_LINK_SIZE 1 -#define MACB_MDIO_OFFSET 1 -#define MACB_MDIO_SIZE 1 -#define MACB_IDLE_OFFSET 2 -#define MACB_IDLE_SIZE 1 - -/* Bitfields in TSR */ -#define MACB_UBR_OFFSET 0 -#define MACB_UBR_SIZE 1 -#define MACB_COL_OFFSET 1 -#define MACB_COL_SIZE 1 -#define MACB_TSR_RLE_OFFSET 2 -#define MACB_TSR_RLE_SIZE 1 -#define MACB_TGO_OFFSET 3 -#define MACB_TGO_SIZE 1 -#define MACB_BEX_OFFSET 4 -#define MACB_BEX_SIZE 1 -#define MACB_COMP_OFFSET 5 -#define MACB_COMP_SIZE 1 -#define MACB_UND_OFFSET 6 -#define MACB_UND_SIZE 1 - -/* Bitfields in RSR */ -#define MACB_BNA_OFFSET 0 -#define MACB_BNA_SIZE 1 -#define MACB_REC_OFFSET 1 -#define MACB_REC_SIZE 1 -#define MACB_OVR_OFFSET 2 -#define MACB_OVR_SIZE 1 - -/* Bitfields in ISR/IER/IDR/IMR */ -#define MACB_MFD_OFFSET 0 -#define MACB_MFD_SIZE 1 -#define MACB_RCOMP_OFFSET 1 -#define MACB_RCOMP_SIZE 1 -#define MACB_RXUBR_OFFSET 2 -#define MACB_RXUBR_SIZE 1 -#define MACB_TXUBR_OFFSET 3 -#define MACB_TXUBR_SIZE 1 -#define MACB_ISR_TUND_OFFSET 4 -#define MACB_ISR_TUND_SIZE 1 -#define MACB_ISR_RLE_OFFSET 5 -#define MACB_ISR_RLE_SIZE 1 -#define MACB_TXERR_OFFSET 6 -#define MACB_TXERR_SIZE 1 -#define MACB_TCOMP_OFFSET 7 -#define MACB_TCOMP_SIZE 1 -#define MACB_ISR_LINK_OFFSET 9 -#define MACB_ISR_LINK_SIZE 1 -#define MACB_ISR_ROVR_OFFSET 10 -#define MACB_ISR_ROVR_SIZE 1 -#define MACB_HRESP_OFFSET 11 -#define MACB_HRESP_SIZE 1 -#define MACB_PFR_OFFSET 12 -#define MACB_PFR_SIZE 1 -#define MACB_PTZ_OFFSET 13 -#define MACB_PTZ_SIZE 1 - -/* Bitfields in MAN */ -#define MACB_DATA_OFFSET 0 -#define MACB_DATA_SIZE 16 -#define MACB_CODE_OFFSET 16 -#define MACB_CODE_SIZE 2 -#define MACB_REGA_OFFSET 18 -#define MACB_REGA_SIZE 5 -#define MACB_PHYA_OFFSET 23 -#define MACB_PHYA_SIZE 5 -#define MACB_RW_OFFSET 28 -#define MACB_RW_SIZE 2 -#define MACB_SOF_OFFSET 30 -#define MACB_SOF_SIZE 2 - -/* Bitfields in USRIO (AVR32) */ -#define MACB_MII_OFFSET 0 -#define MACB_MII_SIZE 1 -#define MACB_EAM_OFFSET 1 -#define MACB_EAM_SIZE 1 -#define MACB_TX_PAUSE_OFFSET 2 -#define MACB_TX_PAUSE_SIZE 1 -#define MACB_TX_PAUSE_ZERO_OFFSET 3 -#define MACB_TX_PAUSE_ZERO_SIZE 1 - -/* Bitfields in USRIO (AT91) */ -#define MACB_RMII_OFFSET 0 -#define MACB_RMII_SIZE 1 -#define MACB_CLKEN_OFFSET 1 -#define MACB_CLKEN_SIZE 1 - -/* Bitfields in WOL */ -#define MACB_IP_OFFSET 0 -#define MACB_IP_SIZE 16 -#define MACB_MAG_OFFSET 16 -#define MACB_MAG_SIZE 1 -#define MACB_ARP_OFFSET 17 -#define MACB_ARP_SIZE 1 -#define MACB_SA1_OFFSET 18 -#define MACB_SA1_SIZE 1 -#define MACB_WOL_MTI_OFFSET 19 -#define MACB_WOL_MTI_SIZE 1 - -/* Constants for CLK */ -#define MACB_CLK_DIV8 0 -#define MACB_CLK_DIV16 1 -#define MACB_CLK_DIV32 2 -#define MACB_CLK_DIV64 3 - -/* Constants for MAN register */ -#define MACB_MAN_SOF 1 -#define MACB_MAN_WRITE 1 -#define MACB_MAN_READ 2 -#define MACB_MAN_CODE 2 - -/* Bit manipulation macros */ -#define MACB_BIT(name) \ - (1 << MACB_##name##_OFFSET) -#define MACB_BF(name,value) \ - (((value) & ((1 << MACB_##name##_SIZE) - 1)) \ - << MACB_##name##_OFFSET) -#define MACB_BFEXT(name,value)\ - (((value) >> MACB_##name##_OFFSET) \ - & ((1 << MACB_##name##_SIZE) - 1)) -#define MACB_BFINS(name,value,old) \ - (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \ - << MACB_##name##_OFFSET)) \ - | MACB_BF(name,value)) - -/* Register access macros */ -#define macb_readl(port,reg) \ - readl((port)->regs + MACB_##reg) -#define macb_writel(port,reg,value) \ - writel((value), (port)->regs + MACB_##reg) - -struct dma_desc { - rt_uint32_t addr; - rt_uint32_t ctrl; -}; - -/* DMA descriptor bitfields */ -#define MACB_RX_USED_OFFSET 0 -#define MACB_RX_USED_SIZE 1 -#define MACB_RX_WRAP_OFFSET 1 -#define MACB_RX_WRAP_SIZE 1 -#define MACB_RX_WADDR_OFFSET 2 -#define MACB_RX_WADDR_SIZE 30 - -#define MACB_RX_FRMLEN_OFFSET 0 -#define MACB_RX_FRMLEN_SIZE 12 -#define MACB_RX_OFFSET_OFFSET 12 -#define MACB_RX_OFFSET_SIZE 2 -#define MACB_RX_SOF_OFFSET 14 -#define MACB_RX_SOF_SIZE 1 -#define MACB_RX_EOF_OFFSET 15 -#define MACB_RX_EOF_SIZE 1 -#define MACB_RX_CFI_OFFSET 16 -#define MACB_RX_CFI_SIZE 1 -#define MACB_RX_VLAN_PRI_OFFSET 17 -#define MACB_RX_VLAN_PRI_SIZE 3 -#define MACB_RX_PRI_TAG_OFFSET 20 -#define MACB_RX_PRI_TAG_SIZE 1 -#define MACB_RX_VLAN_TAG_OFFSET 21 -#define MACB_RX_VLAN_TAG_SIZE 1 -#define MACB_RX_TYPEID_MATCH_OFFSET 22 -#define MACB_RX_TYPEID_MATCH_SIZE 1 -#define MACB_RX_SA4_MATCH_OFFSET 23 -#define MACB_RX_SA4_MATCH_SIZE 1 -#define MACB_RX_SA3_MATCH_OFFSET 24 -#define MACB_RX_SA3_MATCH_SIZE 1 -#define MACB_RX_SA2_MATCH_OFFSET 25 -#define MACB_RX_SA2_MATCH_SIZE 1 -#define MACB_RX_SA1_MATCH_OFFSET 26 -#define MACB_RX_SA1_MATCH_SIZE 1 -#define MACB_RX_EXT_MATCH_OFFSET 28 -#define MACB_RX_EXT_MATCH_SIZE 1 -#define MACB_RX_UHASH_MATCH_OFFSET 29 -#define MACB_RX_UHASH_MATCH_SIZE 1 -#define MACB_RX_MHASH_MATCH_OFFSET 30 -#define MACB_RX_MHASH_MATCH_SIZE 1 -#define MACB_RX_BROADCAST_OFFSET 31 -#define MACB_RX_BROADCAST_SIZE 1 - -#define MACB_TX_FRMLEN_OFFSET 0 -#define MACB_TX_FRMLEN_SIZE 11 -#define MACB_TX_LAST_OFFSET 15 -#define MACB_TX_LAST_SIZE 1 -#define MACB_TX_NOCRC_OFFSET 16 -#define MACB_TX_NOCRC_SIZE 1 -#define MACB_TX_BUF_EXHAUSTED_OFFSET 27 -#define MACB_TX_BUF_EXHAUSTED_SIZE 1 -#define MACB_TX_UNDERRUN_OFFSET 28 -#define MACB_TX_UNDERRUN_SIZE 1 -#define MACB_TX_ERROR_OFFSET 29 -#define MACB_TX_ERROR_SIZE 1 -#define MACB_TX_WRAP_OFFSET 30 -#define MACB_TX_WRAP_SIZE 1 -#define MACB_TX_USED_OFFSET 31 -#define MACB_TX_USED_SIZE 1 - -extern int rt_hw_macb_init(); - -#endif /* _MACB_H */ - diff --git a/bsp/at91sam9g45/drivers/mii.h b/bsp/at91sam9g45/drivers/mii.h deleted file mode 100644 index 2f6dd18e710b90b9fd5fbb1e59e61450438ce9d7..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/drivers/mii.h +++ /dev/null @@ -1,191 +0,0 @@ -/* - * File : mii.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-03-18 weety first version - */ - -#ifndef __MII_H__ -#define __MII_H__ - -/* Generic MII registers. */ - -#define MII_BMCR 0x00 /* Basic mode control register */ -#define MII_BMSR 0x01 /* Basic mode status register */ -#define MII_PHYSID1 0x02 /* PHYS ID 1 */ -#define MII_PHYSID2 0x03 /* PHYS ID 2 */ -#define MII_ADVERTISE 0x04 /* Advertisement control reg */ -#define MII_LPA 0x05 /* Link partner ability reg */ -#define MII_EXPANSION 0x06 /* Expansion register */ -#define MII_CTRL1000 0x09 /* 1000BASE-T control */ -#define MII_STAT1000 0x0a /* 1000BASE-T status */ -#define MII_ESTATUS 0x0f /* Extended Status */ -#define MII_DCOUNTER 0x12 /* Disconnect counter */ -#define MII_FCSCOUNTER 0x13 /* False carrier counter */ -#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ -#define MII_RERRCOUNTER 0x15 /* Receive error counter */ -#define MII_SREVISION 0x16 /* Silicon revision */ -#define MII_RESV1 0x17 /* Reserved... */ -#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ -#define MII_PHYADDR 0x19 /* PHY address */ -#define MII_RESV2 0x1a /* Reserved... */ -#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ -#define MII_NCONFIG 0x1c /* Network interface config */ - -/* Basic mode control register. */ -#define BMCR_RESV 0x003f /* Unused... */ -#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ -#define BMCR_CTST 0x0080 /* Collision test */ -#define BMCR_FULLDPLX 0x0100 /* Full duplex */ -#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ -#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */ -#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */ -#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ -#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ -#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ -#define BMCR_RESET 0x8000 /* Reset the DP83840 */ - -/* Basic mode status register. */ -#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ -#define BMSR_JCD 0x0002 /* Jabber detected */ -#define BMSR_LSTATUS 0x0004 /* Link status */ -#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ -#define BMSR_RFAULT 0x0010 /* Remote fault detected */ -#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ -#define BMSR_RESV 0x00c0 /* Unused... */ -#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ -#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ -#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ -#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ -#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ -#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ -#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ -#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ - -/* Advertisement control register. */ -#define ADVERTISE_SLCT 0x001f /* Selector bits */ -#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ -#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ -#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ -#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ -#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ -#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ -#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ -#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ -#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ -#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ -#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ -#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ -#define ADVERTISE_RESV 0x1000 /* Unused... */ -#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ -#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ -#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ - -#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ - ADVERTISE_CSMA) -#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ - ADVERTISE_100HALF | ADVERTISE_100FULL) - -/* Link partner ability register. */ -#define LPA_SLCT 0x001f /* Same as advertise selector */ -#define LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */ -#define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */ -#define LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */ -#define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */ -#define LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */ -#define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */ -#define LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */ -#define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/ -#define LPA_100BASE4 0x0200 /* Can do 100mbps 4k packets */ -#define LPA_PAUSE_CAP 0x0400 /* Can pause */ -#define LPA_PAUSE_ASYM 0x0800 /* Can pause asymetrically */ -#define LPA_RESV 0x1000 /* Unused... */ -#define LPA_RFAULT 0x2000 /* Link partner faulted */ -#define LPA_LPACK 0x4000 /* Link partner acked us */ -#define LPA_NPAGE 0x8000 /* Next page bit */ - -#define LPA_DUPLEX (LPA_10FULL | LPA_100FULL) -#define LPA_100 (LPA_100FULL | LPA_100HALF | LPA_100BASE4) - -/* Expansion register for auto-negotiation. */ -#define EXPANSION_NWAY 0x0001 /* Can do N-way auto-nego */ -#define EXPANSION_LCWP 0x0002 /* Got new RX page code word */ -#define EXPANSION_ENABLENPAGE 0x0004 /* This enables npage words */ -#define EXPANSION_NPCAPABLE 0x0008 /* Link partner supports npage */ -#define EXPANSION_MFAULTS 0x0010 /* Multiple faults detected */ -#define EXPANSION_RESV 0xffe0 /* Unused... */ - -#define ESTATUS_1000_TFULL 0x2000 /* Can do 1000BT Full */ -#define ESTATUS_1000_THALF 0x1000 /* Can do 1000BT Half */ - -/* N-way test register. */ -#define NWAYTEST_RESV1 0x00ff /* Unused... */ -#define NWAYTEST_LOOPBACK 0x0100 /* Enable loopback for N-way */ -#define NWAYTEST_RESV2 0xfe00 /* Unused... */ - -/* 1000BASE-T Control register */ -#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ -#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ - -/* 1000BASE-T Status register */ -#define LPA_1000LOCALRXOK 0x2000 /* Link partner local receiver status */ -#define LPA_1000REMRXOK 0x1000 /* Link partner remote receiver status */ -#define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */ -#define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */ - -/* Flow control flags */ -#define FLOW_CTRL_TX 0x01 -#define FLOW_CTRL_RX 0x02 - -/** - * mii_nway_result - * @negotiated: value of MII ANAR and'd with ANLPAR - * - * Given a set of MII abilities, check each bit and returns the - * currently supported media, in the priority order defined by - * IEEE 802.3u. We use LPA_xxx constants but note this is not the - * value of LPA solely, as described above. - * - * The one exception to IEEE 802.3u is that 100baseT4 is placed - * between 100T-full and 100T-half. If your phy does not support - * 100T4 this is fine. If your phy places 100T4 elsewhere in the - * priority order, you will need to roll your own function. - */ -rt_inline unsigned int mii_nway_result (unsigned int negotiated) -{ - unsigned int ret; - - if (negotiated & LPA_100FULL) - ret = LPA_100FULL; - else if (negotiated & LPA_100BASE4) - ret = LPA_100BASE4; - else if (negotiated & LPA_100HALF) - ret = LPA_100HALF; - else if (negotiated & LPA_10FULL) - ret = LPA_10FULL; - else - ret = LPA_10HALF; - - return ret; -} - - -#endif /* __MII_H__ */ - diff --git a/bsp/at91sam9g45/drivers/usart.c b/bsp/at91sam9g45/drivers/usart.c deleted file mode 100644 index d4ba657232d68f3ca6b4472151b442f1081bcd9f..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/drivers/usart.c +++ /dev/null @@ -1,398 +0,0 @@ -/* - * File : usart.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - * 2013-07-21 weety using serial component - */ - -#include -#include -#include -#include - - -struct at91_uart { - AT91S_USART *port; - int irq; -}; - - -/** - * This function will handle serial port interrupt - */ -void rt_at91_usart_handler(int vector, void *param) -{ - int status; - struct at91_uart *uart; - rt_device_t dev = (rt_device_t)param; - uart = (struct at91_uart *)dev->user_data; - status = uart->port->US_CSR; - if (!(status & uart->port->US_IMR)) /* check actived and enabled interrupt */ - { - return; - } - rt_interrupt_enter(); - rt_hw_serial_isr((struct rt_serial_device *)dev, RT_SERIAL_EVENT_RX_IND); - rt_interrupt_leave(); -} - -/** - * UART device in RT-Thread - */ -static rt_err_t at91_usart_configure(struct rt_serial_device *serial, - struct serial_configure *cfg) -{ - int div; - int mode = 0; - struct at91_uart *uart; - - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - uart = (struct at91_uart *)serial->parent.user_data; - - uart->port->US_CR = AT91C_US_RSTTX | AT91C_US_RSTRX | - AT91C_US_RXDIS | AT91C_US_TXDIS; - mode |= AT91C_US_USMODE_NORMAL | AT91C_US_CLKS_CLOCK | - AT91C_US_CHMODE_NORMAL; - switch (cfg->data_bits) - { - case DATA_BITS_8: - mode |= AT91C_US_CHRL_8_BITS; - break; - case DATA_BITS_7: - mode |= AT91C_US_CHRL_7_BITS; - break; - case DATA_BITS_6: - mode |= AT91C_US_CHRL_6_BITS; - break; - case DATA_BITS_5: - mode |= AT91C_US_CHRL_5_BITS; - break; - default: - mode |= AT91C_US_CHRL_8_BITS; - break; - } - - switch (cfg->stop_bits) - { - case STOP_BITS_2: - mode |= AT91C_US_NBSTOP_2_BIT; - break; - case STOP_BITS_1: - default: - mode |= AT91C_US_NBSTOP_1_BIT; - break; - } - - switch (cfg->parity) - { - case PARITY_ODD: - mode |= AT91C_US_PAR_ODD; - break; - case PARITY_EVEN: - mode |= AT91C_US_PAR_EVEN; - break; - case PARITY_NONE: - default: - mode |= AT91C_US_PAR_NONE; - break; - } - - uart->port->US_MR = mode; - /* Assume OVER is cleared and fractional baudrate generator is disabled */ - div = (clk_get_rate(clk_get("mck")) / 16 + cfg->baud_rate/2) / cfg->baud_rate; - uart->port->US_BRGR = div; - uart->port->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; - uart->port->US_IER = AT91C_US_RXRDY; - - return RT_EOK; -} - -static rt_err_t at91_usart_control(struct rt_serial_device *serial, - int cmd, void *arg) -{ - struct at91_uart* uart; - - RT_ASSERT(serial != RT_NULL); - uart = (struct at91_uart *)serial->parent.user_data; - - switch (cmd) - { - case RT_DEVICE_CTRL_CLR_INT: - /* disable rx irq */ - rt_hw_interrupt_mask(uart->irq); - break; - case RT_DEVICE_CTRL_SET_INT: - /* enable rx irq */ - rt_hw_interrupt_umask(uart->irq); - break; - } - - return RT_EOK; -} - -static int at91_usart_putc(struct rt_serial_device *serial, char c) -{ - //rt_uint32_t level; - struct at91_uart *uart = serial->parent.user_data; - - while (!(uart->port->US_CSR & AT91C_US_TXRDY)); - uart->port->US_THR = c; - - return 1; -} - -static int at91_usart_getc(struct rt_serial_device *serial) -{ - int result; - struct at91_uart *uart = serial->parent.user_data; - - if (uart->port->US_CSR & AT91C_US_RXRDY) - { - result = uart->port->US_RHR & 0xff; - } - else - { - result = -1; - } - - return result; -} - -static const struct rt_uart_ops at91_usart_ops = -{ - at91_usart_configure, - at91_usart_control, - at91_usart_putc, - at91_usart_getc, -}; - -#if defined(RT_USING_DBGU) -static struct rt_serial_device serial_dbgu; -struct at91_uart dbgu = { - (AT91PS_USART)AT91C_BASE_DBGU, - AT91C_ID_SYS -}; - -#endif - -#if defined(RT_USING_UART0) -static struct rt_serial_device serial0; -struct at91_uart uart0 = { - AT91C_BASE_US0, - AT91C_ID_US0 -}; -#endif - -#if defined(RT_USING_UART1) -static struct rt_serial_device serial1; -struct at91_uart uart1 = { - AT91C_BASE_US1, - AT91C_ID_US1 -}; -#endif - -#if defined(RT_USING_UART2) -static struct rt_serial_device serial2; -struct at91_uart uart2 = { - AT91C_BASE_US2, - AT91C_ID_US2 -}; -#endif - -#if defined(RT_USING_UART3) -static struct rt_serial_device serial3; -struct at91_uart uart3 = { - AT91C_BASE_US3, - AT91C_ID_US3 -}; -#endif - - -void at91_usart_gpio_init(void) -{ -#ifdef RT_USING_DBGU -#define DRXD 12 // DBGU rx as Peripheral A on PB12 -#define DTXD 13 // DBGU tx as Peripheral A on PB13 - AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_SYS; -#endif - -#ifdef RT_USING_UART0 -#define RXD0 18 // UART0 rx as Peripheral A on PB18 -#define TXD0 19 // UART0 tx as Peripheral A on PB19 - AT91C_BASE_PMC->PMC_PCER, 1 << AT91C_ID_US0; - AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_US1; - AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1 << AT91C_ID_US2; - AT91C_BASE_PIOB->PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1<PMC_PCER, 1<PIO_IDR, (1<PIO_PPUER, (1<PIO_PPUDR, (1<PIO_ASR, (1<PIO_PDR, (1< R7 -#define AT91C_ISI_RGB_SWAP_ENABLE (0x1 << 14) // (ISI) D0 -> R7 -#define AT91C_ISI_COL_SPACE (0x1 << 15) // (ISI) Color space for the image data -#define AT91C_ISI_COL_SPACE_YCBCR (0x0 << 15) // (ISI) YCbCr -#define AT91C_ISI_COL_SPACE_RGB (0x1 << 15) // (ISI) RGB -#define AT91C_ISI_IM_HSIZE (0x7FF << 16) // (ISI) Horizontal size of the Image sensor [0..2047] -#define AT91C_ISI_YCC_SWAP (0x3 << 28) // (ISI) Ycc swap -#define AT91C_ISI_YCC_SWAP_YCC_DEFAULT (0x0 << 28) // (ISI) Cb(i) Y(i) Cr(i) Y(i+1) -#define AT91C_ISI_YCC_SWAP_YCC_MODE1 (0x1 << 28) // (ISI) Cr(i) Y(i) Cb(i) Y(i+1) -#define AT91C_ISI_YCC_SWAP_YCC_MODE2 (0x2 << 28) // (ISI) Y(i) Cb(i) Y(i+1) Cr(i) -#define AT91C_ISI_YCC_SWAP_YCC_MODE3 (0x3 << 28) // (ISI) Y(i) Cr(i) Y(i+1) Cb(i) -#define AT91C_ISI_RGB_CFG (0x3 << 30) // (ISI) RGB configuration -#define AT91C_ISI_RGB_CFG_RGB_DEFAULT (0x0 << 30) // (ISI) R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B -#define AT91C_ISI_RGB_CFG_RGB_MODE1 (0x1 << 30) // (ISI) B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R -#define AT91C_ISI_RGB_CFG_RGB_MODE2 (0x2 << 30) // (ISI) G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB) -#define AT91C_ISI_RGB_CFG_RGB_MODE3 (0x3 << 30) // (ISI) G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB) -// -------- ISI_PSIZE : (ISI Offset: 0x8) ISI Preview Register -------- -#define AT91C_ISI_PREV_VSIZE (0x3FF << 0) // (ISI) Vertical size for the preview path -#define AT91C_ISI_PREV_HSIZE (0x3FF << 16) // (ISI) Horizontal size for the preview path -// -------- ISI_PDECF : (ISI Offset: 0xc) ISI Preview Decimation Factor Register -------- -#define AT91C_ISI_DEC_FACTOR (0xFF << 0) // (ISI) Decimation factor -// -------- ISI_Y2RSET0 : (ISI Offset: 0x10) Color Space Conversion YCrCb to RGB Register -------- -#define AT91C_ISI_Y2R_C0 (0xFF << 0) // (ISI) Color Space Conversion Matrix Coefficient C0 -#define AT91C_ISI_Y2R_C1 (0xFF << 8) // (ISI) Color Space Conversion Matrix Coefficient C1 -#define AT91C_ISI_Y2R_C2 (0xFF << 16) // (ISI) Color Space Conversion Matrix Coefficient C2 -#define AT91C_ISI_Y2R_C3 (0xFF << 24) // (ISI) Color Space Conversion Matrix Coefficient C3 -// -------- ISI_Y2RSET1 : (ISI Offset: 0x14) ISI Color Space Conversion YCrCb to RGB set 1 Register -------- -#define AT91C_ISI_Y2R_C4 (0x1FF << 0) // (ISI) Color Space Conversion Matrix Coefficient C4 -#define AT91C_ISI_Y2R_YOFF (0x1 << 12) // (ISI) Color Space Conversion Luninance default offset -#define AT91C_ISI_Y2R_YOFF_0 (0x0 << 12) // (ISI) Offset is 0 -#define AT91C_ISI_Y2R_YOFF_128 (0x1 << 12) // (ISI) Offset is 128 -#define AT91C_ISI_Y2R_CROFF (0x1 << 13) // (ISI) Color Space Conversion Red Chrominance default offset -#define AT91C_ISI_Y2R_CROFF_0 (0x0 << 13) // (ISI) Offset is 0 -#define AT91C_ISI_Y2R_CROFF_16 (0x1 << 13) // (ISI) Offset is 16 -#define AT91C_ISI_Y2R_CBOFF (0x1 << 14) // (ISI) Color Space Conversion Blue Chrominance default offset -#define AT91C_ISI_Y2R_CBOFF_0 (0x0 << 14) // (ISI) Offset is 0 -#define AT91C_ISI_Y2R_CBOFF_16 (0x1 << 14) // (ISI) Offset is 16 -// -------- ISI_R2YSET0 : (ISI Offset: 0x18) Color Space Conversion RGB to YCrCb set 0 register -------- -#define AT91C_ISI_R2Y_C0 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C0 -#define AT91C_ISI_R2Y_C1 (0x7F << 8) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C1 -#define AT91C_ISI_R2Y_C2 (0x7F << 16) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C2 -#define AT91C_ISI_R2Y_ROFF (0x1 << 24) // (ISI) Color Space Conversion Red component offset -#define AT91C_ISI_R2Y_ROFF_0 (0x0 << 24) // (ISI) Offset is 0 -#define AT91C_ISI_R2Y_ROFF_16 (0x1 << 24) // (ISI) Offset is 16 -// -------- ISI_R2YSET1 : (ISI Offset: 0x1c) Color Space Conversion RGB to YCrCb set 1 register -------- -#define AT91C_ISI_R2Y_C3 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C3 -#define AT91C_ISI_R2Y_C4 (0x7F << 8) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C4 -#define AT91C_ISI_R2Y_C5 (0x7F << 16) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C5 -#define AT91C_ISI_R2Y_GOFF (0x1 << 24) // (ISI) Color Space Conversion Green component offset -#define AT91C_ISI_R2Y_GOFF_0 (0x0 << 24) // (ISI) Offset is 0 -#define AT91C_ISI_R2Y_GOFF_128 (0x1 << 24) // (ISI) Offset is 128 -// -------- ISI_R2YSET2 : (ISI Offset: 0x20) Color Space Conversion RGB to YCrCb set 2 register -------- -#define AT91C_ISI_R2Y_C6 (0x7F << 0) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C6 -#define AT91C_ISI_R2Y_C7 (0x7F << 8) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C7 -#define AT91C_ISI_R2Y_C8 (0x7F << 16) // (ISI) Color Space Conversion RGB to YCrCb Matrix coefficient C8 -#define AT91C_ISI_R2Y_BOFF (0x1 << 24) // (ISI) Color Space Conversion Blue component offset -#define AT91C_ISI_R2Y_BOFF_0 (0x0 << 24) // (ISI) Offset is 0 -#define AT91C_ISI_R2Y_BOFF_128 (0x1 << 24) // (ISI) Offset is 128 -// -------- ISI_CTRL : (ISI Offset: 0x24) ISI Control Register -------- -#define AT91C_ISI_EN (0x1 << 0) // (ISI) Image Sensor Interface Enable Request -#define AT91C_ISI_EN_0 (0x0) // (ISI) No effect -#define AT91C_ISI_EN_1 (0x1) // (ISI) Enable the module and the capture -#define AT91C_ISI_DIS (0x1 << 1) // (ISI) Image Sensor Interface Disable Request -#define AT91C_ISI_DIS_0 (0x0 << 1) // (ISI) No effect -#define AT91C_ISI_DIS_1 (0x1 << 1) // (ISI) Disable the module and the capture -#define AT91C_ISI_SRST (0x1 << 2) // (ISI) Software Reset Request -#define AT91C_ISI_SRST_0 (0x0 << 2) // (ISI) No effect -#define AT91C_ISI_SRST_1 (0x1 << 2) // (ISI) Reset the module -#define AT91C_ISI_CDC (0x1 << 8) // (ISI) Codec Request -#define AT91C_ISI_CDC_0 (0x0 << 8) // (ISI) No effect -#define AT91C_ISI_CDC_1 (0x1 << 8) // (ISI) Enable the Codec -// -------- ISI_SR : (ISI Offset: 0x28) ISI Status Register -------- -#define AT91C_ISI_VSYNC (0x1 << 10) // (ISI) Vertical Synchronization -#define AT91C_ISI_VSYNC_0 (0x0 << 10) // (ISI) No effect -#define AT91C_ISI_VSYNC_1 (0x1 << 10) // (ISI) Indicates that a Vertical Synchronization has been detected since last read -#define AT91C_ISI_PXFR_DONE (0x1 << 16) // (ISI) Preview DMA transfer terminated -#define AT91C_ISI_PXFR_DONE_0 (0x0 << 16) // (ISI) No effect -#define AT91C_ISI_PXFR_DONE_1 (0x1 << 16) // (ISI) Indicates that DATA transfer on preview channel has completed since last read -#define AT91C_ISI_CXFR_DONE (0x1 << 17) // (ISI) Codec DMA transfer terminated -#define AT91C_ISI_CXFR_DONE_0 (0x0 << 17) // (ISI) No effect -#define AT91C_ISI_CXFR_DONE_1 (0x1 << 17) // (ISI) Indicates that DATA transfer on preview channel has completed since last read -#define AT91C_ISI_SIP (0x1 << 19) // (ISI) Synchronization In Progress -#define AT91C_ISI_SIP_0 (0x0 << 19) // (ISI) No effect -#define AT91C_ISI_SIP_1 (0x1 << 19) // (ISI) Indicates that Synchronization is in progress -#define AT91C_ISI_P_OVR (0x1 << 24) // (ISI) Fifo Preview Overflow -#define AT91C_ISI_P_OVR_0 (0x0 << 24) // (ISI) No error -#define AT91C_ISI_P_OVR_1 (0x1 << 24) // (ISI) An overrun condition has occurred in input FIFO on the preview path -#define AT91C_ISI_C_OVR (0x1 << 25) // (ISI) Fifo Codec Overflow -#define AT91C_ISI_C_OVR_0 (0x0 << 25) // (ISI) No error -#define AT91C_ISI_C_OVR_1 (0x1 << 25) // (ISI) An overrun condition has occurred in input FIFO on the codec path -#define AT91C_ISI_CRC_ERR (0x1 << 26) // (ISI) CRC synchronisation error -#define AT91C_ISI_CRC_ERR_0 (0x0 << 26) // (ISI) No error -#define AT91C_ISI_CRC_ERR_1 (0x1 << 26) // (ISI) CRC_SYNC is enabled in the control register and an error has been detected and not corrected. The frame is discarded and the ISI waits for a new one. -#define AT91C_ISI_FR_OVR (0x1 << 27) // (ISI) Frame rate overun -#define AT91C_ISI_FR_OVR_0 (0x0 << 27) // (ISI) No error -#define AT91C_ISI_FR_OVR_1 (0x1 << 27) // (ISI) Frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing FIFOs. -// -------- ISI_IER : (ISI Offset: 0x2c) ISI Interrupt Enable Register -------- -// -------- ISI_IDR : (ISI Offset: 0x30) ISI Interrupt Disable Register -------- -// -------- ISI_IMR : (ISI Offset: 0x34) ISI Interrupt Mask Register -------- -// -------- ISI_DMACHER : (ISI Offset: 0x38) DMA Channel Enable Register -------- -#define AT91C_ISI_P_CH_EN (0x1 << 0) // (ISI) Preview Channel Enable -#define AT91C_ISI_P_CH_EN_0 (0x0) // (ISI) No effect -#define AT91C_ISI_P_CH_EN_1 (0x1) // (ISI) Enable the Preview Channel -#define AT91C_ISI_C_CH_EN (0x1 << 1) // (ISI) Codec Channel Enable -#define AT91C_ISI_C_CH_EN_0 (0x0 << 1) // (ISI) No effect -#define AT91C_ISI_C_CH_EN_1 (0x1 << 1) // (ISI) Enable the Codec Channel -// -------- ISI_DMACHDR : (ISI Offset: 0x3c) DMA Channel Enable Register -------- -#define AT91C_ISI_P_CH_DIS (0x1 << 0) // (ISI) Preview Channel Disable -#define AT91C_ISI_P_CH_DIS_0 (0x0) // (ISI) No effect -#define AT91C_ISI_P_CH_DIS_1 (0x1) // (ISI) Disable the Preview Channel -#define AT91C_ISI_C_CH_DIS (0x1 << 1) // (ISI) Codec Channel Disable -#define AT91C_ISI_C_CH_DIS_0 (0x0 << 1) // (ISI) No effect -#define AT91C_ISI_C_CH_DIS_1 (0x1 << 1) // (ISI) Disable the Codec Channel -// -------- ISI_DMACHSR : (ISI Offset: 0x40) DMA Channel Status Register -------- -#define AT91C_ISI_P_CH_S (0x1 << 0) // (ISI) Preview Channel Disable -#define AT91C_ISI_P_CH_S_0 (0x0) // (ISI) Preview Channel is disabled -#define AT91C_ISI_P_CH_S_1 (0x1) // (ISI) Preview Channel is enabled -#define AT91C_ISI_C_CH_S (0x1 << 1) // (ISI) Codec Channel Disable -#define AT91C_ISI_C_CH_S_0 (0x0 << 1) // (ISI) Codec Channel is disabled -#define AT91C_ISI_C_CH_S_1 (0x1 << 1) // (ISI) Codec Channel is enabled -// -------- ISI_DMAPCTRL : (ISI Offset: 0x48) DMA Preview Control Register -------- -#define AT91C_ISI_P_FETCH (0x1 << 0) // (ISI) Preview Descriptor Fetch Control Field -#define AT91C_ISI_P_FETCH_DISABLE (0x0) // (ISI) Preview Channel Fetch Operation is disabled -#define AT91C_ISI_P_FETCH_ENABLE (0x1) // (ISI) Preview Channel Fetch Operation is enabled -#define AT91C_ISI_P_DONE (0x1 << 1) // (ISI) Preview Transfer Done Flag -#define AT91C_ISI_P_DONE_0 (0x0 << 1) // (ISI) Preview Transfer has not been performed -#define AT91C_ISI_P_DONE_1 (0x1 << 1) // (ISI) Preview Transfer has completed -// -------- ISI_DMACCTRL : (ISI Offset: 0x54) DMA Codec Control Register -------- -#define AT91C_ISI_C_FETCH (0x1 << 0) // (ISI) Codec Descriptor Fetch Control Field -#define AT91C_ISI_C_FETCH_DISABLE (0x0) // (ISI) Codec Channel Fetch Operation is disabled -#define AT91C_ISI_C_FETCH_ENABLE (0x1) // (ISI) Codec Channel Fetch Operation is enabled -#define AT91C_ISI_C_DONE (0x1 << 1) // (ISI) Codec Transfer Done Flag -#define AT91C_ISI_C_DONE_0 (0x0 << 1) // (ISI) Codec Transfer has not been performed -#define AT91C_ISI_C_DONE_1 (0x1 << 1) // (ISI) Codec Transfer has completed -// -------- ISI_WPCR : (ISI Offset: 0xe4) Write Protection Control Register -------- -#define AT91C_ISI_WP_EN (0x1 << 0) // (ISI) Write Protection Enable -#define AT91C_ISI_WP_EN_DISABLE (0x0) // (ISI) Write Operation is disabled (if WP_KEY corresponds) -#define AT91C_ISI_WP_EN_ENABLE (0x1) // (ISI) Write Operation is enabled (if WP_KEY corresponds) -#define AT91C_ISI_WP_KEY (0xFFFFFF << 8) // (ISI) Write Protection Key -// -------- ISI_WPSR : (ISI Offset: 0xe8) Write Protection Status Register -------- -#define AT91C_ISI_WP_VS (0xF << 0) // (ISI) Write Protection Violation Status -#define AT91C_ISI_WP_VS_NO_VIOLATION (0x0) // (ISI) No Write Protection Violation detected since last read -#define AT91C_ISI_WP_VS_ON_WRITE (0x1) // (ISI) Write Protection Violation detected since last read -#define AT91C_ISI_WP_VS_ON_RESET (0x2) // (ISI) Software Reset Violation detected since last read -#define AT91C_ISI_WP_VS_ON_BOTH (0x3) // (ISI) Write Protection and Software Reset Violation detected since last read -#define AT91C_ISI_WP_VSRC (0xF << 8) // (ISI) Write Protection Violation Source -#define AT91C_ISI_WP_VSRC_NO_VIOLATION (0x0 << 8) // (ISI) No Write Protection Violation detected since last read -#define AT91C_ISI_WP_VSRC_ISI_CFG1 (0x1 << 8) // (ISI) Write Protection Violation detected on ISI_CFG1 since last read -#define AT91C_ISI_WP_VSRC_ISI_CFG2 (0x2 << 8) // (ISI) Write Protection Violation detected on ISI_CFG2 since last read -#define AT91C_ISI_WP_VSRC_ISI_PSIZE (0x3 << 8) // (ISI) Write Protection Violation detected on ISI_PSIZE since last read -#define AT91C_ISI_WP_VSRC_ISI_PDECF (0x4 << 8) // (ISI) Write Protection Violation detected on ISI_PDECF since last read -#define AT91C_ISI_WP_VSRC_ISI_Y2RSET0 (0x5 << 8) // (ISI) Write Protection Violation detected on ISI_Y2RSET0 since last read -#define AT91C_ISI_WP_VSRC_ISI_Y2RSET1 (0x6 << 8) // (ISI) Write Protection Violation detected on ISI_Y2RSET1 since last read -#define AT91C_ISI_WP_VSRC_ISI_R2YSET0 (0x7 << 8) // (ISI) Write Protection Violation detected on ISI_R2YSET0 since last read -#define AT91C_ISI_WP_VSRC_ISI_R2YSET1 (0x8 << 8) // (ISI) Write Protection Violation detected on ISI_R2YSET1 since last read -#define AT91C_ISI_WP_VSRC_ISI_R2YSET2 (0x9 << 8) // (ISI) Write Protection Violation detected on ISI_R2YSET2 since last read - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Host Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UHPHS_OHCI { - AT91C_REG UHPHS_OHCI_HcRevision; // Revision - AT91C_REG UHPHS_OHCI_HcControl; // Operating modes for the Host Controller - AT91C_REG UHPHS_OHCI_HcCommandStatus; // Command & status Register - AT91C_REG UHPHS_OHCI_HcInterruptStatus; // Interrupt Status Register - AT91C_REG UHPHS_OHCI_HcInterruptEnable; // Interrupt Enable Register - AT91C_REG UHPHS_OHCI_HcInterruptDisable; // Interrupt Disable Register - AT91C_REG UHPHS_OHCI_HcHCCA; // Pointer to the Host Controller Communication Area - AT91C_REG UHPHS_OHCI_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor - AT91C_REG UHPHS_OHCI_HcControlHeadED; // First Endpoint Descriptor of the Control list - AT91C_REG UHPHS_OHCI_HcControlCurrentED; // Endpoint Control and Status Register - AT91C_REG UHPHS_OHCI_HcBulkHeadED; // First endpoint register of the Bulk list - AT91C_REG UHPHS_OHCI_HcBulkCurrentED; // Current endpoint of the Bulk list - AT91C_REG UHPHS_OHCI_HcBulkDoneHead; // Last completed transfer descriptor - AT91C_REG UHPHS_OHCI_HcFmInterval; // Bit time between 2 consecutive SOFs - AT91C_REG UHPHS_OHCI_HcFmRemaining; // Bit time remaining in the current Frame - AT91C_REG UHPHS_OHCI_HcFmNumber; // Frame number - AT91C_REG UHPHS_OHCI_HcPeriodicStart; // Periodic Start - AT91C_REG UHPHS_OHCI_HcLSThreshold; // LS Threshold - AT91C_REG UHPHS_OHCI_HcRhDescriptorA; // Root Hub characteristics A - AT91C_REG UHPHS_OHCI_HcRhDescriptorB; // Root Hub characteristics B - AT91C_REG UHPHS_OHCI_HcRhStatus; // Root Hub Status register - AT91C_REG UHPHS_OHCI_HcRhPortStatus[2]; // Root Hub Port Status Register -} AT91S_UHPHS_OHCI, *AT91PS_UHPHS_OHCI; -#else -#define HcRevision (AT91C_CAST(AT91C_REG *) 0x00000000) // (HcRevision) Revision -#define HcControl (AT91C_CAST(AT91C_REG *) 0x00000004) // (HcControl) Operating modes for the Host Controller -#define HcCommandStatus (AT91C_CAST(AT91C_REG *) 0x00000008) // (HcCommandStatus) Command & status Register -#define HcInterruptStatus (AT91C_CAST(AT91C_REG *) 0x0000000C) // (HcInterruptStatus) Interrupt Status Register -#define HcInterruptEnable (AT91C_CAST(AT91C_REG *) 0x00000010) // (HcInterruptEnable) Interrupt Enable Register -#define HcInterruptDisable (AT91C_CAST(AT91C_REG *) 0x00000014) // (HcInterruptDisable) Interrupt Disable Register -#define HcHCCA (AT91C_CAST(AT91C_REG *) 0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area -#define HcPeriodCurrentED (AT91C_CAST(AT91C_REG *) 0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor -#define HcControlHeadED (AT91C_CAST(AT91C_REG *) 0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list -#define HcControlCurrentED (AT91C_CAST(AT91C_REG *) 0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register -#define HcBulkHeadED (AT91C_CAST(AT91C_REG *) 0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list -#define HcBulkCurrentED (AT91C_CAST(AT91C_REG *) 0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list -#define HcBulkDoneHead (AT91C_CAST(AT91C_REG *) 0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor -#define HcFmInterval (AT91C_CAST(AT91C_REG *) 0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs -#define HcFmRemaining (AT91C_CAST(AT91C_REG *) 0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame -#define HcFmNumber (AT91C_CAST(AT91C_REG *) 0x0000003C) // (HcFmNumber) Frame number -#define HcPeriodicStart (AT91C_CAST(AT91C_REG *) 0x00000040) // (HcPeriodicStart) Periodic Start -#define HcLSThreshold (AT91C_CAST(AT91C_REG *) 0x00000044) // (HcLSThreshold) LS Threshold -#define HcRhDescriptorA (AT91C_CAST(AT91C_REG *) 0x00000048) // (HcRhDescriptorA) Root Hub characteristics A -#define HcRhDescriptorB (AT91C_CAST(AT91C_REG *) 0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B -#define HcRhStatus (AT91C_CAST(AT91C_REG *) 0x00000050) // (HcRhStatus) Root Hub Status register -#define HcRhPortStatus (AT91C_CAST(AT91C_REG *) 0x00000054) // (HcRhPortStatus) Root Hub Port Status Register - -#endif - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Host Interface -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_UHPHS_EHCI { - AT91C_REG UHPHS_EHCI_VERSION; // - AT91C_REG UHPHS_EHCI_HCSPARAMS; // - AT91C_REG UHPHS_EHCI_HCCPARAMS; // - AT91C_REG UHPHS_EHCI_HCSPPORTROUTE; // - AT91C_REG UHPHS_EHCI_USBCMD; // - AT91C_REG UHPHS_EHCI_USBSTS; // - AT91C_REG UHPHS_EHCI_USBINTR; // - AT91C_REG UHPHS_EHCI_FRINDEX; // - AT91C_REG UHPHS_EHCI_CTRLDSSEGMENT; // - AT91C_REG UHPHS_EHCI_PERIODICLISTBASE; // - AT91C_REG UHPHS_EHCI_ASYNCLISTADDR; // - AT91C_REG Reserved0[9]; // - AT91C_REG UHPHS_EHCI_CONFIGFLAG; // - AT91C_REG UHPHS_EHCI_PORTSC[2]; // - AT91C_REG Reserved1[13]; // - AT91C_REG UHPHS_EHCI_INSNREG00; // - AT91C_REG UHPHS_EHCI_INSNREG01; // - AT91C_REG UHPHS_EHCI_INSNREG02; // - AT91C_REG UHPHS_EHCI_INSNREG03; // - AT91C_REG UHPHS_EHCI_INSNREG04; // - AT91C_REG UHPHS_EHCI_INSNREG05; // -} AT91S_UHPHS_EHCI, *AT91PS_UHPHS_EHCI; -#else -#define VERSION (AT91C_CAST(AT91C_REG *) 0x00000000) // (VERSION) -#define HCSPARAMS (AT91C_CAST(AT91C_REG *) 0x00000004) // (HCSPARAMS) -#define HCCPARAMS (AT91C_CAST(AT91C_REG *) 0x00000008) // (HCCPARAMS) -#define HCSPPORTROUTE (AT91C_CAST(AT91C_REG *) 0x0000000C) // (HCSPPORTROUTE) -#define USBCMD (AT91C_CAST(AT91C_REG *) 0x00000010) // (USBCMD) -#define USBSTS (AT91C_CAST(AT91C_REG *) 0x00000014) // (USBSTS) -#define USBINTR (AT91C_CAST(AT91C_REG *) 0x00000018) // (USBINTR) -#define FRINDEX (AT91C_CAST(AT91C_REG *) 0x0000001C) // (FRINDEX) -#define CTRLDSSEGMENT (AT91C_CAST(AT91C_REG *) 0x00000020) // (CTRLDSSEGMENT) -#define PERIODICLISTBASE (AT91C_CAST(AT91C_REG *) 0x00000024) // (PERIODICLISTBASE) -#define ASYNCLISTADDR (AT91C_CAST(AT91C_REG *) 0x00000028) // (ASYNCLISTADDR) -#define CONFIGFLAG (AT91C_CAST(AT91C_REG *) 0x00000050) // (CONFIGFLAG) -#define PORTSC (AT91C_CAST(AT91C_REG *) 0x00000054) // (PORTSC) -#define INSNREG00 (AT91C_CAST(AT91C_REG *) 0x00000090) // (INSNREG00) -#define INSNREG01 (AT91C_CAST(AT91C_REG *) 0x00000094) // (INSNREG01) -#define INSNREG02 (AT91C_CAST(AT91C_REG *) 0x00000098) // (INSNREG02) -#define INSNREG03 (AT91C_CAST(AT91C_REG *) 0x0000009C) // (INSNREG03) -#define INSNREG04 (AT91C_CAST(AT91C_REG *) 0x000000A0) // (INSNREG04) -#define INSNREG05 (AT91C_CAST(AT91C_REG *) 0x000000A4) // (INSNREG05) - -#endif -// -------- VERSION : (UHPHS_EHCI Offset: 0x0) -------- -#define AT91C_UHPHS_CAPLENGTH (0xFF << 0) // (UHPHS_EHCI) CapLength : Offset for control registers -#define AT91C_UHPHS_HCIVERSION (0xFF << 16) // (UHPHS_EHCI) Hci Version - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR True Random Generator -// ***************************************************************************** -#ifndef __ASSEMBLY__ -typedef struct _AT91S_TRNG { - AT91C_REG TRNG_CR; // Control Register - AT91C_REG Reserved0[3]; // - AT91C_REG TRNG_IER; // Interrupt Enable Register - AT91C_REG TRNG_IDR; // Interrupt Disable Register - AT91C_REG TRNG_IMR; // Interrupt Mask Register - AT91C_REG TRNG_ISR; // Interrupt Status Register - AT91C_REG Reserved1[12]; // - AT91C_REG TRNG_ODATA; // Output Data Register - AT91C_REG Reserved2[42]; // - AT91C_REG TRNG_VERSION; // TRNG Version Register -} AT91S_TRNG, *AT91PS_TRNG; -#else -#define TRNG_CR (AT91C_CAST(AT91C_REG *) 0x00000000) // (TRNG_CR) Control Register -#define TRNG_IER (AT91C_CAST(AT91C_REG *) 0x00000010) // (TRNG_IER) Interrupt Enable Register -#define TRNG_IDR (AT91C_CAST(AT91C_REG *) 0x00000014) // (TRNG_IDR) Interrupt Disable Register -#define TRNG_IMR (AT91C_CAST(AT91C_REG *) 0x00000018) // (TRNG_IMR) Interrupt Mask Register -#define TRNG_ISR (AT91C_CAST(AT91C_REG *) 0x0000001C) // (TRNG_ISR) Interrupt Status Register -#define TRNG_ODATA (AT91C_CAST(AT91C_REG *) 0x00000050) // (TRNG_ODATA) Output Data Register -#define TRNG_VERSION (AT91C_CAST(AT91C_REG *) 0x000000FC) // (TRNG_VERSION) TRNG Version Register - -#endif -// -------- TRNG_CR : (TRNG Offset: 0x0) Control Register -------- -#define AT91C_TRNG_ENABLE (0x1 << 0) // (TRNG) Enable TRNG -// -------- TRNG_IER : (TRNG Offset: 0x10) Interrupt Enable Register -------- -#define AT91C_TRNG_DATRDY (0x1 << 0) // (TRNG) DATRDY -// -------- TRNG_IDR : (TRNG Offset: 0x14) Interrupt Disable Register -------- -// -------- TRNG_IMR : (TRNG Offset: 0x18) Interrupt Mask Register -------- -// -------- TRNG_ISR : (TRNG Offset: 0x1c) Interrupt Status Register -------- - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM9G45 -// ***************************************************************************** -// ========== Register definition for SFR peripheral ========== -#define AT91C_SFR_INT (AT91C_CAST(AT91C_REG *) 0xFFF74014) // (SFR) OHCI suspend Interrupt status -#define AT91C_SFR_DDRCFG (AT91C_CAST(AT91C_REG *) 0xFFF74004) // (SFR) DDR2 SSTL18 control -#define AT91C_SFR_UTMICFG (AT91C_CAST(AT91C_REG *) 0xFFF74010) // (SFR) UTMI Software Reset, and OHCI suspend interrupt control -#define AT91C_SFR_EBIDELAY (AT91C_CAST(AT91C_REG *) 0xFFF7400C) // (SFR) EBI DDR controller clock delay -#define AT91C_SFR_DDRDELAY (AT91C_CAST(AT91C_REG *) 0xFFF74008) // (SFR) DDR2 controller clock delay -#define AT91C_SFR_EMA (AT91C_CAST(AT91C_REG *) 0xFFF74000) // (SFR) memory Extra Margin Adjustment control -// ========== Register definition for SYS peripheral ========== -#define AT91C_SYS_SLCKSEL (AT91C_CAST(AT91C_REG *) 0xFFFFFD50) // (SYS) Slow Clock Selection Register -#define AT91C_SYS_GPBR (AT91C_CAST(AT91C_REG *) 0xFFFFFD60) // (SYS) General Purpose Register -// ========== Register definition for EBI peripheral ========== -#define AT91C_EBI_DUMMY (AT91C_CAST(AT91C_REG *) 0xFFFFE200) // (EBI) Dummy register - Do not use -// ========== Register definition for DDR2CP1 peripheral ========== -#define AT91C_DDR2CP1_DELAY2 (AT91C_CAST(AT91C_REG *) 0xFFFFE434) // (DDR2CP1) Pad delay2 Register -#define AT91C_DDR2CP1_T3PR (AT91C_CAST(AT91C_REG *) 0xFFFFE418) // (DDR2CP1) Timing3 Register -#define AT91C_DDR2CP1_RTR (AT91C_CAST(AT91C_REG *) 0xFFFFE404) // (DDR2CP1) Refresh Timer Register -#define AT91C_DDR2CP1_T0PR (AT91C_CAST(AT91C_REG *) 0xFFFFE40C) // (DDR2CP1) Timing0 Register -#define AT91C_DDR2CP1_WPSR (AT91C_CAST(AT91C_REG *) 0xFFFFE4E8) // (DDR2CP1) High Speed Register -#define AT91C_DDR2CP1_DELAY8 (AT91C_CAST(AT91C_REG *) 0xFFFFE44C) // (DDR2CP1) Pad delay8 Register -#define AT91C_DDR2CP1_LPR (AT91C_CAST(AT91C_REG *) 0xFFFFE41C) // (DDR2CP1) Low-power Register -#define AT91C_DDR2CP1_VER (AT91C_CAST(AT91C_REG *) 0xFFFFE428) // (DDR2CP1) DLL Version Register -#define AT91C_DDR2CP1_DELAY7 (AT91C_CAST(AT91C_REG *) 0xFFFFE448) // (DDR2CP1) Pad delay7 Register -#define AT91C_DDR2CP1_CR (AT91C_CAST(AT91C_REG *) 0xFFFFE408) // (DDR2CP1) Configuration Register -#define AT91C_DDR2CP1_WPCR (AT91C_CAST(AT91C_REG *) 0xFFFFE4E4) // (DDR2CP1) High Speed Register -#define AT91C_DDR2CP1_MR (AT91C_CAST(AT91C_REG *) 0xFFFFE400) // (DDR2CP1) Mode Register -#define AT91C_DDR2CP1_DELAY5 (AT91C_CAST(AT91C_REG *) 0xFFFFE440) // (DDR2CP1) Pad delay5 Register -#define AT91C_DDR2CP1_T2PR (AT91C_CAST(AT91C_REG *) 0xFFFFE414) // (DDR2CP1) Timing2 Register -#define AT91C_DDR2CP1_HS (AT91C_CAST(AT91C_REG *) 0xFFFFE42C) // (DDR2CP1) High Speed Register -#define AT91C_DDR2CP1_MDR (AT91C_CAST(AT91C_REG *) 0xFFFFE420) // (DDR2CP1) Memory Device Register -#define AT91C_DDR2CP1_DELAY4 (AT91C_CAST(AT91C_REG *) 0xFFFFE43C) // (DDR2CP1) Pad delay4 Register -#define AT91C_DDR2CP1_DELAY1 (AT91C_CAST(AT91C_REG *) 0xFFFFE430) // (DDR2CP1) Pad delay1 Register -#define AT91C_DDR2CP1_DELAY6 (AT91C_CAST(AT91C_REG *) 0xFFFFE444) // (DDR2CP1) Pad delay6 Register -#define AT91C_DDR2CP1_DLL (AT91C_CAST(AT91C_REG *) 0xFFFFE424) // (DDR2CP1) DLL Information Register -#define AT91C_DDR2CP1_DELAY3 (AT91C_CAST(AT91C_REG *) 0xFFFFE438) // (DDR2CP1) Pad delay3 Register -#define AT91C_DDR2CP1_VERSION (AT91C_CAST(AT91C_REG *) 0xFFFFE4FC) // (DDR2CP1) Version Register -#define AT91C_DDR2CP1_T1PR (AT91C_CAST(AT91C_REG *) 0xFFFFE410) // (DDR2CP1) Timing1 Register -// ========== Register definition for DDR2C peripheral ========== -#define AT91C_DDR2C_DELAY8 (AT91C_CAST(AT91C_REG *) 0xFFFFE64C) // (DDR2C) Pad delay8 Register -#define AT91C_DDR2C_VER (AT91C_CAST(AT91C_REG *) 0xFFFFE628) // (DDR2C) DLL Version Register -#define AT91C_DDR2C_RTR (AT91C_CAST(AT91C_REG *) 0xFFFFE604) // (DDR2C) Refresh Timer Register -#define AT91C_DDR2C_T0PR (AT91C_CAST(AT91C_REG *) 0xFFFFE60C) // (DDR2C) Timing0 Register -#define AT91C_DDR2C_DELAY5 (AT91C_CAST(AT91C_REG *) 0xFFFFE640) // (DDR2C) Pad delay5 Register -#define AT91C_DDR2C_LPR (AT91C_CAST(AT91C_REG *) 0xFFFFE61C) // (DDR2C) Low-power Register -#define AT91C_DDR2C_HS (AT91C_CAST(AT91C_REG *) 0xFFFFE62C) // (DDR2C) High Speed Register -#define AT91C_DDR2C_DELAY2 (AT91C_CAST(AT91C_REG *) 0xFFFFE634) // (DDR2C) Pad delay2 Register -#define AT91C_DDR2C_T2PR (AT91C_CAST(AT91C_REG *) 0xFFFFE614) // (DDR2C) Timing2 Register -#define AT91C_DDR2C_DELAY1 (AT91C_CAST(AT91C_REG *) 0xFFFFE630) // (DDR2C) Pad delay1 Register -#define AT91C_DDR2C_T1PR (AT91C_CAST(AT91C_REG *) 0xFFFFE610) // (DDR2C) Timing1 Register -#define AT91C_DDR2C_MDR (AT91C_CAST(AT91C_REG *) 0xFFFFE620) // (DDR2C) Memory Device Register -#define AT91C_DDR2C_DELAY6 (AT91C_CAST(AT91C_REG *) 0xFFFFE644) // (DDR2C) Pad delay6 Register -#define AT91C_DDR2C_VERSION (AT91C_CAST(AT91C_REG *) 0xFFFFE6FC) // (DDR2C) Version Register -#define AT91C_DDR2C_MR (AT91C_CAST(AT91C_REG *) 0xFFFFE600) // (DDR2C) Mode Register -#define AT91C_DDR2C_DLL (AT91C_CAST(AT91C_REG *) 0xFFFFE624) // (DDR2C) DLL Information Register -#define AT91C_DDR2C_DELAY4 (AT91C_CAST(AT91C_REG *) 0xFFFFE63C) // (DDR2C) Pad delay4 Register -#define AT91C_DDR2C_WPCR (AT91C_CAST(AT91C_REG *) 0xFFFFE6E4) // (DDR2C) High Speed Register -#define AT91C_DDR2C_CR (AT91C_CAST(AT91C_REG *) 0xFFFFE608) // (DDR2C) Configuration Register -#define AT91C_DDR2C_DELAY3 (AT91C_CAST(AT91C_REG *) 0xFFFFE638) // (DDR2C) Pad delay3 Register -#define AT91C_DDR2C_WPSR (AT91C_CAST(AT91C_REG *) 0xFFFFE6E8) // (DDR2C) High Speed Register -#define AT91C_DDR2C_DELAY7 (AT91C_CAST(AT91C_REG *) 0xFFFFE648) // (DDR2C) Pad delay7 Register -#define AT91C_DDR2C_T3PR (AT91C_CAST(AT91C_REG *) 0xFFFFE618) // (DDR2C) Timing3 Register -// ========== Register definition for SMC peripheral ========== -#define AT91C_SMC_PULSE7 (AT91C_CAST(AT91C_REG *) 0xFFFFE874) // (SMC) Pulse Register for CS 7 -#define AT91C_SMC_DELAY1 (AT91C_CAST(AT91C_REG *) 0xFFFFE8C0) // (SMC) SMC Delay Control Register -#define AT91C_SMC_CYCLE2 (AT91C_CAST(AT91C_REG *) 0xFFFFE828) // (SMC) Cycle Register for CS 2 -#define AT91C_SMC_DELAY5 (AT91C_CAST(AT91C_REG *) 0xFFFFE8D0) // (SMC) SMC Delay Control Register -#define AT91C_SMC_DELAY6 (AT91C_CAST(AT91C_REG *) 0xFFFFE8D4) // (SMC) SMC Delay Control Register -#define AT91C_SMC_PULSE2 (AT91C_CAST(AT91C_REG *) 0xFFFFE824) // (SMC) Pulse Register for CS 2 -#define AT91C_SMC_SETUP6 (AT91C_CAST(AT91C_REG *) 0xFFFFE860) // (SMC) Setup Register for CS 6 -#define AT91C_SMC_SETUP5 (AT91C_CAST(AT91C_REG *) 0xFFFFE850) // (SMC) Setup Register for CS 5 -#define AT91C_SMC_CYCLE6 (AT91C_CAST(AT91C_REG *) 0xFFFFE868) // (SMC) Cycle Register for CS 6 -#define AT91C_SMC_PULSE6 (AT91C_CAST(AT91C_REG *) 0xFFFFE864) // (SMC) Pulse Register for CS 6 -#define AT91C_SMC_CTRL5 (AT91C_CAST(AT91C_REG *) 0xFFFFE85C) // (SMC) Control Register for CS 5 -#define AT91C_SMC_CTRL3 (AT91C_CAST(AT91C_REG *) 0xFFFFE83C) // (SMC) Control Register for CS 3 -#define AT91C_SMC_DELAY7 (AT91C_CAST(AT91C_REG *) 0xFFFFE8D8) // (SMC) SMC Delay Control Register -#define AT91C_SMC_DELAY3 (AT91C_CAST(AT91C_REG *) 0xFFFFE8C8) // (SMC) SMC Delay Control Register -#define AT91C_SMC_CYCLE0 (AT91C_CAST(AT91C_REG *) 0xFFFFE808) // (SMC) Cycle Register for CS 0 -#define AT91C_SMC_SETUP1 (AT91C_CAST(AT91C_REG *) 0xFFFFE810) // (SMC) Setup Register for CS 1 -#define AT91C_SMC_PULSE5 (AT91C_CAST(AT91C_REG *) 0xFFFFE854) // (SMC) Pulse Register for CS 5 -#define AT91C_SMC_SETUP7 (AT91C_CAST(AT91C_REG *) 0xFFFFE870) // (SMC) Setup Register for CS 7 -#define AT91C_SMC_CTRL4 (AT91C_CAST(AT91C_REG *) 0xFFFFE84C) // (SMC) Control Register for CS 4 -#define AT91C_SMC_DELAY2 (AT91C_CAST(AT91C_REG *) 0xFFFFE8C4) // (SMC) SMC Delay Control Register -#define AT91C_SMC_PULSE3 (AT91C_CAST(AT91C_REG *) 0xFFFFE834) // (SMC) Pulse Register for CS 3 -#define AT91C_SMC_CYCLE4 (AT91C_CAST(AT91C_REG *) 0xFFFFE848) // (SMC) Cycle Register for CS 4 -#define AT91C_SMC_CTRL1 (AT91C_CAST(AT91C_REG *) 0xFFFFE81C) // (SMC) Control Register for CS 1 -#define AT91C_SMC_SETUP3 (AT91C_CAST(AT91C_REG *) 0xFFFFE830) // (SMC) Setup Register for CS 3 -#define AT91C_SMC_CTRL0 (AT91C_CAST(AT91C_REG *) 0xFFFFE80C) // (SMC) Control Register for CS 0 -#define AT91C_SMC_CYCLE7 (AT91C_CAST(AT91C_REG *) 0xFFFFE878) // (SMC) Cycle Register for CS 7 -#define AT91C_SMC_DELAY4 (AT91C_CAST(AT91C_REG *) 0xFFFFE8CC) // (SMC) SMC Delay Control Register -#define AT91C_SMC_CYCLE1 (AT91C_CAST(AT91C_REG *) 0xFFFFE818) // (SMC) Cycle Register for CS 1 -#define AT91C_SMC_SETUP2 (AT91C_CAST(AT91C_REG *) 0xFFFFE820) // (SMC) Setup Register for CS 2 -#define AT91C_SMC_PULSE1 (AT91C_CAST(AT91C_REG *) 0xFFFFE814) // (SMC) Pulse Register for CS 1 -#define AT91C_SMC_DELAY8 (AT91C_CAST(AT91C_REG *) 0xFFFFE8DC) // (SMC) SMC Delay Control Register -#define AT91C_SMC_CTRL2 (AT91C_CAST(AT91C_REG *) 0xFFFFE82C) // (SMC) Control Register for CS 2 -#define AT91C_SMC_PULSE4 (AT91C_CAST(AT91C_REG *) 0xFFFFE844) // (SMC) Pulse Register for CS 4 -#define AT91C_SMC_SETUP4 (AT91C_CAST(AT91C_REG *) 0xFFFFE840) // (SMC) Setup Register for CS 4 -#define AT91C_SMC_CYCLE3 (AT91C_CAST(AT91C_REG *) 0xFFFFE838) // (SMC) Cycle Register for CS 3 -#define AT91C_SMC_SETUP0 (AT91C_CAST(AT91C_REG *) 0xFFFFE800) // (SMC) Setup Register for CS 0 -#define AT91C_SMC_CYCLE5 (AT91C_CAST(AT91C_REG *) 0xFFFFE858) // (SMC) Cycle Register for CS 5 -#define AT91C_SMC_PULSE0 (AT91C_CAST(AT91C_REG *) 0xFFFFE804) // (SMC) Pulse Register for CS 0 -#define AT91C_SMC_CTRL6 (AT91C_CAST(AT91C_REG *) 0xFFFFE86C) // (SMC) Control Register for CS 6 -#define AT91C_SMC_CTRL7 (AT91C_CAST(AT91C_REG *) 0xFFFFE87C) // (SMC) Control Register for CS 7 -// ========== Register definition for MATRIX peripheral ========== -#define AT91C_MATRIX_SCFG1 (AT91C_CAST(AT91C_REG *) 0xFFFFEA44) // (MATRIX) Slave Configuration Register 1 : SRAM S1 -#define AT91C_MATRIX_MRCR (AT91C_CAST(AT91C_REG *) 0xFFFFEB00) // (MATRIX) Master Remap Control Register -#define AT91C_MATRIX_PRAS2 (AT91C_CAST(AT91C_REG *) 0xFFFFEA90) // (MATRIX) PRAS2 : SRAM S2 -#define AT91C_MATRIX_PRAS1 (AT91C_CAST(AT91C_REG *) 0xFFFFEA88) // (MATRIX) PRAS1 : SRAM S1 -#define AT91C_MATRIX_PRAS0 (AT91C_CAST(AT91C_REG *) 0xFFFFEA80) // (MATRIX) PRAS0 : SRAM S0 -#define AT91C_MATRIX_MCFG8 (AT91C_CAST(AT91C_REG *) 0xFFFFEA20) // (MATRIX) Master Configuration Register 8 : eMAC -#define AT91C_MATRIX_MCFG2 (AT91C_CAST(AT91C_REG *) 0xFFFFEA08) // (MATRIX) Master Configuration Register 2 : pdc -#define AT91C_MATRIX_EBICSA (AT91C_CAST(AT91C_REG *) 0xFFFFEB28) // (MATRIX) EBI Chip Select Assignment Register -#define AT91C_MATRIX_PRAS4 (AT91C_CAST(AT91C_REG *) 0xFFFFEAA0) // (MATRIX) PRAS4 : ROM + USB Dev + USB EHCI + USB OHCI + LCD + Video Decoder -#define AT91C_MATRIX_MCFG3 (AT91C_CAST(AT91C_REG *) 0xFFFFEA0C) // (MATRIX) Master Configuration Register 3 : USB Host OHCI -#define AT91C_MATRIX_SCFG0 (AT91C_CAST(AT91C_REG *) 0xFFFFEA40) // (MATRIX) Slave Configuration Register 0 : SRAM S0 -#define AT91C_MATRIX_MCFG7 (AT91C_CAST(AT91C_REG *) 0xFFFFEA1C) // (MATRIX) Master Configuration Register 7 : lcdc -#define AT91C_MATRIX_PRAS6 (AT91C_CAST(AT91C_REG *) 0xFFFFEAB0) // (MATRIX) PRAS6 : DDR2 S1 -#define AT91C_MATRIX_SCFG7 (AT91C_CAST(AT91C_REG *) 0xFFFFEA5C) // (MATRIX) Slave Configuration Register 7 : DDR2 S2 -#define AT91C_MATRIX_PRAS7 (AT91C_CAST(AT91C_REG *) 0xFFFFEAB8) // (MATRIX) PRAS7 : DDR2 S2 -#define AT91C_MATRIX_SCFG2 (AT91C_CAST(AT91C_REG *) 0xFFFFEA48) // (MATRIX) Slave Configuration Register 2 : SRAM S2 -#define AT91C_MATRIX_WRPROTST (AT91C_CAST(AT91C_REG *) 0xFFFFEBE8) // (MATRIX) Write Protection Status Register -#define AT91C_MATRIX_PRBS0 (AT91C_CAST(AT91C_REG *) 0xFFFFEA84) // (MATRIX) PRBS0 : SRAM S0 -#define AT91C_MATRIX_PRBS2 (AT91C_CAST(AT91C_REG *) 0xFFFFEA94) // (MATRIX) PRBS2 : SRAM S2 -#define AT91C_MATRIX_MCFG4 (AT91C_CAST(AT91C_REG *) 0xFFFFEA10) // (MATRIX) Master Configuration Register 4 : DMA0 -#define AT91C_MATRIX_SCFG5 (AT91C_CAST(AT91C_REG *) 0xFFFFEA54) // (MATRIX) Slave Configuration Register 5 : DDR2 S0 -#define AT91C_MATRIX_PRBS6 (AT91C_CAST(AT91C_REG *) 0xFFFFEAB4) // (MATRIX) PRBS6 : DDR2 S1 -#define AT91C_MATRIX_MCFG1 (AT91C_CAST(AT91C_REG *) 0xFFFFEA04) // (MATRIX) Master Configuration Register 1 ; ARM-D -#define AT91C_MATRIX_SCFG6 (AT91C_CAST(AT91C_REG *) 0xFFFFEA58) // (MATRIX) Slave Configuration Register 6 : DDR2 S1 -#define AT91C_MATRIX_SCFG4 (AT91C_CAST(AT91C_REG *) 0xFFFFEA50) // (MATRIX) Slave Configuration Register 4 ; ROM + USB Dev + USB EHCI + USB OHCI + LCD + Video Decoder -#define AT91C_MATRIX_PRBS1 (AT91C_CAST(AT91C_REG *) 0xFFFFEA8C) // (MATRIX) PRBS1 : SRAM S1 -#define AT91C_MATRIX_PRBS3 (AT91C_CAST(AT91C_REG *) 0xFFFFEA9C) // (MATRIX) PRBS3 : SRAM S3 -#define AT91C_MATRIX_WRPROTEN (AT91C_CAST(AT91C_REG *) 0xFFFFEBE4) // (MATRIX) Write Protection Control Register -#define AT91C_MATRIX_TCMR (AT91C_CAST(AT91C_REG *) 0xFFFFEB10) // (MATRIX) Bus Matrix TCM Configuration Register -#define AT91C_MATRIX_MCFG0 (AT91C_CAST(AT91C_REG *) 0xFFFFEA00) // (MATRIX) Master Configuration Register 0 : ARM-I -#define AT91C_MATRIX_PRAS5 (AT91C_CAST(AT91C_REG *) 0xFFFFEAA8) // (MATRIX) PRAS5 : DDR2 S0 -#define AT91C_MATRIX_DDRMPR (AT91C_CAST(AT91C_REG *) 0xFFFFEB18) // (MATRIX) DDR Multi-Port Register -#define AT91C_MATRIX_PRBS4 (AT91C_CAST(AT91C_REG *) 0xFFFFEAA4) // (MATRIX) PRBS4 : ROM + USB Dev + USB EHCI + USB OHCI + LCD + Video Decoder -#define AT91C_MATRIX_MCFG6 (AT91C_CAST(AT91C_REG *) 0xFFFFEA18) // (MATRIX) Master Configuration Register 6 : hisi -#define AT91C_MATRIX_PRBS5 (AT91C_CAST(AT91C_REG *) 0xFFFFEAAC) // (MATRIX) PRBS5 : DDR2 S0 -#define AT91C_MATRIX_MCFG9 (AT91C_CAST(AT91C_REG *) 0xFFFFEA24) // (MATRIX) Master Configuration Register 9 : USB Device -#define AT91C_MATRIX_MCFG5 (AT91C_CAST(AT91C_REG *) 0xFFFFEA14) // (MATRIX) Master Configuration Register 5 : DMA1 -#define AT91C_MATRIX_PRBS7 (AT91C_CAST(AT91C_REG *) 0xFFFFEABC) // (MATRIX) PRBS7 : DDR2 S2 -#define AT91C_MATRIX_MCFG10 (AT91C_CAST(AT91C_REG *) 0xFFFFEA28) // (MATRIX) Master Configuration Register 10 : USB Host EHCI -#define AT91C_MATRIX_PRAS3 (AT91C_CAST(AT91C_REG *) 0xFFFFEA98) // (MATRIX) PRAS3 : SRAM S3 -#define AT91C_MATRIX_SCFG3 (AT91C_CAST(AT91C_REG *) 0xFFFFEA4C) // (MATRIX) Slave Configuration Register 3 : SRAM S3 -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (AT91C_CAST(AT91C_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (AT91C_CAST(AT91C_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (AT91C_CAST(AT91C_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (AT91C_CAST(AT91C_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (AT91C_CAST(AT91C_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (AT91C_CAST(AT91C_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (AT91C_CAST(AT91C_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (AT91C_CAST(AT91C_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (AT91C_CAST(AT91C_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (AT91C_CAST(AT91C_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (AT91C_CAST(AT91C_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (AT91C_CAST(AT91C_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (AT91C_CAST(AT91C_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (AT91C_CAST(AT91C_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (AT91C_CAST(AT91C_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (AT91C_CAST(AT91C_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (AT91C_CAST(AT91C_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (AT91C_CAST(AT91C_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_PTCR (AT91C_CAST(AT91C_REG *) 0xFFFFEF20) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_RCR (AT91C_CAST(AT91C_REG *) 0xFFFFEF04) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_TCR (AT91C_CAST(AT91C_REG *) 0xFFFFEF0C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNCR (AT91C_CAST(AT91C_REG *) 0xFFFFEF14) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_TNPR (AT91C_CAST(AT91C_REG *) 0xFFFFEF18) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_RNPR (AT91C_CAST(AT91C_REG *) 0xFFFFEF10) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_PTSR (AT91C_CAST(AT91C_REG *) 0xFFFFEF24) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_RPR (AT91C_CAST(AT91C_REG *) 0xFFFFEF00) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_TPR (AT91C_CAST(AT91C_REG *) 0xFFFFEF08) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_TNCR (AT91C_CAST(AT91C_REG *) 0xFFFFEF1C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_BRGR (AT91C_CAST(AT91C_REG *) 0xFFFFEE20) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_CR (AT91C_CAST(AT91C_REG *) 0xFFFFEE00) // (DBGU) Control Register -#define AT91C_DBGU_THR (AT91C_CAST(AT91C_REG *) 0xFFFFEE1C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_IDR (AT91C_CAST(AT91C_REG *) 0xFFFFEE0C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_EXID (AT91C_CAST(AT91C_REG *) 0xFFFFEE44) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_IMR (AT91C_CAST(AT91C_REG *) 0xFFFFEE10) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_FNTR (AT91C_CAST(AT91C_REG *) 0xFFFFEE48) // (DBGU) Force NTRST Register -#define AT91C_DBGU_IER (AT91C_CAST(AT91C_REG *) 0xFFFFEE08) // (DBGU) Interrupt Enable Register -#define AT91C_DBGU_CSR (AT91C_CAST(AT91C_REG *) 0xFFFFEE14) // (DBGU) Channel Status Register -#define AT91C_DBGU_MR (AT91C_CAST(AT91C_REG *) 0xFFFFEE04) // (DBGU) Mode Register -#define AT91C_DBGU_RHR (AT91C_CAST(AT91C_REG *) 0xFFFFEE18) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_CIDR (AT91C_CAST(AT91C_REG *) 0xFFFFEE40) // (DBGU) Chip ID Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_OWDR (AT91C_CAST(AT91C_REG *) 0xFFFFF2A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_DELAY3 (AT91C_CAST(AT91C_REG *) 0xFFFFF2C8) // (PIOA) PIO Delay Control Register -#define AT91C_PIOA_ISR (AT91C_CAST(AT91C_REG *) 0xFFFFF24C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PDR (AT91C_CAST(AT91C_REG *) 0xFFFFF204) // (PIOA) PIO Disable Register -#define AT91C_PIOA_OSR (AT91C_CAST(AT91C_REG *) 0xFFFFF218) // (PIOA) Output Status Register -#define AT91C_PIOA_ABSR (AT91C_CAST(AT91C_REG *) 0xFFFFF278) // (PIOA) AB Select Status Register -#define AT91C_PIOA_DELAY2 (AT91C_CAST(AT91C_REG *) 0xFFFFF2C4) // (PIOA) PIO Delay Control Register -#define AT91C_PIOA_PDSR (AT91C_CAST(AT91C_REG *) 0xFFFFF23C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_BSR (AT91C_CAST(AT91C_REG *) 0xFFFFF274) // (PIOA) Select B Register -#define AT91C_PIOA_DELAY1 (AT91C_CAST(AT91C_REG *) 0xFFFFF2C0) // (PIOA) PIO Delay Control Register -#define AT91C_PIOA_PPUER (AT91C_CAST(AT91C_REG *) 0xFFFFF264) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OER (AT91C_CAST(AT91C_REG *) 0xFFFFF210) // (PIOA) Output Enable Register -#define AT91C_PIOA_PER (AT91C_CAST(AT91C_REG *) 0xFFFFF200) // (PIOA) PIO Enable Register -#define AT91C_PIOA_VERSION (AT91C_CAST(AT91C_REG *) 0xFFFFF2FC) // (PIOA) PIO Version Register -#define AT91C_PIOA_PPUDR (AT91C_CAST(AT91C_REG *) 0xFFFFF260) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_ODSR (AT91C_CAST(AT91C_REG *) 0xFFFFF238) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SLEWRATE1 (AT91C_CAST(AT91C_REG *) 0xFFFFF2B0) // (PIOA) PIO Slewrate Control Register -#define AT91C_PIOA_MDDR (AT91C_CAST(AT91C_REG *) 0xFFFFF254) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_IFSR (AT91C_CAST(AT91C_REG *) 0xFFFFF228) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_CODR (AT91C_CAST(AT91C_REG *) 0xFFFFF234) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_ASR (AT91C_CAST(AT91C_REG *) 0xFFFFF270) // (PIOA) Select A Register -#define AT91C_PIOA_OWSR (AT91C_CAST(AT91C_REG *) 0xFFFFF2A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_IMR (AT91C_CAST(AT91C_REG *) 0xFFFFF248) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PPUSR (AT91C_CAST(AT91C_REG *) 0xFFFFF268) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_MDER (AT91C_CAST(AT91C_REG *) 0xFFFFF250) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_IFDR (AT91C_CAST(AT91C_REG *) 0xFFFFF224) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_SODR (AT91C_CAST(AT91C_REG *) 0xFFFFF230) // (PIOA) Set Output Data Register -#define AT91C_PIOA_OWER (AT91C_CAST(AT91C_REG *) 0xFFFFF2A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IDR (AT91C_CAST(AT91C_REG *) 0xFFFFF244) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_IFER (AT91C_CAST(AT91C_REG *) 0xFFFFF220) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_IER (AT91C_CAST(AT91C_REG *) 0xFFFFF240) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_ODR (AT91C_CAST(AT91C_REG *) 0xFFFFF214) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_MDSR (AT91C_CAST(AT91C_REG *) 0xFFFFF258) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_DELAY4 (AT91C_CAST(AT91C_REG *) 0xFFFFF2CC) // (PIOA) PIO Delay Control Register -#define AT91C_PIOA_PSR (AT91C_CAST(AT91C_REG *) 0xFFFFF208) // (PIOA) PIO Status Register -// ========== Register definition for PIOB peripheral ========== -#define AT91C_PIOB_ODR (AT91C_CAST(AT91C_REG *) 0xFFFFF414) // (PIOB) Output Disable Registerr -#define AT91C_PIOB_DELAY4 (AT91C_CAST(AT91C_REG *) 0xFFFFF4CC) // (PIOB) PIO Delay Control Register -#define AT91C_PIOB_SODR (AT91C_CAST(AT91C_REG *) 0xFFFFF430) // (PIOB) Set Output Data Register -#define AT91C_PIOB_ISR (AT91C_CAST(AT91C_REG *) 0xFFFFF44C) // (PIOB) Interrupt Status Register -#define AT91C_PIOB_ABSR (AT91C_CAST(AT91C_REG *) 0xFFFFF478) // (PIOB) AB Select Status Register -#define AT91C_PIOB_IMR (AT91C_CAST(AT91C_REG *) 0xFFFFF448) // (PIOB) Interrupt Mask Register -#define AT91C_PIOB_MDSR (AT91C_CAST(AT91C_REG *) 0xFFFFF458) // (PIOB) Multi-driver Status Register -#define AT91C_PIOB_PPUSR (AT91C_CAST(AT91C_REG *) 0xFFFFF468) // (PIOB) Pull-up Status Register -#define AT91C_PIOB_PDSR (AT91C_CAST(AT91C_REG *) 0xFFFFF43C) // (PIOB) Pin Data Status Register -#define AT91C_PIOB_DELAY3 (AT91C_CAST(AT91C_REG *) 0xFFFFF4C8) // (PIOB) PIO Delay Control Register -#define AT91C_PIOB_MDDR (AT91C_CAST(AT91C_REG *) 0xFFFFF454) // (PIOB) Multi-driver Disable Register -#define AT91C_PIOB_CODR (AT91C_CAST(AT91C_REG *) 0xFFFFF434) // (PIOB) Clear Output Data Register -#define AT91C_PIOB_MDER (AT91C_CAST(AT91C_REG *) 0xFFFFF450) // (PIOB) Multi-driver Enable Register -#define AT91C_PIOB_PDR (AT91C_CAST(AT91C_REG *) 0xFFFFF404) // (PIOB) PIO Disable Register -#define AT91C_PIOB_IFSR (AT91C_CAST(AT91C_REG *) 0xFFFFF428) // (PIOB) Input Filter Status Register -#define AT91C_PIOB_PSR (AT91C_CAST(AT91C_REG *) 0xFFFFF408) // (PIOB) PIO Status Register -#define AT91C_PIOB_SLEWRATE1 (AT91C_CAST(AT91C_REG *) 0xFFFFF4B0) // (PIOB) PIO Slewrate Control Register -#define AT91C_PIOB_IER (AT91C_CAST(AT91C_REG *) 0xFFFFF440) // (PIOB) Interrupt Enable Register -#define AT91C_PIOB_PPUDR (AT91C_CAST(AT91C_REG *) 0xFFFFF460) // (PIOB) Pull-up Disable Register -#define AT91C_PIOB_PER (AT91C_CAST(AT91C_REG *) 0xFFFFF400) // (PIOB) PIO Enable Register -#define AT91C_PIOB_IFDR (AT91C_CAST(AT91C_REG *) 0xFFFFF424) // (PIOB) Input Filter Disable Register -#define AT91C_PIOB_IDR (AT91C_CAST(AT91C_REG *) 0xFFFFF444) // (PIOB) Interrupt Disable Register -#define AT91C_PIOB_OWDR (AT91C_CAST(AT91C_REG *) 0xFFFFF4A4) // (PIOB) Output Write Disable Register -#define AT91C_PIOB_ODSR (AT91C_CAST(AT91C_REG *) 0xFFFFF438) // (PIOB) Output Data Status Register -#define AT91C_PIOB_DELAY2 (AT91C_CAST(AT91C_REG *) 0xFFFFF4C4) // (PIOB) PIO Delay Control Register -#define AT91C_PIOB_OWSR (AT91C_CAST(AT91C_REG *) 0xFFFFF4A8) // (PIOB) Output Write Status Register -#define AT91C_PIOB_BSR (AT91C_CAST(AT91C_REG *) 0xFFFFF474) // (PIOB) Select B Register -#define AT91C_PIOB_IFER (AT91C_CAST(AT91C_REG *) 0xFFFFF420) // (PIOB) Input Filter Enable Register -#define AT91C_PIOB_OWER (AT91C_CAST(AT91C_REG *) 0xFFFFF4A0) // (PIOB) Output Write Enable Register -#define AT91C_PIOB_PPUER (AT91C_CAST(AT91C_REG *) 0xFFFFF464) // (PIOB) Pull-up Enable Register -#define AT91C_PIOB_OSR (AT91C_CAST(AT91C_REG *) 0xFFFFF418) // (PIOB) Output Status Register -#define AT91C_PIOB_ASR (AT91C_CAST(AT91C_REG *) 0xFFFFF470) // (PIOB) Select A Register -#define AT91C_PIOB_OER (AT91C_CAST(AT91C_REG *) 0xFFFFF410) // (PIOB) Output Enable Register -#define AT91C_PIOB_VERSION (AT91C_CAST(AT91C_REG *) 0xFFFFF4FC) // (PIOB) PIO Version Register -#define AT91C_PIOB_DELAY1 (AT91C_CAST(AT91C_REG *) 0xFFFFF4C0) // (PIOB) PIO Delay Control Register -// ========== Register definition for PIOC peripheral ========== -#define AT91C_PIOC_OWDR (AT91C_CAST(AT91C_REG *) 0xFFFFF6A4) // (PIOC) Output Write Disable Register -#define AT91C_PIOC_IMR (AT91C_CAST(AT91C_REG *) 0xFFFFF648) // (PIOC) Interrupt Mask Register -#define AT91C_PIOC_ASR (AT91C_CAST(AT91C_REG *) 0xFFFFF670) // (PIOC) Select A Register -#define AT91C_PIOC_PPUDR (AT91C_CAST(AT91C_REG *) 0xFFFFF660) // (PIOC) Pull-up Disable Register -#define AT91C_PIOC_CODR (AT91C_CAST(AT91C_REG *) 0xFFFFF634) // (PIOC) Clear Output Data Register -#define AT91C_PIOC_OWER (AT91C_CAST(AT91C_REG *) 0xFFFFF6A0) // (PIOC) Output Write Enable Register -#define AT91C_PIOC_ABSR (AT91C_CAST(AT91C_REG *) 0xFFFFF678) // (PIOC) AB Select Status Register -#define AT91C_PIOC_IFDR (AT91C_CAST(AT91C_REG *) 0xFFFFF624) // (PIOC) Input Filter Disable Register -#define AT91C_PIOC_VERSION (AT91C_CAST(AT91C_REG *) 0xFFFFF6FC) // (PIOC) PIO Version Register -#define AT91C_PIOC_ODR (AT91C_CAST(AT91C_REG *) 0xFFFFF614) // (PIOC) Output Disable Registerr -#define AT91C_PIOC_PPUER (AT91C_CAST(AT91C_REG *) 0xFFFFF664) // (PIOC) Pull-up Enable Register -#define AT91C_PIOC_SODR (AT91C_CAST(AT91C_REG *) 0xFFFFF630) // (PIOC) Set Output Data Register -#define AT91C_PIOC_ISR (AT91C_CAST(AT91C_REG *) 0xFFFFF64C) // (PIOC) Interrupt Status Register -#define AT91C_PIOC_OSR (AT91C_CAST(AT91C_REG *) 0xFFFFF618) // (PIOC) Output Status Register -#define AT91C_PIOC_MDSR (AT91C_CAST(AT91C_REG *) 0xFFFFF658) // (PIOC) Multi-driver Status Register -#define AT91C_PIOC_IFER (AT91C_CAST(AT91C_REG *) 0xFFFFF620) // (PIOC) Input Filter Enable Register -#define AT91C_PIOC_DELAY2 (AT91C_CAST(AT91C_REG *) 0xFFFFF6C4) // (PIOC) PIO Delay Control Register -#define AT91C_PIOC_MDER (AT91C_CAST(AT91C_REG *) 0xFFFFF650) // (PIOC) Multi-driver Enable Register -#define AT91C_PIOC_PPUSR (AT91C_CAST(AT91C_REG *) 0xFFFFF668) // (PIOC) Pull-up Status Register -#define AT91C_PIOC_PSR (AT91C_CAST(AT91C_REG *) 0xFFFFF608) // (PIOC) PIO Status Register -#define AT91C_PIOC_DELAY4 (AT91C_CAST(AT91C_REG *) 0xFFFFF6CC) // (PIOC) PIO Delay Control Register -#define AT91C_PIOC_DELAY3 (AT91C_CAST(AT91C_REG *) 0xFFFFF6C8) // (PIOC) PIO Delay Control Register -#define AT91C_PIOC_IER (AT91C_CAST(AT91C_REG *) 0xFFFFF640) // (PIOC) Interrupt Enable Register -#define AT91C_PIOC_SLEWRATE1 (AT91C_CAST(AT91C_REG *) 0xFFFFF6B0) // (PIOC) PIO Slewrate Control Register -#define AT91C_PIOC_IDR (AT91C_CAST(AT91C_REG *) 0xFFFFF644) // (PIOC) Interrupt Disable Register -#define AT91C_PIOC_PDSR (AT91C_CAST(AT91C_REG *) 0xFFFFF63C) // (PIOC) Pin Data Status Register -#define AT91C_PIOC_DELAY1 (AT91C_CAST(AT91C_REG *) 0xFFFFF6C0) // (PIOC) PIO Delay Control Register -#define AT91C_PIOC_PDR (AT91C_CAST(AT91C_REG *) 0xFFFFF604) // (PIOC) PIO Disable Register -#define AT91C_PIOC_OWSR (AT91C_CAST(AT91C_REG *) 0xFFFFF6A8) // (PIOC) Output Write Status Register -#define AT91C_PIOC_IFSR (AT91C_CAST(AT91C_REG *) 0xFFFFF628) // (PIOC) Input Filter Status Register -#define AT91C_PIOC_ODSR (AT91C_CAST(AT91C_REG *) 0xFFFFF638) // (PIOC) Output Data Status Register -#define AT91C_PIOC_OER (AT91C_CAST(AT91C_REG *) 0xFFFFF610) // (PIOC) Output Enable Register -#define AT91C_PIOC_MDDR (AT91C_CAST(AT91C_REG *) 0xFFFFF654) // (PIOC) Multi-driver Disable Register -#define AT91C_PIOC_BSR (AT91C_CAST(AT91C_REG *) 0xFFFFF674) // (PIOC) Select B Register -#define AT91C_PIOC_PER (AT91C_CAST(AT91C_REG *) 0xFFFFF600) // (PIOC) PIO Enable Register -// ========== Register definition for PIOD peripheral ========== -#define AT91C_PIOD_DELAY1 (AT91C_CAST(AT91C_REG *) 0xFFFFF8C0) // (PIOD) PIO Delay Control Register -#define AT91C_PIOD_OWDR (AT91C_CAST(AT91C_REG *) 0xFFFFF8A4) // (PIOD) Output Write Disable Register -#define AT91C_PIOD_SODR (AT91C_CAST(AT91C_REG *) 0xFFFFF830) // (PIOD) Set Output Data Register -#define AT91C_PIOD_PPUER (AT91C_CAST(AT91C_REG *) 0xFFFFF864) // (PIOD) Pull-up Enable Register -#define AT91C_PIOD_CODR (AT91C_CAST(AT91C_REG *) 0xFFFFF834) // (PIOD) Clear Output Data Register -#define AT91C_PIOD_DELAY4 (AT91C_CAST(AT91C_REG *) 0xFFFFF8CC) // (PIOD) PIO Delay Control Register -#define AT91C_PIOD_PSR (AT91C_CAST(AT91C_REG *) 0xFFFFF808) // (PIOD) PIO Status Register -#define AT91C_PIOD_PDR (AT91C_CAST(AT91C_REG *) 0xFFFFF804) // (PIOD) PIO Disable Register -#define AT91C_PIOD_ODR (AT91C_CAST(AT91C_REG *) 0xFFFFF814) // (PIOD) Output Disable Registerr -#define AT91C_PIOD_PPUSR (AT91C_CAST(AT91C_REG *) 0xFFFFF868) // (PIOD) Pull-up Status Register -#define AT91C_PIOD_IFSR (AT91C_CAST(AT91C_REG *) 0xFFFFF828) // (PIOD) Input Filter Status Register -#define AT91C_PIOD_IMR (AT91C_CAST(AT91C_REG *) 0xFFFFF848) // (PIOD) Interrupt Mask Register -#define AT91C_PIOD_ASR (AT91C_CAST(AT91C_REG *) 0xFFFFF870) // (PIOD) Select A Register -#define AT91C_PIOD_DELAY2 (AT91C_CAST(AT91C_REG *) 0xFFFFF8C4) // (PIOD) PIO Delay Control Register -#define AT91C_PIOD_OWSR (AT91C_CAST(AT91C_REG *) 0xFFFFF8A8) // (PIOD) Output Write Status Register -#define AT91C_PIOD_PER (AT91C_CAST(AT91C_REG *) 0xFFFFF800) // (PIOD) PIO Enable Register -#define AT91C_PIOD_MDER (AT91C_CAST(AT91C_REG *) 0xFFFFF850) // (PIOD) Multi-driver Enable Register -#define AT91C_PIOD_PDSR (AT91C_CAST(AT91C_REG *) 0xFFFFF83C) // (PIOD) Pin Data Status Register -#define AT91C_PIOD_MDSR (AT91C_CAST(AT91C_REG *) 0xFFFFF858) // (PIOD) Multi-driver Status Register -#define AT91C_PIOD_OWER (AT91C_CAST(AT91C_REG *) 0xFFFFF8A0) // (PIOD) Output Write Enable Register -#define AT91C_PIOD_BSR (AT91C_CAST(AT91C_REG *) 0xFFFFF874) // (PIOD) Select B Register -#define AT91C_PIOD_IFDR (AT91C_CAST(AT91C_REG *) 0xFFFFF824) // (PIOD) Input Filter Disable Register -#define AT91C_PIOD_DELAY3 (AT91C_CAST(AT91C_REG *) 0xFFFFF8C8) // (PIOD) PIO Delay Control Register -#define AT91C_PIOD_ABSR (AT91C_CAST(AT91C_REG *) 0xFFFFF878) // (PIOD) AB Select Status Register -#define AT91C_PIOD_OER (AT91C_CAST(AT91C_REG *) 0xFFFFF810) // (PIOD) Output Enable Register -#define AT91C_PIOD_MDDR (AT91C_CAST(AT91C_REG *) 0xFFFFF854) // (PIOD) Multi-driver Disable Register -#define AT91C_PIOD_IDR (AT91C_CAST(AT91C_REG *) 0xFFFFF844) // (PIOD) Interrupt Disable Register -#define AT91C_PIOD_IER (AT91C_CAST(AT91C_REG *) 0xFFFFF840) // (PIOD) Interrupt Enable Register -#define AT91C_PIOD_PPUDR (AT91C_CAST(AT91C_REG *) 0xFFFFF860) // (PIOD) Pull-up Disable Register -#define AT91C_PIOD_VERSION (AT91C_CAST(AT91C_REG *) 0xFFFFF8FC) // (PIOD) PIO Version Register -#define AT91C_PIOD_ISR (AT91C_CAST(AT91C_REG *) 0xFFFFF84C) // (PIOD) Interrupt Status Register -#define AT91C_PIOD_ODSR (AT91C_CAST(AT91C_REG *) 0xFFFFF838) // (PIOD) Output Data Status Register -#define AT91C_PIOD_OSR (AT91C_CAST(AT91C_REG *) 0xFFFFF818) // (PIOD) Output Status Register -#define AT91C_PIOD_IFER (AT91C_CAST(AT91C_REG *) 0xFFFFF820) // (PIOD) Input Filter Enable Register -#define AT91C_PIOD_SLEWRATE1 (AT91C_CAST(AT91C_REG *) 0xFFFFF8B0) // (PIOD) PIO Slewrate Control Register -// ========== Register definition for PIOE peripheral ========== -#define AT91C_PIOE_ODSR (AT91C_CAST(AT91C_REG *) 0xFFFFFA38) // (PIOE) Output Data Status Register -#define AT91C_PIOE_ABSR (AT91C_CAST(AT91C_REG *) 0xFFFFFA78) // (PIOE) AB Select Status Register -#define AT91C_PIOE_PSR (AT91C_CAST(AT91C_REG *) 0xFFFFFA08) // (PIOE) PIO Status Register -#define AT91C_PIOE_PPUDR (AT91C_CAST(AT91C_REG *) 0xFFFFFA60) // (PIOE) Pull-up Disable Register -#define AT91C_PIOE_OER (AT91C_CAST(AT91C_REG *) 0xFFFFFA10) // (PIOE) Output Enable Register -#define AT91C_PIOE_IFSR (AT91C_CAST(AT91C_REG *) 0xFFFFFA28) // (PIOE) Input Filter Status Register -#define AT91C_PIOE_IFER (AT91C_CAST(AT91C_REG *) 0xFFFFFA20) // (PIOE) Input Filter Enable Register -#define AT91C_PIOE_DELAY3 (AT91C_CAST(AT91C_REG *) 0xFFFFFAC8) // (PIOE) PIO Delay Control Register -#define AT91C_PIOE_ODR (AT91C_CAST(AT91C_REG *) 0xFFFFFA14) // (PIOE) Output Disable Registerr -#define AT91C_PIOE_IDR (AT91C_CAST(AT91C_REG *) 0xFFFFFA44) // (PIOE) Interrupt Disable Register -#define AT91C_PIOE_DELAY1 (AT91C_CAST(AT91C_REG *) 0xFFFFFAC0) // (PIOE) PIO Delay Control Register -#define AT91C_PIOE_OSR (AT91C_CAST(AT91C_REG *) 0xFFFFFA18) // (PIOE) Output Status Register -#define AT91C_PIOE_CODR (AT91C_CAST(AT91C_REG *) 0xFFFFFA34) // (PIOE) Clear Output Data Register -#define AT91C_PIOE_VERSION (AT91C_CAST(AT91C_REG *) 0xFFFFFAFC) // (PIOE) PIO Version Register -#define AT91C_PIOE_MDSR (AT91C_CAST(AT91C_REG *) 0xFFFFFA58) // (PIOE) Multi-driver Status Register -#define AT91C_PIOE_PDR (AT91C_CAST(AT91C_REG *) 0xFFFFFA04) // (PIOE) PIO Disable Register -#define AT91C_PIOE_IER (AT91C_CAST(AT91C_REG *) 0xFFFFFA40) // (PIOE) Interrupt Enable Register -#define AT91C_PIOE_OWSR (AT91C_CAST(AT91C_REG *) 0xFFFFFAA8) // (PIOE) Output Write Status Register -#define AT91C_PIOE_BSR (AT91C_CAST(AT91C_REG *) 0xFFFFFA74) // (PIOE) Select B Register -#define AT91C_PIOE_SLEWRATE1 (AT91C_CAST(AT91C_REG *) 0xFFFFFAB0) // (PIOE) PIO Slewrate Control Register -#define AT91C_PIOE_DELAY4 (AT91C_CAST(AT91C_REG *) 0xFFFFFACC) // (PIOE) PIO Delay Control Register -#define AT91C_PIOE_PER (AT91C_CAST(AT91C_REG *) 0xFFFFFA00) // (PIOE) PIO Enable Register -#define AT91C_PIOE_OWDR (AT91C_CAST(AT91C_REG *) 0xFFFFFAA4) // (PIOE) Output Write Disable Register -#define AT91C_PIOE_IFDR (AT91C_CAST(AT91C_REG *) 0xFFFFFA24) // (PIOE) Input Filter Disable Register -#define AT91C_PIOE_PPUSR (AT91C_CAST(AT91C_REG *) 0xFFFFFA68) // (PIOE) Pull-up Status Register -#define AT91C_PIOE_PDSR (AT91C_CAST(AT91C_REG *) 0xFFFFFA3C) // (PIOE) Pin Data Status Register -#define AT91C_PIOE_PPUER (AT91C_CAST(AT91C_REG *) 0xFFFFFA64) // (PIOE) Pull-up Enable Register -#define AT91C_PIOE_MDDR (AT91C_CAST(AT91C_REG *) 0xFFFFFA54) // (PIOE) Multi-driver Disable Register -#define AT91C_PIOE_ISR (AT91C_CAST(AT91C_REG *) 0xFFFFFA4C) // (PIOE) Interrupt Status Register -#define AT91C_PIOE_DELAY2 (AT91C_CAST(AT91C_REG *) 0xFFFFFAC4) // (PIOE) PIO Delay Control Register -#define AT91C_PIOE_SODR (AT91C_CAST(AT91C_REG *) 0xFFFFFA30) // (PIOE) Set Output Data Register -#define AT91C_PIOE_ASR (AT91C_CAST(AT91C_REG *) 0xFFFFFA70) // (PIOE) Select A Register -#define AT91C_PIOE_IMR (AT91C_CAST(AT91C_REG *) 0xFFFFFA48) // (PIOE) Interrupt Mask Register -#define AT91C_PIOE_OWER (AT91C_CAST(AT91C_REG *) 0xFFFFFAA0) // (PIOE) Output Write Enable Register -#define AT91C_PIOE_MDER (AT91C_CAST(AT91C_REG *) 0xFFFFFA50) // (PIOE) Multi-driver Enable Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFFFFCEC) // (PMC) -#define AT91C_PMC_PCER (AT91C_CAST(AT91C_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (AT91C_CAST(AT91C_REG *) 0xFFFFFC40) // (PMC) Programmable Clock 0 Register -#define AT91C_PMC_MCKR (AT91C_CAST(AT91C_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_PLLAR (AT91C_CAST(AT91C_REG *) 0xFFFFFC28) // (PMC) PLL A Register -#define AT91C_PMC_NAME2 (AT91C_CAST(AT91C_REG *) 0xFFFFFCF4) // (PMC) -#define AT91C_PMC_PCDR (AT91C_CAST(AT91C_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (AT91C_CAST(AT91C_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_MCFR (AT91C_CAST(AT91C_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFFFFCF8) // (PMC) -#define AT91C_PMC_PLLICPR (AT91C_CAST(AT91C_REG *) 0xFFFFFC80) // (PMC) PLL Charge Pump Current Register -#define AT91C_PMC_IMR (AT91C_CAST(AT91C_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (AT91C_CAST(AT91C_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_UCKR (AT91C_CAST(AT91C_REG *) 0xFFFFFC1C) // (PMC) UTMI Clock Configuration Register -#define AT91C_PMC_USB (AT91C_CAST(AT91C_REG *) 0xFFFFFC38) // (PMC) USB clock register -#define AT91C_PMC_MOR (AT91C_CAST(AT91C_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_IDR (AT91C_CAST(AT91C_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_NAME1 (AT91C_CAST(AT91C_REG *) 0xFFFFFCF0) // (PMC) -#define AT91C_PMC_SCDR (AT91C_CAST(AT91C_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCSR (AT91C_CAST(AT91C_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_SCER (AT91C_CAST(AT91C_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_VERSION (AT91C_CAST(AT91C_REG *) 0xFFFFFCFC) // (PMC) -#define AT91C_PMC_SR (AT91C_CAST(AT91C_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (AT91C_CAST(AT91C_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_MCFR (AT91C_CAST(AT91C_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -#define AT91C_CKGR_PLLAR (AT91C_CAST(AT91C_REG *) 0xFFFFFC28) // (CKGR) PLL A Register -#define AT91C_CKGR_UCKR (AT91C_CAST(AT91C_REG *) 0xFFFFFC1C) // (CKGR) UTMI Clock Configuration Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (AT91C_CAST(AT91C_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_VER (AT91C_CAST(AT91C_REG *) 0xFFFFFDFC) // (RSTC) Version Register -#define AT91C_RSTC_RMR (AT91C_CAST(AT91C_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (AT91C_CAST(AT91C_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for SHDWC peripheral ========== -#define AT91C_SHDWC_SHSR (AT91C_CAST(AT91C_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register -#define AT91C_SHDWC_SHMR (AT91C_CAST(AT91C_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register -#define AT91C_SHDWC_SHCR (AT91C_CAST(AT91C_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (AT91C_CAST(AT91C_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (AT91C_CAST(AT91C_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (AT91C_CAST(AT91C_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (AT91C_CAST(AT91C_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (AT91C_CAST(AT91C_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (AT91C_CAST(AT91C_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (AT91C_CAST(AT91C_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (AT91C_CAST(AT91C_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (AT91C_CAST(AT91C_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (AT91C_CAST(AT91C_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (AT91C_CAST(AT91C_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for RTC peripheral ========== -#define AT91C_RTC_IDR (AT91C_CAST(AT91C_REG *) 0xFFFFFDD4) // (RTC) Interrupt Disable Register -#define AT91C_RTC_SR (AT91C_CAST(AT91C_REG *) 0xFFFFFDC8) // (RTC) Status Register -#define AT91C_RTC_MR (AT91C_CAST(AT91C_REG *) 0xFFFFFDB4) // (RTC) Mode Register -#define AT91C_RTC_IER (AT91C_CAST(AT91C_REG *) 0xFFFFFDD0) // (RTC) Interrupt Enable Register -#define AT91C_RTC_TIMALR (AT91C_CAST(AT91C_REG *) 0xFFFFFDC0) // (RTC) Time Alarm Register -#define AT91C_RTC_CALALR (AT91C_CAST(AT91C_REG *) 0xFFFFFDC4) // (RTC) Calendar Alarm Register -#define AT91C_RTC_CR (AT91C_CAST(AT91C_REG *) 0xFFFFFDB0) // (RTC) Control Register -#define AT91C_RTC_TIMR (AT91C_CAST(AT91C_REG *) 0xFFFFFDB8) // (RTC) Time Register -#define AT91C_RTC_CALR (AT91C_CAST(AT91C_REG *) 0xFFFFFDBC) // (RTC) Calendar Register -#define AT91C_RTC_VER (AT91C_CAST(AT91C_REG *) 0xFFFFFDDC) // (RTC) Valid Entry Register -#define AT91C_RTC_SCCR (AT91C_CAST(AT91C_REG *) 0xFFFFFDCC) // (RTC) Status Clear Command Register -#define AT91C_RTC_IMR (AT91C_CAST(AT91C_REG *) 0xFFFFFDD8) // (RTC) Interrupt Mask Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IER (AT91C_CAST(AT91C_REG *) 0xFFF7C024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_IMR (AT91C_CAST(AT91C_REG *) 0xFFF7C02C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_CCR (AT91C_CAST(AT91C_REG *) 0xFFF7C000) // (TC0) Channel Control Register -#define AT91C_TC0_RB (AT91C_CAST(AT91C_REG *) 0xFFF7C018) // (TC0) Register B -#define AT91C_TC0_CV (AT91C_CAST(AT91C_REG *) 0xFFF7C010) // (TC0) Counter Value -#define AT91C_TC0_SR (AT91C_CAST(AT91C_REG *) 0xFFF7C020) // (TC0) Status Register -#define AT91C_TC0_CMR (AT91C_CAST(AT91C_REG *) 0xFFF7C004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_RA (AT91C_CAST(AT91C_REG *) 0xFFF7C014) // (TC0) Register A -#define AT91C_TC0_RC (AT91C_CAST(AT91C_REG *) 0xFFF7C01C) // (TC0) Register C -#define AT91C_TC0_IDR (AT91C_CAST(AT91C_REG *) 0xFFF7C028) // (TC0) Interrupt Disable Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IER (AT91C_CAST(AT91C_REG *) 0xFFF7C064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_SR (AT91C_CAST(AT91C_REG *) 0xFFF7C060) // (TC1) Status Register -#define AT91C_TC1_RC (AT91C_CAST(AT91C_REG *) 0xFFF7C05C) // (TC1) Register C -#define AT91C_TC1_CV (AT91C_CAST(AT91C_REG *) 0xFFF7C050) // (TC1) Counter Value -#define AT91C_TC1_RA (AT91C_CAST(AT91C_REG *) 0xFFF7C054) // (TC1) Register A -#define AT91C_TC1_CMR (AT91C_CAST(AT91C_REG *) 0xFFF7C044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_IDR (AT91C_CAST(AT91C_REG *) 0xFFF7C068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_RB (AT91C_CAST(AT91C_REG *) 0xFFF7C058) // (TC1) Register B -#define AT91C_TC1_IMR (AT91C_CAST(AT91C_REG *) 0xFFF7C06C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CCR (AT91C_CAST(AT91C_REG *) 0xFFF7C040) // (TC1) Channel Control Register -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_SR (AT91C_CAST(AT91C_REG *) 0xFFF7C0A0) // (TC2) Status Register -#define AT91C_TC2_IMR (AT91C_CAST(AT91C_REG *) 0xFFF7C0AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER (AT91C_CAST(AT91C_REG *) 0xFFF7C0A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_CV (AT91C_CAST(AT91C_REG *) 0xFFF7C090) // (TC2) Counter Value -#define AT91C_TC2_RB (AT91C_CAST(AT91C_REG *) 0xFFF7C098) // (TC2) Register B -#define AT91C_TC2_CCR (AT91C_CAST(AT91C_REG *) 0xFFF7C080) // (TC2) Channel Control Register -#define AT91C_TC2_CMR (AT91C_CAST(AT91C_REG *) 0xFFF7C084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_RA (AT91C_CAST(AT91C_REG *) 0xFFF7C094) // (TC2) Register A -#define AT91C_TC2_IDR (AT91C_CAST(AT91C_REG *) 0xFFF7C0A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_RC (AT91C_CAST(AT91C_REG *) 0xFFF7C09C) // (TC2) Register C -// ========== Register definition for TC3 peripheral ========== -#define AT91C_TC3_SR (AT91C_CAST(AT91C_REG *) 0xFFFD4020) // (TC3) Status Register -#define AT91C_TC3_RC (AT91C_CAST(AT91C_REG *) 0xFFFD401C) // (TC3) Register C -#define AT91C_TC3_IER (AT91C_CAST(AT91C_REG *) 0xFFFD4024) // (TC3) Interrupt Enable Register -#define AT91C_TC3_CV (AT91C_CAST(AT91C_REG *) 0xFFFD4010) // (TC3) Counter Value -#define AT91C_TC3_IDR (AT91C_CAST(AT91C_REG *) 0xFFFD4028) // (TC3) Interrupt Disable Register -#define AT91C_TC3_IMR (AT91C_CAST(AT91C_REG *) 0xFFFD402C) // (TC3) Interrupt Mask Register -#define AT91C_TC3_CMR (AT91C_CAST(AT91C_REG *) 0xFFFD4004) // (TC3) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC3_RB (AT91C_CAST(AT91C_REG *) 0xFFFD4018) // (TC3) Register B -#define AT91C_TC3_CCR (AT91C_CAST(AT91C_REG *) 0xFFFD4000) // (TC3) Channel Control Register -#define AT91C_TC3_RA (AT91C_CAST(AT91C_REG *) 0xFFFD4014) // (TC3) Register A -// ========== Register definition for TC4 peripheral ========== -#define AT91C_TC4_CV (AT91C_CAST(AT91C_REG *) 0xFFFD4050) // (TC4) Counter Value -#define AT91C_TC4_RA (AT91C_CAST(AT91C_REG *) 0xFFFD4054) // (TC4) Register A -#define AT91C_TC4_IDR (AT91C_CAST(AT91C_REG *) 0xFFFD4068) // (TC4) Interrupt Disable Register -#define AT91C_TC4_SR (AT91C_CAST(AT91C_REG *) 0xFFFD4060) // (TC4) Status Register -#define AT91C_TC4_CMR (AT91C_CAST(AT91C_REG *) 0xFFFD4044) // (TC4) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC4_CCR (AT91C_CAST(AT91C_REG *) 0xFFFD4040) // (TC4) Channel Control Register -#define AT91C_TC4_RB (AT91C_CAST(AT91C_REG *) 0xFFFD4058) // (TC4) Register B -#define AT91C_TC4_RC (AT91C_CAST(AT91C_REG *) 0xFFFD405C) // (TC4) Register C -#define AT91C_TC4_IER (AT91C_CAST(AT91C_REG *) 0xFFFD4064) // (TC4) Interrupt Enable Register -#define AT91C_TC4_IMR (AT91C_CAST(AT91C_REG *) 0xFFFD406C) // (TC4) Interrupt Mask Register -// ========== Register definition for TC5 peripheral ========== -#define AT91C_TC5_IER (AT91C_CAST(AT91C_REG *) 0xFFFD40A4) // (TC5) Interrupt Enable Register -#define AT91C_TC5_IDR (AT91C_CAST(AT91C_REG *) 0xFFFD40A8) // (TC5) Interrupt Disable Register -#define AT91C_TC5_RA (AT91C_CAST(AT91C_REG *) 0xFFFD4094) // (TC5) Register A -#define AT91C_TC5_RB (AT91C_CAST(AT91C_REG *) 0xFFFD4098) // (TC5) Register B -#define AT91C_TC5_CCR (AT91C_CAST(AT91C_REG *) 0xFFFD4080) // (TC5) Channel Control Register -#define AT91C_TC5_SR (AT91C_CAST(AT91C_REG *) 0xFFFD40A0) // (TC5) Status Register -#define AT91C_TC5_CV (AT91C_CAST(AT91C_REG *) 0xFFFD4090) // (TC5) Counter Value -#define AT91C_TC5_RC (AT91C_CAST(AT91C_REG *) 0xFFFD409C) // (TC5) Register C -#define AT91C_TC5_IMR (AT91C_CAST(AT91C_REG *) 0xFFFD40AC) // (TC5) Interrupt Mask Register -#define AT91C_TC5_CMR (AT91C_CAST(AT91C_REG *) 0xFFFD4084) // (TC5) Channel Mode Register (Capture Mode / Waveform Mode) -// ========== Register definition for TCB0 peripheral ========== -#define AT91C_TCB0_IPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFF7C0F0) // (TCB0) TC IPNAME1 REGISTER -#define AT91C_TCB0_IPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFF7C0F4) // (TCB0) TC IPNAME2 REGISTER -#define AT91C_TCB0_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFF7C0F8) // (TCB0) TC FEATURES REGISTER -#define AT91C_TCB0_BCR (AT91C_CAST(AT91C_REG *) 0xFFF7C0C0) // (TCB0) TC Block Control Register -#define AT91C_TCB0_VER (AT91C_CAST(AT91C_REG *) 0xFFF7C0FC) // (TCB0) Version Register -#define AT91C_TCB0_BMR (AT91C_CAST(AT91C_REG *) 0xFFF7C0C4) // (TCB0) TC Block Mode Register -#define AT91C_TCB0_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFF7C0EC) // (TCB0) TC ADDRSIZE REGISTER -// ========== Register definition for TCB1 peripheral ========== -#define AT91C_TCB1_VER (AT91C_CAST(AT91C_REG *) 0xFFFD40FC) // (TCB1) Version Register -#define AT91C_TCB1_IPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFFD40F4) // (TCB1) TC IPNAME2 REGISTER -#define AT91C_TCB1_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFFD40EC) // (TCB1) TC ADDRSIZE REGISTER -#define AT91C_TCB1_BMR (AT91C_CAST(AT91C_REG *) 0xFFFD40C4) // (TCB1) TC Block Mode Register -#define AT91C_TCB1_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFFD40F8) // (TCB1) TC FEATURES REGISTER -#define AT91C_TCB1_IPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFFD40F0) // (TCB1) TC IPNAME1 REGISTER -#define AT91C_TCB1_BCR (AT91C_CAST(AT91C_REG *) 0xFFFD40C0) // (TCB1) TC Block Control Register -// ========== Register definition for MCI0 peripheral ========== -#define AT91C_MCI0_IMR (AT91C_CAST(AT91C_REG *) 0xFFF8004C) // (MCI0) MCI Interrupt Mask Register -#define AT91C_MCI0_MR (AT91C_CAST(AT91C_REG *) 0xFFF80004) // (MCI0) MCI Mode Register -#define AT91C_MCI0_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFF800EC) // (MCI0) MCI ADDRSIZE REGISTER -#define AT91C_MCI0_CR (AT91C_CAST(AT91C_REG *) 0xFFF80000) // (MCI0) MCI Control Register -#define AT91C_MCI0_IPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFF800F4) // (MCI0) MCI IPNAME2 REGISTER -#define AT91C_MCI0_IER (AT91C_CAST(AT91C_REG *) 0xFFF80044) // (MCI0) MCI Interrupt Enable Register -#define AT91C_MCI0_FIFO (AT91C_CAST(AT91C_REG *) 0xFFF80200) // (MCI0) MCI FIFO Aperture Register -#define AT91C_MCI0_DTOR (AT91C_CAST(AT91C_REG *) 0xFFF80008) // (MCI0) MCI Data Timeout Register -#define AT91C_MCI0_SDCR (AT91C_CAST(AT91C_REG *) 0xFFF8000C) // (MCI0) MCI SD/SDIO Card Register -#define AT91C_MCI0_BLKR (AT91C_CAST(AT91C_REG *) 0xFFF80018) // (MCI0) MCI Block Register -#define AT91C_MCI0_VER (AT91C_CAST(AT91C_REG *) 0xFFF800FC) // (MCI0) MCI VERSION REGISTER -#define AT91C_MCI0_WPSR (AT91C_CAST(AT91C_REG *) 0xFFF800E8) // (MCI0) MCI Write Protection Status Register -#define AT91C_MCI0_CMDR (AT91C_CAST(AT91C_REG *) 0xFFF80014) // (MCI0) MCI Command Register -#define AT91C_MCI0_CSTOR (AT91C_CAST(AT91C_REG *) 0xFFF8001C) // (MCI0) MCI Completion Signal Timeout Register -#define AT91C_MCI0_IPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFF800F0) // (MCI0) MCI IPNAME1 REGISTER -#define AT91C_MCI0_DMA (AT91C_CAST(AT91C_REG *) 0xFFF80050) // (MCI0) MCI DMA Configuration Register -#define AT91C_MCI0_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFF800F8) // (MCI0) MCI FEATURES REGISTER -#define AT91C_MCI0_RDR (AT91C_CAST(AT91C_REG *) 0xFFF80030) // (MCI0) MCI Receive Data Register -#define AT91C_MCI0_SR (AT91C_CAST(AT91C_REG *) 0xFFF80040) // (MCI0) MCI Status Register -#define AT91C_MCI0_TDR (AT91C_CAST(AT91C_REG *) 0xFFF80034) // (MCI0) MCI Transmit Data Register -#define AT91C_MCI0_CFG (AT91C_CAST(AT91C_REG *) 0xFFF80054) // (MCI0) MCI Configuration Register -#define AT91C_MCI0_ARGR (AT91C_CAST(AT91C_REG *) 0xFFF80010) // (MCI0) MCI Argument Register -#define AT91C_MCI0_RSPR (AT91C_CAST(AT91C_REG *) 0xFFF80020) // (MCI0) MCI Response Register -#define AT91C_MCI0_WPCR (AT91C_CAST(AT91C_REG *) 0xFFF800E4) // (MCI0) MCI Write Protection Control Register -#define AT91C_MCI0_IDR (AT91C_CAST(AT91C_REG *) 0xFFF80048) // (MCI0) MCI Interrupt Disable Register -// ========== Register definition for MCI1 peripheral ========== -#define AT91C_MCI1_IPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFFD00F0) // (MCI1) MCI IPNAME1 REGISTER -#define AT91C_MCI1_IDR (AT91C_CAST(AT91C_REG *) 0xFFFD0048) // (MCI1) MCI Interrupt Disable Register -#define AT91C_MCI1_IPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFFD00F4) // (MCI1) MCI IPNAME2 REGISTER -#define AT91C_MCI1_MR (AT91C_CAST(AT91C_REG *) 0xFFFD0004) // (MCI1) MCI Mode Register -#define AT91C_MCI1_SR (AT91C_CAST(AT91C_REG *) 0xFFFD0040) // (MCI1) MCI Status Register -#define AT91C_MCI1_DTOR (AT91C_CAST(AT91C_REG *) 0xFFFD0008) // (MCI1) MCI Data Timeout Register -#define AT91C_MCI1_WPCR (AT91C_CAST(AT91C_REG *) 0xFFFD00E4) // (MCI1) MCI Write Protection Control Register -#define AT91C_MCI1_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFFD00EC) // (MCI1) MCI ADDRSIZE REGISTER -#define AT91C_MCI1_ARGR (AT91C_CAST(AT91C_REG *) 0xFFFD0010) // (MCI1) MCI Argument Register -#define AT91C_MCI1_FIFO (AT91C_CAST(AT91C_REG *) 0xFFFD0200) // (MCI1) MCI FIFO Aperture Register -#define AT91C_MCI1_IER (AT91C_CAST(AT91C_REG *) 0xFFFD0044) // (MCI1) MCI Interrupt Enable Register -#define AT91C_MCI1_SDCR (AT91C_CAST(AT91C_REG *) 0xFFFD000C) // (MCI1) MCI SD/SDIO Card Register -#define AT91C_MCI1_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFFD00F8) // (MCI1) MCI FEATURES REGISTER -#define AT91C_MCI1_CR (AT91C_CAST(AT91C_REG *) 0xFFFD0000) // (MCI1) MCI Control Register -#define AT91C_MCI1_CSTOR (AT91C_CAST(AT91C_REG *) 0xFFFD001C) // (MCI1) MCI Completion Signal Timeout Register -#define AT91C_MCI1_RSPR (AT91C_CAST(AT91C_REG *) 0xFFFD0020) // (MCI1) MCI Response Register -#define AT91C_MCI1_IMR (AT91C_CAST(AT91C_REG *) 0xFFFD004C) // (MCI1) MCI Interrupt Mask Register -#define AT91C_MCI1_DMA (AT91C_CAST(AT91C_REG *) 0xFFFD0050) // (MCI1) MCI DMA Configuration Register -#define AT91C_MCI1_BLKR (AT91C_CAST(AT91C_REG *) 0xFFFD0018) // (MCI1) MCI Block Register -#define AT91C_MCI1_RDR (AT91C_CAST(AT91C_REG *) 0xFFFD0030) // (MCI1) MCI Receive Data Register -#define AT91C_MCI1_CFG (AT91C_CAST(AT91C_REG *) 0xFFFD0054) // (MCI1) MCI Configuration Register -#define AT91C_MCI1_WPSR (AT91C_CAST(AT91C_REG *) 0xFFFD00E8) // (MCI1) MCI Write Protection Status Register -#define AT91C_MCI1_CMDR (AT91C_CAST(AT91C_REG *) 0xFFFD0014) // (MCI1) MCI Command Register -#define AT91C_MCI1_TDR (AT91C_CAST(AT91C_REG *) 0xFFFD0034) // (MCI1) MCI Transmit Data Register -#define AT91C_MCI1_VER (AT91C_CAST(AT91C_REG *) 0xFFFD00FC) // (MCI1) MCI VERSION REGISTER -// ========== Register definition for TWI0 peripheral ========== -#define AT91C_TWI0_RHR (AT91C_CAST(AT91C_REG *) 0xFFF84030) // (TWI0) Receive Holding Register -#define AT91C_TWI0_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFF840EC) // (TWI0) TWI ADDRSIZE REGISTER -#define AT91C_TWI0_SMR (AT91C_CAST(AT91C_REG *) 0xFFF84008) // (TWI0) Slave Mode Register -#define AT91C_TWI0_IDR (AT91C_CAST(AT91C_REG *) 0xFFF84028) // (TWI0) Interrupt Disable Register -#define AT91C_TWI0_CWGR (AT91C_CAST(AT91C_REG *) 0xFFF84010) // (TWI0) Clock Waveform Generator Register -#define AT91C_TWI0_IER (AT91C_CAST(AT91C_REG *) 0xFFF84024) // (TWI0) Interrupt Enable Register -#define AT91C_TWI0_THR (AT91C_CAST(AT91C_REG *) 0xFFF84034) // (TWI0) Transmit Holding Register -#define AT91C_TWI0_IPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFF840F4) // (TWI0) TWI IPNAME2 REGISTER -#define AT91C_TWI0_CR (AT91C_CAST(AT91C_REG *) 0xFFF84000) // (TWI0) Control Register -#define AT91C_TWI0_MMR (AT91C_CAST(AT91C_REG *) 0xFFF84004) // (TWI0) Master Mode Register -#define AT91C_TWI0_SR (AT91C_CAST(AT91C_REG *) 0xFFF84020) // (TWI0) Status Register -#define AT91C_TWI0_IMR (AT91C_CAST(AT91C_REG *) 0xFFF8402C) // (TWI0) Interrupt Mask Register -#define AT91C_TWI0_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFF840F8) // (TWI0) TWI FEATURES REGISTER -#define AT91C_TWI0_IADR (AT91C_CAST(AT91C_REG *) 0xFFF8400C) // (TWI0) Internal Address Register -#define AT91C_TWI0_IPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFF840F0) // (TWI0) TWI IPNAME1 REGISTER -#define AT91C_TWI0_VER (AT91C_CAST(AT91C_REG *) 0xFFF840FC) // (TWI0) Version Register -// ========== Register definition for TWI1 peripheral ========== -#define AT91C_TWI1_VER (AT91C_CAST(AT91C_REG *) 0xFFF880FC) // (TWI1) Version Register -#define AT91C_TWI1_IMR (AT91C_CAST(AT91C_REG *) 0xFFF8802C) // (TWI1) Interrupt Mask Register -#define AT91C_TWI1_THR (AT91C_CAST(AT91C_REG *) 0xFFF88034) // (TWI1) Transmit Holding Register -#define AT91C_TWI1_IER (AT91C_CAST(AT91C_REG *) 0xFFF88024) // (TWI1) Interrupt Enable Register -#define AT91C_TWI1_MMR (AT91C_CAST(AT91C_REG *) 0xFFF88004) // (TWI1) Master Mode Register -#define AT91C_TWI1_IPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFF880F0) // (TWI1) TWI IPNAME1 REGISTER -#define AT91C_TWI1_CR (AT91C_CAST(AT91C_REG *) 0xFFF88000) // (TWI1) Control Register -#define AT91C_TWI1_SR (AT91C_CAST(AT91C_REG *) 0xFFF88020) // (TWI1) Status Register -#define AT91C_TWI1_CWGR (AT91C_CAST(AT91C_REG *) 0xFFF88010) // (TWI1) Clock Waveform Generator Register -#define AT91C_TWI1_IPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFF880F4) // (TWI1) TWI IPNAME2 REGISTER -#define AT91C_TWI1_IDR (AT91C_CAST(AT91C_REG *) 0xFFF88028) // (TWI1) Interrupt Disable Register -#define AT91C_TWI1_RHR (AT91C_CAST(AT91C_REG *) 0xFFF88030) // (TWI1) Receive Holding Register -#define AT91C_TWI1_IADR (AT91C_CAST(AT91C_REG *) 0xFFF8800C) // (TWI1) Internal Address Register -#define AT91C_TWI1_SMR (AT91C_CAST(AT91C_REG *) 0xFFF88008) // (TWI1) Slave Mode Register -#define AT91C_TWI1_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFF880F8) // (TWI1) TWI FEATURES REGISTER -#define AT91C_TWI1_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFF880EC) // (TWI1) TWI ADDRSIZE REGISTER -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (AT91C_CAST(AT91C_REG *) 0xFFF8C118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_PTSR (AT91C_CAST(AT91C_REG *) 0xFFF8C124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_PTCR (AT91C_CAST(AT91C_REG *) 0xFFF8C120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_RNCR (AT91C_CAST(AT91C_REG *) 0xFFF8C114) // (PDC_US0) Receive Next Counter Register -#define AT91C_US0_RCR (AT91C_CAST(AT91C_REG *) 0xFFF8C104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_TNCR (AT91C_CAST(AT91C_REG *) 0xFFF8C11C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TCR (AT91C_CAST(AT91C_REG *) 0xFFF8C10C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RNPR (AT91C_CAST(AT91C_REG *) 0xFFF8C110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_RPR (AT91C_CAST(AT91C_REG *) 0xFFF8C100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_TPR (AT91C_CAST(AT91C_REG *) 0xFFF8C108) // (PDC_US0) Transmit Pointer Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_MAN (AT91C_CAST(AT91C_REG *) 0xFFF8C050) // (US0) Manchester Encoder Decoder Register -#define AT91C_US0_MR (AT91C_CAST(AT91C_REG *) 0xFFF8C004) // (US0) Mode Register -#define AT91C_US0_RHR (AT91C_CAST(AT91C_REG *) 0xFFF8C018) // (US0) Receiver Holding Register -#define AT91C_US0_CSR (AT91C_CAST(AT91C_REG *) 0xFFF8C014) // (US0) Channel Status Register -#define AT91C_US0_CR (AT91C_CAST(AT91C_REG *) 0xFFF8C000) // (US0) Control Register -#define AT91C_US0_VER (AT91C_CAST(AT91C_REG *) 0xFFF8C0FC) // (US0) VERSION Register -#define AT91C_US0_IER (AT91C_CAST(AT91C_REG *) 0xFFF8C008) // (US0) Interrupt Enable Register -#define AT91C_US0_BRGR (AT91C_CAST(AT91C_REG *) 0xFFF8C020) // (US0) Baud Rate Generator Register -#define AT91C_US0_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFF8C0F8) // (US0) US FEATURES REGISTER -#define AT91C_US0_RTOR (AT91C_CAST(AT91C_REG *) 0xFFF8C024) // (US0) Receiver Time-out Register -#define AT91C_US0_THR (AT91C_CAST(AT91C_REG *) 0xFFF8C01C) // (US0) Transmitter Holding Register -#define AT91C_US0_NER (AT91C_CAST(AT91C_REG *) 0xFFF8C044) // (US0) Nb Errors Register -#define AT91C_US0_IPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFF8C0F0) // (US0) US IPNAME1 REGISTER -#define AT91C_US0_IMR (AT91C_CAST(AT91C_REG *) 0xFFF8C010) // (US0) Interrupt Mask Register -#define AT91C_US0_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFF8C0EC) // (US0) US ADDRSIZE REGISTER -#define AT91C_US0_IDR (AT91C_CAST(AT91C_REG *) 0xFFF8C00C) // (US0) Interrupt Disable Register -#define AT91C_US0_FIDI (AT91C_CAST(AT91C_REG *) 0xFFF8C040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_IPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFF8C0F4) // (US0) US IPNAME2 REGISTER -#define AT91C_US0_TTGR (AT91C_CAST(AT91C_REG *) 0xFFF8C028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_IF (AT91C_CAST(AT91C_REG *) 0xFFF8C04C) // (US0) IRDA_FILTER Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_PTCR (AT91C_CAST(AT91C_REG *) 0xFFF90120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TNCR (AT91C_CAST(AT91C_REG *) 0xFFF9011C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_RCR (AT91C_CAST(AT91C_REG *) 0xFFF90104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RPR (AT91C_CAST(AT91C_REG *) 0xFFF90100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TPR (AT91C_CAST(AT91C_REG *) 0xFFF90108) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_TCR (AT91C_CAST(AT91C_REG *) 0xFFF9010C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RNPR (AT91C_CAST(AT91C_REG *) 0xFFF90110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_TNPR (AT91C_CAST(AT91C_REG *) 0xFFF90118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RNCR (AT91C_CAST(AT91C_REG *) 0xFFF90114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTSR (AT91C_CAST(AT91C_REG *) 0xFFF90124) // (PDC_US1) PDC Transfer Status Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFF900F8) // (US1) US FEATURES REGISTER -#define AT91C_US1_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFF900EC) // (US1) US ADDRSIZE REGISTER -#define AT91C_US1_NER (AT91C_CAST(AT91C_REG *) 0xFFF90044) // (US1) Nb Errors Register -#define AT91C_US1_RHR (AT91C_CAST(AT91C_REG *) 0xFFF90018) // (US1) Receiver Holding Register -#define AT91C_US1_IF (AT91C_CAST(AT91C_REG *) 0xFFF9004C) // (US1) IRDA_FILTER Register -#define AT91C_US1_CR (AT91C_CAST(AT91C_REG *) 0xFFF90000) // (US1) Control Register -#define AT91C_US1_TTGR (AT91C_CAST(AT91C_REG *) 0xFFF90028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_MR (AT91C_CAST(AT91C_REG *) 0xFFF90004) // (US1) Mode Register -#define AT91C_US1_FIDI (AT91C_CAST(AT91C_REG *) 0xFFF90040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_RTOR (AT91C_CAST(AT91C_REG *) 0xFFF90024) // (US1) Receiver Time-out Register -#define AT91C_US1_IER (AT91C_CAST(AT91C_REG *) 0xFFF90008) // (US1) Interrupt Enable Register -#define AT91C_US1_MAN (AT91C_CAST(AT91C_REG *) 0xFFF90050) // (US1) Manchester Encoder Decoder Register -#define AT91C_US1_IPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFF900F4) // (US1) US IPNAME2 REGISTER -#define AT91C_US1_IMR (AT91C_CAST(AT91C_REG *) 0xFFF90010) // (US1) Interrupt Mask Register -#define AT91C_US1_IDR (AT91C_CAST(AT91C_REG *) 0xFFF9000C) // (US1) Interrupt Disable Register -#define AT91C_US1_CSR (AT91C_CAST(AT91C_REG *) 0xFFF90014) // (US1) Channel Status Register -#define AT91C_US1_BRGR (AT91C_CAST(AT91C_REG *) 0xFFF90020) // (US1) Baud Rate Generator Register -#define AT91C_US1_THR (AT91C_CAST(AT91C_REG *) 0xFFF9001C) // (US1) Transmitter Holding Register -#define AT91C_US1_VER (AT91C_CAST(AT91C_REG *) 0xFFF900FC) // (US1) VERSION Register -#define AT91C_US1_IPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFF900F0) // (US1) US IPNAME1 REGISTER -// ========== Register definition for PDC_US2 peripheral ========== -#define AT91C_US2_RNCR (AT91C_CAST(AT91C_REG *) 0xFFF94114) // (PDC_US2) Receive Next Counter Register -#define AT91C_US2_PTCR (AT91C_CAST(AT91C_REG *) 0xFFF94120) // (PDC_US2) PDC Transfer Control Register -#define AT91C_US2_TNPR (AT91C_CAST(AT91C_REG *) 0xFFF94118) // (PDC_US2) Transmit Next Pointer Register -#define AT91C_US2_TNCR (AT91C_CAST(AT91C_REG *) 0xFFF9411C) // (PDC_US2) Transmit Next Counter Register -#define AT91C_US2_TPR (AT91C_CAST(AT91C_REG *) 0xFFF94108) // (PDC_US2) Transmit Pointer Register -#define AT91C_US2_RCR (AT91C_CAST(AT91C_REG *) 0xFFF94104) // (PDC_US2) Receive Counter Register -#define AT91C_US2_PTSR (AT91C_CAST(AT91C_REG *) 0xFFF94124) // (PDC_US2) PDC Transfer Status Register -#define AT91C_US2_TCR (AT91C_CAST(AT91C_REG *) 0xFFF9410C) // (PDC_US2) Transmit Counter Register -#define AT91C_US2_RPR (AT91C_CAST(AT91C_REG *) 0xFFF94100) // (PDC_US2) Receive Pointer Register -#define AT91C_US2_RNPR (AT91C_CAST(AT91C_REG *) 0xFFF94110) // (PDC_US2) Receive Next Pointer Register -// ========== Register definition for US2 peripheral ========== -#define AT91C_US2_TTGR (AT91C_CAST(AT91C_REG *) 0xFFF94028) // (US2) Transmitter Time-guard Register -#define AT91C_US2_IER (AT91C_CAST(AT91C_REG *) 0xFFF94008) // (US2) Interrupt Enable Register -#define AT91C_US2_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFF940EC) // (US2) US ADDRSIZE REGISTER -#define AT91C_US2_NER (AT91C_CAST(AT91C_REG *) 0xFFF94044) // (US2) Nb Errors Register -#define AT91C_US2_CR (AT91C_CAST(AT91C_REG *) 0xFFF94000) // (US2) Control Register -#define AT91C_US2_IDR (AT91C_CAST(AT91C_REG *) 0xFFF9400C) // (US2) Interrupt Disable Register -#define AT91C_US2_VER (AT91C_CAST(AT91C_REG *) 0xFFF940FC) // (US2) VERSION Register -#define AT91C_US2_THR (AT91C_CAST(AT91C_REG *) 0xFFF9401C) // (US2) Transmitter Holding Register -#define AT91C_US2_BRGR (AT91C_CAST(AT91C_REG *) 0xFFF94020) // (US2) Baud Rate Generator Register -#define AT91C_US2_CSR (AT91C_CAST(AT91C_REG *) 0xFFF94014) // (US2) Channel Status Register -#define AT91C_US2_IPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFF940F4) // (US2) US IPNAME2 REGISTER -#define AT91C_US2_IMR (AT91C_CAST(AT91C_REG *) 0xFFF94010) // (US2) Interrupt Mask Register -#define AT91C_US2_RHR (AT91C_CAST(AT91C_REG *) 0xFFF94018) // (US2) Receiver Holding Register -#define AT91C_US2_MR (AT91C_CAST(AT91C_REG *) 0xFFF94004) // (US2) Mode Register -#define AT91C_US2_FIDI (AT91C_CAST(AT91C_REG *) 0xFFF94040) // (US2) FI_DI_Ratio Register -#define AT91C_US2_MAN (AT91C_CAST(AT91C_REG *) 0xFFF94050) // (US2) Manchester Encoder Decoder Register -#define AT91C_US2_IF (AT91C_CAST(AT91C_REG *) 0xFFF9404C) // (US2) IRDA_FILTER Register -#define AT91C_US2_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFF940F8) // (US2) US FEATURES REGISTER -#define AT91C_US2_IPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFF940F0) // (US2) US IPNAME1 REGISTER -#define AT91C_US2_RTOR (AT91C_CAST(AT91C_REG *) 0xFFF94024) // (US2) Receiver Time-out Register -// ========== Register definition for PDC_US3 peripheral ========== -#define AT91C_US3_PTSR (AT91C_CAST(AT91C_REG *) 0xFFF98124) // (PDC_US3) PDC Transfer Status Register -#define AT91C_US3_TCR (AT91C_CAST(AT91C_REG *) 0xFFF9810C) // (PDC_US3) Transmit Counter Register -#define AT91C_US3_RNPR (AT91C_CAST(AT91C_REG *) 0xFFF98110) // (PDC_US3) Receive Next Pointer Register -#define AT91C_US3_RNCR (AT91C_CAST(AT91C_REG *) 0xFFF98114) // (PDC_US3) Receive Next Counter Register -#define AT91C_US3_TNPR (AT91C_CAST(AT91C_REG *) 0xFFF98118) // (PDC_US3) Transmit Next Pointer Register -#define AT91C_US3_RPR (AT91C_CAST(AT91C_REG *) 0xFFF98100) // (PDC_US3) Receive Pointer Register -#define AT91C_US3_TPR (AT91C_CAST(AT91C_REG *) 0xFFF98108) // (PDC_US3) Transmit Pointer Register -#define AT91C_US3_RCR (AT91C_CAST(AT91C_REG *) 0xFFF98104) // (PDC_US3) Receive Counter Register -#define AT91C_US3_TNCR (AT91C_CAST(AT91C_REG *) 0xFFF9811C) // (PDC_US3) Transmit Next Counter Register -#define AT91C_US3_PTCR (AT91C_CAST(AT91C_REG *) 0xFFF98120) // (PDC_US3) PDC Transfer Control Register -// ========== Register definition for US3 peripheral ========== -#define AT91C_US3_VER (AT91C_CAST(AT91C_REG *) 0xFFF980FC) // (US3) VERSION Register -#define AT91C_US3_BRGR (AT91C_CAST(AT91C_REG *) 0xFFF98020) // (US3) Baud Rate Generator Register -#define AT91C_US3_TTGR (AT91C_CAST(AT91C_REG *) 0xFFF98028) // (US3) Transmitter Time-guard Register -#define AT91C_US3_RTOR (AT91C_CAST(AT91C_REG *) 0xFFF98024) // (US3) Receiver Time-out Register -#define AT91C_US3_MAN (AT91C_CAST(AT91C_REG *) 0xFFF98050) // (US3) Manchester Encoder Decoder Register -#define AT91C_US3_NER (AT91C_CAST(AT91C_REG *) 0xFFF98044) // (US3) Nb Errors Register -#define AT91C_US3_CR (AT91C_CAST(AT91C_REG *) 0xFFF98000) // (US3) Control Register -#define AT91C_US3_IDR (AT91C_CAST(AT91C_REG *) 0xFFF9800C) // (US3) Interrupt Disable Register -#define AT91C_US3_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFF980EC) // (US3) US ADDRSIZE REGISTER -#define AT91C_US3_CSR (AT91C_CAST(AT91C_REG *) 0xFFF98014) // (US3) Channel Status Register -#define AT91C_US3_IPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFF980F4) // (US3) US IPNAME2 REGISTER -#define AT91C_US3_IER (AT91C_CAST(AT91C_REG *) 0xFFF98008) // (US3) Interrupt Enable Register -#define AT91C_US3_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFF980F8) // (US3) US FEATURES REGISTER -#define AT91C_US3_MR (AT91C_CAST(AT91C_REG *) 0xFFF98004) // (US3) Mode Register -#define AT91C_US3_IF (AT91C_CAST(AT91C_REG *) 0xFFF9804C) // (US3) IRDA_FILTER Register -#define AT91C_US3_THR (AT91C_CAST(AT91C_REG *) 0xFFF9801C) // (US3) Transmitter Holding Register -#define AT91C_US3_IMR (AT91C_CAST(AT91C_REG *) 0xFFF98010) // (US3) Interrupt Mask Register -#define AT91C_US3_FIDI (AT91C_CAST(AT91C_REG *) 0xFFF98040) // (US3) FI_DI_Ratio Register -#define AT91C_US3_RHR (AT91C_CAST(AT91C_REG *) 0xFFF98018) // (US3) Receiver Holding Register -#define AT91C_US3_IPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFF980F0) // (US3) US IPNAME1 REGISTER -// ========== Register definition for PDC_SSC0 peripheral ========== -#define AT91C_SSC0_TNPR (AT91C_CAST(AT91C_REG *) 0xFFF9C118) // (PDC_SSC0) Transmit Next Pointer Register -#define AT91C_SSC0_PTSR (AT91C_CAST(AT91C_REG *) 0xFFF9C124) // (PDC_SSC0) PDC Transfer Status Register -#define AT91C_SSC0_TNCR (AT91C_CAST(AT91C_REG *) 0xFFF9C11C) // (PDC_SSC0) Transmit Next Counter Register -#define AT91C_SSC0_RNCR (AT91C_CAST(AT91C_REG *) 0xFFF9C114) // (PDC_SSC0) Receive Next Counter Register -#define AT91C_SSC0_TPR (AT91C_CAST(AT91C_REG *) 0xFFF9C108) // (PDC_SSC0) Transmit Pointer Register -#define AT91C_SSC0_RCR (AT91C_CAST(AT91C_REG *) 0xFFF9C104) // (PDC_SSC0) Receive Counter Register -#define AT91C_SSC0_PTCR (AT91C_CAST(AT91C_REG *) 0xFFF9C120) // (PDC_SSC0) PDC Transfer Control Register -#define AT91C_SSC0_RNPR (AT91C_CAST(AT91C_REG *) 0xFFF9C110) // (PDC_SSC0) Receive Next Pointer Register -#define AT91C_SSC0_TCR (AT91C_CAST(AT91C_REG *) 0xFFF9C10C) // (PDC_SSC0) Transmit Counter Register -#define AT91C_SSC0_RPR (AT91C_CAST(AT91C_REG *) 0xFFF9C100) // (PDC_SSC0) Receive Pointer Register -// ========== Register definition for SSC0 peripheral ========== -#define AT91C_SSC0_IPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFF9C0F4) // (SSC0) SSC IPNAME2 REGISTER -#define AT91C_SSC0_SR (AT91C_CAST(AT91C_REG *) 0xFFF9C040) // (SSC0) Status Register -#define AT91C_SSC0_TSHR (AT91C_CAST(AT91C_REG *) 0xFFF9C034) // (SSC0) Transmit Sync Holding Register -#define AT91C_SSC0_TCMR (AT91C_CAST(AT91C_REG *) 0xFFF9C018) // (SSC0) Transmit Clock Mode Register -#define AT91C_SSC0_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFF9C0EC) // (SSC0) SSC ADDRSIZE REGISTER -#define AT91C_SSC0_IMR (AT91C_CAST(AT91C_REG *) 0xFFF9C04C) // (SSC0) Interrupt Mask Register -#define AT91C_SSC0_IDR (AT91C_CAST(AT91C_REG *) 0xFFF9C048) // (SSC0) Interrupt Disable Register -#define AT91C_SSC0_CR (AT91C_CAST(AT91C_REG *) 0xFFF9C000) // (SSC0) Control Register -#define AT91C_SSC0_VER (AT91C_CAST(AT91C_REG *) 0xFFF9C0FC) // (SSC0) Version Register -#define AT91C_SSC0_RHR (AT91C_CAST(AT91C_REG *) 0xFFF9C020) // (SSC0) Receive Holding Register -#define AT91C_SSC0_THR (AT91C_CAST(AT91C_REG *) 0xFFF9C024) // (SSC0) Transmit Holding Register -#define AT91C_SSC0_CMR (AT91C_CAST(AT91C_REG *) 0xFFF9C004) // (SSC0) Clock Mode Register -#define AT91C_SSC0_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFF9C0F8) // (SSC0) SSC FEATURES REGISTER -#define AT91C_SSC0_RCMR (AT91C_CAST(AT91C_REG *) 0xFFF9C010) // (SSC0) Receive Clock ModeRegister -#define AT91C_SSC0_IPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFF9C0F0) // (SSC0) SSC IPNAME1 REGISTER -#define AT91C_SSC0_RSHR (AT91C_CAST(AT91C_REG *) 0xFFF9C030) // (SSC0) Receive Sync Holding Register -#define AT91C_SSC0_IER (AT91C_CAST(AT91C_REG *) 0xFFF9C044) // (SSC0) Interrupt Enable Register -#define AT91C_SSC0_TFMR (AT91C_CAST(AT91C_REG *) 0xFFF9C01C) // (SSC0) Transmit Frame Mode Register -#define AT91C_SSC0_RFMR (AT91C_CAST(AT91C_REG *) 0xFFF9C014) // (SSC0) Receive Frame Mode Register -// ========== Register definition for PDC_SSC1 peripheral ========== -#define AT91C_SSC1_RNPR (AT91C_CAST(AT91C_REG *) 0xFFFA0110) // (PDC_SSC1) Receive Next Pointer Register -#define AT91C_SSC1_TCR (AT91C_CAST(AT91C_REG *) 0xFFFA010C) // (PDC_SSC1) Transmit Counter Register -#define AT91C_SSC1_TNCR (AT91C_CAST(AT91C_REG *) 0xFFFA011C) // (PDC_SSC1) Transmit Next Counter Register -#define AT91C_SSC1_RCR (AT91C_CAST(AT91C_REG *) 0xFFFA0104) // (PDC_SSC1) Receive Counter Register -#define AT91C_SSC1_RNCR (AT91C_CAST(AT91C_REG *) 0xFFFA0114) // (PDC_SSC1) Receive Next Counter Register -#define AT91C_SSC1_PTCR (AT91C_CAST(AT91C_REG *) 0xFFFA0120) // (PDC_SSC1) PDC Transfer Control Register -#define AT91C_SSC1_TPR (AT91C_CAST(AT91C_REG *) 0xFFFA0108) // (PDC_SSC1) Transmit Pointer Register -#define AT91C_SSC1_RPR (AT91C_CAST(AT91C_REG *) 0xFFFA0100) // (PDC_SSC1) Receive Pointer Register -#define AT91C_SSC1_PTSR (AT91C_CAST(AT91C_REG *) 0xFFFA0124) // (PDC_SSC1) PDC Transfer Status Register -#define AT91C_SSC1_TNPR (AT91C_CAST(AT91C_REG *) 0xFFFA0118) // (PDC_SSC1) Transmit Next Pointer Register -// ========== Register definition for SSC1 peripheral ========== -#define AT91C_SSC1_SR (AT91C_CAST(AT91C_REG *) 0xFFFA0040) // (SSC1) Status Register -#define AT91C_SSC1_TFMR (AT91C_CAST(AT91C_REG *) 0xFFFA001C) // (SSC1) Transmit Frame Mode Register -#define AT91C_SSC1_IPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFFA00F0) // (SSC1) SSC IPNAME1 REGISTER -#define AT91C_SSC1_CMR (AT91C_CAST(AT91C_REG *) 0xFFFA0004) // (SSC1) Clock Mode Register -#define AT91C_SSC1_THR (AT91C_CAST(AT91C_REG *) 0xFFFA0024) // (SSC1) Transmit Holding Register -#define AT91C_SSC1_FEATURES (AT91C_CAST(AT91C_REG *) 0xFFFA00F8) // (SSC1) SSC FEATURES REGISTER -#define AT91C_SSC1_TSHR (AT91C_CAST(AT91C_REG *) 0xFFFA0034) // (SSC1) Transmit Sync Holding Register -#define AT91C_SSC1_RCMR (AT91C_CAST(AT91C_REG *) 0xFFFA0010) // (SSC1) Receive Clock ModeRegister -#define AT91C_SSC1_RHR (AT91C_CAST(AT91C_REG *) 0xFFFA0020) // (SSC1) Receive Holding Register -#define AT91C_SSC1_VER (AT91C_CAST(AT91C_REG *) 0xFFFA00FC) // (SSC1) Version Register -#define AT91C_SSC1_TCMR (AT91C_CAST(AT91C_REG *) 0xFFFA0018) // (SSC1) Transmit Clock Mode Register -#define AT91C_SSC1_CR (AT91C_CAST(AT91C_REG *) 0xFFFA0000) // (SSC1) Control Register -#define AT91C_SSC1_RSHR (AT91C_CAST(AT91C_REG *) 0xFFFA0030) // (SSC1) Receive Sync Holding Register -#define AT91C_SSC1_IER (AT91C_CAST(AT91C_REG *) 0xFFFA0044) // (SSC1) Interrupt Enable Register -#define AT91C_SSC1_ADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFFA00EC) // (SSC1) SSC ADDRSIZE REGISTER -#define AT91C_SSC1_RFMR (AT91C_CAST(AT91C_REG *) 0xFFFA0014) // (SSC1) Receive Frame Mode Register -#define AT91C_SSC1_IMR (AT91C_CAST(AT91C_REG *) 0xFFFA004C) // (SSC1) Interrupt Mask Register -#define AT91C_SSC1_IDR (AT91C_CAST(AT91C_REG *) 0xFFFA0048) // (SSC1) Interrupt Disable Register -#define AT91C_SSC1_IPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFFA00F4) // (SSC1) SSC IPNAME2 REGISTER -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_CCNTR (AT91C_CAST(AT91C_REG *) 0xFFFB820C) // (PWMC_CH0) Channel Counter Register -#define AT91C_PWMC_CH0_CPRDR (AT91C_CAST(AT91C_REG *) 0xFFFB8208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CUPDR (AT91C_CAST(AT91C_REG *) 0xFFFB8210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CDTYR (AT91C_CAST(AT91C_REG *) 0xFFFB8204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (AT91C_CAST(AT91C_REG *) 0xFFFB8200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_Reserved (AT91C_CAST(AT91C_REG *) 0xFFFB8214) // (PWMC_CH0) Reserved -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_CCNTR (AT91C_CAST(AT91C_REG *) 0xFFFB822C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (AT91C_CAST(AT91C_REG *) 0xFFFB8224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (AT91C_CAST(AT91C_REG *) 0xFFFB8220) // (PWMC_CH1) Channel Mode Register -#define AT91C_PWMC_CH1_CPRDR (AT91C_CAST(AT91C_REG *) 0xFFFB8228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_Reserved (AT91C_CAST(AT91C_REG *) 0xFFFB8234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (AT91C_CAST(AT91C_REG *) 0xFFFB8230) // (PWMC_CH1) Channel Update Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_CUPDR (AT91C_CAST(AT91C_REG *) 0xFFFB8250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CMR (AT91C_CAST(AT91C_REG *) 0xFFFB8240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_Reserved (AT91C_CAST(AT91C_REG *) 0xFFFB8254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CPRDR (AT91C_CAST(AT91C_REG *) 0xFFFB8248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CDTYR (AT91C_CAST(AT91C_REG *) 0xFFFB8244) // (PWMC_CH2) Channel Duty Cycle Register -#define AT91C_PWMC_CH2_CCNTR (AT91C_CAST(AT91C_REG *) 0xFFFB824C) // (PWMC_CH2) Channel Counter Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CPRDR (AT91C_CAST(AT91C_REG *) 0xFFFB8268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_Reserved (AT91C_CAST(AT91C_REG *) 0xFFFB8274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CUPDR (AT91C_CAST(AT91C_REG *) 0xFFFB8270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_CDTYR (AT91C_CAST(AT91C_REG *) 0xFFFB8264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (AT91C_CAST(AT91C_REG *) 0xFFFB826C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (AT91C_CAST(AT91C_REG *) 0xFFFB8260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (AT91C_CAST(AT91C_REG *) 0xFFFB8014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_MR (AT91C_CAST(AT91C_REG *) 0xFFFB8000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_VR (AT91C_CAST(AT91C_REG *) 0xFFFB80FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_IMR (AT91C_CAST(AT91C_REG *) 0xFFFB8018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_SR (AT91C_CAST(AT91C_REG *) 0xFFFB800C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_ISR (AT91C_CAST(AT91C_REG *) 0xFFFB801C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_ENA (AT91C_CAST(AT91C_REG *) 0xFFFB8004) // (PWMC) PWMC Enable Register -#define AT91C_PWMC_IER (AT91C_CAST(AT91C_REG *) 0xFFFB8010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_DIS (AT91C_CAST(AT91C_REG *) 0xFFFB8008) // (PWMC) PWMC Disable Register -// ========== Register definition for PDC_SPI0 peripheral ========== -#define AT91C_SPI0_TPR (AT91C_CAST(AT91C_REG *) 0xFFFA4108) // (PDC_SPI0) Transmit Pointer Register -#define AT91C_SPI0_PTCR (AT91C_CAST(AT91C_REG *) 0xFFFA4120) // (PDC_SPI0) PDC Transfer Control Register -#define AT91C_SPI0_RNPR (AT91C_CAST(AT91C_REG *) 0xFFFA4110) // (PDC_SPI0) Receive Next Pointer Register -#define AT91C_SPI0_TNCR (AT91C_CAST(AT91C_REG *) 0xFFFA411C) // (PDC_SPI0) Transmit Next Counter Register -#define AT91C_SPI0_TCR (AT91C_CAST(AT91C_REG *) 0xFFFA410C) // (PDC_SPI0) Transmit Counter Register -#define AT91C_SPI0_RCR (AT91C_CAST(AT91C_REG *) 0xFFFA4104) // (PDC_SPI0) Receive Counter Register -#define AT91C_SPI0_RNCR (AT91C_CAST(AT91C_REG *) 0xFFFA4114) // (PDC_SPI0) Receive Next Counter Register -#define AT91C_SPI0_TNPR (AT91C_CAST(AT91C_REG *) 0xFFFA4118) // (PDC_SPI0) Transmit Next Pointer Register -#define AT91C_SPI0_RPR (AT91C_CAST(AT91C_REG *) 0xFFFA4100) // (PDC_SPI0) Receive Pointer Register -#define AT91C_SPI0_PTSR (AT91C_CAST(AT91C_REG *) 0xFFFA4124) // (PDC_SPI0) PDC Transfer Status Register -// ========== Register definition for PDC_SPI1 peripheral ========== -#define AT91C_SPI1_RNCR (AT91C_CAST(AT91C_REG *) 0xFFFA8114) // (PDC_SPI1) Receive Next Counter Register -#define AT91C_SPI1_TCR (AT91C_CAST(AT91C_REG *) 0xFFFA810C) // (PDC_SPI1) Transmit Counter Register -#define AT91C_SPI1_RCR (AT91C_CAST(AT91C_REG *) 0xFFFA8104) // (PDC_SPI1) Receive Counter Register -#define AT91C_SPI1_TNPR (AT91C_CAST(AT91C_REG *) 0xFFFA8118) // (PDC_SPI1) Transmit Next Pointer Register -#define AT91C_SPI1_RNPR (AT91C_CAST(AT91C_REG *) 0xFFFA8110) // (PDC_SPI1) Receive Next Pointer Register -#define AT91C_SPI1_RPR (AT91C_CAST(AT91C_REG *) 0xFFFA8100) // (PDC_SPI1) Receive Pointer Register -#define AT91C_SPI1_TNCR (AT91C_CAST(AT91C_REG *) 0xFFFA811C) // (PDC_SPI1) Transmit Next Counter Register -#define AT91C_SPI1_TPR (AT91C_CAST(AT91C_REG *) 0xFFFA8108) // (PDC_SPI1) Transmit Pointer Register -#define AT91C_SPI1_PTSR (AT91C_CAST(AT91C_REG *) 0xFFFA8124) // (PDC_SPI1) PDC Transfer Status Register -#define AT91C_SPI1_PTCR (AT91C_CAST(AT91C_REG *) 0xFFFA8120) // (PDC_SPI1) PDC Transfer Control Register -// ========== Register definition for SPI0 peripheral ========== -#define AT91C_SPI0_MR (AT91C_CAST(AT91C_REG *) 0xFFFA4004) // (SPI0) Mode Register -#define AT91C_SPI0_RDR (AT91C_CAST(AT91C_REG *) 0xFFFA4008) // (SPI0) Receive Data Register -#define AT91C_SPI0_CR (AT91C_CAST(AT91C_REG *) 0xFFFA4000) // (SPI0) Control Register -#define AT91C_SPI0_IER (AT91C_CAST(AT91C_REG *) 0xFFFA4014) // (SPI0) Interrupt Enable Register -#define AT91C_SPI0_TDR (AT91C_CAST(AT91C_REG *) 0xFFFA400C) // (SPI0) Transmit Data Register -#define AT91C_SPI0_IDR (AT91C_CAST(AT91C_REG *) 0xFFFA4018) // (SPI0) Interrupt Disable Register -#define AT91C_SPI0_CSR (AT91C_CAST(AT91C_REG *) 0xFFFA4030) // (SPI0) Chip Select Register -#define AT91C_SPI0_SR (AT91C_CAST(AT91C_REG *) 0xFFFA4010) // (SPI0) Status Register -#define AT91C_SPI0_IMR (AT91C_CAST(AT91C_REG *) 0xFFFA401C) // (SPI0) Interrupt Mask Register -// ========== Register definition for SPI1 peripheral ========== -#define AT91C_SPI1_CSR (AT91C_CAST(AT91C_REG *) 0xFFFA8030) // (SPI1) Chip Select Register -#define AT91C_SPI1_IER (AT91C_CAST(AT91C_REG *) 0xFFFA8014) // (SPI1) Interrupt Enable Register -#define AT91C_SPI1_RDR (AT91C_CAST(AT91C_REG *) 0xFFFA8008) // (SPI1) Receive Data Register -#define AT91C_SPI1_IDR (AT91C_CAST(AT91C_REG *) 0xFFFA8018) // (SPI1) Interrupt Disable Register -#define AT91C_SPI1_MR (AT91C_CAST(AT91C_REG *) 0xFFFA8004) // (SPI1) Mode Register -#define AT91C_SPI1_CR (AT91C_CAST(AT91C_REG *) 0xFFFA8000) // (SPI1) Control Register -#define AT91C_SPI1_SR (AT91C_CAST(AT91C_REG *) 0xFFFA8010) // (SPI1) Status Register -#define AT91C_SPI1_TDR (AT91C_CAST(AT91C_REG *) 0xFFFA800C) // (SPI1) Transmit Data Register -#define AT91C_SPI1_IMR (AT91C_CAST(AT91C_REG *) 0xFFFA801C) // (SPI1) Interrupt Mask Register -// ========== Register definition for PDC_TSADC peripheral ========== -#define AT91C_TSADC_TCR (AT91C_CAST(AT91C_REG *) 0xFFFB010C) // (PDC_TSADC) Transmit Counter Register -#define AT91C_TSADC_PTCR (AT91C_CAST(AT91C_REG *) 0xFFFB0120) // (PDC_TSADC) PDC Transfer Control Register -#define AT91C_TSADC_RNCR (AT91C_CAST(AT91C_REG *) 0xFFFB0114) // (PDC_TSADC) Receive Next Counter Register -#define AT91C_TSADC_PTSR (AT91C_CAST(AT91C_REG *) 0xFFFB0124) // (PDC_TSADC) PDC Transfer Status Register -#define AT91C_TSADC_TNCR (AT91C_CAST(AT91C_REG *) 0xFFFB011C) // (PDC_TSADC) Transmit Next Counter Register -#define AT91C_TSADC_RNPR (AT91C_CAST(AT91C_REG *) 0xFFFB0110) // (PDC_TSADC) Receive Next Pointer Register -#define AT91C_TSADC_RCR (AT91C_CAST(AT91C_REG *) 0xFFFB0104) // (PDC_TSADC) Receive Counter Register -#define AT91C_TSADC_TPR (AT91C_CAST(AT91C_REG *) 0xFFFB0108) // (PDC_TSADC) Transmit Pointer Register -#define AT91C_TSADC_TNPR (AT91C_CAST(AT91C_REG *) 0xFFFB0118) // (PDC_TSADC) Transmit Next Pointer Register -#define AT91C_TSADC_RPR (AT91C_CAST(AT91C_REG *) 0xFFFB0100) // (PDC_TSADC) Receive Pointer Register -// ========== Register definition for TSADC peripheral ========== -#define AT91C_TSADC_CHSR (AT91C_CAST(AT91C_REG *) 0xFFFB0018) // (TSADC) Channel Status Register -#define AT91C_TSADC_CDR5 (AT91C_CAST(AT91C_REG *) 0xFFFB0044) // (TSADC) Channel Data Register 5 -#define AT91C_TSADC_CR (AT91C_CAST(AT91C_REG *) 0xFFFB0000) // (TSADC) Control Register -#define AT91C_TSADC_IMR (AT91C_CAST(AT91C_REG *) 0xFFFB002C) // (TSADC) Interrupt Mask Register -#define AT91C_TSADC_CHDR (AT91C_CAST(AT91C_REG *) 0xFFFB0014) // (TSADC) Channel Disable Register -#define AT91C_TSADC_LCDR (AT91C_CAST(AT91C_REG *) 0xFFFB0020) // (TSADC) Last Converted Register -#define AT91C_TSADC_IER (AT91C_CAST(AT91C_REG *) 0xFFFB0024) // (TSADC) Interrupt Enable Register -#define AT91C_TSADC_TSR (AT91C_CAST(AT91C_REG *) 0xFFFB000C) // (TSADC) Touch Screen Register -#define AT91C_TSADC_CDR2 (AT91C_CAST(AT91C_REG *) 0xFFFB0038) // (TSADC) Channel Data Register 2 -#define AT91C_TSADC_CDR4 (AT91C_CAST(AT91C_REG *) 0xFFFB0040) // (TSADC) Channel Data Register 4 -#define AT91C_TSADC_CHER (AT91C_CAST(AT91C_REG *) 0xFFFB0010) // (TSADC) Channel Enable Register -#define AT91C_TSADC_TRGR (AT91C_CAST(AT91C_REG *) 0xFFFB0008) // (TSADC) Trigger Register -#define AT91C_TSADC_CDR3 (AT91C_CAST(AT91C_REG *) 0xFFFB003C) // (TSADC) Channel Data Register 3 -#define AT91C_TSADC_SR (AT91C_CAST(AT91C_REG *) 0xFFFB001C) // (TSADC) Status Register -#define AT91C_TSADC_CDR0 (AT91C_CAST(AT91C_REG *) 0xFFFB0030) // (TSADC) Channel Data Register 0 -#define AT91C_TSADC_CDR6 (AT91C_CAST(AT91C_REG *) 0xFFFB0048) // (TSADC) Channel Data Register 6 -#define AT91C_TSADC_IDR (AT91C_CAST(AT91C_REG *) 0xFFFB0028) // (TSADC) Interrupt Disable Register -#define AT91C_TSADC_MR (AT91C_CAST(AT91C_REG *) 0xFFFB0004) // (TSADC) Mode Register -#define AT91C_TSADC_CDR7 (AT91C_CAST(AT91C_REG *) 0xFFFB004C) // (TSADC) Channel Data Register 7 -#define AT91C_TSADC_CDR1 (AT91C_CAST(AT91C_REG *) 0xFFFB0034) // (TSADC) Channel Data Register 1 -// ========== Register definition for UDPHS_EPTFIFO peripheral ========== -#define AT91C_UDPHS_EPTFIFO_READEPT3 (AT91C_CAST(AT91C_REG *) 0x00630000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 3 -#define AT91C_UDPHS_EPTFIFO_READEPT5 (AT91C_CAST(AT91C_REG *) 0x00650000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 5 -#define AT91C_UDPHS_EPTFIFO_READEPT1 (AT91C_CAST(AT91C_REG *) 0x00610000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 1 -#define AT91C_UDPHS_EPTFIFO_READEPT0 (AT91C_CAST(AT91C_REG *) 0x00600000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 0 -#define AT91C_UDPHS_EPTFIFO_READEPT6 (AT91C_CAST(AT91C_REG *) 0x00660000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 6 -#define AT91C_UDPHS_EPTFIFO_READEPT2 (AT91C_CAST(AT91C_REG *) 0x00620000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 2 -#define AT91C_UDPHS_EPTFIFO_READEPT4 (AT91C_CAST(AT91C_REG *) 0x00640000) // (UDPHS_EPTFIFO) FIFO Endpoint Data Register 4 -// ========== Register definition for UDPHS_EPT_0 peripheral ========== -#define AT91C_UDPHS_EPT_0_EPTSTA (AT91C_CAST(AT91C_REG *) 0xFFF7811C) // (UDPHS_EPT_0) UDPHS Endpoint Status Register -#define AT91C_UDPHS_EPT_0_EPTCTL (AT91C_CAST(AT91C_REG *) 0xFFF7810C) // (UDPHS_EPT_0) UDPHS Endpoint Control Register -#define AT91C_UDPHS_EPT_0_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 0xFFF78108) // (UDPHS_EPT_0) UDPHS Endpoint Control Disable Register -#define AT91C_UDPHS_EPT_0_EPTCFG (AT91C_CAST(AT91C_REG *) 0xFFF78100) // (UDPHS_EPT_0) UDPHS Endpoint Config Register -#define AT91C_UDPHS_EPT_0_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 0xFFF78118) // (UDPHS_EPT_0) UDPHS Endpoint Clear Status Register -#define AT91C_UDPHS_EPT_0_EPTSETSTA (AT91C_CAST(AT91C_REG *) 0xFFF78114) // (UDPHS_EPT_0) UDPHS Endpoint Set Status Register -#define AT91C_UDPHS_EPT_0_EPTCTLENB (AT91C_CAST(AT91C_REG *) 0xFFF78104) // (UDPHS_EPT_0) UDPHS Endpoint Control Enable Register -// ========== Register definition for UDPHS_EPT_1 peripheral ========== -#define AT91C_UDPHS_EPT_1_EPTCTLENB (AT91C_CAST(AT91C_REG *) 0xFFF78124) // (UDPHS_EPT_1) UDPHS Endpoint Control Enable Register -#define AT91C_UDPHS_EPT_1_EPTCFG (AT91C_CAST(AT91C_REG *) 0xFFF78120) // (UDPHS_EPT_1) UDPHS Endpoint Config Register -#define AT91C_UDPHS_EPT_1_EPTCTL (AT91C_CAST(AT91C_REG *) 0xFFF7812C) // (UDPHS_EPT_1) UDPHS Endpoint Control Register -#define AT91C_UDPHS_EPT_1_EPTSTA (AT91C_CAST(AT91C_REG *) 0xFFF7813C) // (UDPHS_EPT_1) UDPHS Endpoint Status Register -#define AT91C_UDPHS_EPT_1_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 0xFFF78138) // (UDPHS_EPT_1) UDPHS Endpoint Clear Status Register -#define AT91C_UDPHS_EPT_1_EPTSETSTA (AT91C_CAST(AT91C_REG *) 0xFFF78134) // (UDPHS_EPT_1) UDPHS Endpoint Set Status Register -#define AT91C_UDPHS_EPT_1_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 0xFFF78128) // (UDPHS_EPT_1) UDPHS Endpoint Control Disable Register -// ========== Register definition for UDPHS_EPT_2 peripheral ========== -#define AT91C_UDPHS_EPT_2_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 0xFFF78158) // (UDPHS_EPT_2) UDPHS Endpoint Clear Status Register -#define AT91C_UDPHS_EPT_2_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 0xFFF78148) // (UDPHS_EPT_2) UDPHS Endpoint Control Disable Register -#define AT91C_UDPHS_EPT_2_EPTSTA (AT91C_CAST(AT91C_REG *) 0xFFF7815C) // (UDPHS_EPT_2) UDPHS Endpoint Status Register -#define AT91C_UDPHS_EPT_2_EPTSETSTA (AT91C_CAST(AT91C_REG *) 0xFFF78154) // (UDPHS_EPT_2) UDPHS Endpoint Set Status Register -#define AT91C_UDPHS_EPT_2_EPTCTL (AT91C_CAST(AT91C_REG *) 0xFFF7814C) // (UDPHS_EPT_2) UDPHS Endpoint Control Register -#define AT91C_UDPHS_EPT_2_EPTCFG (AT91C_CAST(AT91C_REG *) 0xFFF78140) // (UDPHS_EPT_2) UDPHS Endpoint Config Register -#define AT91C_UDPHS_EPT_2_EPTCTLENB (AT91C_CAST(AT91C_REG *) 0xFFF78144) // (UDPHS_EPT_2) UDPHS Endpoint Control Enable Register -// ========== Register definition for UDPHS_EPT_3 peripheral ========== -#define AT91C_UDPHS_EPT_3_EPTCTL (AT91C_CAST(AT91C_REG *) 0xFFF7816C) // (UDPHS_EPT_3) UDPHS Endpoint Control Register -#define AT91C_UDPHS_EPT_3_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 0xFFF78178) // (UDPHS_EPT_3) UDPHS Endpoint Clear Status Register -#define AT91C_UDPHS_EPT_3_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 0xFFF78168) // (UDPHS_EPT_3) UDPHS Endpoint Control Disable Register -#define AT91C_UDPHS_EPT_3_EPTSTA (AT91C_CAST(AT91C_REG *) 0xFFF7817C) // (UDPHS_EPT_3) UDPHS Endpoint Status Register -#define AT91C_UDPHS_EPT_3_EPTSETSTA (AT91C_CAST(AT91C_REG *) 0xFFF78174) // (UDPHS_EPT_3) UDPHS Endpoint Set Status Register -#define AT91C_UDPHS_EPT_3_EPTCTLENB (AT91C_CAST(AT91C_REG *) 0xFFF78164) // (UDPHS_EPT_3) UDPHS Endpoint Control Enable Register -#define AT91C_UDPHS_EPT_3_EPTCFG (AT91C_CAST(AT91C_REG *) 0xFFF78160) // (UDPHS_EPT_3) UDPHS Endpoint Config Register -// ========== Register definition for UDPHS_EPT_4 peripheral ========== -#define AT91C_UDPHS_EPT_4_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 0xFFF78198) // (UDPHS_EPT_4) UDPHS Endpoint Clear Status Register -#define AT91C_UDPHS_EPT_4_EPTCTL (AT91C_CAST(AT91C_REG *) 0xFFF7818C) // (UDPHS_EPT_4) UDPHS Endpoint Control Register -#define AT91C_UDPHS_EPT_4_EPTCTLENB (AT91C_CAST(AT91C_REG *) 0xFFF78184) // (UDPHS_EPT_4) UDPHS Endpoint Control Enable Register -#define AT91C_UDPHS_EPT_4_EPTSTA (AT91C_CAST(AT91C_REG *) 0xFFF7819C) // (UDPHS_EPT_4) UDPHS Endpoint Status Register -#define AT91C_UDPHS_EPT_4_EPTSETSTA (AT91C_CAST(AT91C_REG *) 0xFFF78194) // (UDPHS_EPT_4) UDPHS Endpoint Set Status Register -#define AT91C_UDPHS_EPT_4_EPTCFG (AT91C_CAST(AT91C_REG *) 0xFFF78180) // (UDPHS_EPT_4) UDPHS Endpoint Config Register -#define AT91C_UDPHS_EPT_4_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 0xFFF78188) // (UDPHS_EPT_4) UDPHS Endpoint Control Disable Register -// ========== Register definition for UDPHS_EPT_5 peripheral ========== -#define AT91C_UDPHS_EPT_5_EPTSTA (AT91C_CAST(AT91C_REG *) 0xFFF781BC) // (UDPHS_EPT_5) UDPHS Endpoint Status Register -#define AT91C_UDPHS_EPT_5_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 0xFFF781B8) // (UDPHS_EPT_5) UDPHS Endpoint Clear Status Register -#define AT91C_UDPHS_EPT_5_EPTCTLENB (AT91C_CAST(AT91C_REG *) 0xFFF781A4) // (UDPHS_EPT_5) UDPHS Endpoint Control Enable Register -#define AT91C_UDPHS_EPT_5_EPTSETSTA (AT91C_CAST(AT91C_REG *) 0xFFF781B4) // (UDPHS_EPT_5) UDPHS Endpoint Set Status Register -#define AT91C_UDPHS_EPT_5_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 0xFFF781A8) // (UDPHS_EPT_5) UDPHS Endpoint Control Disable Register -#define AT91C_UDPHS_EPT_5_EPTCFG (AT91C_CAST(AT91C_REG *) 0xFFF781A0) // (UDPHS_EPT_5) UDPHS Endpoint Config Register -#define AT91C_UDPHS_EPT_5_EPTCTL (AT91C_CAST(AT91C_REG *) 0xFFF781AC) // (UDPHS_EPT_5) UDPHS Endpoint Control Register -// ========== Register definition for UDPHS_EPT_6 peripheral ========== -#define AT91C_UDPHS_EPT_6_EPTCLRSTA (AT91C_CAST(AT91C_REG *) 0xFFF781D8) // (UDPHS_EPT_6) UDPHS Endpoint Clear Status Register -#define AT91C_UDPHS_EPT_6_EPTCTLENB (AT91C_CAST(AT91C_REG *) 0xFFF781C4) // (UDPHS_EPT_6) UDPHS Endpoint Control Enable Register -#define AT91C_UDPHS_EPT_6_EPTCTL (AT91C_CAST(AT91C_REG *) 0xFFF781CC) // (UDPHS_EPT_6) UDPHS Endpoint Control Register -#define AT91C_UDPHS_EPT_6_EPTSETSTA (AT91C_CAST(AT91C_REG *) 0xFFF781D4) // (UDPHS_EPT_6) UDPHS Endpoint Set Status Register -#define AT91C_UDPHS_EPT_6_EPTCTLDIS (AT91C_CAST(AT91C_REG *) 0xFFF781C8) // (UDPHS_EPT_6) UDPHS Endpoint Control Disable Register -#define AT91C_UDPHS_EPT_6_EPTSTA (AT91C_CAST(AT91C_REG *) 0xFFF781DC) // (UDPHS_EPT_6) UDPHS Endpoint Status Register -#define AT91C_UDPHS_EPT_6_EPTCFG (AT91C_CAST(AT91C_REG *) 0xFFF781C0) // (UDPHS_EPT_6) UDPHS Endpoint Config Register -// ========== Register definition for UDPHS_DMA_1 peripheral ========== -#define AT91C_UDPHS_DMA_1_DMASTATUS (AT91C_CAST(AT91C_REG *) 0xFFF7831C) // (UDPHS_DMA_1) UDPHS DMA Channel Status Register -#define AT91C_UDPHS_DMA_1_DMANXTDSC (AT91C_CAST(AT91C_REG *) 0xFFF78310) // (UDPHS_DMA_1) UDPHS DMA Channel Next Descriptor Address -#define AT91C_UDPHS_DMA_1_DMACONTROL (AT91C_CAST(AT91C_REG *) 0xFFF78318) // (UDPHS_DMA_1) UDPHS DMA Channel Control Register -#define AT91C_UDPHS_DMA_1_DMAADDRESS (AT91C_CAST(AT91C_REG *) 0xFFF78314) // (UDPHS_DMA_1) UDPHS DMA Channel Address Register -// ========== Register definition for UDPHS_DMA_2 peripheral ========== -#define AT91C_UDPHS_DMA_2_DMACONTROL (AT91C_CAST(AT91C_REG *) 0xFFF78328) // (UDPHS_DMA_2) UDPHS DMA Channel Control Register -#define AT91C_UDPHS_DMA_2_DMASTATUS (AT91C_CAST(AT91C_REG *) 0xFFF7832C) // (UDPHS_DMA_2) UDPHS DMA Channel Status Register -#define AT91C_UDPHS_DMA_2_DMAADDRESS (AT91C_CAST(AT91C_REG *) 0xFFF78324) // (UDPHS_DMA_2) UDPHS DMA Channel Address Register -#define AT91C_UDPHS_DMA_2_DMANXTDSC (AT91C_CAST(AT91C_REG *) 0xFFF78320) // (UDPHS_DMA_2) UDPHS DMA Channel Next Descriptor Address -// ========== Register definition for UDPHS_DMA_3 peripheral ========== -#define AT91C_UDPHS_DMA_3_DMAADDRESS (AT91C_CAST(AT91C_REG *) 0xFFF78334) // (UDPHS_DMA_3) UDPHS DMA Channel Address Register -#define AT91C_UDPHS_DMA_3_DMANXTDSC (AT91C_CAST(AT91C_REG *) 0xFFF78330) // (UDPHS_DMA_3) UDPHS DMA Channel Next Descriptor Address -#define AT91C_UDPHS_DMA_3_DMACONTROL (AT91C_CAST(AT91C_REG *) 0xFFF78338) // (UDPHS_DMA_3) UDPHS DMA Channel Control Register -#define AT91C_UDPHS_DMA_3_DMASTATUS (AT91C_CAST(AT91C_REG *) 0xFFF7833C) // (UDPHS_DMA_3) UDPHS DMA Channel Status Register -// ========== Register definition for UDPHS_DMA_4 peripheral ========== -#define AT91C_UDPHS_DMA_4_DMANXTDSC (AT91C_CAST(AT91C_REG *) 0xFFF78340) // (UDPHS_DMA_4) UDPHS DMA Channel Next Descriptor Address -#define AT91C_UDPHS_DMA_4_DMAADDRESS (AT91C_CAST(AT91C_REG *) 0xFFF78344) // (UDPHS_DMA_4) UDPHS DMA Channel Address Register -#define AT91C_UDPHS_DMA_4_DMACONTROL (AT91C_CAST(AT91C_REG *) 0xFFF78348) // (UDPHS_DMA_4) UDPHS DMA Channel Control Register -#define AT91C_UDPHS_DMA_4_DMASTATUS (AT91C_CAST(AT91C_REG *) 0xFFF7834C) // (UDPHS_DMA_4) UDPHS DMA Channel Status Register -// ========== Register definition for UDPHS_DMA_5 peripheral ========== -#define AT91C_UDPHS_DMA_5_DMASTATUS (AT91C_CAST(AT91C_REG *) 0xFFF7835C) // (UDPHS_DMA_5) UDPHS DMA Channel Status Register -#define AT91C_UDPHS_DMA_5_DMACONTROL (AT91C_CAST(AT91C_REG *) 0xFFF78358) // (UDPHS_DMA_5) UDPHS DMA Channel Control Register -#define AT91C_UDPHS_DMA_5_DMANXTDSC (AT91C_CAST(AT91C_REG *) 0xFFF78350) // (UDPHS_DMA_5) UDPHS DMA Channel Next Descriptor Address -#define AT91C_UDPHS_DMA_5_DMAADDRESS (AT91C_CAST(AT91C_REG *) 0xFFF78354) // (UDPHS_DMA_5) UDPHS DMA Channel Address Register -// ========== Register definition for UDPHS_DMA_6 peripheral ========== -#define AT91C_UDPHS_DMA_6_DMANXTDSC (AT91C_CAST(AT91C_REG *) 0xFFF78360) // (UDPHS_DMA_6) UDPHS DMA Channel Next Descriptor Address -#define AT91C_UDPHS_DMA_6_DMACONTROL (AT91C_CAST(AT91C_REG *) 0xFFF78368) // (UDPHS_DMA_6) UDPHS DMA Channel Control Register -#define AT91C_UDPHS_DMA_6_DMASTATUS (AT91C_CAST(AT91C_REG *) 0xFFF7836C) // (UDPHS_DMA_6) UDPHS DMA Channel Status Register -#define AT91C_UDPHS_DMA_6_DMAADDRESS (AT91C_CAST(AT91C_REG *) 0xFFF78364) // (UDPHS_DMA_6) UDPHS DMA Channel Address Register -// ========== Register definition for UDPHS peripheral ========== -#define AT91C_UDPHS_IEN (AT91C_CAST(AT91C_REG *) 0xFFF78010) // (UDPHS) UDPHS Interrupt Enable Register -#define AT91C_UDPHS_TSTSOFCNT (AT91C_CAST(AT91C_REG *) 0xFFF780D0) // (UDPHS) UDPHS Test SOF Counter Register -#define AT91C_UDPHS_IPFEATURES (AT91C_CAST(AT91C_REG *) 0xFFF780F8) // (UDPHS) UDPHS Features Register -#define AT91C_UDPHS_TST (AT91C_CAST(AT91C_REG *) 0xFFF780E0) // (UDPHS) UDPHS Test Register -#define AT91C_UDPHS_FNUM (AT91C_CAST(AT91C_REG *) 0xFFF78004) // (UDPHS) UDPHS Frame Number Register -#define AT91C_UDPHS_TSTCNTB (AT91C_CAST(AT91C_REG *) 0xFFF780D8) // (UDPHS) UDPHS Test B Counter Register -#define AT91C_UDPHS_RIPPADDRSIZE (AT91C_CAST(AT91C_REG *) 0xFFF780EC) // (UDPHS) UDPHS PADDRSIZE Register -#define AT91C_UDPHS_INTSTA (AT91C_CAST(AT91C_REG *) 0xFFF78014) // (UDPHS) UDPHS Interrupt Status Register -#define AT91C_UDPHS_EPTRST (AT91C_CAST(AT91C_REG *) 0xFFF7801C) // (UDPHS) UDPHS Endpoints Reset Register -#define AT91C_UDPHS_TSTCNTA (AT91C_CAST(AT91C_REG *) 0xFFF780D4) // (UDPHS) UDPHS Test A Counter Register -#define AT91C_UDPHS_RIPNAME2 (AT91C_CAST(AT91C_REG *) 0xFFF780F4) // (UDPHS) UDPHS Name2 Register -#define AT91C_UDPHS_RIPNAME1 (AT91C_CAST(AT91C_REG *) 0xFFF780F0) // (UDPHS) UDPHS Name1 Register -#define AT91C_UDPHS_TSTMODREG (AT91C_CAST(AT91C_REG *) 0xFFF780DC) // (UDPHS) UDPHS Test Mode Register -#define AT91C_UDPHS_CLRINT (AT91C_CAST(AT91C_REG *) 0xFFF78018) // (UDPHS) UDPHS Clear Interrupt Register -#define AT91C_UDPHS_IPVERSION (AT91C_CAST(AT91C_REG *) 0xFFF780FC) // (UDPHS) UDPHS Version Register -#define AT91C_UDPHS_CTRL (AT91C_CAST(AT91C_REG *) 0xFFF78000) // (UDPHS) UDPHS Control Register -// ========== Register definition for PDC_AC97C peripheral ========== -#define AT91C_AC97C_PTSR (AT91C_CAST(AT91C_REG *) 0xFFFAC124) // (PDC_AC97C) PDC Transfer Status Register -#define AT91C_AC97C_RPR (AT91C_CAST(AT91C_REG *) 0xFFFAC100) // (PDC_AC97C) Receive Pointer Register -#define AT91C_AC97C_RNCR (AT91C_CAST(AT91C_REG *) 0xFFFAC114) // (PDC_AC97C) Receive Next Counter Register -#define AT91C_AC97C_RCR (AT91C_CAST(AT91C_REG *) 0xFFFAC104) // (PDC_AC97C) Receive Counter Register -#define AT91C_AC97C_PTCR (AT91C_CAST(AT91C_REG *) 0xFFFAC120) // (PDC_AC97C) PDC Transfer Control Register -#define AT91C_AC97C_TPR (AT91C_CAST(AT91C_REG *) 0xFFFAC108) // (PDC_AC97C) Transmit Pointer Register -#define AT91C_AC97C_RNPR (AT91C_CAST(AT91C_REG *) 0xFFFAC110) // (PDC_AC97C) Receive Next Pointer Register -#define AT91C_AC97C_TNPR (AT91C_CAST(AT91C_REG *) 0xFFFAC118) // (PDC_AC97C) Transmit Next Pointer Register -#define AT91C_AC97C_TCR (AT91C_CAST(AT91C_REG *) 0xFFFAC10C) // (PDC_AC97C) Transmit Counter Register -#define AT91C_AC97C_TNCR (AT91C_CAST(AT91C_REG *) 0xFFFAC11C) // (PDC_AC97C) Transmit Next Counter Register -// ========== Register definition for AC97C peripheral ========== -#define AT91C_AC97C_IER (AT91C_CAST(AT91C_REG *) 0xFFFAC054) // (AC97C) Interrupt Enable Register -#define AT91C_AC97C_COTHR (AT91C_CAST(AT91C_REG *) 0xFFFAC044) // (AC97C) COdec Transmit Holding Register -#define AT91C_AC97C_IDR (AT91C_CAST(AT91C_REG *) 0xFFFAC058) // (AC97C) Interrupt Disable Register -#define AT91C_AC97C_ICA (AT91C_CAST(AT91C_REG *) 0xFFFAC010) // (AC97C) Input Channel AssignementRegister -#define AT91C_AC97C_CATHR (AT91C_CAST(AT91C_REG *) 0xFFFAC024) // (AC97C) Channel A Transmit Holding Register -#define AT91C_AC97C_CBSR (AT91C_CAST(AT91C_REG *) 0xFFFAC038) // (AC97C) Channel B Status Register -#define AT91C_AC97C_CAMR (AT91C_CAST(AT91C_REG *) 0xFFFAC02C) // (AC97C) Channel A Mode Register -#define AT91C_AC97C_SR (AT91C_CAST(AT91C_REG *) 0xFFFAC050) // (AC97C) Status Register -#define AT91C_AC97C_CBTHR (AT91C_CAST(AT91C_REG *) 0xFFFAC034) // (AC97C) Channel B Transmit Holding Register (optional) -#define AT91C_AC97C_CASR (AT91C_CAST(AT91C_REG *) 0xFFFAC028) // (AC97C) Channel A Status Register -#define AT91C_AC97C_COSR (AT91C_CAST(AT91C_REG *) 0xFFFAC048) // (AC97C) CODEC Status Register -#define AT91C_AC97C_MR (AT91C_CAST(AT91C_REG *) 0xFFFAC008) // (AC97C) Mode Register -#define AT91C_AC97C_OCA (AT91C_CAST(AT91C_REG *) 0xFFFAC014) // (AC97C) Output Channel Assignement Register -#define AT91C_AC97C_CORHR (AT91C_CAST(AT91C_REG *) 0xFFFAC040) // (AC97C) COdec Transmit Holding Register -#define AT91C_AC97C_CBRHR (AT91C_CAST(AT91C_REG *) 0xFFFAC030) // (AC97C) Channel B Receive Holding Register (optional) -#define AT91C_AC97C_IMR (AT91C_CAST(AT91C_REG *) 0xFFFAC05C) // (AC97C) Interrupt Mask Register -#define AT91C_AC97C_COMR (AT91C_CAST(AT91C_REG *) 0xFFFAC04C) // (AC97C) CODEC Mask Status Register -#define AT91C_AC97C_CARHR (AT91C_CAST(AT91C_REG *) 0xFFFAC020) // (AC97C) Channel A Receive Holding Register -#define AT91C_AC97C_VERSION (AT91C_CAST(AT91C_REG *) 0xFFFAC0FC) // (AC97C) Version Register -#define AT91C_AC97C_CBMR (AT91C_CAST(AT91C_REG *) 0xFFFAC03C) // (AC97C) Channel B Mode Register -// ========== Register definition for LCDC peripheral ========== -#define AT91C_LCDC_MVAL (AT91C_CAST(AT91C_REG *) 0x00500818) // (LCDC) LCD Mode Toggle Rate Value Register -#define AT91C_LCDC_PWRCON (AT91C_CAST(AT91C_REG *) 0x0050083C) // (LCDC) Power Control Register -#define AT91C_LCDC_ISR (AT91C_CAST(AT91C_REG *) 0x00500854) // (LCDC) Interrupt Enable Register -#define AT91C_LCDC_FRMP1 (AT91C_CAST(AT91C_REG *) 0x00500008) // (LCDC) DMA Frame Pointer Register 1 -#define AT91C_LCDC_CTRSTVAL (AT91C_CAST(AT91C_REG *) 0x00500844) // (LCDC) Contrast Value Register -#define AT91C_LCDC_ICR (AT91C_CAST(AT91C_REG *) 0x00500858) // (LCDC) Interrupt Clear Register -#define AT91C_LCDC_TIM1 (AT91C_CAST(AT91C_REG *) 0x00500808) // (LCDC) LCD Timing Config 1 Register -#define AT91C_LCDC_DMACON (AT91C_CAST(AT91C_REG *) 0x0050001C) // (LCDC) DMA Control Register -#define AT91C_LCDC_ITR (AT91C_CAST(AT91C_REG *) 0x00500860) // (LCDC) Interrupts Test Register -#define AT91C_LCDC_IDR (AT91C_CAST(AT91C_REG *) 0x0050084C) // (LCDC) Interrupt Disable Register -#define AT91C_LCDC_DP4_7 (AT91C_CAST(AT91C_REG *) 0x00500820) // (LCDC) Dithering Pattern DP4_7 Register -#define AT91C_LCDC_DP5_7 (AT91C_CAST(AT91C_REG *) 0x0050082C) // (LCDC) Dithering Pattern DP5_7 Register -#define AT91C_LCDC_IRR (AT91C_CAST(AT91C_REG *) 0x00500864) // (LCDC) Interrupts Raw Status Register -#define AT91C_LCDC_DP3_4 (AT91C_CAST(AT91C_REG *) 0x00500830) // (LCDC) Dithering Pattern DP3_4 Register -#define AT91C_LCDC_IMR (AT91C_CAST(AT91C_REG *) 0x00500850) // (LCDC) Interrupt Mask Register -#define AT91C_LCDC_LCDFRCFG (AT91C_CAST(AT91C_REG *) 0x00500810) // (LCDC) LCD Frame Config Register -#define AT91C_LCDC_CTRSTCON (AT91C_CAST(AT91C_REG *) 0x00500840) // (LCDC) Contrast Control Register -#define AT91C_LCDC_DP1_2 (AT91C_CAST(AT91C_REG *) 0x0050081C) // (LCDC) Dithering Pattern DP1_2 Register -#define AT91C_LCDC_FRMP2 (AT91C_CAST(AT91C_REG *) 0x0050000C) // (LCDC) DMA Frame Pointer Register 2 -#define AT91C_LCDC_LCDCON1 (AT91C_CAST(AT91C_REG *) 0x00500800) // (LCDC) LCD Control 1 Register -#define AT91C_LCDC_DP4_5 (AT91C_CAST(AT91C_REG *) 0x00500834) // (LCDC) Dithering Pattern DP4_5 Register -#define AT91C_LCDC_FRMA2 (AT91C_CAST(AT91C_REG *) 0x00500014) // (LCDC) DMA Frame Address Register 2 -#define AT91C_LCDC_BA1 (AT91C_CAST(AT91C_REG *) 0x00500000) // (LCDC) DMA Base Address Register 1 -#define AT91C_LCDC_DMA2DCFG (AT91C_CAST(AT91C_REG *) 0x00500020) // (LCDC) DMA 2D addressing configuration -#define AT91C_LCDC_LUT_ENTRY (AT91C_CAST(AT91C_REG *) 0x00500C00) // (LCDC) LUT Entries Register -#define AT91C_LCDC_DP6_7 (AT91C_CAST(AT91C_REG *) 0x00500838) // (LCDC) Dithering Pattern DP6_7 Register -#define AT91C_LCDC_FRMCFG (AT91C_CAST(AT91C_REG *) 0x00500018) // (LCDC) DMA Frame Configuration Register -#define AT91C_LCDC_TIM2 (AT91C_CAST(AT91C_REG *) 0x0050080C) // (LCDC) LCD Timing Config 2 Register -#define AT91C_LCDC_DP3_5 (AT91C_CAST(AT91C_REG *) 0x00500824) // (LCDC) Dithering Pattern DP3_5 Register -#define AT91C_LCDC_FRMA1 (AT91C_CAST(AT91C_REG *) 0x00500010) // (LCDC) DMA Frame Address Register 1 -#define AT91C_LCDC_IER (AT91C_CAST(AT91C_REG *) 0x00500848) // (LCDC) Interrupt Enable Register -#define AT91C_LCDC_DP2_3 (AT91C_CAST(AT91C_REG *) 0x00500828) // (LCDC) Dithering Pattern DP2_3 Register -#define AT91C_LCDC_FIFO (AT91C_CAST(AT91C_REG *) 0x00500814) // (LCDC) LCD FIFO Register -#define AT91C_LCDC_BA2 (AT91C_CAST(AT91C_REG *) 0x00500004) // (LCDC) DMA Base Address Register 2 -#define AT91C_LCDC_LCDCON2 (AT91C_CAST(AT91C_REG *) 0x00500804) // (LCDC) LCD Control 2 Register -#define AT91C_LCDC_GPR (AT91C_CAST(AT91C_REG *) 0x0050085C) // (LCDC) General Purpose Register -// ========== Register definition for LCDC_16B_TFT peripheral ========== -#define AT91C_TFT_MVAL (AT91C_CAST(AT91C_REG *) 0x00500818) // (LCDC_16B_TFT) LCD Mode Toggle Rate Value Register -#define AT91C_TFT_PWRCON (AT91C_CAST(AT91C_REG *) 0x0050083C) // (LCDC_16B_TFT) Power Control Register -#define AT91C_TFT_ISR (AT91C_CAST(AT91C_REG *) 0x00500854) // (LCDC_16B_TFT) Interrupt Enable Register -#define AT91C_TFT_FRMP1 (AT91C_CAST(AT91C_REG *) 0x00500008) // (LCDC_16B_TFT) DMA Frame Pointer Register 1 -#define AT91C_TFT_CTRSTVAL (AT91C_CAST(AT91C_REG *) 0x00500844) // (LCDC_16B_TFT) Contrast Value Register -#define AT91C_TFT_ICR (AT91C_CAST(AT91C_REG *) 0x00500858) // (LCDC_16B_TFT) Interrupt Clear Register -#define AT91C_TFT_TIM1 (AT91C_CAST(AT91C_REG *) 0x00500808) // (LCDC_16B_TFT) LCD Timing Config 1 Register -#define AT91C_TFT_DMACON (AT91C_CAST(AT91C_REG *) 0x0050001C) // (LCDC_16B_TFT) DMA Control Register -#define AT91C_TFT_ITR (AT91C_CAST(AT91C_REG *) 0x00500860) // (LCDC_16B_TFT) Interrupts Test Register -#define AT91C_TFT_IDR (AT91C_CAST(AT91C_REG *) 0x0050084C) // (LCDC_16B_TFT) Interrupt Disable Register -#define AT91C_TFT_DP4_7 (AT91C_CAST(AT91C_REG *) 0x00500820) // (LCDC_16B_TFT) Dithering Pattern DP4_7 Register -#define AT91C_TFT_DP5_7 (AT91C_CAST(AT91C_REG *) 0x0050082C) // (LCDC_16B_TFT) Dithering Pattern DP5_7 Register -#define AT91C_TFT_IRR (AT91C_CAST(AT91C_REG *) 0x00500864) // (LCDC_16B_TFT) Interrupts Raw Status Register -#define AT91C_TFT_DP3_4 (AT91C_CAST(AT91C_REG *) 0x00500830) // (LCDC_16B_TFT) Dithering Pattern DP3_4 Register -#define AT91C_TFT_IMR (AT91C_CAST(AT91C_REG *) 0x00500850) // (LCDC_16B_TFT) Interrupt Mask Register -#define AT91C_TFT_LCDFRCFG (AT91C_CAST(AT91C_REG *) 0x00500810) // (LCDC_16B_TFT) LCD Frame Config Register -#define AT91C_TFT_CTRSTCON (AT91C_CAST(AT91C_REG *) 0x00500840) // (LCDC_16B_TFT) Contrast Control Register -#define AT91C_TFT_DP1_2 (AT91C_CAST(AT91C_REG *) 0x0050081C) // (LCDC_16B_TFT) Dithering Pattern DP1_2 Register -#define AT91C_TFT_FRMP2 (AT91C_CAST(AT91C_REG *) 0x0050000C) // (LCDC_16B_TFT) DMA Frame Pointer Register 2 -#define AT91C_TFT_LCDCON1 (AT91C_CAST(AT91C_REG *) 0x00500800) // (LCDC_16B_TFT) LCD Control 1 Register -#define AT91C_TFT_DP4_5 (AT91C_CAST(AT91C_REG *) 0x00500834) // (LCDC_16B_TFT) Dithering Pattern DP4_5 Register -#define AT91C_TFT_FRMA2 (AT91C_CAST(AT91C_REG *) 0x00500014) // (LCDC_16B_TFT) DMA Frame Address Register 2 -#define AT91C_TFT_BA1 (AT91C_CAST(AT91C_REG *) 0x00500000) // (LCDC_16B_TFT) DMA Base Address Register 1 -#define AT91C_TFT_DMA2DCFG (AT91C_CAST(AT91C_REG *) 0x00500020) // (LCDC_16B_TFT) DMA 2D addressing configuration -#define AT91C_TFT_LUT_ENTRY (AT91C_CAST(AT91C_REG *) 0x00500C00) // (LCDC_16B_TFT) LUT Entries Register -#define AT91C_TFT_DP6_7 (AT91C_CAST(AT91C_REG *) 0x00500838) // (LCDC_16B_TFT) Dithering Pattern DP6_7 Register -#define AT91C_TFT_FRMCFG (AT91C_CAST(AT91C_REG *) 0x00500018) // (LCDC_16B_TFT) DMA Frame Configuration Register -#define AT91C_TFT_TIM2 (AT91C_CAST(AT91C_REG *) 0x0050080C) // (LCDC_16B_TFT) LCD Timing Config 2 Register -#define AT91C_TFT_DP3_5 (AT91C_CAST(AT91C_REG *) 0x00500824) // (LCDC_16B_TFT) Dithering Pattern DP3_5 Register -#define AT91C_TFT_FRMA1 (AT91C_CAST(AT91C_REG *) 0x00500010) // (LCDC_16B_TFT) DMA Frame Address Register 1 -#define AT91C_TFT_IER (AT91C_CAST(AT91C_REG *) 0x00500848) // (LCDC_16B_TFT) Interrupt Enable Register -#define AT91C_TFT_DP2_3 (AT91C_CAST(AT91C_REG *) 0x00500828) // (LCDC_16B_TFT) Dithering Pattern DP2_3 Register -#define AT91C_TFT_FIFO (AT91C_CAST(AT91C_REG *) 0x00500814) // (LCDC_16B_TFT) LCD FIFO Register -#define AT91C_TFT_BA2 (AT91C_CAST(AT91C_REG *) 0x00500004) // (LCDC_16B_TFT) DMA Base Address Register 2 -#define AT91C_TFT_LCDCON2 (AT91C_CAST(AT91C_REG *) 0x00500804) // (LCDC_16B_TFT) LCD Control 2 Register -#define AT91C_TFT_GPR (AT91C_CAST(AT91C_REG *) 0x0050085C) // (LCDC_16B_TFT) General Purpose Register -// ========== Register definition for HDMA_CH_0 peripheral ========== -#define AT91C_HDMA_CH_0_BDSCR (AT91C_CAST(AT91C_REG *) 0xFFFFEC5C) // (HDMA_CH_0) HDMA Reserved -#define AT91C_HDMA_CH_0_DADDR (AT91C_CAST(AT91C_REG *) 0xFFFFEC40) // (HDMA_CH_0) HDMA Channel Destination Address Register -#define AT91C_HDMA_CH_0_DPIP (AT91C_CAST(AT91C_REG *) 0xFFFFEC58) // (HDMA_CH_0) HDMA Channel Destination Picture in Picture Configuration Register -#define AT91C_HDMA_CH_0_DSCR (AT91C_CAST(AT91C_REG *) 0xFFFFEC44) // (HDMA_CH_0) HDMA Channel Descriptor Address Register -#define AT91C_HDMA_CH_0_CFG (AT91C_CAST(AT91C_REG *) 0xFFFFEC50) // (HDMA_CH_0) HDMA Channel Configuration Register -#define AT91C_HDMA_CH_0_SPIP (AT91C_CAST(AT91C_REG *) 0xFFFFEC54) // (HDMA_CH_0) HDMA Channel Source Picture in Picture Configuration Register -#define AT91C_HDMA_CH_0_CADDR (AT91C_CAST(AT91C_REG *) 0xFFFFEC60) // (HDMA_CH_0) HDMA Reserved -#define AT91C_HDMA_CH_0_CTRLA (AT91C_CAST(AT91C_REG *) 0xFFFFEC48) // (HDMA_CH_0) HDMA Channel Control A Register -#define AT91C_HDMA_CH_0_CTRLB (AT91C_CAST(AT91C_REG *) 0xFFFFEC4C) // (HDMA_CH_0) HDMA Channel Control B Register -#define AT91C_HDMA_CH_0_SADDR (AT91C_CAST(AT91C_REG *) 0xFFFFEC3C) // (HDMA_CH_0) HDMA Channel Source Address Register -// ========== Register definition for HDMA_CH_1 peripheral ========== -#define AT91C_HDMA_CH_1_CADDR (AT91C_CAST(AT91C_REG *) 0xFFFFEC88) // (HDMA_CH_1) HDMA Reserved -#define AT91C_HDMA_CH_1_DPIP (AT91C_CAST(AT91C_REG *) 0xFFFFEC80) // (HDMA_CH_1) HDMA Channel Destination Picture in Picture Configuration Register -#define AT91C_HDMA_CH_1_CTRLB (AT91C_CAST(AT91C_REG *) 0xFFFFEC74) // (HDMA_CH_1) HDMA Channel Control B Register -#define AT91C_HDMA_CH_1_SADDR (AT91C_CAST(AT91C_REG *) 0xFFFFEC64) // (HDMA_CH_1) HDMA Channel Source Address Register -#define AT91C_HDMA_CH_1_BDSCR (AT91C_CAST(AT91C_REG *) 0xFFFFEC84) // (HDMA_CH_1) HDMA Reserved -#define AT91C_HDMA_CH_1_CFG (AT91C_CAST(AT91C_REG *) 0xFFFFEC78) // (HDMA_CH_1) HDMA Channel Configuration Register -#define AT91C_HDMA_CH_1_DSCR (AT91C_CAST(AT91C_REG *) 0xFFFFEC6C) // (HDMA_CH_1) HDMA Channel Descriptor Address Register -#define AT91C_HDMA_CH_1_DADDR (AT91C_CAST(AT91C_REG *) 0xFFFFEC68) // (HDMA_CH_1) HDMA Channel Destination Address Register -#define AT91C_HDMA_CH_1_CTRLA (AT91C_CAST(AT91C_REG *) 0xFFFFEC70) // (HDMA_CH_1) HDMA Channel Control A Register -#define AT91C_HDMA_CH_1_SPIP (AT91C_CAST(AT91C_REG *) 0xFFFFEC7C) // (HDMA_CH_1) HDMA Channel Source Picture in Picture Configuration Register -// ========== Register definition for HDMA_CH_2 peripheral ========== -#define AT91C_HDMA_CH_2_SADDR (AT91C_CAST(AT91C_REG *) 0xFFFFEC8C) // (HDMA_CH_2) HDMA Channel Source Address Register -#define AT91C_HDMA_CH_2_BDSCR (AT91C_CAST(AT91C_REG *) 0xFFFFECAC) // (HDMA_CH_2) HDMA Reserved -#define AT91C_HDMA_CH_2_DPIP (AT91C_CAST(AT91C_REG *) 0xFFFFECA8) // (HDMA_CH_2) HDMA Channel Destination Picture in Picture Configuration Register -#define AT91C_HDMA_CH_2_SPIP (AT91C_CAST(AT91C_REG *) 0xFFFFECA4) // (HDMA_CH_2) HDMA Channel Source Picture in Picture Configuration Register -#define AT91C_HDMA_CH_2_DADDR (AT91C_CAST(AT91C_REG *) 0xFFFFEC90) // (HDMA_CH_2) HDMA Channel Destination Address Register -#define AT91C_HDMA_CH_2_DSCR (AT91C_CAST(AT91C_REG *) 0xFFFFEC94) // (HDMA_CH_2) HDMA Channel Descriptor Address Register -#define AT91C_HDMA_CH_2_CTRLA (AT91C_CAST(AT91C_REG *) 0xFFFFEC98) // (HDMA_CH_2) HDMA Channel Control A Register -#define AT91C_HDMA_CH_2_CADDR (AT91C_CAST(AT91C_REG *) 0xFFFFECB0) // (HDMA_CH_2) HDMA Reserved -#define AT91C_HDMA_CH_2_CFG (AT91C_CAST(AT91C_REG *) 0xFFFFECA0) // (HDMA_CH_2) HDMA Channel Configuration Register -#define AT91C_HDMA_CH_2_CTRLB (AT91C_CAST(AT91C_REG *) 0xFFFFEC9C) // (HDMA_CH_2) HDMA Channel Control B Register -// ========== Register definition for HDMA_CH_3 peripheral ========== -#define AT91C_HDMA_CH_3_SPIP (AT91C_CAST(AT91C_REG *) 0xFFFFECCC) // (HDMA_CH_3) HDMA Channel Source Picture in Picture Configuration Register -#define AT91C_HDMA_CH_3_CTRLA (AT91C_CAST(AT91C_REG *) 0xFFFFECC0) // (HDMA_CH_3) HDMA Channel Control A Register -#define AT91C_HDMA_CH_3_DPIP (AT91C_CAST(AT91C_REG *) 0xFFFFECD0) // (HDMA_CH_3) HDMA Channel Destination Picture in Picture Configuration Register -#define AT91C_HDMA_CH_3_CTRLB (AT91C_CAST(AT91C_REG *) 0xFFFFECC4) // (HDMA_CH_3) HDMA Channel Control B Register -#define AT91C_HDMA_CH_3_BDSCR (AT91C_CAST(AT91C_REG *) 0xFFFFECD4) // (HDMA_CH_3) HDMA Reserved -#define AT91C_HDMA_CH_3_DSCR (AT91C_CAST(AT91C_REG *) 0xFFFFECBC) // (HDMA_CH_3) HDMA Channel Descriptor Address Register -#define AT91C_HDMA_CH_3_CADDR (AT91C_CAST(AT91C_REG *) 0xFFFFECD8) // (HDMA_CH_3) HDMA Reserved -#define AT91C_HDMA_CH_3_CFG (AT91C_CAST(AT91C_REG *) 0xFFFFECC8) // (HDMA_CH_3) HDMA Channel Configuration Register -#define AT91C_HDMA_CH_3_DADDR (AT91C_CAST(AT91C_REG *) 0xFFFFECB8) // (HDMA_CH_3) HDMA Channel Destination Address Register -#define AT91C_HDMA_CH_3_SADDR (AT91C_CAST(AT91C_REG *) 0xFFFFECB4) // (HDMA_CH_3) HDMA Channel Source Address Register -// ========== Register definition for HDMA_CH_4 peripheral ========== -#define AT91C_HDMA_CH_4_CFG (AT91C_CAST(AT91C_REG *) 0xFFFFECF0) // (HDMA_CH_4) HDMA Channel Configuration Register -#define AT91C_HDMA_CH_4_BDSCR (AT91C_CAST(AT91C_REG *) 0xFFFFECFC) // (HDMA_CH_4) HDMA Reserved -#define AT91C_HDMA_CH_4_CADDR (AT91C_CAST(AT91C_REG *) 0xFFFFED00) // (HDMA_CH_4) HDMA Reserved -#define AT91C_HDMA_CH_4_DADDR (AT91C_CAST(AT91C_REG *) 0xFFFFECE0) // (HDMA_CH_4) HDMA Channel Destination Address Register -#define AT91C_HDMA_CH_4_CTRLA (AT91C_CAST(AT91C_REG *) 0xFFFFECE8) // (HDMA_CH_4) HDMA Channel Control A Register -#define AT91C_HDMA_CH_4_SADDR (AT91C_CAST(AT91C_REG *) 0xFFFFECDC) // (HDMA_CH_4) HDMA Channel Source Address Register -#define AT91C_HDMA_CH_4_CTRLB (AT91C_CAST(AT91C_REG *) 0xFFFFECEC) // (HDMA_CH_4) HDMA Channel Control B Register -#define AT91C_HDMA_CH_4_DSCR (AT91C_CAST(AT91C_REG *) 0xFFFFECE4) // (HDMA_CH_4) HDMA Channel Descriptor Address Register -#define AT91C_HDMA_CH_4_SPIP (AT91C_CAST(AT91C_REG *) 0xFFFFECF4) // (HDMA_CH_4) HDMA Channel Source Picture in Picture Configuration Register -#define AT91C_HDMA_CH_4_DPIP (AT91C_CAST(AT91C_REG *) 0xFFFFECF8) // (HDMA_CH_4) HDMA Channel Destination Picture in Picture Configuration Register -// ========== Register definition for HDMA_CH_5 peripheral ========== -#define AT91C_HDMA_CH_5_CTRLB (AT91C_CAST(AT91C_REG *) 0xFFFFED14) // (HDMA_CH_5) HDMA Channel Control B Register -#define AT91C_HDMA_CH_5_DADDR (AT91C_CAST(AT91C_REG *) 0xFFFFED08) // (HDMA_CH_5) HDMA Channel Destination Address Register -#define AT91C_HDMA_CH_5_SPIP (AT91C_CAST(AT91C_REG *) 0xFFFFED1C) // (HDMA_CH_5) HDMA Channel Source Picture in Picture Configuration Register -#define AT91C_HDMA_CH_5_DSCR (AT91C_CAST(AT91C_REG *) 0xFFFFED0C) // (HDMA_CH_5) HDMA Channel Descriptor Address Register -#define AT91C_HDMA_CH_5_DPIP (AT91C_CAST(AT91C_REG *) 0xFFFFED20) // (HDMA_CH_5) HDMA Channel Destination Picture in Picture Configuration Register -#define AT91C_HDMA_CH_5_CFG (AT91C_CAST(AT91C_REG *) 0xFFFFED18) // (HDMA_CH_5) HDMA Channel Configuration Register -#define AT91C_HDMA_CH_5_CADDR (AT91C_CAST(AT91C_REG *) 0xFFFFED28) // (HDMA_CH_5) HDMA Reserved -#define AT91C_HDMA_CH_5_SADDR (AT91C_CAST(AT91C_REG *) 0xFFFFED04) // (HDMA_CH_5) HDMA Channel Source Address Register -#define AT91C_HDMA_CH_5_BDSCR (AT91C_CAST(AT91C_REG *) 0xFFFFED24) // (HDMA_CH_5) HDMA Reserved -#define AT91C_HDMA_CH_5_CTRLA (AT91C_CAST(AT91C_REG *) 0xFFFFED10) // (HDMA_CH_5) HDMA Channel Control A Register -// ========== Register definition for HDMA_CH_6 peripheral ========== -#define AT91C_HDMA_CH_6_SADDR (AT91C_CAST(AT91C_REG *) 0xFFFFED2C) // (HDMA_CH_6) HDMA Channel Source Address Register -#define AT91C_HDMA_CH_6_BDSCR (AT91C_CAST(AT91C_REG *) 0xFFFFED4C) // (HDMA_CH_6) HDMA Reserved -#define AT91C_HDMA_CH_6_CADDR (AT91C_CAST(AT91C_REG *) 0xFFFFED50) // (HDMA_CH_6) HDMA Reserved -#define AT91C_HDMA_CH_6_SPIP (AT91C_CAST(AT91C_REG *) 0xFFFFED44) // (HDMA_CH_6) HDMA Channel Source Picture in Picture Configuration Register -#define AT91C_HDMA_CH_6_CTRLB (AT91C_CAST(AT91C_REG *) 0xFFFFED3C) // (HDMA_CH_6) HDMA Channel Control B Register -#define AT91C_HDMA_CH_6_DSCR (AT91C_CAST(AT91C_REG *) 0xFFFFED34) // (HDMA_CH_6) HDMA Channel Descriptor Address Register -#define AT91C_HDMA_CH_6_CFG (AT91C_CAST(AT91C_REG *) 0xFFFFED40) // (HDMA_CH_6) HDMA Channel Configuration Register -#define AT91C_HDMA_CH_6_DPIP (AT91C_CAST(AT91C_REG *) 0xFFFFED48) // (HDMA_CH_6) HDMA Channel Destination Picture in Picture Configuration Register -#define AT91C_HDMA_CH_6_DADDR (AT91C_CAST(AT91C_REG *) 0xFFFFED30) // (HDMA_CH_6) HDMA Channel Destination Address Register -#define AT91C_HDMA_CH_6_CTRLA (AT91C_CAST(AT91C_REG *) 0xFFFFED38) // (HDMA_CH_6) HDMA Channel Control A Register -// ========== Register definition for HDMA_CH_7 peripheral ========== -#define AT91C_HDMA_CH_7_CADDR (AT91C_CAST(AT91C_REG *) 0xFFFFED78) // (HDMA_CH_7) HDMA Reserved -#define AT91C_HDMA_CH_7_CFG (AT91C_CAST(AT91C_REG *) 0xFFFFED68) // (HDMA_CH_7) HDMA Channel Configuration Register -#define AT91C_HDMA_CH_7_DADDR (AT91C_CAST(AT91C_REG *) 0xFFFFED58) // (HDMA_CH_7) HDMA Channel Destination Address Register -#define AT91C_HDMA_CH_7_CTRLB (AT91C_CAST(AT91C_REG *) 0xFFFFED64) // (HDMA_CH_7) HDMA Channel Control B Register -#define AT91C_HDMA_CH_7_DSCR (AT91C_CAST(AT91C_REG *) 0xFFFFED5C) // (HDMA_CH_7) HDMA Channel Descriptor Address Register -#define AT91C_HDMA_CH_7_DPIP (AT91C_CAST(AT91C_REG *) 0xFFFFED70) // (HDMA_CH_7) HDMA Channel Destination Picture in Picture Configuration Register -#define AT91C_HDMA_CH_7_CTRLA (AT91C_CAST(AT91C_REG *) 0xFFFFED60) // (HDMA_CH_7) HDMA Channel Control A Register -#define AT91C_HDMA_CH_7_BDSCR (AT91C_CAST(AT91C_REG *) 0xFFFFED74) // (HDMA_CH_7) HDMA Reserved -#define AT91C_HDMA_CH_7_SPIP (AT91C_CAST(AT91C_REG *) 0xFFFFED6C) // (HDMA_CH_7) HDMA Channel Source Picture in Picture Configuration Register -#define AT91C_HDMA_CH_7_SADDR (AT91C_CAST(AT91C_REG *) 0xFFFFED54) // (HDMA_CH_7) HDMA Channel Source Address Register -// ========== Register definition for HDMA peripheral ========== -#define AT91C_HDMA_EBCIDR (AT91C_CAST(AT91C_REG *) 0xFFFFEC1C) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register -#define AT91C_HDMA_LAST (AT91C_CAST(AT91C_REG *) 0xFFFFEC10) // (HDMA) HDMA Software Last Transfer Flag Register -#define AT91C_HDMA_SREQ (AT91C_CAST(AT91C_REG *) 0xFFFFEC08) // (HDMA) HDMA Software Single Request Register -#define AT91C_HDMA_RSVD0 (AT91C_CAST(AT91C_REG *) 0xFFFFEC34) // (HDMA) HDMA Reserved -#define AT91C_HDMA_EBCIER (AT91C_CAST(AT91C_REG *) 0xFFFFEC18) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register -#define AT91C_HDMA_GCFG (AT91C_CAST(AT91C_REG *) 0xFFFFEC00) // (HDMA) HDMA Global Configuration Register -#define AT91C_HDMA_CHER (AT91C_CAST(AT91C_REG *) 0xFFFFEC28) // (HDMA) HDMA Channel Handler Enable Register -#define AT91C_HDMA_RSVD1 (AT91C_CAST(AT91C_REG *) 0xFFFFEC38) // (HDMA) HDMA Reserved -#define AT91C_HDMA_CHDR (AT91C_CAST(AT91C_REG *) 0xFFFFEC2C) // (HDMA) HDMA Channel Handler Disable Register -#define AT91C_HDMA_EBCIMR (AT91C_CAST(AT91C_REG *) 0xFFFFEC20) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register -#define AT91C_HDMA_CREQ (AT91C_CAST(AT91C_REG *) 0xFFFFEC0C) // (HDMA) HDMA Software Chunk Transfer Request Register -#define AT91C_HDMA_SYNC (AT91C_CAST(AT91C_REG *) 0xFFFFEC14) // (HDMA) HDMA Request Synchronization Register -#define AT91C_HDMA_EN (AT91C_CAST(AT91C_REG *) 0xFFFFEC04) // (HDMA) HDMA Controller Enable Register -#define AT91C_HDMA_EBCISR (AT91C_CAST(AT91C_REG *) 0xFFFFEC24) // (HDMA) HDMA Error, Chained Buffer transfer completed and Buffer transfer completed Status Register -#define AT91C_HDMA_CHSR (AT91C_CAST(AT91C_REG *) 0xFFFFEC30) // (HDMA) HDMA Channel Handler Status Register -// ========== Register definition for HECC peripheral ========== -#define AT91C_HECC_VR (AT91C_CAST(AT91C_REG *) 0xFFFFE2FC) // (HECC) ECC Version register -#define AT91C_HECC_SR (AT91C_CAST(AT91C_REG *) 0xFFFFE208) // (HECC) ECC Status register -#define AT91C_HECC_CR (AT91C_CAST(AT91C_REG *) 0xFFFFE200) // (HECC) ECC reset register -#define AT91C_HECC_NPR (AT91C_CAST(AT91C_REG *) 0xFFFFE210) // (HECC) ECC Parity N register -#define AT91C_HECC_PR (AT91C_CAST(AT91C_REG *) 0xFFFFE20C) // (HECC) ECC Parity register -#define AT91C_HECC_MR (AT91C_CAST(AT91C_REG *) 0xFFFFE204) // (HECC) ECC Page size register -// ========== Register definition for EMACB peripheral ========== -#define AT91C_EMACB_ALE (AT91C_CAST(AT91C_REG *) 0xFFFBC054) // (EMACB) Alignment Error Register -#define AT91C_EMACB_RRE (AT91C_CAST(AT91C_REG *) 0xFFFBC06C) // (EMACB) Receive Ressource Error Register -#define AT91C_EMACB_SA4H (AT91C_CAST(AT91C_REG *) 0xFFFBC0B4) // (EMACB) Specific Address 4 Top, Last 2 bytes -#define AT91C_EMACB_TPQ (AT91C_CAST(AT91C_REG *) 0xFFFBC0BC) // (EMACB) Transmit Pause Quantum Register -#define AT91C_EMACB_RJA (AT91C_CAST(AT91C_REG *) 0xFFFBC07C) // (EMACB) Receive Jabbers Register -#define AT91C_EMACB_SA2H (AT91C_CAST(AT91C_REG *) 0xFFFBC0A4) // (EMACB) Specific Address 2 Top, Last 2 bytes -#define AT91C_EMACB_TPF (AT91C_CAST(AT91C_REG *) 0xFFFBC08C) // (EMACB) Transmitted Pause Frames Register -#define AT91C_EMACB_ROV (AT91C_CAST(AT91C_REG *) 0xFFFBC070) // (EMACB) Receive Overrun Errors Register -#define AT91C_EMACB_SA4L (AT91C_CAST(AT91C_REG *) 0xFFFBC0B0) // (EMACB) Specific Address 4 Bottom, First 4 bytes -#define AT91C_EMACB_MAN (AT91C_CAST(AT91C_REG *) 0xFFFBC034) // (EMACB) PHY Maintenance Register -#define AT91C_EMACB_TID (AT91C_CAST(AT91C_REG *) 0xFFFBC0B8) // (EMACB) Type ID Checking Register -#define AT91C_EMACB_TBQP (AT91C_CAST(AT91C_REG *) 0xFFFBC01C) // (EMACB) Transmit Buffer Queue Pointer -#define AT91C_EMACB_SA3L (AT91C_CAST(AT91C_REG *) 0xFFFBC0A8) // (EMACB) Specific Address 3 Bottom, First 4 bytes -#define AT91C_EMACB_DTF (AT91C_CAST(AT91C_REG *) 0xFFFBC058) // (EMACB) Deferred Transmission Frame Register -#define AT91C_EMACB_PTR (AT91C_CAST(AT91C_REG *) 0xFFFBC038) // (EMACB) Pause Time Register -#define AT91C_EMACB_CSE (AT91C_CAST(AT91C_REG *) 0xFFFBC068) // (EMACB) Carrier Sense Error Register -#define AT91C_EMACB_ECOL (AT91C_CAST(AT91C_REG *) 0xFFFBC060) // (EMACB) Excessive Collision Register -#define AT91C_EMACB_STE (AT91C_CAST(AT91C_REG *) 0xFFFBC084) // (EMACB) SQE Test Error Register -#define AT91C_EMACB_MCF (AT91C_CAST(AT91C_REG *) 0xFFFBC048) // (EMACB) Multiple Collision Frame Register -#define AT91C_EMACB_IER (AT91C_CAST(AT91C_REG *) 0xFFFBC028) // (EMACB) Interrupt Enable Register -#define AT91C_EMACB_ELE (AT91C_CAST(AT91C_REG *) 0xFFFBC078) // (EMACB) Excessive Length Errors Register -#define AT91C_EMACB_USRIO (AT91C_CAST(AT91C_REG *) 0xFFFBC0C0) // (EMACB) USER Input/Output Register -#define AT91C_EMACB_PFR (AT91C_CAST(AT91C_REG *) 0xFFFBC03C) // (EMACB) Pause Frames received Register -#define AT91C_EMACB_FCSE (AT91C_CAST(AT91C_REG *) 0xFFFBC050) // (EMACB) Frame Check Sequence Error Register -#define AT91C_EMACB_SA1L (AT91C_CAST(AT91C_REG *) 0xFFFBC098) // (EMACB) Specific Address 1 Bottom, First 4 bytes -#define AT91C_EMACB_NCR (AT91C_CAST(AT91C_REG *) 0xFFFBC000) // (EMACB) Network Control Register -#define AT91C_EMACB_HRT (AT91C_CAST(AT91C_REG *) 0xFFFBC094) // (EMACB) Hash Address Top[63:32] -#define AT91C_EMACB_NCFGR (AT91C_CAST(AT91C_REG *) 0xFFFBC004) // (EMACB) Network Configuration Register -#define AT91C_EMACB_SCF (AT91C_CAST(AT91C_REG *) 0xFFFBC044) // (EMACB) Single Collision Frame Register -#define AT91C_EMACB_LCOL (AT91C_CAST(AT91C_REG *) 0xFFFBC05C) // (EMACB) Late Collision Register -#define AT91C_EMACB_SA3H (AT91C_CAST(AT91C_REG *) 0xFFFBC0AC) // (EMACB) Specific Address 3 Top, Last 2 bytes -#define AT91C_EMACB_HRB (AT91C_CAST(AT91C_REG *) 0xFFFBC090) // (EMACB) Hash Address Bottom[31:0] -#define AT91C_EMACB_ISR (AT91C_CAST(AT91C_REG *) 0xFFFBC024) // (EMACB) Interrupt Status Register -#define AT91C_EMACB_IMR (AT91C_CAST(AT91C_REG *) 0xFFFBC030) // (EMACB) Interrupt Mask Register -#define AT91C_EMACB_WOL (AT91C_CAST(AT91C_REG *) 0xFFFBC0C4) // (EMACB) Wake On LAN Register -#define AT91C_EMACB_USF (AT91C_CAST(AT91C_REG *) 0xFFFBC080) // (EMACB) Undersize Frames Register -#define AT91C_EMACB_TSR (AT91C_CAST(AT91C_REG *) 0xFFFBC014) // (EMACB) Transmit Status Register -#define AT91C_EMACB_FRO (AT91C_CAST(AT91C_REG *) 0xFFFBC04C) // (EMACB) Frames Received OK Register -#define AT91C_EMACB_IDR (AT91C_CAST(AT91C_REG *) 0xFFFBC02C) // (EMACB) Interrupt Disable Register -#define AT91C_EMACB_SA1H (AT91C_CAST(AT91C_REG *) 0xFFFBC09C) // (EMACB) Specific Address 1 Top, Last 2 bytes -#define AT91C_EMACB_RLE (AT91C_CAST(AT91C_REG *) 0xFFFBC088) // (EMACB) Receive Length Field Mismatch Register -#define AT91C_EMACB_TUND (AT91C_CAST(AT91C_REG *) 0xFFFBC064) // (EMACB) Transmit Underrun Error Register -#define AT91C_EMACB_RSR (AT91C_CAST(AT91C_REG *) 0xFFFBC020) // (EMACB) Receive Status Register -#define AT91C_EMACB_SA2L (AT91C_CAST(AT91C_REG *) 0xFFFBC0A0) // (EMACB) Specific Address 2 Bottom, First 4 bytes -#define AT91C_EMACB_FTO (AT91C_CAST(AT91C_REG *) 0xFFFBC040) // (EMACB) Frames Transmitted OK Register -#define AT91C_EMACB_RSE (AT91C_CAST(AT91C_REG *) 0xFFFBC074) // (EMACB) Receive Symbol Errors Register -#define AT91C_EMACB_NSR (AT91C_CAST(AT91C_REG *) 0xFFFBC008) // (EMACB) Network Status Register -#define AT91C_EMACB_RBQP (AT91C_CAST(AT91C_REG *) 0xFFFBC018) // (EMACB) Receive Buffer Queue Pointer -#define AT91C_EMACB_REV (AT91C_CAST(AT91C_REG *) 0xFFFBC0FC) // (EMACB) Revision Register -// ========== Register definition for ISI peripheral ========== -#define AT91C_ISI_DMACHDR (AT91C_CAST(AT91C_REG *) 0xFFFB403C) // (ISI) DMA Channel Disable Register -#define AT91C_ISI_IMR (AT91C_CAST(AT91C_REG *) 0xFFFB4034) // (ISI) Interrupt Mask Register -#define AT91C_ISI_R2YSET1 (AT91C_CAST(AT91C_REG *) 0xFFFB401C) // (ISI) Color Space Conversion RGB to YCrCb Register -#define AT91C_ISI_PDECF (AT91C_CAST(AT91C_REG *) 0xFFFB400C) // (ISI) Preview Decimation Factor Register -#define AT91C_ISI_CFG2 (AT91C_CAST(AT91C_REG *) 0xFFFB4004) // (ISI) Configuration Register 2 -#define AT91C_ISI_DMACCTRL (AT91C_CAST(AT91C_REG *) 0xFFFB4054) // (ISI) DMA Codec Control Register -#define AT91C_ISI_CTRL (AT91C_CAST(AT91C_REG *) 0xFFFB4024) // (ISI) Control Register -#define AT91C_ISI_Y2RSET0 (AT91C_CAST(AT91C_REG *) 0xFFFB4010) // (ISI) Color Space Conversion YCrCb to RGB Register -#define AT91C_ISI_WPSR (AT91C_CAST(AT91C_REG *) 0xFFFB40E8) // (ISI) Write Protection Status Register -#define AT91C_ISI_DMACHER (AT91C_CAST(AT91C_REG *) 0xFFFB4038) // (ISI) DMA Channel Enable Register -#define AT91C_ISI_DMACHSR (AT91C_CAST(AT91C_REG *) 0xFFFB4040) // (ISI) DMA Channel Status Register -#define AT91C_ISI_IDR (AT91C_CAST(AT91C_REG *) 0xFFFB4030) // (ISI) Interrupt Disable Register -#define AT91C_ISI_VER (AT91C_CAST(AT91C_REG *) 0xFFFB40FC) // (ISI) Version Register -#define AT91C_ISI_Y2RSET1 (AT91C_CAST(AT91C_REG *) 0xFFFB4014) // (ISI) Color Space Conversion YCrCb to RGB Register -#define AT91C_ISI_R2YSET2 (AT91C_CAST(AT91C_REG *) 0xFFFB4020) // (ISI) Color Space Conversion RGB to YCrCb Register -#define AT91C_ISI_SR (AT91C_CAST(AT91C_REG *) 0xFFFB4028) // (ISI) Status Register -#define AT91C_ISI_DMACDSCR (AT91C_CAST(AT91C_REG *) 0xFFFB4058) // (ISI) DMA Codec Descriptor Address Register -#define AT91C_ISI_IER (AT91C_CAST(AT91C_REG *) 0xFFFB402C) // (ISI) Interrupt Enable Register -#define AT91C_ISI_WPCR (AT91C_CAST(AT91C_REG *) 0xFFFB40E4) // (ISI) Write Protection Control Register -#define AT91C_ISI_DMACADDR (AT91C_CAST(AT91C_REG *) 0xFFFB4050) // (ISI) DMA Codec Base Address Register -#define AT91C_ISI_CFG1 (AT91C_CAST(AT91C_REG *) 0xFFFB4000) // (ISI) Configuration Register 1 -#define AT91C_ISI_R2YSET0 (AT91C_CAST(AT91C_REG *) 0xFFFB4018) // (ISI) Color Space Conversion RGB to YCrCb Register -#define AT91C_ISI_PSIZE (AT91C_CAST(AT91C_REG *) 0xFFFB4008) // (ISI) Preview Size Register -#define AT91C_ISI_DMAPDSCR (AT91C_CAST(AT91C_REG *) 0xFFFB404C) // (ISI) DMA Preview Descriptor Address Register -#define AT91C_ISI_DMAPADDR (AT91C_CAST(AT91C_REG *) 0xFFFB4044) // (ISI) DMA Preview Base Address Register -#define AT91C_ISI_DMAPCTRL (AT91C_CAST(AT91C_REG *) 0xFFFB4048) // (ISI) DMA Preview Control Register -// ========== Register definition for UHPHS_OHCI peripheral ========== -#define AT91C_OHCI_HcRhPortStatus (AT91C_CAST(AT91C_REG *) 0x00700054) // (UHPHS_OHCI) Root Hub Port Status Register -#define AT91C_OHCI_HcFmRemaining (AT91C_CAST(AT91C_REG *) 0x00700038) // (UHPHS_OHCI) Bit time remaining in the current Frame -#define AT91C_OHCI_HcInterruptEnable (AT91C_CAST(AT91C_REG *) 0x00700010) // (UHPHS_OHCI) Interrupt Enable Register -#define AT91C_OHCI_HcControl (AT91C_CAST(AT91C_REG *) 0x00700004) // (UHPHS_OHCI) Operating modes for the Host Controller -#define AT91C_OHCI_HcPeriodicStart (AT91C_CAST(AT91C_REG *) 0x00700040) // (UHPHS_OHCI) Periodic Start -#define AT91C_OHCI_HcInterruptStatus (AT91C_CAST(AT91C_REG *) 0x0070000C) // (UHPHS_OHCI) Interrupt Status Register -#define AT91C_OHCI_HcRhDescriptorB (AT91C_CAST(AT91C_REG *) 0x0070004C) // (UHPHS_OHCI) Root Hub characteristics B -#define AT91C_OHCI_HcInterruptDisable (AT91C_CAST(AT91C_REG *) 0x00700014) // (UHPHS_OHCI) Interrupt Disable Register -#define AT91C_OHCI_HcPeriodCurrentED (AT91C_CAST(AT91C_REG *) 0x0070001C) // (UHPHS_OHCI) Current Isochronous or Interrupt Endpoint Descriptor -#define AT91C_OHCI_HcRhDescriptorA (AT91C_CAST(AT91C_REG *) 0x00700048) // (UHPHS_OHCI) Root Hub characteristics A -#define AT91C_OHCI_HcRhStatus (AT91C_CAST(AT91C_REG *) 0x00700050) // (UHPHS_OHCI) Root Hub Status register -#define AT91C_OHCI_HcBulkCurrentED (AT91C_CAST(AT91C_REG *) 0x0070002C) // (UHPHS_OHCI) Current endpoint of the Bulk list -#define AT91C_OHCI_HcControlHeadED (AT91C_CAST(AT91C_REG *) 0x00700020) // (UHPHS_OHCI) First Endpoint Descriptor of the Control list -#define AT91C_OHCI_HcLSThreshold (AT91C_CAST(AT91C_REG *) 0x00700044) // (UHPHS_OHCI) LS Threshold -#define AT91C_OHCI_HcRevision (AT91C_CAST(AT91C_REG *) 0x00700000) // (UHPHS_OHCI) Revision -#define AT91C_OHCI_HcBulkDoneHead (AT91C_CAST(AT91C_REG *) 0x00700030) // (UHPHS_OHCI) Last completed transfer descriptor -#define AT91C_OHCI_HcFmNumber (AT91C_CAST(AT91C_REG *) 0x0070003C) // (UHPHS_OHCI) Frame number -#define AT91C_OHCI_HcFmInterval (AT91C_CAST(AT91C_REG *) 0x00700034) // (UHPHS_OHCI) Bit time between 2 consecutive SOFs -#define AT91C_OHCI_HcBulkHeadED (AT91C_CAST(AT91C_REG *) 0x00700028) // (UHPHS_OHCI) First endpoint register of the Bulk list -#define AT91C_OHCI_HcHCCA (AT91C_CAST(AT91C_REG *) 0x00700018) // (UHPHS_OHCI) Pointer to the Host Controller Communication Area -#define AT91C_OHCI_HcCommandStatus (AT91C_CAST(AT91C_REG *) 0x00700008) // (UHPHS_OHCI) Command & status Register -#define AT91C_OHCI_HcControlCurrentED (AT91C_CAST(AT91C_REG *) 0x00700024) // (UHPHS_OHCI) Endpoint Control and Status Register -// ========== Register definition for UHPHS_EHCI peripheral ========== -#define AT91C_EHCI_USBSTS (AT91C_CAST(AT91C_REG *) 0x00800014) // (UHPHS_EHCI) -#define AT91C_EHCI_INSNREG03 (AT91C_CAST(AT91C_REG *) 0x0080009C) // (UHPHS_EHCI) -#define AT91C_EHCI_INSNREG00 (AT91C_CAST(AT91C_REG *) 0x00800090) // (UHPHS_EHCI) -#define AT91C_EHCI_HCSPPORTROUTE (AT91C_CAST(AT91C_REG *) 0x0080000C) // (UHPHS_EHCI) -#define AT91C_EHCI_FRINDEX (AT91C_CAST(AT91C_REG *) 0x0080001C) // (UHPHS_EHCI) -#define AT91C_EHCI_CONFIGFLAG (AT91C_CAST(AT91C_REG *) 0x00800050) // (UHPHS_EHCI) -#define AT91C_EHCI_HCCPARAMS (AT91C_CAST(AT91C_REG *) 0x00800008) // (UHPHS_EHCI) -#define AT91C_EHCI_USBINTR (AT91C_CAST(AT91C_REG *) 0x00800018) // (UHPHS_EHCI) -#define AT91C_EHCI_PORTSC (AT91C_CAST(AT91C_REG *) 0x00800054) // (UHPHS_EHCI) -#define AT91C_EHCI_CTRLDSSEGMENT (AT91C_CAST(AT91C_REG *) 0x00800020) // (UHPHS_EHCI) -#define AT91C_EHCI_VERSION (AT91C_CAST(AT91C_REG *) 0x00800000) // (UHPHS_EHCI) -#define AT91C_EHCI_USBCMD (AT91C_CAST(AT91C_REG *) 0x00800010) // (UHPHS_EHCI) -#define AT91C_EHCI_INSNREG04 (AT91C_CAST(AT91C_REG *) 0x008000A0) // (UHPHS_EHCI) -#define AT91C_EHCI_PERIODICLISTBASE (AT91C_CAST(AT91C_REG *) 0x00800024) // (UHPHS_EHCI) -#define AT91C_EHCI_INSNREG01 (AT91C_CAST(AT91C_REG *) 0x00800094) // (UHPHS_EHCI) -#define AT91C_EHCI_HCSPARAMS (AT91C_CAST(AT91C_REG *) 0x00800004) // (UHPHS_EHCI) -#define AT91C_EHCI_INSNREG05 (AT91C_CAST(AT91C_REG *) 0x008000A4) // (UHPHS_EHCI) -#define AT91C_EHCI_ASYNCLISTADDR (AT91C_CAST(AT91C_REG *) 0x00800028) // (UHPHS_EHCI) -#define AT91C_EHCI_INSNREG02 (AT91C_CAST(AT91C_REG *) 0x00800098) // (UHPHS_EHCI) -// ========== Register definition for TRNG peripheral ========== -#define AT91C_TRNG_IDR (AT91C_CAST(AT91C_REG *) 0xFFFCC014) // (TRNG) Interrupt Disable Register -#define AT91C_TRNG_IER (AT91C_CAST(AT91C_REG *) 0xFFFCC010) // (TRNG) Interrupt Enable Register -#define AT91C_TRNG_VERSION (AT91C_CAST(AT91C_REG *) 0xFFFCC0FC) // (TRNG) TRNG Version Register -#define AT91C_TRNG_ISR (AT91C_CAST(AT91C_REG *) 0xFFFCC01C) // (TRNG) Interrupt Status Register -#define AT91C_TRNG_CR (AT91C_CAST(AT91C_REG *) 0xFFFCC000) // (TRNG) Control Register -#define AT91C_TRNG_ODATA (AT91C_CAST(AT91C_REG *) 0xFFFCC050) // (TRNG) Output Data Register -#define AT91C_TRNG_IMR (AT91C_CAST(AT91C_REG *) 0xFFFCC018) // (TRNG) Interrupt Mask Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM9G45 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_MCI0_CK (AT91C_PIO_PA0) // -#define AT91C_PA0_TCLK3 (AT91C_PIO_PA0) // -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_MCI0_CDA (AT91C_PIO_PA1) // -#define AT91C_PA1_TIOA3 (AT91C_PIO_PA1) // -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_ETX0 (AT91C_PIO_PA10) // Ethernet MAC Transmit Data 0 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_ETX1 (AT91C_PIO_PA11) // Ethernet MAC Transmit Data 1 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_ERX0 (AT91C_PIO_PA12) // Ethernet MAC Receive Data 0 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_ERX1 (AT91C_PIO_PA13) // Ethernet MAC Receive Data 1 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_ETXEN (AT91C_PIO_PA14) // Ethernet MAC Transmit Enable -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_ERXDV (AT91C_PIO_PA15) // Ethernet MAC Receive Data Valid -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_ERXER (AT91C_PIO_PA16) // Ethernet MAC Receive Error -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_ETXCK_EREFCK (AT91C_PIO_PA17) // Ethernet MAC Transmit Clock/Reference Clock -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_EMDC (AT91C_PIO_PA18) // Ethernet MAC Management Data Clock -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_EMDIO (AT91C_PIO_PA19) // Ethernet MAC Management Data Input/Output -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_MCI0_DA0 (AT91C_PIO_PA2) // -#define AT91C_PA2_TIOB3 (AT91C_PIO_PA2) // -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_TWD0 (AT91C_PIO_PA20) // TWI Two-wire Serial Data -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_TWCK0 (AT91C_PIO_PA21) // TWI Two-wire Serial Clock -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_MCI1_CDA (AT91C_PIO_PA22) // -#define AT91C_PA22_SCK3 (AT91C_PIO_PA22) // -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_MCI1_DA0 (AT91C_PIO_PA23) // -#define AT91C_PA23_RTS3 (AT91C_PIO_PA23) // -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_MCI1_DA1 (AT91C_PIO_PA24) // -#define AT91C_PA24_CTS3 (AT91C_PIO_PA24) // -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_MCI1_DA2 (AT91C_PIO_PA25) // -#define AT91C_PA25_PWM3 (AT91C_PIO_PA25) // -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_MCI1_DA3 (AT91C_PIO_PA26) // -#define AT91C_PA26_TIOB2 (AT91C_PIO_PA26) // -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_MCI1_DA4 (AT91C_PIO_PA27) // -#define AT91C_PA27_ETXER (AT91C_PIO_PA27) // Ethernet MAC Transmikt Coding Error -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_MCI1_DA5 (AT91C_PIO_PA28) // -#define AT91C_PA28_ERXCK (AT91C_PIO_PA28) // Ethernet MAC Receive Clock -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_MCI1_DA6 (AT91C_PIO_PA29) // -#define AT91C_PA29_ECRS (AT91C_PIO_PA29) // Ethernet MAC Carrier Sense/Carrier Sense and Data Valid -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_MCI0_DA1 (AT91C_PIO_PA3) // -#define AT91C_PA3_TCLK4 (AT91C_PIO_PA3) // -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_MCI1_DA7 (AT91C_PIO_PA30) // -#define AT91C_PA30_ECOL (AT91C_PIO_PA30) // Ethernet MAC Collision Detected -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_MCI1_CK (AT91C_PIO_PA31) // -#define AT91C_PA31_PCK0 (AT91C_PIO_PA31) // -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_MCI0_DA2 (AT91C_PIO_PA4) // -#define AT91C_PA4_TIOA4 (AT91C_PIO_PA4) // -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_MCI0_DA3 (AT91C_PIO_PA5) // -#define AT91C_PA5_TIOB4 (AT91C_PIO_PA5) // -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_MCI0_DA4 (AT91C_PIO_PA6) // -#define AT91C_PA6_ETX2 (AT91C_PIO_PA6) // Ethernet MAC Transmit Data 2 -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_MCI0_DA5 (AT91C_PIO_PA7) // -#define AT91C_PA7_ETX3 (AT91C_PIO_PA7) // Ethernet MAC Transmit Data 3 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_MCI0_DA6 (AT91C_PIO_PA8) // -#define AT91C_PA8_ERX2 (AT91C_PIO_PA8) // Ethernet MAC Receive Data 2 -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_MCI0_DA7 (AT91C_PIO_PA9) // -#define AT91C_PA9_ERX3 (AT91C_PIO_PA9) // Ethernet MAC Receive Data 3 -#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0 -#define AT91C_PB0_SPI0_MISO (AT91C_PIO_PB0) // SPI 0 Master In Slave -#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1 -#define AT91C_PB1_SPI0_MOSI (AT91C_PIO_PB1) // SPI 0 Master Out Slave -#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10 -#define AT91C_PB10_TWD1 (AT91C_PIO_PB10) // -#define AT91C_PB10_ISI_D10 (AT91C_PIO_PB10) // -#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11 -#define AT91C_PB11_TWCK1 (AT91C_PIO_PB11) // -#define AT91C_PB11_ISI_D11 (AT91C_PIO_PB11) // -#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12 -#define AT91C_PB12_DRXD (AT91C_PIO_PB12) // -#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13 -#define AT91C_PB13_DTXD (AT91C_PIO_PB13) // -#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14 -#define AT91C_PB14_SPI1_MISO (AT91C_PIO_PB14) // -#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15 -#define AT91C_PB15_SPI1_MOSI (AT91C_PIO_PB15) // -#define AT91C_PB15_CTS0 (AT91C_PIO_PB15) // -#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16 -#define AT91C_PB16_SPI1_SPCK (AT91C_PIO_PB16) // -#define AT91C_PB16_SCK0 (AT91C_PIO_PB16) // -#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17 -#define AT91C_PB17_SPI1_NPCS0 (AT91C_PIO_PB17) // -#define AT91C_PB17_RTS0 (AT91C_PIO_PB17) // -#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18 -#define AT91C_PB18_RXD0 (AT91C_PIO_PB18) // -#define AT91C_PB18_SPI0_NPCS1 (AT91C_PIO_PB18) // -#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19 -#define AT91C_PB19_TXD0 (AT91C_PIO_PB19) // -#define AT91C_PB19_SPI0_NPCS2 (AT91C_PIO_PB19) // -#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2 -#define AT91C_PB2_SPI0_SPCK (AT91C_PIO_PB2) // SPI 0 Serial Clock -#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20 -#define AT91C_PB20_ISI_D0 (AT91C_PIO_PB20) // -#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21 -#define AT91C_PB21_ISI_D1 (AT91C_PIO_PB21) // -#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22 -#define AT91C_PB22_ISI_D2 (AT91C_PIO_PB22) // -#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23 -#define AT91C_PB23_ISI_D3 (AT91C_PIO_PB23) // -#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24 -#define AT91C_PB24_ISI_D4 (AT91C_PIO_PB24) // -#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25 -#define AT91C_PB25_ISI_D5 (AT91C_PIO_PB25) // -#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26 -#define AT91C_PB26_ISI_D6 (AT91C_PIO_PB26) // -#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27 -#define AT91C_PB27_ISI_D7 (AT91C_PIO_PB27) // -#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28 -#define AT91C_PB28_ISI_PCK (AT91C_PIO_PB28) // -#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29 -#define AT91C_PB29_ISI_VSYNC (AT91C_PIO_PB29) // -#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3 -#define AT91C_PB3_SPI0_NPCS0 (AT91C_PIO_PB3) // SPI 0 Peripheral Chip Select 0 -#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30 -#define AT91C_PB30_ISI_HSYNC (AT91C_PIO_PB30) // -#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31 -#define AT91C_PB31_ (AT91C_PIO_PB31) // -#define AT91C_PB31_PCK1 (AT91C_PIO_PB31) // -#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4 -#define AT91C_PB4_TXD1 (AT91C_PIO_PB4) // USART 1 Transmit Data -#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5 -#define AT91C_PB5_RXD1 (AT91C_PIO_PB5) // USART 1 Receive Data -#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6 -#define AT91C_PB6_TXD2 (AT91C_PIO_PB6) // USART 2 Transmit Data -#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7 -#define AT91C_PB7_RXD2 (AT91C_PIO_PB7) // USART 2 Receive Data -#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8 -#define AT91C_PB8_TXD3 (AT91C_PIO_PB8) // USART 3 Transmit Data -#define AT91C_PB8_ISI_D8 (AT91C_PIO_PB8) // -#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9 -#define AT91C_PB9_RXD3 (AT91C_PIO_PB9) // USART 3 Receive Data -#define AT91C_PB9_ISI_D9 (AT91C_PIO_PB9) // -#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0 -#define AT91C_PC0_DQM2 (AT91C_PIO_PC0) // DQM2 -#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1 -#define AT91C_PC1_DQM3 (AT91C_PIO_PC1) // DQM3 -#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10 -#define AT91C_PC10_NCS4_CFCS0 (AT91C_PIO_PC10) // -#define AT91C_PC10_TCLK2 (AT91C_PIO_PC10) // -#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11 -#define AT91C_PC11_NCS5_CFCS1 (AT91C_PIO_PC11) // -#define AT91C_PC11_CTS2 (AT91C_PIO_PC11) // -#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12 -#define AT91C_PC12_A25_CFRNW (AT91C_PIO_PC12) // -#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13 -#define AT91C_PC13_NCS2 (AT91C_PIO_PC13) // -#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14 -#define AT91C_PC14_NCS3_NANDCS (AT91C_PIO_PC14) // -#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15 -#define AT91C_PC15_NWAIT (AT91C_PIO_PC15) // -#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16 -#define AT91C_PC16_D16 (AT91C_PIO_PC16) // -#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17 -#define AT91C_PC17_D17 (AT91C_PIO_PC17) // -#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18 -#define AT91C_PC18_D18 (AT91C_PIO_PC18) // -#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19 -#define AT91C_PC19_D19 (AT91C_PIO_PC19) // -#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2 -#define AT91C_PC2_A19 (AT91C_PIO_PC2) // -#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20 -#define AT91C_PC20_D20 (AT91C_PIO_PC20) // -#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21 -#define AT91C_PC21_D21 (AT91C_PIO_PC21) // -#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22 -#define AT91C_PC22_D22 (AT91C_PIO_PC22) // -#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23 -#define AT91C_PC23_D23 (AT91C_PIO_PC23) // -#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24 -#define AT91C_PC24_D24 (AT91C_PIO_PC24) // -#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25 -#define AT91C_PC25_D25 (AT91C_PIO_PC25) // -#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26 -#define AT91C_PC26_D26 (AT91C_PIO_PC26) // -#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27 -#define AT91C_PC27_D27 (AT91C_PIO_PC27) // -#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28 -#define AT91C_PC28_D28 (AT91C_PIO_PC28) // -#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29 -#define AT91C_PC29_D29 (AT91C_PIO_PC29) // -#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3 -#define AT91C_PC3_A20 (AT91C_PIO_PC3) // -#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30 -#define AT91C_PC30_D30 (AT91C_PIO_PC30) // -#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31 -#define AT91C_PC31_D31 (AT91C_PIO_PC31) // -#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4 -#define AT91C_PC4_A21_NANDALE (AT91C_PIO_PC4) // -#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5 -#define AT91C_PC5_A22_NANDCLE (AT91C_PIO_PC5) // -#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6 -#define AT91C_PC6_A23 (AT91C_PIO_PC6) // -#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7 -#define AT91C_PC7_A24 (AT91C_PIO_PC7) // -#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8 -#define AT91C_PC8_CFCE1 (AT91C_PIO_PC8) // -#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9 -#define AT91C_PC9_CFCE2 (AT91C_PIO_PC9) // -#define AT91C_PC9_RTS2 (AT91C_PIO_PC9) // -#define AT91C_PIO_PD0 (1 << 0) // Pin Controlled by PD0 -#define AT91C_PD0_TK0 (AT91C_PIO_PD0) // -#define AT91C_PD0_PWM3 (AT91C_PIO_PD0) // -#define AT91C_PIO_PD1 (1 << 1) // Pin Controlled by PD1 -#define AT91C_PD1_TF0 (AT91C_PIO_PD1) // -#define AT91C_PIO_PD10 (1 << 10) // Pin Controlled by PD10 -#define AT91C_PD10_TD1 (AT91C_PIO_PD10) // -#define AT91C_PIO_PD11 (1 << 11) // Pin Controlled by PD11 -#define AT91C_PD11_RD1 (AT91C_PIO_PD11) // -#define AT91C_PIO_PD12 (1 << 12) // Pin Controlled by PD12 -#define AT91C_PD12_TK1 (AT91C_PIO_PD12) // -#define AT91C_PD12_PCK0 (AT91C_PIO_PD12) // -#define AT91C_PIO_PD13 (1 << 13) // Pin Controlled by PD13 -#define AT91C_PD13_RK1 (AT91C_PIO_PD13) // -#define AT91C_PIO_PD14 (1 << 14) // Pin Controlled by PD14 -#define AT91C_PD14_TF1 (AT91C_PIO_PD14) // -#define AT91C_PIO_PD15 (1 << 15) // Pin Controlled by PD15 -#define AT91C_PD15_RF1 (AT91C_PIO_PD15) // -#define AT91C_PIO_PD16 (1 << 16) // Pin Controlled by PD16 -#define AT91C_PD16_RTS1 (AT91C_PIO_PD16) // -#define AT91C_PIO_PD17 (1 << 17) // Pin Controlled by PD17 -#define AT91C_PD17_CTS1 (AT91C_PIO_PD17) // -#define AT91C_PIO_PD18 (1 << 18) // Pin Controlled by PD18 -#define AT91C_PD18_SPI1_NPCS2 (AT91C_PIO_PD18) // -#define AT91C_PD18_IRQ (AT91C_PIO_PD18) // -#define AT91C_PIO_PD19 (1 << 19) // Pin Controlled by PD19 -#define AT91C_PD19_SPI1_NPCS3 (AT91C_PIO_PD19) // -#define AT91C_PD19_FIQ (AT91C_PIO_PD19) // -#define AT91C_PIO_PD2 (1 << 2) // Pin Controlled by PD2 -#define AT91C_PD2_TD0 (AT91C_PIO_PD2) // -#define AT91C_PIO_PD20 (1 << 20) // Pin Controlled by PD20 -#define AT91C_PD20_TIOA0 (AT91C_PIO_PD20) // -#define AT91C_PIO_PD21 (1 << 21) // Pin Controlled by PD21 -#define AT91C_PD21_TIOA1 (AT91C_PIO_PD21) // -#define AT91C_PIO_PD22 (1 << 22) // Pin Controlled by PD22 -#define AT91C_PD22_TIOA2 (AT91C_PIO_PD22) // -#define AT91C_PIO_PD23 (1 << 23) // Pin Controlled by PD23 -#define AT91C_PD23_TCLK0 (AT91C_PIO_PD23) // -#define AT91C_PIO_PD24 (1 << 24) // Pin Controlled by PD24 -#define AT91C_PD24_SPI0_NPCS1 (AT91C_PIO_PD24) // -#define AT91C_PD24_PWM0 (AT91C_PIO_PD24) // -#define AT91C_PIO_PD25 (1 << 25) // Pin Controlled by PD25 -#define AT91C_PD25_SPI0_NPCS2 (AT91C_PIO_PD25) // -#define AT91C_PD25_PWM1 (AT91C_PIO_PD25) // -#define AT91C_PIO_PD26 (1 << 26) // Pin Controlled by PD26 -#define AT91C_PD26_PCK0 (AT91C_PIO_PD26) // -#define AT91C_PD26_PWM2 (AT91C_PIO_PD26) // -#define AT91C_PIO_PD27 (1 << 27) // Pin Controlled by PD27 -#define AT91C_PD27_PCK1 (AT91C_PIO_PD27) // -#define AT91C_PD27_SPI0_NPCS3 (AT91C_PIO_PD27) // -#define AT91C_PIO_PD28 (1 << 28) // Pin Controlled by PD28 -#define AT91C_PD28_TSADTRG (AT91C_PIO_PD28) // -#define AT91C_PD28_SPI1_NPCS1 (AT91C_PIO_PD28) // -#define AT91C_PIO_PD29 (1 << 29) // Pin Controlled by PD29 -#define AT91C_PD29_TCLK1 (AT91C_PIO_PD29) // -#define AT91C_PD29_SCK1 (AT91C_PIO_PD29) // -#define AT91C_PIO_PD3 (1 << 3) // Pin Controlled by PD3 -#define AT91C_PD3_RD0 (AT91C_PIO_PD3) // -#define AT91C_PIO_PD30 (1 << 30) // Pin Controlled by PD30 -#define AT91C_PD30_TIOB0 (AT91C_PIO_PD30) // -#define AT91C_PD30_SCK2 (AT91C_PIO_PD30) // -#define AT91C_PIO_PD31 (1 << 31) // Pin Controlled by PD31 -#define AT91C_PD31_TIOB1 (AT91C_PIO_PD31) // -#define AT91C_PD31_PWM1 (AT91C_PIO_PD31) // -#define AT91C_PIO_PD4 (1 << 4) // Pin Controlled by PD4 -#define AT91C_PD4_RK0 (AT91C_PIO_PD4) // -#define AT91C_PIO_PD5 (1 << 5) // Pin Controlled by PD5 -#define AT91C_PD5_RF0 (AT91C_PIO_PD5) // -#define AT91C_PIO_PD6 (1 << 6) // Pin Controlled by PD6 -#define AT91C_PD6_AC97RX (AT91C_PIO_PD6) // -#define AT91C_PIO_PD7 (1 << 7) // Pin Controlled by PD7 -#define AT91C_PD7_AC97TX (AT91C_PIO_PD7) // -#define AT91C_PD7_TIOA5 (AT91C_PIO_PD7) // -#define AT91C_PIO_PD8 (1 << 8) // Pin Controlled by PD8 -#define AT91C_PD8_AC97FS (AT91C_PIO_PD8) // -#define AT91C_PD8_TIOB5 (AT91C_PIO_PD8) // -#define AT91C_PIO_PD9 (1 << 9) // Pin Controlled by PD9 -#define AT91C_PD9_AC97CK (AT91C_PIO_PD9) // -#define AT91C_PD9_TCLK5 (AT91C_PIO_PD9) // -#define AT91C_PIO_PE0 (1 << 0) // Pin Controlled by PE0 -#define AT91C_PE0_LCDPWR (AT91C_PIO_PE0) // -#define AT91C_PE0_PCK0 (AT91C_PIO_PE0) // -#define AT91C_PIO_PE1 (1 << 1) // Pin Controlled by PE1 -#define AT91C_PE1_LCDMOD (AT91C_PIO_PE1) // -#define AT91C_PIO_PE10 (1 << 10) // Pin Controlled by PE10 -#define AT91C_PE10_LCDD3 (AT91C_PIO_PE10) // -#define AT91C_PE10_LCDD5 (AT91C_PIO_PE10) // -#define AT91C_PIO_PE11 (1 << 11) // Pin Controlled by PE11 -#define AT91C_PE11_LCDD4 (AT91C_PIO_PE11) // -#define AT91C_PE11_LCDD6 (AT91C_PIO_PE11) // -#define AT91C_PIO_PE12 (1 << 12) // Pin Controlled by PE12 -#define AT91C_PE12_LCDD5 (AT91C_PIO_PE12) // -#define AT91C_PE12_LCDD7 (AT91C_PIO_PE12) // -#define AT91C_PIO_PE13 (1 << 13) // Pin Controlled by PE13 -#define AT91C_PE13_LCDD6 (AT91C_PIO_PE13) // -#define AT91C_PE13_LCDD10 (AT91C_PIO_PE13) // -#define AT91C_PIO_PE14 (1 << 14) // Pin Controlled by PE14 -#define AT91C_PE14_LCDD7 (AT91C_PIO_PE14) // -#define AT91C_PE14_LCDD11 (AT91C_PIO_PE14) // -#define AT91C_PIO_PE15 (1 << 15) // Pin Controlled by PE15 -#define AT91C_PE15_LCDD8 (AT91C_PIO_PE15) // -#define AT91C_PE15_LCDD12 (AT91C_PIO_PE15) // -#define AT91C_PIO_PE16 (1 << 16) // Pin Controlled by PE16 -#define AT91C_PE16_LCDD9 (AT91C_PIO_PE16) // -#define AT91C_PE16_LCDD13 (AT91C_PIO_PE16) // -#define AT91C_PIO_PE17 (1 << 17) // Pin Controlled by PE17 -#define AT91C_PE17_LCDD10 (AT91C_PIO_PE17) // -#define AT91C_PE17_LCDD14 (AT91C_PIO_PE17) // -#define AT91C_PIO_PE18 (1 << 18) // Pin Controlled by PE18 -#define AT91C_PE18_LCDD11 (AT91C_PIO_PE18) // -#define AT91C_PE18_LCDD15 (AT91C_PIO_PE18) // -#define AT91C_PIO_PE19 (1 << 19) // Pin Controlled by PE19 -#define AT91C_PE19_LCDD12 (AT91C_PIO_PE19) // -#define AT91C_PE19_LCDD18 (AT91C_PIO_PE19) // -#define AT91C_PIO_PE2 (1 << 2) // Pin Controlled by PE2 -#define AT91C_PE2_LCDCC (AT91C_PIO_PE2) // -#define AT91C_PIO_PE20 (1 << 20) // Pin Controlled by PE20 -#define AT91C_PE20_LCDD13 (AT91C_PIO_PE20) // -#define AT91C_PE20_LCDD19 (AT91C_PIO_PE20) // -#define AT91C_PIO_PE21 (1 << 21) // Pin Controlled by PE21 -#define AT91C_PE21_LCDD14 (AT91C_PIO_PE21) // -#define AT91C_PE21_LCDD20 (AT91C_PIO_PE21) // -#define AT91C_PIO_PE22 (1 << 22) // Pin Controlled by PE22 -#define AT91C_PE22_LCDD15 (AT91C_PIO_PE22) // -#define AT91C_PE22_LCDD21 (AT91C_PIO_PE22) // -#define AT91C_PIO_PE23 (1 << 23) // Pin Controlled by PE23 -#define AT91C_PE23_LCDD16 (AT91C_PIO_PE23) // -#define AT91C_PE23_LCDD22 (AT91C_PIO_PE23) // -#define AT91C_PIO_PE24 (1 << 24) // Pin Controlled by PE24 -#define AT91C_PE24_LCDD17 (AT91C_PIO_PE24) // -#define AT91C_PE24_LCDD23 (AT91C_PIO_PE24) // -#define AT91C_PIO_PE25 (1 << 25) // Pin Controlled by PE25 -#define AT91C_PE25_LCDD18 (AT91C_PIO_PE25) // -#define AT91C_PIO_PE26 (1 << 26) // Pin Controlled by PE26 -#define AT91C_PE26_LCDD19 (AT91C_PIO_PE26) // -#define AT91C_PIO_PE27 (1 << 27) // Pin Controlled by PE27 -#define AT91C_PE27_LCDD20 (AT91C_PIO_PE27) // -#define AT91C_PIO_PE28 (1 << 28) // Pin Controlled by PE28 -#define AT91C_PE28_LCDD21 (AT91C_PIO_PE28) // -#define AT91C_PIO_PE29 (1 << 29) // Pin Controlled by PE29 -#define AT91C_PE29_LCDD22 (AT91C_PIO_PE29) // -#define AT91C_PIO_PE3 (1 << 3) // Pin Controlled by PE3 -#define AT91C_PE3_LCDVSYNC (AT91C_PIO_PE3) // -#define AT91C_PIO_PE30 (1 << 30) // Pin Controlled by PE30 -#define AT91C_PE30_LCDD23 (AT91C_PIO_PE30) // -#define AT91C_PIO_PE31 (1 << 31) // Pin Controlled by PE31 -#define AT91C_PE31_PWM2 (AT91C_PIO_PE31) // -#define AT91C_PE31_PCK1 (AT91C_PIO_PE31) // -#define AT91C_PIO_PE4 (1 << 4) // Pin Controlled by PE4 -#define AT91C_PE4_LCDHSYNC (AT91C_PIO_PE4) // -#define AT91C_PIO_PE5 (1 << 5) // Pin Controlled by PE5 -#define AT91C_PE5_LCDDOTCK (AT91C_PIO_PE5) // -#define AT91C_PIO_PE6 (1 << 6) // Pin Controlled by PE6 -#define AT91C_PE6_LCDDEN (AT91C_PIO_PE6) // -#define AT91C_PIO_PE7 (1 << 7) // Pin Controlled by PE7 -#define AT91C_PE7_LCDD0 (AT91C_PIO_PE7) // -#define AT91C_PE7_LCDD2 (AT91C_PIO_PE7) // -#define AT91C_PIO_PE8 (1 << 8) // Pin Controlled by PE8 -#define AT91C_PE8_LCDD1 (AT91C_PIO_PE8) // -#define AT91C_PE8_LCDD3 (AT91C_PIO_PE8) // -#define AT91C_PIO_PE9 (1 << 9) // Pin Controlled by PE9 -#define AT91C_PE9_LCDD2 (AT91C_PIO_PE9) // -#define AT91C_PE9_LCDD4 (AT91C_PIO_PE9) // - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM9G45 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Controller -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A -#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B -#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C -#define AT91C_ID_PIOD_E ( 5) // Parallel IO Controller D and E -#define AT91C_ID_TRNG ( 6) // True Random Number Generator -#define AT91C_ID_US0 ( 7) // USART 0 -#define AT91C_ID_US1 ( 8) // USART 1 -#define AT91C_ID_US2 ( 9) // USART 2 -#define AT91C_ID_US3 (10) // USART 2 -#define AT91C_ID_MCI0 (11) // Multimedia Card Interface 0 -#define AT91C_ID_TWI0 (12) // TWI 0 -#define AT91C_ID_TWI1 (13) // TWI 1 -#define AT91C_ID_SPI0 (14) // Serial Peripheral Interface -#define AT91C_ID_SPI1 (15) // Serial Peripheral Interface -#define AT91C_ID_SSC0 (16) // Serial Synchronous Controller 0 -#define AT91C_ID_SSC1 (17) // Serial Synchronous Controller 1 -#define AT91C_ID_TC (18) // Timer Counter 0, 1, 2, 3, 4, 5 -#define AT91C_ID_PWMC (19) // Pulse Width Modulation Controller -#define AT91C_ID_TSADC (20) // Touch Screen Controller -#define AT91C_ID_HDMA (21) // HDMA -#define AT91C_ID_UHPHS (22) // USB Host High Speed -#define AT91C_ID_LCDC (23) // LCD Controller -#define AT91C_ID_AC97C (24) // AC97 Controller -#define AT91C_ID_EMAC (25) // Ethernet MAC -#define AT91C_ID_ISI (26) // Image Sensor Interface -#define AT91C_ID_UDPHS (27) // USB Device HS -#define AT91C_ID_MCI1 (29) // Multimedia Card Interface 1 -#define AT91C_ID_VDEC (30) // Video Decoder -#define AT91C_ID_IRQ0 (31) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ALL_INT (0xEFFFFFFF) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM9G45 -// ***************************************************************************** -#define AT91C_BASE_SFR (AT91C_CAST(AT91PS_SFR) 0xFFF74000) // (SFR) Base Address -#define AT91C_BASE_SYS (AT91C_CAST(AT91PS_SYS) 0xFFFFC000) // (SYS) Base Address -#define AT91C_BASE_EBI (AT91C_CAST(AT91PS_EBI) 0xFFFFE200) // (EBI) Base Address -#define AT91C_BASE_DDR2CP1 (AT91C_CAST(AT91PS_HDDRSDRC2) 0xFFFFE400) // (DDR2CP1) Base Address -#define AT91C_BASE_DDR2C (AT91C_CAST(AT91PS_HDDRSDRC2) 0xFFFFE600) // (DDR2C) Base Address -#define AT91C_BASE_SMC (AT91C_CAST(AT91PS_SMC) 0xFFFFE800) // (SMC) Base Address -#define AT91C_BASE_MATRIX (AT91C_CAST(AT91PS_MATRIX) 0xFFFFEA00) // (MATRIX) Base Address -#define AT91C_BASE_AIC (AT91C_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (AT91C_CAST(AT91PS_PDC) 0xFFFFEF00) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (AT91C_CAST(AT91PS_DBGU) 0xFFFFEE00) // (DBGU) Base Address -#define AT91C_BASE_PIOA (AT91C_CAST(AT91PS_PIO) 0xFFFFF200) // (PIOA) Base Address -#define AT91C_BASE_PIOB (AT91C_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOB) Base Address -#define AT91C_BASE_PIOC (AT91C_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOC) Base Address -#define AT91C_BASE_PIOD (AT91C_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOD) Base Address -#define AT91C_BASE_PIOE (AT91C_CAST(AT91PS_PIO) 0xFFFFFA00) // (PIOE) Base Address -#define AT91C_BASE_PMC (AT91C_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_CKGR (AT91C_CAST(AT91PS_CKGR) 0xFFFFFC1C) // (CKGR) Base Address -#define AT91C_BASE_RSTC (AT91C_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_SHDWC (AT91C_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address -#define AT91C_BASE_RTTC (AT91C_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (AT91C_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (AT91C_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_RTC (AT91C_CAST(AT91PS_RTC) 0xFFFFFDB0) // (RTC) Base Address -#define AT91C_BASE_TC0 (AT91C_CAST(AT91PS_TC) 0xFFF7C000) // (TC0) Base Address -#define AT91C_BASE_TC1 (AT91C_CAST(AT91PS_TC) 0xFFF7C040) // (TC1) Base Address -#define AT91C_BASE_TC2 (AT91C_CAST(AT91PS_TC) 0xFFF7C080) // (TC2) Base Address -#define AT91C_BASE_TC3 (AT91C_CAST(AT91PS_TC) 0xFFFD4000) // (TC3) Base Address -#define AT91C_BASE_TC4 (AT91C_CAST(AT91PS_TC) 0xFFFD4040) // (TC4) Base Address -#define AT91C_BASE_TC5 (AT91C_CAST(AT91PS_TC) 0xFFFD4080) // (TC5) Base Address -#define AT91C_BASE_TCB0 (AT91C_CAST(AT91PS_TCB) 0xFFF7C000) // (TCB0) Base Address -#define AT91C_BASE_TCB1 (AT91C_CAST(AT91PS_TCB) 0xFFFD4000) // (TCB1) Base Address -#define AT91C_BASE_MCI0 (AT91C_CAST(AT91PS_MCI) 0xFFF80000) // (MCI0) Base Address -#define AT91C_BASE_MCI1 (AT91C_CAST(AT91PS_MCI) 0xFFFD0000) // (MCI1) Base Address -#define AT91C_BASE_TWI0 (AT91C_CAST(AT91PS_TWI) 0xFFF84000) // (TWI0) Base Address -#define AT91C_BASE_TWI1 (AT91C_CAST(AT91PS_TWI) 0xFFF88000) // (TWI1) Base Address -#define AT91C_BASE_PDC_US0 (AT91C_CAST(AT91PS_PDC) 0xFFF8C100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (AT91C_CAST(AT91PS_USART) 0xFFF8C000) // (US0) Base Address -#define AT91C_BASE_PDC_US1 (AT91C_CAST(AT91PS_PDC) 0xFFF90100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (AT91C_CAST(AT91PS_USART) 0xFFF90000) // (US1) Base Address -#define AT91C_BASE_PDC_US2 (AT91C_CAST(AT91PS_PDC) 0xFFF94100) // (PDC_US2) Base Address -#define AT91C_BASE_US2 (AT91C_CAST(AT91PS_USART) 0xFFF94000) // (US2) Base Address -#define AT91C_BASE_PDC_US3 (AT91C_CAST(AT91PS_PDC) 0xFFF98100) // (PDC_US3) Base Address -#define AT91C_BASE_US3 (AT91C_CAST(AT91PS_USART) 0xFFF98000) // (US3) Base Address -#define AT91C_BASE_PDC_SSC0 (AT91C_CAST(AT91PS_PDC) 0xFFF9C100) // (PDC_SSC0) Base Address -#define AT91C_BASE_SSC0 (AT91C_CAST(AT91PS_SSC) 0xFFF9C000) // (SSC0) Base Address -#define AT91C_BASE_PDC_SSC1 (AT91C_CAST(AT91PS_PDC) 0xFFFA0100) // (PDC_SSC1) Base Address -#define AT91C_BASE_SSC1 (AT91C_CAST(AT91PS_SSC) 0xFFFA0000) // (SSC1) Base Address -#define AT91C_BASE_PWMC_CH0 (AT91C_CAST(AT91PS_PWMC_CH) 0xFFFB8200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC_CH1 (AT91C_CAST(AT91PS_PWMC_CH) 0xFFFB8220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH2 (AT91C_CAST(AT91PS_PWMC_CH) 0xFFFB8240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH3 (AT91C_CAST(AT91PS_PWMC_CH) 0xFFFB8260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC (AT91C_CAST(AT91PS_PWMC) 0xFFFB8000) // (PWMC) Base Address -#define AT91C_BASE_PDC_SPI0 (AT91C_CAST(AT91PS_PDC) 0xFFFA4100) // (PDC_SPI0) Base Address -#define AT91C_BASE_PDC_SPI1 (AT91C_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_SPI1) Base Address -#define AT91C_BASE_SPI0 (AT91C_CAST(AT91PS_SPI) 0xFFFA4000) // (SPI0) Base Address -#define AT91C_BASE_SPI1 (AT91C_CAST(AT91PS_SPI) 0xFFFA8000) // (SPI1) Base Address -#define AT91C_BASE_PDC_TSADC (AT91C_CAST(AT91PS_PDC) 0xFFFB0100) // (PDC_TSADC) Base Address -#define AT91C_BASE_TSADC (AT91C_CAST(AT91PS_TSADC) 0xFFFB0000) // (TSADC) Base Address -#define AT91C_BASE_UDPHS_EPTFIFO (AT91C_CAST(AT91PS_UDPHS_EPTFIFO) 0x00600000) // (UDPHS_EPTFIFO) Base Address -#define AT91C_BASE_UDPHS_EPT_0 (AT91C_CAST(AT91PS_UDPHS_EPT) 0xFFF78100) // (UDPHS_EPT_0) Base Address -#define AT91C_BASE_UDPHS_EPT_1 (AT91C_CAST(AT91PS_UDPHS_EPT) 0xFFF78120) // (UDPHS_EPT_1) Base Address -#define AT91C_BASE_UDPHS_EPT_2 (AT91C_CAST(AT91PS_UDPHS_EPT) 0xFFF78140) // (UDPHS_EPT_2) Base Address -#define AT91C_BASE_UDPHS_EPT_3 (AT91C_CAST(AT91PS_UDPHS_EPT) 0xFFF78160) // (UDPHS_EPT_3) Base Address -#define AT91C_BASE_UDPHS_EPT_4 (AT91C_CAST(AT91PS_UDPHS_EPT) 0xFFF78180) // (UDPHS_EPT_4) Base Address -#define AT91C_BASE_UDPHS_EPT_5 (AT91C_CAST(AT91PS_UDPHS_EPT) 0xFFF781A0) // (UDPHS_EPT_5) Base Address -#define AT91C_BASE_UDPHS_EPT_6 (AT91C_CAST(AT91PS_UDPHS_EPT) 0xFFF781C0) // (UDPHS_EPT_6) Base Address -#define AT91C_BASE_UDPHS_DMA_1 (AT91C_CAST(AT91PS_UDPHS_DMA) 0xFFF78310) // (UDPHS_DMA_1) Base Address -#define AT91C_BASE_UDPHS_DMA_2 (AT91C_CAST(AT91PS_UDPHS_DMA) 0xFFF78320) // (UDPHS_DMA_2) Base Address -#define AT91C_BASE_UDPHS_DMA_3 (AT91C_CAST(AT91PS_UDPHS_DMA) 0xFFF78330) // (UDPHS_DMA_3) Base Address -#define AT91C_BASE_UDPHS_DMA_4 (AT91C_CAST(AT91PS_UDPHS_DMA) 0xFFF78340) // (UDPHS_DMA_4) Base Address -#define AT91C_BASE_UDPHS_DMA_5 (AT91C_CAST(AT91PS_UDPHS_DMA) 0xFFF78350) // (UDPHS_DMA_5) Base Address -#define AT91C_BASE_UDPHS_DMA_6 (AT91C_CAST(AT91PS_UDPHS_DMA) 0xFFF78360) // (UDPHS_DMA_6) Base Address -#define AT91C_BASE_UDPHS (AT91C_CAST(AT91PS_UDPHS) 0xFFF78000) // (UDPHS) Base Address -#define AT91C_BASE_PDC_AC97C (AT91C_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_AC97C) Base Address -#define AT91C_BASE_AC97C (AT91C_CAST(AT91PS_AC97C) 0xFFFAC000) // (AC97C) Base Address -#define AT91C_BASE_LCDC (AT91C_CAST(AT91PS_LCDC) 0x00500000) // (LCDC) Base Address -#define AT91C_BASE_LCDC_16B_TFT (AT91C_CAST(AT91PS_LCDC) 0x00500000) // (LCDC_16B_TFT) Base Address -#define AT91C_BASE_HDMA_CH_0 (AT91C_CAST(AT91PS_HDMA_CH) 0xFFFFEC3C) // (HDMA_CH_0) Base Address -#define AT91C_BASE_HDMA_CH_1 (AT91C_CAST(AT91PS_HDMA_CH) 0xFFFFEC64) // (HDMA_CH_1) Base Address -#define AT91C_BASE_HDMA_CH_2 (AT91C_CAST(AT91PS_HDMA_CH) 0xFFFFEC8C) // (HDMA_CH_2) Base Address -#define AT91C_BASE_HDMA_CH_3 (AT91C_CAST(AT91PS_HDMA_CH) 0xFFFFECB4) // (HDMA_CH_3) Base Address -#define AT91C_BASE_HDMA_CH_4 (AT91C_CAST(AT91PS_HDMA_CH) 0xFFFFECDC) // (HDMA_CH_4) Base Address -#define AT91C_BASE_HDMA_CH_5 (AT91C_CAST(AT91PS_HDMA_CH) 0xFFFFED04) // (HDMA_CH_5) Base Address -#define AT91C_BASE_HDMA_CH_6 (AT91C_CAST(AT91PS_HDMA_CH) 0xFFFFED2C) // (HDMA_CH_6) Base Address -#define AT91C_BASE_HDMA_CH_7 (AT91C_CAST(AT91PS_HDMA_CH) 0xFFFFED54) // (HDMA_CH_7) Base Address -#define AT91C_BASE_HDMA (AT91C_CAST(AT91PS_HDMA) 0xFFFFEC00) // (HDMA) Base Address -#define AT91C_BASE_HECC (AT91C_CAST(AT91PS_ECC) 0xFFFFE200) // (HECC) Base Address -#define AT91C_BASE_EMACB (AT91C_CAST(AT91PS_EMAC) 0xFFFBC000) // (EMACB) Base Address -#define AT91C_BASE_ISI (AT91C_CAST(AT91PS_ISI) 0xFFFB4000) // (ISI) Base Address -#define AT91C_BASE_UHPHS_OHCI (AT91C_CAST(AT91PS_UHPHS_OHCI) 0x00700000) // (UHPHS_OHCI) Base Address -#define AT91C_BASE_UHPHS_EHCI (AT91C_CAST(AT91PS_UHPHS_EHCI) 0x00800000) // (UHPHS_EHCI) Base Address -#define AT91C_BASE_TRNG (AT91C_CAST(AT91PS_TRNG) 0xFFFCC000) // (TRNG) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM9G45 -// ***************************************************************************** -// ITCM -#define AT91C_ITCM (0x00100000) // Maximum ITCM Area base address -// DTCM -#define AT91C_DTCM (0x00200000) // Maximum DTCM Area base address -// IRAM -#define AT91C_IRAM (0x00300000) // Maximum Internal SRAM base address -#define AT91C_IRAM_SIZE (0x00010000) // Maximum Internal SRAM size in byte (64 Kbytes) -// IRAM_MIN -#define AT91C_IRAM_MIN (0x00300000) // Minimum Internal RAM base address -#define AT91C_IRAM_MIN_SIZE (0x00004000) // Minimum Internal RAM size in byte (16 Kbytes) -// IROM -#define AT91C_IROM (0x00400000) // Internal ROM base address -#define AT91C_IROM_SIZE (0x00010000) // Internal ROM size in byte (64 Kbytes) -// EBI_CS0 -#define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address -#define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes) -// EBI_CS1 -#define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address -#define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes) -// EBI_SDRAM -#define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address -#define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes) -// EBI_SDRAM_16BIT -#define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address -#define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes) -// EBI_SDRAM_32BIT -#define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address -#define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes) -// EBI_CS2 -#define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address -#define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes) -// EBI_CS3 -#define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address -#define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes) -// EBI_SM -#define AT91C_EBI_SM (0x40000000) // NANDFLASH on EBI Chip Select 3 base address -#define AT91C_EBI_SM_SIZE (0x10000000) // NANDFLASH on EBI Chip Select 3 size in byte (262144 Kbytes) -// EBI_CS4 -#define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address -#define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes) -// EBI_CF0 -#define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on EBI Chip Select 4 base address -#define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on EBI Chip Select 4 size in byte (262144 Kbytes) -// EBI_CS5 -#define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address -#define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes) -// EBI_CF1 -#define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on EBIChip Select 5 base address -#define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on EBIChip Select 5 size in byte (262144 Kbytes) -// DDR2 -#define AT91C_DDR2 (0x70000000) // DDR2/LPDDR space base address -#define AT91C_DDR2_SIZE (0x10000000) // DDR2/LPDDR space size in byte (262144 Kbytes) - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "io.h" -#include "irq.h" -#include "gpio.h" - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) - -extern struct clk *clk_get(const char *id); -extern rt_uint32_t clk_get_rate(struct clk *clk); -extern void rt_hw_clock_init(void); - -#define AT91C_SLOW_CLOCK 32768 /* slow clock */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/at91sam9g45/platform/gpio.h b/bsp/at91sam9g45/platform/gpio.h deleted file mode 100644 index f0c53b52714ec15ab4256c8f8fb812c70956769f..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/platform/gpio.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * File : gpio.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - */ - -#ifndef __GPIO_H__ -#define __GPIO_H__ - -#include - -#define PIN_BASE AIC_IRQS - -#define MAX_GPIO_BANKS 5 - -#define PIN_IRQS (MAX_GPIO_BANKS*32) - -/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */ - -#define AT91C_PIN_PA0 (PIN_BASE + 0x00 + 0) -#define AT91C_PIN_PA1 (PIN_BASE + 0x00 + 1) -#define AT91C_PIN_PA2 (PIN_BASE + 0x00 + 2) -#define AT91C_PIN_PA3 (PIN_BASE + 0x00 + 3) -#define AT91C_PIN_PA4 (PIN_BASE + 0x00 + 4) -#define AT91C_PIN_PA5 (PIN_BASE + 0x00 + 5) -#define AT91C_PIN_PA6 (PIN_BASE + 0x00 + 6) -#define AT91C_PIN_PA7 (PIN_BASE + 0x00 + 7) -#define AT91C_PIN_PA8 (PIN_BASE + 0x00 + 8) -#define AT91C_PIN_PA9 (PIN_BASE + 0x00 + 9) -#define AT91C_PIN_PA10 (PIN_BASE + 0x00 + 10) -#define AT91C_PIN_PA11 (PIN_BASE + 0x00 + 11) -#define AT91C_PIN_PA12 (PIN_BASE + 0x00 + 12) -#define AT91C_PIN_PA13 (PIN_BASE + 0x00 + 13) -#define AT91C_PIN_PA14 (PIN_BASE + 0x00 + 14) -#define AT91C_PIN_PA15 (PIN_BASE + 0x00 + 15) -#define AT91C_PIN_PA16 (PIN_BASE + 0x00 + 16) -#define AT91C_PIN_PA17 (PIN_BASE + 0x00 + 17) -#define AT91C_PIN_PA18 (PIN_BASE + 0x00 + 18) -#define AT91C_PIN_PA19 (PIN_BASE + 0x00 + 19) -#define AT91C_PIN_PA20 (PIN_BASE + 0x00 + 20) -#define AT91C_PIN_PA21 (PIN_BASE + 0x00 + 21) -#define AT91C_PIN_PA22 (PIN_BASE + 0x00 + 22) -#define AT91C_PIN_PA23 (PIN_BASE + 0x00 + 23) -#define AT91C_PIN_PA24 (PIN_BASE + 0x00 + 24) -#define AT91C_PIN_PA25 (PIN_BASE + 0x00 + 25) -#define AT91C_PIN_PA26 (PIN_BASE + 0x00 + 26) -#define AT91C_PIN_PA27 (PIN_BASE + 0x00 + 27) -#define AT91C_PIN_PA28 (PIN_BASE + 0x00 + 28) -#define AT91C_PIN_PA29 (PIN_BASE + 0x00 + 29) -#define AT91C_PIN_PA30 (PIN_BASE + 0x00 + 30) -#define AT91C_PIN_PA31 (PIN_BASE + 0x00 + 31) - -#define AT91C_PIN_PB0 (PIN_BASE + 0x20 + 0) -#define AT91C_PIN_PB1 (PIN_BASE + 0x20 + 1) -#define AT91C_PIN_PB2 (PIN_BASE + 0x20 + 2) -#define AT91C_PIN_PB3 (PIN_BASE + 0x20 + 3) -#define AT91C_PIN_PB4 (PIN_BASE + 0x20 + 4) -#define AT91C_PIN_PB5 (PIN_BASE + 0x20 + 5) -#define AT91C_PIN_PB6 (PIN_BASE + 0x20 + 6) -#define AT91C_PIN_PB7 (PIN_BASE + 0x20 + 7) -#define AT91C_PIN_PB8 (PIN_BASE + 0x20 + 8) -#define AT91C_PIN_PB9 (PIN_BASE + 0x20 + 9) -#define AT91C_PIN_PB10 (PIN_BASE + 0x20 + 10) -#define AT91C_PIN_PB11 (PIN_BASE + 0x20 + 11) -#define AT91C_PIN_PB12 (PIN_BASE + 0x20 + 12) -#define AT91C_PIN_PB13 (PIN_BASE + 0x20 + 13) -#define AT91C_PIN_PB14 (PIN_BASE + 0x20 + 14) -#define AT91C_PIN_PB15 (PIN_BASE + 0x20 + 15) -#define AT91C_PIN_PB16 (PIN_BASE + 0x20 + 16) -#define AT91C_PIN_PB17 (PIN_BASE + 0x20 + 17) -#define AT91C_PIN_PB18 (PIN_BASE + 0x20 + 18) -#define AT91C_PIN_PB19 (PIN_BASE + 0x20 + 19) -#define AT91C_PIN_PB20 (PIN_BASE + 0x20 + 20) -#define AT91C_PIN_PB21 (PIN_BASE + 0x20 + 21) -#define AT91C_PIN_PB22 (PIN_BASE + 0x20 + 22) -#define AT91C_PIN_PB23 (PIN_BASE + 0x20 + 23) -#define AT91C_PIN_PB24 (PIN_BASE + 0x20 + 24) -#define AT91C_PIN_PB25 (PIN_BASE + 0x20 + 25) -#define AT91C_PIN_PB26 (PIN_BASE + 0x20 + 26) -#define AT91C_PIN_PB27 (PIN_BASE + 0x20 + 27) -#define AT91C_PIN_PB28 (PIN_BASE + 0x20 + 28) -#define AT91C_PIN_PB29 (PIN_BASE + 0x20 + 29) -#define AT91C_PIN_PB30 (PIN_BASE + 0x20 + 30) -#define AT91C_PIN_PB31 (PIN_BASE + 0x20 + 31) - -#define AT91C_PIN_PC0 (PIN_BASE + 0x40 + 0) -#define AT91C_PIN_PC1 (PIN_BASE + 0x40 + 1) -#define AT91C_PIN_PC2 (PIN_BASE + 0x40 + 2) -#define AT91C_PIN_PC3 (PIN_BASE + 0x40 + 3) -#define AT91C_PIN_PC4 (PIN_BASE + 0x40 + 4) -#define AT91C_PIN_PC5 (PIN_BASE + 0x40 + 5) -#define AT91C_PIN_PC6 (PIN_BASE + 0x40 + 6) -#define AT91C_PIN_PC7 (PIN_BASE + 0x40 + 7) -#define AT91C_PIN_PC8 (PIN_BASE + 0x40 + 8) -#define AT91C_PIN_PC9 (PIN_BASE + 0x40 + 9) -#define AT91C_PIN_PC10 (PIN_BASE + 0x40 + 10) -#define AT91C_PIN_PC11 (PIN_BASE + 0x40 + 11) -#define AT91C_PIN_PC12 (PIN_BASE + 0x40 + 12) -#define AT91C_PIN_PC13 (PIN_BASE + 0x40 + 13) -#define AT91C_PIN_PC14 (PIN_BASE + 0x40 + 14) -#define AT91C_PIN_PC15 (PIN_BASE + 0x40 + 15) -#define AT91C_PIN_PC16 (PIN_BASE + 0x40 + 16) -#define AT91C_PIN_PC17 (PIN_BASE + 0x40 + 17) -#define AT91C_PIN_PC18 (PIN_BASE + 0x40 + 18) -#define AT91C_PIN_PC19 (PIN_BASE + 0x40 + 19) -#define AT91C_PIN_PC20 (PIN_BASE + 0x40 + 20) -#define AT91C_PIN_PC21 (PIN_BASE + 0x40 + 21) -#define AT91C_PIN_PC22 (PIN_BASE + 0x40 + 22) -#define AT91C_PIN_PC23 (PIN_BASE + 0x40 + 23) -#define AT91C_PIN_PC24 (PIN_BASE + 0x40 + 24) -#define AT91C_PIN_PC25 (PIN_BASE + 0x40 + 25) -#define AT91C_PIN_PC26 (PIN_BASE + 0x40 + 26) -#define AT91C_PIN_PC27 (PIN_BASE + 0x40 + 27) -#define AT91C_PIN_PC28 (PIN_BASE + 0x40 + 28) -#define AT91C_PIN_PC29 (PIN_BASE + 0x40 + 29) -#define AT91C_PIN_PC30 (PIN_BASE + 0x40 + 30) -#define AT91C_PIN_PC31 (PIN_BASE + 0x40 + 31) - -#define AT91C_PIN_PD0 (PIN_BASE + 0x60 + 0) -#define AT91C_PIN_PD1 (PIN_BASE + 0x60 + 1) -#define AT91C_PIN_PD2 (PIN_BASE + 0x60 + 2) -#define AT91C_PIN_PD3 (PIN_BASE + 0x60 + 3) -#define AT91C_PIN_PD4 (PIN_BASE + 0x60 + 4) -#define AT91C_PIN_PD5 (PIN_BASE + 0x60 + 5) -#define AT91C_PIN_PD6 (PIN_BASE + 0x60 + 6) -#define AT91C_PIN_PD7 (PIN_BASE + 0x60 + 7) -#define AT91C_PIN_PD8 (PIN_BASE + 0x60 + 8) -#define AT91C_PIN_PD9 (PIN_BASE + 0x60 + 9) -#define AT91C_PIN_PD10 (PIN_BASE + 0x60 + 10) -#define AT91C_PIN_PD11 (PIN_BASE + 0x60 + 11) -#define AT91C_PIN_PD12 (PIN_BASE + 0x60 + 12) -#define AT91C_PIN_PD13 (PIN_BASE + 0x60 + 13) -#define AT91C_PIN_PD14 (PIN_BASE + 0x60 + 14) -#define AT91C_PIN_PD15 (PIN_BASE + 0x60 + 15) -#define AT91C_PIN_PD16 (PIN_BASE + 0x60 + 16) -#define AT91C_PIN_PD17 (PIN_BASE + 0x60 + 17) -#define AT91C_PIN_PD18 (PIN_BASE + 0x60 + 18) -#define AT91C_PIN_PD19 (PIN_BASE + 0x60 + 19) -#define AT91C_PIN_PD20 (PIN_BASE + 0x60 + 20) -#define AT91C_PIN_PD21 (PIN_BASE + 0x60 + 21) -#define AT91C_PIN_PD22 (PIN_BASE + 0x60 + 22) -#define AT91C_PIN_PD23 (PIN_BASE + 0x60 + 23) -#define AT91C_PIN_PD24 (PIN_BASE + 0x60 + 24) -#define AT91C_PIN_PD25 (PIN_BASE + 0x60 + 25) -#define AT91C_PIN_PD26 (PIN_BASE + 0x60 + 26) -#define AT91C_PIN_PD27 (PIN_BASE + 0x60 + 27) -#define AT91C_PIN_PD28 (PIN_BASE + 0x60 + 28) -#define AT91C_PIN_PD29 (PIN_BASE + 0x60 + 29) -#define AT91C_PIN_PD30 (PIN_BASE + 0x60 + 30) -#define AT91C_PIN_PD31 (PIN_BASE + 0x60 + 31) - -#define AT91C_PIN_PE0 (PIN_BASE + 0x80 + 0) -#define AT91C_PIN_PE1 (PIN_BASE + 0x80 + 1) -#define AT91C_PIN_PE2 (PIN_BASE + 0x80 + 2) -#define AT91C_PIN_PE3 (PIN_BASE + 0x80 + 3) -#define AT91C_PIN_PE4 (PIN_BASE + 0x80 + 4) -#define AT91C_PIN_PE5 (PIN_BASE + 0x80 + 5) -#define AT91C_PIN_PE6 (PIN_BASE + 0x80 + 6) -#define AT91C_PIN_PE7 (PIN_BASE + 0x80 + 7) -#define AT91C_PIN_PE8 (PIN_BASE + 0x80 + 8) -#define AT91C_PIN_PE9 (PIN_BASE + 0x80 + 9) -#define AT91C_PIN_PE10 (PIN_BASE + 0x80 + 10) -#define AT91C_PIN_PE11 (PIN_BASE + 0x80 + 11) -#define AT91C_PIN_PE12 (PIN_BASE + 0x80 + 12) -#define AT91C_PIN_PE13 (PIN_BASE + 0x80 + 13) -#define AT91C_PIN_PE14 (PIN_BASE + 0x80 + 14) -#define AT91C_PIN_PE15 (PIN_BASE + 0x80 + 15) -#define AT91C_PIN_PE16 (PIN_BASE + 0x80 + 16) -#define AT91C_PIN_PE17 (PIN_BASE + 0x80 + 17) -#define AT91C_PIN_PE18 (PIN_BASE + 0x80 + 18) -#define AT91C_PIN_PE19 (PIN_BASE + 0x80 + 19) -#define AT91C_PIN_PE20 (PIN_BASE + 0x80 + 20) -#define AT91C_PIN_PE21 (PIN_BASE + 0x80 + 21) -#define AT91C_PIN_PE22 (PIN_BASE + 0x80 + 22) -#define AT91C_PIN_PE23 (PIN_BASE + 0x80 + 23) -#define AT91C_PIN_PE24 (PIN_BASE + 0x80 + 24) -#define AT91C_PIN_PE25 (PIN_BASE + 0x80 + 25) -#define AT91C_PIN_PE26 (PIN_BASE + 0x80 + 26) -#define AT91C_PIN_PE27 (PIN_BASE + 0x80 + 27) -#define AT91C_PIN_PE28 (PIN_BASE + 0x80 + 28) -#define AT91C_PIN_PE29 (PIN_BASE + 0x80 + 29) -#define AT91C_PIN_PE30 (PIN_BASE + 0x80 + 30) -#define AT91C_PIN_PE31 (PIN_BASE + 0x80 + 31) - -rt_inline rt_uint32_t gpio_to_irq(rt_uint32_t gpio) -{ - return gpio; -} - -#endif diff --git a/bsp/at91sam9g45/platform/interrupt.c b/bsp/at91sam9g45/platform/interrupt.c deleted file mode 100644 index b19bcb3bdeef336a26b1d04d04a5ccd79d3bfd5e..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/platform/interrupt.c +++ /dev/null @@ -1,453 +0,0 @@ -/* - * File : interrupt.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - */ - -#include -#include "at91sam9g45.h" -#include "interrupt.h" - -#define AIC_IRQS 32 -#define MAX_HANDLERS (AIC_IRQS + PIN_IRQS) - -extern rt_uint32_t rt_interrupt_nest; - -/* exception and interrupt handler table */ -struct rt_irq_desc irq_desc[MAX_HANDLERS]; - -rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread; -rt_uint32_t rt_thread_switch_interrupt_flag; - - -/* -------------------------------------------------------------------- - * Interrupt initialization - * -------------------------------------------------------------------- */ - -rt_uint32_t at91_extern_irq; - -#define is_extern_irq(irq) ((1 << (irq)) & at91_extern_irq) - -/* - * The default interrupt priority levels (0 = lowest, 7 = highest). - */ -static rt_uint32_t at91sam9g45_default_irq_priority[MAX_HANDLERS] = { - 7, /* Advanced Interrupt Controller - FIQ */ - 7, /* System Controller Interrupt */ - 1, /* Parallel I/O Controller A, */ - 1, /* Parallel I/O Controller B */ - 1, /* Parallel I/O Controller C */ - 0, /* Parallel I/O Controller D/E */ - 5, /* True Random Number Generator */ - 5, /* USART 0 */ - 5, /* USART 1 */ - 0, /* USART 2 */ - 2, /* USART 3 */ - 6, /* High Speed Multimedia Card Interface 0 */ - 5, /* Two-Wire Interface 0 */ - 5, /* Two-Wire Interface 1 */ - 5, /* Serial Peripheral Interface */ - 0, /* Serial Peripheral Interface */ - 0, /* Synchronous Serial Controller 0 */ - 0, /* Synchronous Serial Controller 1 */ - 0, /* Timer Counter 0,1,2,3,4,5 */ - 0, /* Pulse Width Modulation Controller */ - 2, /* Touch Screen ADC Controller */ - 3, /* DMA Controller */ - 0, /* USB Host High Speed */ - 5, /* LCD Controller */ - 5, /* AC97 Controller */ - 5, /* Ethernet MAC */ - 0, /* Image Sensor Interface */ - 0, /* USB Device High Speed */ - 0, /* N/A */ - 0, /* High Speed Multimedia Card Interface 1 */ - 0, /* Reserved */ - 0, /* Advanced Interrupt Controller - IRQ */ -}; - -/** - * @addtogroup AT91SAM9G45 - */ -/*@{*/ - -void rt_hw_interrupt_mask(int irq); -void rt_hw_interrupt_umask(int irq); - -rt_isr_handler_t rt_hw_interrupt_handle(rt_uint32_t vector, void *param) -{ - rt_kprintf("Unhandled interrupt %d occured!!!\n", vector); - return RT_NULL; -} - -rt_isr_handler_t at91_gpio_irq_handle(rt_uint32_t bank, void *param) -{ - rt_uint32_t isr, irq_n; - AT91PS_PIO pio; - void *parameter; - - switch (bank) - { - case 0: pio = AT91C_BASE_PIOA; break; - case 1: pio = AT91C_BASE_PIOB; break; - case 2: pio = AT91C_BASE_PIOC; break; - case 3: pio = AT91C_BASE_PIOD; break; - case 4: pio = AT91C_BASE_PIOE; break; - default: return RT_NULL; - } - irq_n = AIC_IRQS + 32*bank; - isr = readl(pio->PIO_ISR); - isr &= readl(pio->PIO_IMR); - while (isr) - { - if (isr & 1) - { - parameter = irq_desc[irq_n].param; - irq_desc[irq_n].handler(irq_n, parameter); - } - isr >>= 1; - irq_n++; - } - - return RT_NULL; -} - -unsigned int SpuriousCount = 0; -static void DefaultSpuriousHandler( void ) -{ - SpuriousCount++; - rt_kprintf("Spurious interrupt %d occured!!!\n", SpuriousCount); - return ; -} - -static void DefaultFiqHandler(void) -{ - rt_kprintf("Unhandled FIQ occured!!!\n"); - while (1); -} - -static void DefaultIrqHandler(void) -{ - rt_kprintf("Unhandled IRQ %d occured!!!\n", AT91C_BASE_AIC->AIC_ISR); - while (1); -} - -/* - * Initialize the AIC interrupt controller. - */ -void at91_aic_init(rt_uint32_t *priority) -{ - rt_uint32_t i; - - /* - * The IVR is used by macro get_irqnr_and_base to read and verify. - * The irq number is NR_AIC_IRQS when a spurious interrupt has occurred. - */ - AT91C_BASE_AIC->AIC_SVR[0] = (rt_uint32_t)DefaultFiqHandler; - for (i = 1; i < AIC_IRQS; i++) { - /* Put irq number in Source Vector Register: */ - AT91C_BASE_AIC->AIC_SVR[i] = (rt_uint32_t)DefaultIrqHandler; // no-used - /* Active Low interrupt, with the specified priority */ - AT91C_BASE_AIC->AIC_SMR[i] = AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE | priority[i]; - //AT91C_AIC_SRCTYPE_FALLING - } - - /* - * Spurious Interrupt ID in Spurious Vector Register is NR_AIC_IRQS - * When there is no current interrupt, the IRQ Vector Register reads the value stored in AIC_SPU - */ - AT91C_BASE_AIC->AIC_SPU = (rt_uint32_t)DefaultSpuriousHandler; - - /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ - for (i = 0; i < 8; i++) - AT91C_BASE_AIC->AIC_EOICR = 0; - - /* No debugging in AIC: Debug (Protect) Control Register */ - AT91C_BASE_AIC->AIC_DCR = 0; - - /* Disable and clear all interrupts initially */ - AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF; - AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF; -} - - -static void at91_gpio_irq_init() -{ - int i, idx; - char *name[] = {"PIOA", "PIOB", "PIOC", "PIODE"}; - rt_uint32_t aic_pids[] = { AT91C_ID_PIOA, AT91C_ID_PIOB, AT91C_ID_PIOC, AT91C_ID_PIOD_E }; - - AT91C_BASE_PIOA->PIO_IDR = 0xffffffff; - AT91C_BASE_PIOB->PIO_IDR = 0xffffffff; - AT91C_BASE_PIOC->PIO_IDR = 0xffffffff; - AT91C_BASE_PIOD->PIO_IDR = 0xffffffff; - AT91C_BASE_PIOE->PIO_IDR = 0xffffffff; - - for (i = 0; i < 4; i++) - { - idx = aic_pids[i]; - irq_desc[idx].handler = (rt_isr_handler_t)at91_gpio_irq_handle; - irq_desc[idx].param = RT_NULL; -#ifdef RT_USING_INTERRUPT_INFO - rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, name[i]); - irq_desc[idx].counter = 0; -#endif - - rt_hw_interrupt_umask(idx); - } -} - - -/** - * This function will initialize hardware interrupt - */ -void rt_hw_interrupt_init(void) -{ - register rt_uint32_t idx; - rt_uint32_t *priority = at91sam9g45_default_irq_priority; - - at91_extern_irq = (1UL << AT91C_ID_IRQ0); - - /* Initialize the AIC interrupt controller */ - at91_aic_init(priority); - - /* init exceptions table */ - for(idx=0; idx < MAX_HANDLERS; idx++) - { - irq_desc[idx].handler = (rt_isr_handler_t)rt_hw_interrupt_handle; - irq_desc[idx].param = RT_NULL; -#ifdef RT_USING_INTERRUPT_INFO - rt_snprintf(irq_desc[idx].name, RT_NAME_MAX - 1, "default"); - irq_desc[idx].counter = 0; -#endif - } - - at91_gpio_irq_init(); - - /* init interrupt nest, and context in thread sp */ - rt_interrupt_nest = 0; - rt_interrupt_from_thread = 0; - rt_interrupt_to_thread = 0; - rt_thread_switch_interrupt_flag = 0; -} - -static void at91_gpio_irq_mask(int irq) -{ - rt_uint32_t pin, bank; - AT91PS_PIO pio; - - bank = (irq - AIC_IRQS)>>5; - - switch (bank) - { - case 0: pio = AT91C_BASE_PIOA; break; - case 1: pio = AT91C_BASE_PIOB; break; - case 2: pio = AT91C_BASE_PIOC; break; - case 3: pio = AT91C_BASE_PIOD; break; - case 4: pio = AT91C_BASE_PIOE; break; - default: return; - } - pin = 1 << ((irq - AIC_IRQS) & 31); - pio->PIO_IDR = pin; -} - -/** - * This function will mask a interrupt. - * @param irq the interrupt number - */ -void rt_hw_interrupt_mask(int irq) -{ - if (irq >= AIC_IRQS) - { - at91_gpio_irq_mask(irq); - } - else - { - /* Disable interrupt on AIC */ - AT91C_BASE_AIC->AIC_IDCR = 1 << irq; - } -} - -static void at91_gpio_irq_umask(int irq) -{ - rt_uint32_t pin, bank; - AT91PS_PIO pio; - - bank = (irq - AIC_IRQS)>>5; - - switch (bank) - { - case 0: pio = AT91C_BASE_PIOA; break; - case 1: pio = AT91C_BASE_PIOB; break; - case 2: pio = AT91C_BASE_PIOC; break; - case 3: pio = AT91C_BASE_PIOD; break; - case 4: pio = AT91C_BASE_PIOE; break; - default: return; - } - pin = 1 << ((irq - AIC_IRQS) & 31); - pio->PIO_IER = pin; -} - -/** - * This function will un-mask a interrupt. - * @param vector the interrupt number - */ -void rt_hw_interrupt_umask(int irq) -{ - if (irq >= AIC_IRQS) - { - at91_gpio_irq_umask(irq); - } - else - { - /* Enable interrupt on AIC */ - AT91C_BASE_AIC->AIC_IECR = 1 << irq; - } -} - -/** - * This function will install a interrupt service routine to a interrupt. - * @param vector the interrupt number - * @param handler the interrupt service routine to be installed - * @param param the interrupt service function parameter - * @param name the interrupt name - * @return old handler - */ -rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, - void *param, char *name) -{ - rt_isr_handler_t old_handler = RT_NULL; - - if (vector < MAX_HANDLERS) - { - old_handler = irq_desc[vector].handler; - if (handler != RT_NULL) - { - irq_desc[vector].handler = (rt_isr_handler_t)handler; - irq_desc[vector].param = param; -#ifdef RT_USING_INTERRUPT_INFO - rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name); - irq_desc[vector].counter = 0; -#endif - } - } - - return old_handler; -} - -/*@}*/ - -/* -static int at91_aic_set_type(unsigned irq, unsigned type) -{ - unsigned int smr, srctype; - - switch (type) { - case AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL: - srctype = AT91C_AIC_SRCTYPE_HIGH; - break; - case AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE: - srctype = AT91C_AIC_SRCTYPE_RISING; - break; - case AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE: - // only supported on external interrupts - if ((irq == AT91C_ID_FIQ) || is_extern_irq(irq)) - srctype = AT91C_AIC_SRCTYPE_LOW; - else - return -1; - break; - case AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED: - // only supported on external interrupts - if ((irq == AT91C_ID_FIQ) || is_extern_irq(irq)) - srctype = AT91C_AIC_SRCTYPE_FALLING; - else - return -1; - break; - default: - return -1; - } - - smr = readl(AT91C_AIC_SMR(irq)) & ~AT91C_AIC_SRCTYPE; - AT91C_BASE_AIC->AIC_SMR[irq] = smr | srctype; - return 0; -} -*/ -rt_uint32_t rt_hw_interrupt_get_active(rt_uint32_t fiq_irq) -{ - - //volatile rt_uint32_t irqstat; - rt_uint32_t id; - if (fiq_irq == INT_FIQ) - return 0; - - //IRQ - /* AIC need this dummy read */ - readl(AT91C_AIC_IVR); - /* clear pending register */ - id = readl(AT91C_AIC_ISR); - - return id; -} - -void rt_hw_interrupt_ack(rt_uint32_t fiq_irq, rt_uint32_t id) -{ - /* new FIQ generation */ - if (fiq_irq == INT_FIQ) - return; - - /* new IRQ generation */ - // EIOCR must be write any value after interrupt, - // or else can't response next interrupt - AT91C_BASE_AIC->AIC_EOICR = 0x0; -} - -#ifdef RT_USING_FINSH -#ifdef RT_USING_INTERRUPT_INFO -void list_irq(void) -{ - int irq; - - rt_kprintf("number\tcount\tname\n"); - for (irq = 0; irq < MAX_HANDLERS; irq++) - { - if (rt_strncmp(irq_desc[irq].name, "default", sizeof("default"))) - { - rt_kprintf("%02ld: %10ld %s\n", irq, irq_desc[irq].counter, irq_desc[irq].name); - } - } -} - -#include -FINSH_FUNCTION_EXPORT(list_irq, list system irq); - -#ifdef FINSH_USING_MSH -int cmd_list_irq(int argc, char** argv) -{ - list_irq(); - return 0; -} -FINSH_FUNCTION_EXPORT_ALIAS(cmd_list_irq, __cmd_list_irq, list system irq.); - -#endif -#endif -#endif - - diff --git a/bsp/at91sam9g45/platform/interrupt.h b/bsp/at91sam9g45/platform/interrupt.h deleted file mode 100644 index 7780e7a3a880270355298536baefd2ffd3504586..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/platform/interrupt.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * File : interrupt.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2015-04-14 ArdaFu first version - */ -#ifndef __INTERRUPT_H__ -#define __INTERRUPT_H__ - -#define INT_IRQ 0x00 -#define INT_FIQ 0x01 - - -#endif diff --git a/bsp/at91sam9g45/platform/io.h b/bsp/at91sam9g45/platform/io.h deleted file mode 100644 index 80919c52cb348fde73f5676fce54d05902305102..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/platform/io.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * File : io.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - */ - -#ifndef __ASM_ARCH_IO_H -#define __ASM_ARCH_IO_H - -#define IO_SPACE_LIMIT 0xFFFFFFFF - -#define readb(a) (*(volatile unsigned char *)(a)) -#define readw(a) (*(volatile unsigned short *)(a)) -#define readl(a) (*(volatile unsigned int *)(a)) - -#define writeb(v,a) (*(volatile unsigned char *)(a) = (v)) -#define writew(v,a) (*(volatile unsigned short *)(a) = (v)) -#define writel(v,a) (*(volatile unsigned int *)(a) = (v)) - -#endif - diff --git a/bsp/at91sam9g45/platform/irq.h b/bsp/at91sam9g45/platform/irq.h deleted file mode 100644 index fe1fea41d04d778391bea0137e60e8e32741fd97..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/platform/irq.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * File : irq.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - */ - -#ifndef __IRQ_H__ -#define __IRQ_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * IRQ line status. - * - * Bits 0-7 are reserved - * - * IRQ types - */ -#define IRQ_TYPE_NONE 0x00000000 /* Default, unspecified type */ -#define IRQ_TYPE_EDGE_RISING 0x00000001 /* Edge rising type */ -#define IRQ_TYPE_EDGE_FALLING 0x00000002 /* Edge falling type */ -#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING) -#define IRQ_TYPE_LEVEL_HIGH 0x00000004 /* Level high type */ -#define IRQ_TYPE_LEVEL_LOW 0x00000008 /* Level low type */ -#define IRQ_TYPE_SENSE_MASK 0x0000000f /* Mask of the above */ -#define IRQ_TYPE_PROBE 0x00000010 /* Probing in progress */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/at91sam9g45/platform/reset.c b/bsp/at91sam9g45/platform/reset.c deleted file mode 100644 index 2e7bec1e5d890234b338255b01d60f0fdb15920f..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/platform/reset.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * File : reset.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Develop Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety modified from mini2440 - */ - -#include -#include -#include "at91sam9g45.h" - -/** - * @addtogroup AT91SAM926X - */ -/*@{*/ - -void machine_reset(void) -{ - AT91C_BASE_RSTC->RSTC_RCR = AT91C_RSTC_KEY | AT91C_RSTC_PROCRST | AT91C_RSTC_PERRST; -} - -void machine_shutdown(void) -{ - AT91C_BASE_SHDWC->SHDWC_SHCR = AT91C_SHDWC_KEY | AT91C_SHDWC_SHDW; -} - -#ifdef RT_USING_FINSH - -#include -FINSH_FUNCTION_EXPORT_ALIAS(rt_hw_cpu_reset, reset, restart the system); - -#ifdef FINSH_USING_MSH -int cmd_reset(int argc, char** argv) -{ - rt_hw_cpu_reset(); - return 0; -} - -int cmd_shutdown(int argc, char** argv) -{ - rt_hw_cpu_shutdown(); - return 0; -} - -FINSH_FUNCTION_EXPORT_ALIAS(cmd_reset, __cmd_reset, restart the system.); -FINSH_FUNCTION_EXPORT_ALIAS(cmd_shutdown, __cmd_shutdown, shutdown the system.); - -#endif -#endif - -/*@}*/ diff --git a/bsp/at91sam9g45/platform/rt_low_level_init.c b/bsp/at91sam9g45/platform/rt_low_level_init.c deleted file mode 100644 index 5df468d771d1d446d46490f134b65969a107020f..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/platform/rt_low_level_init.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * File : rt_low_level_init.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2015-04-14 ArdaFu first version - */ - -/* write register a=address, v=value */ -#define write_reg(a,v) (*(volatile unsigned int *)(a) = (v)) -/* Processor Reset */ -#define AT91C_RSTC_PROCRST (1 << 0) -#define AT91C_RSTC_PERRST (1 << 2) -#define AT91C_RSTC_KEY (0xa5 << 24) -#define AT91C_MATRIX_BASE (0XFFFFEE00) -/* Master Remap Control Register */ -#define AT91C_MATRIX_MRCR (AT91C_MATRIX_BASE + 0x100) -/* Remap Command for AHB Master 0 (ARM926EJ-S InSTRuction Master) */ -#define AT91C_MATRIX_RCB0 (1 << 0) -/* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */ -#define AT91C_MATRIX_RCB1 (1 << 1) - -#define AT91C_AIC_BASE (0XFFFFF000) -/* Interrupt DisaBLe Command Register */ -#define AT91C_AIC_IDCR (AT91C_AIC_BASE + 0x124) -/* Interrupt Clear Command Register */ -#define AT91C_AIC_ICCR (AT91C_AIC_BASE + 0x128) - -#define AT91C_WDT_BASE (0XFFFFFD40) -#define AT91C_WDT_CR (AT91C_WDT_BASE + 0x00) -#define AT91C_WDT_CR_KEY (0xA5000000) -#define AT91C_WDT_CR_WDRSTT (0x00000001) -#define AT91C_WDT_MR (AT91C_WDT_BASE + 0x04) -#define AT91C_WDT_MR_WDDIS (0x00008000) - -void rt_low_level_init(void) -{ - // Mask all IRQs by clearing all bits in the INTMRS - write_reg(AT91C_AIC_IDCR, 0xFFFFFFFF); - write_reg(AT91C_AIC_ICCR, 0xFFFFFFFF); - // Remap internal ram to 0x00000000 Address - write_reg(AT91C_MATRIX_MRCR, AT91C_MATRIX_RCB0 | AT91C_MATRIX_RCB1); - // Disable the watchdog - //write_reg(AT91C_WDT_CR, AT91C_WDT_CR_KEY|AT91C_WDT_CR_WDRSTT); - //write_reg(AT91C_WDT_MR, AT91C_WDT_MR_WDDIS); -} - diff --git a/bsp/at91sam9g45/platform/rt_low_level_init.h b/bsp/at91sam9g45/platform/rt_low_level_init.h deleted file mode 100644 index 86dcfb59dc92ded9b54b17491927a83636e46f9f..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/platform/rt_low_level_init.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * File : rt_low_level_init.h - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006 - 2015, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2018-06-04 ArdaFu first version - */ -#ifndef __RT_LOW_LEVEL_INIT_H__ -#define __RT_LOW_LEVEL_INIT_H__ - -/*-------- Stack size of CPU modes -------------------------------------------*/ -#define UND_STK_SIZE 512 -#define SVC_STK_SIZE 4096 -#define ABT_STK_SIZE 512 -#define IRQ_STK_SIZE 1024 -#define FIQ_STK_SIZE 1024 -#define SYS_STK_SIZE 512 -#define Heap_Size 512 -#endif diff --git a/bsp/at91sam9g45/platform/system_clock.c b/bsp/at91sam9g45/platform/system_clock.c deleted file mode 100644 index 59c3c320abf0eef6300922da22db6f3d1b0d0e75..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/platform/system_clock.c +++ /dev/null @@ -1,270 +0,0 @@ -/* - * File : clock.c - * This file is part of RT-Thread RTOS - * COPYRIGHT (C) 2006, RT-Thread Development Team - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. - * - * Change Logs: - * Date Author Notes - * 2011-01-13 weety first version - */ - -#include -#include "at91sam9g45.h" - -static rt_list_t clocks; - -struct clk { - char name[32]; - rt_uint32_t rate_hz; - struct clk *parent; - rt_list_t node; -}; - -static struct clk clk32k = { - "clk32k", - AT91C_SLOW_CLOCK, - RT_NULL, - {RT_NULL, RT_NULL}, -}; - -static struct clk main_clk = { - "main", - 0, - RT_NULL, - {RT_NULL, RT_NULL}, -}; - -static struct clk plla = { - "plla", - 0, - &main_clk, - {RT_NULL, RT_NULL}, -}; - -static struct clk mck = { - "mck", - 0, - NULL, - {RT_NULL, RT_NULL}, -}; - -static struct clk upllck = { - "upllck", - 480*1000*1000, - &main_clk, - {RT_NULL, RT_NULL}, -}; - -static struct clk *const standard_pmc_clocks[] = { - /* four primary clocks */ - &clk32k, - &main_clk, - &plla, - - /* MCK */ - &mck -}; - -/* clocks cannot be de-registered no refcounting necessary */ -struct clk *clk_get(const char *id) -{ - struct clk *clk; - rt_list_t *list; - - for (list = (&clocks)->next; list != &clocks; list = list->next) - { - clk = (struct clk *)rt_list_entry(list, struct clk, node); - if (rt_strcmp(id, clk->name) == 0) - return clk; - } - - return RT_NULL; -} - -rt_uint32_t clk_get_rate(struct clk *clk) -{ - rt_uint32_t rate; - - for (;;) { - rate = clk->rate_hz; - if (rate || !clk->parent) - break; - clk = clk->parent; - } - return rate; -} - -static void at91_upllck_init(rt_uint32_t main_clock) -{ - // EHCI USB use fixed 480MHz clock -} - -static struct clk *at91_css_to_clk(unsigned long css) -{ - switch (css) { - case AT91C_PMC_CSS_SLOW_CLK: - return &clk32k; - case AT91C_PMC_CSS_MAIN_CLK: - return &main_clk; - case AT91C_PMC_CSS_PLLA_CLK: - return &plla; - case AT91C_PMC_CSS_UPLL_CLK: - return &upllck; - } - - return RT_NULL; -} - -// TODO: how to auto-set register value by OSC and MCK -/* Settings at 400/133MHz */ -// In datasheet, ATMEL says 12MHz main crystal startup time less than 2ms, so we -// configure OSC startup timeout to 64*8/32768=15.6ms, should enough -#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8)) -// MAINCK => Divider(DIVA) => PLLA(MULA, OUTA) => /1/2 Divider(PLLADIV2) => PLLACK -// pls. refer to doc6438G figure 24-6 on pg294. ICPLLA in reg PMC_PLLICPR -// 12MHz / 3 * (199 + 1) = 800MHz -// OUTA/ICPLLA can as ICPLLA:OUTA[1]:OUTA[0] = (800-PLLAOUT(MHz))/50 -// PLLACOUNT field occupy bit[13:8], max value is 0x3F, then about 19.2ms -#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_0) -#define BOARD_PLLACOUNT (0x3F << 8) -#define BOARD_MULA (AT91C_CKGR_MULA & (199 << 16)) -#define BOARD_DIVA (AT91C_CKGR_DIVA & 3) -// Clock Source => select(CCS) => Prescaler(PRES) => Master Clock Divider(MDIV) => MCK -// => Processor Clock Divider => PCK -// Master clock can refer to doc6438G figure 25-2 on pg298 -// PLLADIV2=1(div 2, 400MHz), PRES=0(no div, 400MHz), -// MDIV=3(Master Clock divided by 3, 133MHz), CSS=0(still Slow Clock) -#define BOARD_PRESCALER (0x00001300) //400/133MHz - -#define MHz(n) ((n) * 1000 * 1000) -#define OSC_FREQ MHz(12) -#define PLLA_FREQ MHz(800) - -static void at91_plla_init(void) -{ - rt_uint32_t pllar, mckr; - - // Code refer to doc6438G, 25.10 Programming Sequence - /* Initialize main oscillator - ****************************/ - // enable main OSC and wait OSC startup time timeout. - AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS)); - - /* Initialize PLLA, Set PLL to 800MHz and wait PLL stable */ - pllar = (MHz(800) - PLLA_FREQ) / MHz(50); // please refer to Table 46-15 of doc 6438G - AT91C_BASE_PMC->PMC_PLLICPR = (pllar >> 2) & 1; // ICPLLA - pllar = (pllar & 3) << 14; // OUTA - pllar |= BOARD_DIVA; // PLLA input clock as 4MHz - pllar |= BOARD_MULA; // PLLA output clock as 800MHz - pllar |= BOARD_PLLACOUNT; - pllar |= AT91C_CKGR_SRCA; // I don't known what means, but seems must set it - AT91C_BASE_PMC->PMC_PLLAR = pllar; - - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA)); - - /* Wait for the master clock if it was already initialized */ - // make sure Master clock in READY status before operate it - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); - - /* Switch to fast clock - **********************/ - /* setup main clock divisor and prescaler, 400MHz/133MHz, but don't switch */ - mckr = AT91C_BASE_PMC->PMC_MCKR; - if ((mckr & AT91C_PMC_MDIV) != (BOARD_PRESCALER & AT91C_PMC_MDIV)) - { - mckr = (mckr & ~(unsigned int)AT91C_PMC_MDIV) | (BOARD_PRESCALER & AT91C_PMC_MDIV); - AT91C_BASE_PMC->PMC_MCKR = mckr; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); - } - - /* Switch to PLL + prescaler, now Switch to PLLA as source, run on the fly */ - if ((mckr & AT91C_PMC_CSS) != AT91C_PMC_CSS_PLLA_CLK) - { - mckr = (mckr & ~(unsigned int)AT91C_PMC_CSS) | AT91C_PMC_CSS_PLLA_CLK; - AT91C_BASE_PMC->PMC_MCKR = mckr; - while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY)); - } - - plla.rate_hz = PLLA_FREQ; -} - -#define false 0 -#define true 1 -int at91_clock_init(rt_uint32_t main_clock) -{ - unsigned tmp, freq, mckr, mdiv; - int i; - - /* - * When the bootloader initialized the main oscillator correctly, - * there's no problem using the cycle counter. But if it didn't, - * or when using oscillator bypass mode, we must be told the speed - * of the main clock. - */ - if (!main_clock) { - do { - tmp = readl(AT91C_CKGR_MCFR); - } while (!(tmp & AT91C_CKGR_MAINRDY)); - main_clock = (tmp & AT91C_CKGR_MAINF) * (AT91C_SLOW_CLOCK / 16); - } - main_clk.rate_hz = main_clock; - - at91_plla_init(); - - at91_upllck_init(main_clock); - - /* - * MCK and CPU derive from one of those primary clocks. - * For now, assume this parentage won't change. - */ - mckr = readl(AT91C_PMC_MCKR); - mck.parent = at91_css_to_clk(mckr & AT91C_PMC_CSS); - freq = mck.parent->rate_hz; - freq /= (1 << ((mckr & AT91C_PMC_PRES) >> 2)); /* prescale */ - mdiv = 1 << ((mckr & AT91C_PMC_MDIV) >> 8); - if (mdiv == 8) mdiv = 3; - freq /= mdiv; /* mdiv */ - if (mckr & AT91C_PMC_PLLADIV2) freq /= 2; /* plla_div2 */ - mck.rate_hz = freq; - - /* Register the PMC's standard clocks */ - rt_list_init(&clocks); - for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++) - rt_list_insert_after(&clocks, &standard_pmc_clocks[i]->node); - - rt_list_insert_after(&clocks, &upllck.node); - - /* MCK and CPU clock are "always on" */ - //clk_enable(&mck); - - /*rt_kprintf("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n", - freq / 1000000, (unsigned) mck.rate_hz / 1000000, - (unsigned) main_clock / 1000000, - ((unsigned) main_clock % 1000000) / 1000);*///cause blocked - - return 0; -} - -/** - * @brief System Clock Configuration - */ -void rt_hw_clock_init(void) -{ - at91_clock_init(MHz(12)); -} - diff --git a/bsp/at91sam9g45/rtconfig.h b/bsp/at91sam9g45/rtconfig.h deleted file mode 100644 index 5d638ce1c9739a219ab4620802de2d9b58aff0a1..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/rtconfig.h +++ /dev/null @@ -1,159 +0,0 @@ -#ifndef RT_CONFIG_H__ -#define RT_CONFIG_H__ - -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - -/* RT-Thread Kernel */ - -#define RT_NAME_MAX 16 -#define RT_ALIGN_SIZE 4 -#define RT_THREAD_PRIORITY_32 -#define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 -#define RT_USING_OVERFLOW_CHECK -#define RT_USING_HOOK -#define RT_IDEL_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 -#define RT_DEBUG - -/* Inter-Thread communication */ - -#define RT_USING_SEMAPHORE -#define RT_USING_MUTEX -#define RT_USING_EVENT -#define RT_USING_MAILBOX -#define RT_USING_MESSAGEQUEUE - -/* Memory Management */ - -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM -#define RT_USING_HEAP - -/* Kernel Device Object */ - -#define RT_USING_DEVICE -#define RT_USING_INTERRUPT_INFO -#define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 -#define RT_CONSOLE_DEVICE_NAME "dbgu" - -/* RT-Thread Components */ - -#define RT_USING_COMPONENTS_INIT -#define RT_USING_USER_MAIN -#define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 - -/* C++ features */ - -#define RT_USING_CPLUSPLUS - -/* Command shell */ - -#define RT_USING_FINSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_USING_HISTORY -#define FINSH_HISTORY_LINES 5 -#define FINSH_USING_SYMTAB -#define FINSH_USING_DESCRIPTION -#define FINSH_THREAD_PRIORITY 20 -#define FINSH_THREAD_STACK_SIZE 4096 -#define FINSH_CMD_SIZE 80 -#define FINSH_USING_MSH -#define FINSH_USING_MSH_DEFAULT -#define FINSH_ARG_MAX 10 - -/* Device virtual file system */ - -#define RT_USING_DFS -#define DFS_USING_WORKDIR -#define DFS_FILESYSTEMS_MAX 2 -#define DFS_FILESYSTEM_TYPES_MAX 2 -#define DFS_FD_MAX 16 -#define RT_USING_DFS_DEVFS - -/* Device Drivers */ - -#define RT_USING_DEVICE_IPC -#define RT_PIPE_BUFSZ 512 -#define RT_USING_SERIAL -#define RT_USING_PIN - -/* Using USB */ - - -/* POSIX layer and C standard library */ - -#define RT_USING_LIBC -#define RT_USING_PTHREADS - -/* Network */ - -/* Socket abstraction layer */ - - -/* light weight TCP/IP stack */ - - -/* Modbus master and slave stack */ - - -/* AT commands */ - - -/* VBUS(Virtual Software BUS) */ - - -/* Utilities */ - - -/* RT-Thread online packages */ - -/* IoT - internet of things */ - - -/* Wi-Fi */ - -/* Marvell WiFi */ - - -/* Wiced WiFi */ - - -/* IoT Cloud */ - - -/* security packages */ - - -/* language packages */ - - -/* multimedia packages */ - - -/* tools packages */ - - -/* system packages */ - - -/* peripheral libraries and drivers */ - - -/* miscellaneous packages */ - - -/* sample package */ - -/* samples: kernel and components samples */ - - -/* example package: hello */ - -#define RT_USING_DBGU -#define RT_USING_LED - -#endif diff --git a/bsp/at91sam9g45/rtconfig.py b/bsp/at91sam9g45/rtconfig.py deleted file mode 100644 index 3684b54578225db34ca761b0810f20cbe81fd893..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/rtconfig.py +++ /dev/null @@ -1,138 +0,0 @@ -import os -ARCH = 'arm' -CPU = 'arm926' -# toolchains options -CROSS_TOOL = 'gcc' - -#------- toolchains path ------------------------------------------------------- -if os.getenv('RTT_CC'): - CROSS_TOOL = os.getenv('RTT_CC') - -if CROSS_TOOL == 'gcc': - PLATFORM = 'gcc' - EXEC_PATH = r'D:\arm-2013.11\bin' -elif CROSS_TOOL == 'keil': - PLATFORM = 'armcc' - EXEC_PATH = 'C:/Keil_v5' -elif CROSS_TOOL == 'iar': - PLATFORM = 'iar' - EXEC_PATH = 'C:/Program Files (x86)/IAR Systems/Embedded Workbench 7.2' - -if os.getenv('RTT_EXEC_PATH'): - EXEC_PATH = os.getenv('RTT_EXEC_PATH') - -#BUILD = 'debug' -BUILD = 'release' - -CORE = 'arm926ej-s' -MAP_FILE = 'rtthread_at91sam9g45.map' -LINK_FILE = 'link_scripts/at91sam9g45_ram' -TARGET_NAME = 'rtthread.bin' - -#------- GCC settings ---------------------------------------------------------- -if PLATFORM == 'gcc': - # toolchains - PREFIX = 'arm-none-eabi-' - CC = PREFIX + 'gcc' - CXX = PREFIX + 'g++' - AS = PREFIX + 'gcc' - AR = PREFIX + 'ar' - LINK = PREFIX + 'gcc' - TARGET_EXT = 'elf' - SIZE = PREFIX + 'size' - OBJDUMP = PREFIX + 'objdump' - OBJCPY = PREFIX + 'objcopy' - - DEVICE = ' -mcpu=arm926ej-s' - CFLAGS = DEVICE - AFLAGS = '-c'+ DEVICE + ' -x assembler-with-cpp' - AFLAGS += ' -Iplatform' - LFLAGS = DEVICE - LFLAGS += ' -Wl,--gc-sections,-cref,-Map=' + MAP_FILE - LFLAGS += ' -T ' + LINK_FILE + '.ld' - - CPATH = '' - LPATH = '' - - if BUILD == 'debug': - CFLAGS += ' -O0 -gdwarf-2' - AFLAGS += ' -gdwarf-2' - else: - CFLAGS += ' -O2' - - POST_ACTION = OBJCPY + ' -O binary $TARGET ' + TARGET_NAME + '\n' - POST_ACTION += SIZE + ' $TARGET\n' -#------- Keil settings --------------------------------------------------------- -elif PLATFORM == 'armcc': - # toolchains - CC = 'armcc' - AS = 'armasm' - AR = 'armar' - LINK = 'armlink' - TARGET_EXT = 'axf' - EXEC_PATH += '/arm/armcc/bin/' - - DEVICE = ' --cpu=' + CORE - CFLAGS = DEVICE + ' --apcs=interwork --diag_suppress=870' - AFLAGS = DEVICE + ' -Iplatform' - LFLAGS = DEVICE + ' --strict' - LFLAGS += ' --info sizes --info totals --info unused --info veneers' - LFLAGS += ' --list ' + MAP_FILE - LFLAGS += ' --scatter ' + LINK_FILE + '.scat' - - if BUILD == 'debug': - CFLAGS += ' -g -O0' - AFLAGS += ' -g' - else: - CFLAGS += ' -O2' - - POST_ACTION = 'fromelf --bin $TARGET --output ' + TARGET_NAME + ' \n' - POST_ACTION += 'fromelf -z $TARGET\n' -#------- IAR settings ---------------------------------------------------------- -elif PLATFORM == 'iar': - # toolchains - CC = 'iccarm' - AS = 'iasmarm' - AR = 'iarchive' - LINK = 'ilinkarm' - TARGET_EXT = 'out' - - DEVICE = CORE - - CFLAGS = '--cpu=' + DEVICE - CFLAGS += ' --diag_suppress Pa050' - CFLAGS += ' --no_cse' - CFLAGS += ' --no_unroll' - CFLAGS += ' --no_inline' - CFLAGS += ' --no_code_motion' - CFLAGS += ' --no_tbaa' - CFLAGS += ' --no_clustering' - CFLAGS += ' --no_scheduling' - - CFLAGS += ' --endian=little' - CFLAGS += ' -e' - CFLAGS += ' --fpu=none' - CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' - CFLAGS += ' --silent' - - AFLAGS = '--cpu '+ DEVICE - AFLAGS += ' -s+' - AFLAGS += ' -w+' - AFLAGS += ' -r' - AFLAGS += ' --fpu none' - AFLAGS += ' -S' - AFLAGS += ' -Iplatform' - - if BUILD == 'debug': - CFLAGS += ' --debug' - CFLAGS += ' -On' - else: - CFLAGS += ' -Oh' - - LFLAGS = '--config ' + LINK_FILE +'.icf' - LFLAGS += ' --entry __iar_program_start' - LFLAGS += ' --map ' + MAP_FILE - LFLAGS += ' --silent' - - EXEC_PATH = EXEC_PATH + '/arm/bin/' - POST_ACTION = 'ielftool --silent --bin $TARGET ' + TARGET_NAME diff --git a/bsp/at91sam9g45/template.ewp b/bsp/at91sam9g45/template.ewp deleted file mode 100644 index 5f2fa0e0a9b79708347e9bb041e5c3b6090cfa32..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/template.ewp +++ /dev/null @@ -1,1914 +0,0 @@ - - - - 2 - - Debug - - ARM - - 1 - - General - 3 - - 24 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 1 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 1 - - - - - - - BILINK - 0 - - - - - Release - - ARM - - 0 - - General - 3 - - 24 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ICCARM - 2 - - 31 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - AARM - 2 - - 9 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - OBJCOPY - 0 - - 1 - 1 - 0 - - - - - - - - - CUSTOM - 3 - - - - 0 - - - - BICOMP - 0 - - - - BUILDACTION - 1 - - - - - - - ILINK - 0 - - 16 - 1 - 0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - IARCHIVE - 0 - - 0 - 1 - 0 - - - - - - - BILINK - 0 - - - - - - diff --git a/bsp/at91sam9g45/template.eww b/bsp/at91sam9g45/template.eww deleted file mode 100644 index bd036bb4c98c1598f04b85f64b0dff37f6ec6028..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/template.eww +++ /dev/null @@ -1,10 +0,0 @@ - - - - - $WS_DIR$\template.ewp - - - - - diff --git a/bsp/at91sam9g45/template.uvopt b/bsp/at91sam9g45/template.uvopt deleted file mode 100644 index 2dca5102b8b599e958225474ae294068a7d2f9ae..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/template.uvopt +++ /dev/null @@ -1,174 +0,0 @@ - - - - 1.0 - -
### uVision Project, (C) Keil Software
- - - *.c - *.s*; *.src; *.a* - *.obj - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - - - - 0 - 0 - - - - rtthread - 0x4 - ARM-ADS - - 18432000 - - 1 - 1 - 1 - 0 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\Listings\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 16 - - - 0 - Datasheet - DATASHTS\ATMEL\AT91SAM9260_DS.PDF - - - 1 - Summary - DATASHTS\ATMEL\AT91SAM9260_DC.PDF - - - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - 5 - - - - - - - - - - .\jlink\at91sam9260.ini - Segger\JLTAgdi.dll - - - - 0 - JLTAgdi - -O558 -J1 -Y1000 -Z1 -FO0 -FD200000 -FC800 -FN0 - - - 0 - UL2ARM - -UV2077N9E -O47 -S0 -C0 -N00("ARM926EJ-S Core") -D00(0792603F) -L00(4) -FO7 -FD300000 -FC1000 -FN1 -FF0AT91SAM9_DF_P1056_CS1 -FS020000000 -FL083BE00) - - - - - 0 - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - - - - diff --git a/bsp/at91sam9g45/template.uvproj b/bsp/at91sam9g45/template.uvproj deleted file mode 100644 index ea6226f1011e9fb5611ddda720cc8aeb2bbc652b..0000000000000000000000000000000000000000 --- a/bsp/at91sam9g45/template.uvproj +++ /dev/null @@ -1,407 +0,0 @@ - - - - 1.1 - -
### uVision Project, (C) Keil Software
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