fixed bug: correct cortex-m SCB->VTOR address.

libcpu/arm/cortex-m0/context_gcc.S

@@ -22,7 +22,7 @@
     .thumb
     .text
 
-    .equ    SCB_VTOR, 0xE000ED04            /* Vector Table Offset Register */
+    .equ    SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
     .equ    ICSR, 0xE000ED04                /* interrupt control state register */
     .equ    PENDSVSET_BIT, 0x10000000       /* value to trigger PendSV exception */
     

libcpu/arm/cortex-m3/context_gcc.S

@@ -22,7 +22,7 @@
     .thumb
     .text
 
-    .equ    SCB_VTOR, 0xE000ED04            /* Vector Table Offset Register */
+    .equ    SCB_VTOR, 0xE000ED08            /* Vector Table Offset Register */
     .equ    ICSR, 0xE000ED04                /* interrupt control state register */
     .equ    PENDSVSET_BIT, 0x10000000       /* value to trigger PendSV exception */
     

libcpu/arm/cortex-m4/context_gcc.S

@@ -24,7 +24,7 @@
 .thumb
 .text
 
-.equ    SCB_VTOR,           0xE000ED04              /* Vector Table Offset Register */
+.equ    SCB_VTOR,           0xE000ED08              /* Vector Table Offset Register */
 .equ    NVIC_INT_CTRL,      0xE000ED04              /* interrupt control state register */
 .equ    NVIC_SYSPRI2,       0xE000ED20              /* system priority register (2) */
 .equ    NVIC_PENDSV_PRI,    0x00FF0000              /* PendSV priority value (lowest) */