From b045f93b47d4da57df034e201fff168219880605 Mon Sep 17 00:00:00 2001 From: aozima Date: Sun, 23 Jun 2013 18:08:16 +0800 Subject: [PATCH] fixed bug: correct cortex-m SCB->VTOR address. --- libcpu/arm/cortex-m0/context_gcc.S | 2 +- libcpu/arm/cortex-m3/context_gcc.S | 2 +- libcpu/arm/cortex-m4/context_gcc.S | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/libcpu/arm/cortex-m0/context_gcc.S b/libcpu/arm/cortex-m0/context_gcc.S index 309ac04cb2..fafdb0e744 100644 --- a/libcpu/arm/cortex-m0/context_gcc.S +++ b/libcpu/arm/cortex-m0/context_gcc.S @@ -22,7 +22,7 @@ .thumb .text - .equ SCB_VTOR, 0xE000ED04 /* Vector Table Offset Register */ + .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ ICSR, 0xE000ED04 /* interrupt control state register */ .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */ diff --git a/libcpu/arm/cortex-m3/context_gcc.S b/libcpu/arm/cortex-m3/context_gcc.S index fad274aea8..c36ca9a7c3 100644 --- a/libcpu/arm/cortex-m3/context_gcc.S +++ b/libcpu/arm/cortex-m3/context_gcc.S @@ -22,7 +22,7 @@ .thumb .text - .equ SCB_VTOR, 0xE000ED04 /* Vector Table Offset Register */ + .equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ ICSR, 0xE000ED04 /* interrupt control state register */ .equ PENDSVSET_BIT, 0x10000000 /* value to trigger PendSV exception */ diff --git a/libcpu/arm/cortex-m4/context_gcc.S b/libcpu/arm/cortex-m4/context_gcc.S index 2fe9747d6f..b66e257051 100644 --- a/libcpu/arm/cortex-m4/context_gcc.S +++ b/libcpu/arm/cortex-m4/context_gcc.S @@ -24,7 +24,7 @@ .thumb .text -.equ SCB_VTOR, 0xE000ED04 /* Vector Table Offset Register */ +.equ SCB_VTOR, 0xE000ED08 /* Vector Table Offset Register */ .equ NVIC_INT_CTRL, 0xE000ED04 /* interrupt control state register */ .equ NVIC_SYSPRI2, 0xE000ED20 /* system priority register (2) */ .equ NVIC_PENDSV_PRI, 0x00FF0000 /* PendSV priority value (lowest) */ -- GitLab