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.github/labeler.yml
浏览文件 @ 1b15cb21
......@@ -25,6 +25,7 @@
- "package/boot/uboot-bcm4908/**"
"target/bcm53xx":
- "target/linux/bcm53xx/**"
- "package/boot/uboot-bcm53xx/**"
"target/bcm63xx":
- "target/linux/bcm63xx/**"
- "package/kernel/bcm63xx-cfe/**"
......
config/Config-kernel.in
浏览文件 @ 1b15cb21
......@@ -47,6 +47,7 @@ config KERNEL_MIPS_FP_SUPPORT
config KERNEL_ARM_PMU
bool
default y if TARGET_armsr_armv8
depends on (arm || aarch64)
config KERNEL_X86_VSYSCALL_EMULATION
......
include/kernel-5.15
浏览文件 @ 1b15cb21
LINUX_VERSION-5.15 = .126
LINUX_KERNEL_HASH-5.15.126 = adf4aab9840f89ee151b837defbe16e9f388e8eef20df7ee94bf63be33b3ed6f
LINUX_VERSION-5.15 = .130
LINUX_KERNEL_HASH-5.15.130 = ab464e4107329ff5262f1c585c40fc29dc68f17687a9a918f3e90faba5303d62
include/kernel-6.1
浏览文件 @ 1b15cb21
LINUX_VERSION-6.1 = .45
LINUX_KERNEL_HASH-6.1.45 = bd2343396e7ddad8974f3689a5a067ec931f4ade793e72b1070a85cd19f1f192
LINUX_VERSION-6.1 = .51
LINUX_KERNEL_HASH-6.1.51 = 58b0446d8ea4bc0b26a35e2e3509bd53efcdeb295c9e4f48d33a23b1cdaa103b
include/prereq.mk
浏览文件 @ 1b15cb21
......@@ -107,16 +107,9 @@ define SetupHostCommand
bin="$$$$$$$$(command -v "$$$$$$$${cmd%% *}")"; \
if [ -x "$$$$$$$$bin" ] && eval "$$$$$$$$cmd" >/dev/null 2>/dev/null; then \
case "$$$$$$$$(ls -dl -- $(STAGING_DIR_HOST)/bin/$(strip $(1)))" in \
*" -> $$$$$$$$bin"*) \
[ -x "$(STAGING_DIR_HOST)/bin/$(strip $(1))" ] && exit 0 \
;; \
"-"*) \
find "$(STAGING_DIR_HOST)/stamp" | grep $(strip $(1)) && \
[ -x "$(STAGING_DIR_HOST)/bin/$(strip $(1))" ] && exit 0 \
;; \
*" -> /"*) \
;; \
*" -> "*) \
"-"* | \
*" -> $$$$$$$$bin"* | \
*" -> "[!/]*) \
[ -x "$(STAGING_DIR_HOST)/bin/$(strip $(1))" ] && exit 0 \
;; \
esac; \
......
package/boot/arm-trusted-firmware-mediatek/patches/001-mt7988-enable-2p5g-phy.patch 0 → 100644
浏览文件 @ 1b15cb21
--- a/plat/mediatek/mt7988/bl2/bl2_plat_init.c
+++ b/plat/mediatek/mt7988/bl2/bl2_plat_init.c
@@ -90,6 +90,8 @@ static void mtk_i2p5g_phy_init(void)
* clear bit 22 to use external MDIO.
*/
mmio_setbits_32(GBE_TOP_REG, I2P5G_MDIO);
+ /* Internal 2.5Gphy power on sequence */
+ eth_2p5g_phy_mtcmos_ctrl(true);
}
static void mt7988_i2c_init(void)
package/boot/arm-trusted-firmware-mvebu/Makefile
浏览文件 @ 1b15cb21
......@@ -7,9 +7,9 @@
include $(TOPDIR)/rules.mk
PKG_VERSION:=2.7
PKG_RELEASE:=6
PKG_HASH:=53422dc649153838e03820330ba17cb10afe3e330ecde0db11e4d5f1361a33e6
PKG_VERSION:=2.9
PKG_RELEASE:=1
PKG_HASH:=76a66a1de0c01aeb83dfc7b72b51173fe62c6e51d6fca17cc562393117bed08b
PKG_MAINTAINER:=Vladimir Vid <vladimir.vid@sartura.hr>
......@@ -123,7 +123,7 @@ TFA_MAKE_FLAGS += \
BL33=$(STAGING_DIR_IMAGE)/$(UBOOT)-u-boot.bin \
MV_DDR_PATH=$(BUILD_DIR)/$(MV_DDR_NAME) \
WTP=$(BUILD_DIR)/$(A3700_UTILS_NAME) \
WTMI_IMG=$(BUILD_DIR)/$(MOX_BB_NAME)-$(MOX_BB_RELEASE)/wtmi_app.bin \
WTMI_IMG=$(BUILD_DIR)/$(MOX_BB_NAME)/wtmi_app.bin \
CRYPTOPP_PATH=$(BUILD_DIR)/$(CRYPTOPP_NAME) \
HOST_LDFLAGS="$(HOST_LDFLAGS)" \
HOST_CPPFLAGS="$(HOST_CPPFLAGS)" \
......@@ -138,56 +138,60 @@ TFA_MAKE_FLAGS += \
mrvl_uart
A3700_UTILS_NAME:=a3700-utils
A3700_UTILS_RELEASE:=1d977157
A3700_UTILS_RELEASE:=a3e1c67
A3700_UTILS_SOURCE=$(A3700_UTILS_NAME)-$(A3700_UTILS_RELEASE).tar.bz2
define Download/a3700-utils
FILE:=$(A3700_UTILS_SOURCE)
PROTO:=git
URL:=https://github.com/MarvellEmbeddedProcessors/A3700-utils-marvell.git
VERSION:=1d977157e37151b272f88f2406a245c833fb2d8c
MIRROR_HASH:=322821ec8c04afea260254e927c59cd1ec0bd84e7ec6507cc1f155f18afb8eb9
VERSION:=a3e1c67bb378e1d8a938e1b826cb602af83628d2
MIRROR_HASH:=0e6b8ef6423dcb52a5e282669a8aeebc6eea2d45a7c3a2c9a2fc7a749b3275a7
SUBDIR:=$(A3700_UTILS_NAME)
endef
CRYPTOPP_NAME:=cryptopp
CRYPTOPP_RELEASE:=f210224
CRYPTOPP_RELEASE:=4d0cad5
CRYPTOPP_SOURCE=$(CRYPTOPP_NAME)-$(CRYPTOPP_RELEASE).tar.bz2
define Download/cryptopp
FILE:=$(CRYPTOPP_SOURCE)
PROTO:=git
URL:=https://github.com/weidai11/cryptopp.git
VERSION:=f2102243e6fdd48c0b2a393a0993cca228f20573
VERSION:=4d0cad5401d1a2c998b314bc89288c9620d3021d
MIRROR_HASH:=74ec9e48ee04b9f2d9a1d8c4f2392ed0ab52780d7af0f70405d7bbb23d1504fa
SUBDIR:=$(CRYPTOPP_NAME)
endef
MV_DDR_NAME:=mv-ddr-marvell
MV_DDR_RELEASE:=d5acc10c
MV_DDR_RELEASE:=541616b
MV_DDR_SOURCE:=$(MV_DDR_NAME)-$(MV_DDR_RELEASE).tar.bz2
define Download/mv-ddr-marvell
FILE:=$(MV_DDR_SOURCE)
PROTO:=git
URL:=https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
VERSION:=d5acc10c287e40cc2feeb28710b92e45c93c702c
MIRROR_HASH:=c149ab737935b5fb822f48da8e2d7fba4388f48e645f9f6da857bee20f0333ea
VERSION:=541616bc5d25a0167c9901546255c55973e2c0f0
MIRROR_HASH:=9e86a986c7400ed1a72165a88150b6c494ebd87303b16314b43e5785e3f13068
SUBDIR:=$(MV_DDR_NAME)
endef
MOX_BB_NAME:=mox-boot-builder
MOX_BB_RELEASE:=v2022.06.11
MOX_BB_RELEASE:=604f8f51
MOX_BB_SOURCE:=$(MOX_BB_NAME)-$(MOX_BB_RELEASE).tar.bz2
define Download/mox-boot-builder
FILE:=$(MOX_BB_SOURCE)
URL:=https://gitlab.nic.cz/turris/mox-boot-builder/-/archive/$(MOX_BB_RELEASE)
HASH:=75e7661c38f4f5e6d8910dd789d6d9ffd8652455548b68c98e5bf45eaab5b6eb
PROTO:=git
SUBMODULES:=skip
URL:=https://gitlab.nic.cz/turris/mox-boot-builder.git
VERSION:=604f8f51d97b4e59fa6d1e579101daa194d6ed2d
MIRROR_HASH:=b09337a7dde140f57e40133b6e7b7e1eb338e7cea9b15a3af6874824462f15f7
SUBDIR:=$(MOX_BB_NAME)
endef
CM3_GCC_NAME:=gcc-arm
CM3_GCC_RELEASE:=11.2-2022.02
CM3_GCC_NAME:=arm-gnu-toolchain
CM3_GCC_RELEASE:=12.3.rel1
CM3_GCC_VERSION:=$(HOST_ARCH)-arm-none-eabi
CM3_GCC_SOURCE=$(CM3_GCC_NAME)-$(CM3_GCC_RELEASE)-$(CM3_GCC_VERSION).tar.xz
......@@ -195,9 +199,9 @@ define Download/cm3-gcc
FILE:=$(CM3_GCC_SOURCE)
URL:=https://developer.arm.com/-/media/Files/downloads/gnu/$(CM3_GCC_RELEASE)/binrel
ifeq ($(HOST_ARCH),aarch64)
HASH:=ef1d82e5894e3908cb7ed49c5485b5b95deefa32872f79c2b5f6f5447cabf55f
HASH:=14c0487d5753f6071d24e568881f7c7e67f80dd83165dec5164b3731394af431
else
HASH:=8c5acd5ae567c0100245b0556941c237369f210bceb196edfe5a2e7532c60326
HASH:=12a2815644318ebcceaf84beabb665d0924b6e79e21048452c5331a56332b309
endif
endef
......@@ -206,7 +210,7 @@ define Build/Clean
$(BUILD_DIR)/$(CRYPTOPP_NAME) \
$(BUILD_DIR)/$(A3700_UTILS_NAME) \
$(BUILD_DIR)/$(MV_DDR_NAME) \
$(BUILD_DIR)/$(MOX_BB_NAME)-$(MOX_BB_RELEASE) \
$(BUILD_DIR)/$(MOX_BB_NAME) \
$(BUILD_DIR)/$(CM3_GCC_NAME)-$(CM3_GCC_RELEASE)-$(CM3_GCC_VERSION)
endef
......@@ -226,7 +230,7 @@ define Build/Prepare
$(TAR) -C $(BUILD_DIR) -xf $(DL_DIR)/$(MV_DDR_SOURCE)
$(call PatchDir/Default,$(BUILD_DIR)/$(MV_DDR_NAME),./patches-mv-ddr-marvell)
$(TAR) -C $(BUILD_DIR) -xf $(DL_DIR)/$(MOX_BB_SOURCE)
$(call PatchDir/Default,$(BUILD_DIR)/$(MOX_BB_NAME)-$(MOX_BB_RELEASE),./patches-mox-boot-builder)
$(call PatchDir/Default,$(BUILD_DIR)/$(MOX_BB_NAME),./patches-mox-boot-builder)
$(TAR) -C $(BUILD_DIR) -xf $(DL_DIR)/$(CM3_GCC_SOURCE)
endef
......@@ -235,7 +239,7 @@ define Build/Compile
CROSS_CM3=$(BUILD_DIR)/$(CM3_GCC_NAME)-$(CM3_GCC_RELEASE)-$(CM3_GCC_VERSION)/bin/arm-none-eabi- \
WTMI_VERSION=$(MOX_BB_RELEASE) \
CRYPTOPP_PATH=$PWD/cryptopp/ \
-C $(BUILD_DIR)/$(MOX_BB_NAME)-$(MOX_BB_RELEASE) \
-C $(BUILD_DIR)/$(MOX_BB_NAME) \
wtmi_app.bin
$(call Build/Compile/Default)
endef
......
package/boot/uboot-bcm53xx/Makefile 0 → 100644
浏览文件 @ 1b15cb21
include $(TOPDIR)/rules.mk
PKG_VERSION:=2023.04
PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341
PKG_RELEASE:=$(AUTORELEASE)
include $(INCLUDE_DIR)/u-boot.mk
include $(INCLUDE_DIR)/package.mk
define U-Boot/Default
BUILD_TARGET:=bcm53xx
BUILD_SUBTARGET:=generic
UBOOT_CONFIG:=bcmns
UBOOT_BOARD:=$(1)
endef
define U-Boot/dir-885l
NAME:=D-Link DIR-885L
BUILD_DEVICES:=dlink_dir-885l
endef
define U-Boot/dir-890l
NAME:=D-Link DIR-890L
BUILD_DEVICES:=dlink_dir-890l
endef
UBOOT_TARGETS := dir-885l dir-890l
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
$(CP) $(PKG_BUILD_DIR)/$(UBOOT_IMAGE) $(STAGING_DIR_IMAGE)/$(BUILD_DEVICES)-u-boot.bin
endef
define Package/u-boot/install/default
endef
$(eval $(call BuildPackage/U-Boot))
package/boot/uboot-bcm53xx/patches/0001-nand-brcmnand-add-iproc-support.patch 0 → 100644
浏览文件 @ 1b15cb21
From 854dc4b790ce1291326d52b8405ebe771bff2edd Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Wed, 8 Mar 2023 22:42:31 +0100
Subject: [PATCH 1/5] nand: brcmnand: add iproc support
Add support for the iproc Broadcom NAND controller,
used in Northstar SoCs for example. Based on the Linux
driver.
Cc: Philippe Reynes <philippe.reynes@softathome.com>
Cc: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: William Zhang <william.zhang@broadcom.com>
Link: https://lore.kernel.org/all/20230308214231.378013-1-linus.walleij@linaro.org/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
drivers/mtd/nand/raw/Kconfig | 7 +
drivers/mtd/nand/raw/brcmnand/Makefile | 1 +
drivers/mtd/nand/raw/brcmnand/iproc_nand.c | 148 +++++++++++++++++++++
3 files changed, 156 insertions(+)
create mode 100644 drivers/mtd/nand/raw/brcmnand/iproc_nand.c
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -156,6 +156,13 @@ config NAND_BRCMNAND_63158
help
Enable support for broadcom nand driver on bcm63158.
+config NAND_BRCMNAND_IPROC
+ bool "Support Broadcom NAND controller on the iproc family"
+ depends on NAND_BRCMNAND
+ help
+ Enable support for broadcom nand driver on the Broadcom
+ iproc family such as Northstar (BCM5301x, BCM4708...)
+
config NAND_DAVINCI
bool "Support TI Davinci NAND controller"
select SYS_NAND_SELF_INIT if TARGET_DA850EVM
--- a/drivers/mtd/nand/raw/brcmnand/Makefile
+++ b/drivers/mtd/nand/raw/brcmnand/Makefile
@@ -6,5 +6,6 @@ obj-$(CONFIG_NAND_BRCMNAND_6753) += bcm6
obj-$(CONFIG_NAND_BRCMNAND_68360) += bcm68360_nand.o
obj-$(CONFIG_NAND_BRCMNAND_6838) += bcm6838_nand.o
obj-$(CONFIG_NAND_BRCMNAND_6858) += bcm6858_nand.o
+obj-$(CONFIG_NAND_BRCMNAND_IPROC) += iproc_nand.o
obj-$(CONFIG_NAND_BRCMNAND) += brcmnand.o
obj-$(CONFIG_NAND_BRCMNAND) += brcmnand_compat.o
--- /dev/null
+++ b/drivers/mtd/nand/raw/brcmnand/iproc_nand.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Code borrowed from the Linux driver
+ * Copyright (C) 2015 Broadcom Corporation
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <memalign.h>
+#include <nand.h>
+#include <linux/bitops.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <dm.h>
+
+#include "brcmnand.h"
+
+struct iproc_nand_soc {
+ struct brcmnand_soc soc;
+ void __iomem *idm_base;
+ void __iomem *ext_base;
+};
+
+#define IPROC_NAND_CTLR_READY_OFFSET 0x10
+#define IPROC_NAND_CTLR_READY BIT(0)
+
+#define IPROC_NAND_IO_CTRL_OFFSET 0x00
+#define IPROC_NAND_APB_LE_MODE BIT(24)
+#define IPROC_NAND_INT_CTRL_READ_ENABLE BIT(6)
+
+static bool iproc_nand_intc_ack(struct brcmnand_soc *soc)
+{
+ struct iproc_nand_soc *priv =
+ container_of(soc, struct iproc_nand_soc, soc);
+ void __iomem *mmio = priv->ext_base + IPROC_NAND_CTLR_READY_OFFSET;
+ u32 val = brcmnand_readl(mmio);
+
+ if (val & IPROC_NAND_CTLR_READY) {
+ brcmnand_writel(IPROC_NAND_CTLR_READY, mmio);
+ return true;
+ }
+
+ return false;
+}
+
+static void iproc_nand_intc_set(struct brcmnand_soc *soc, bool en)
+{
+ struct iproc_nand_soc *priv =
+ container_of(soc, struct iproc_nand_soc, soc);
+ void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET;
+ u32 val = brcmnand_readl(mmio);
+
+ if (en)
+ val |= IPROC_NAND_INT_CTRL_READ_ENABLE;
+ else
+ val &= ~IPROC_NAND_INT_CTRL_READ_ENABLE;
+
+ brcmnand_writel(val, mmio);
+}
+
+static void iproc_nand_apb_access(struct brcmnand_soc *soc, bool prepare,
+ bool is_param)
+{
+ struct iproc_nand_soc *priv =
+ container_of(soc, struct iproc_nand_soc, soc);
+ void __iomem *mmio = priv->idm_base + IPROC_NAND_IO_CTRL_OFFSET;
+ u32 val;
+
+ val = brcmnand_readl(mmio);
+
+ /*
+ * In the case of BE or when dealing with NAND data, always configure
+ * the APB bus to LE mode before accessing the FIFO and back to BE mode
+ * after the access is done
+ */
+ if (IS_ENABLED(CONFIG_SYS_BIG_ENDIAN) || !is_param) {
+ if (prepare)
+ val |= IPROC_NAND_APB_LE_MODE;
+ else
+ val &= ~IPROC_NAND_APB_LE_MODE;
+ } else { /* when in LE accessing the parameter page, keep APB in BE */
+ val &= ~IPROC_NAND_APB_LE_MODE;
+ }
+
+ brcmnand_writel(val, mmio);
+}
+
+static int iproc_nand_probe(struct udevice *dev)
+{
+ struct udevice *pdev = dev;
+ struct iproc_nand_soc *priv = dev_get_priv(dev);
+ struct brcmnand_soc *soc;
+ struct resource res;
+ int ret;
+
+ soc = &priv->soc;
+
+ ret = dev_read_resource_byname(pdev, "iproc-idm", &res);
+ if (ret)
+ return ret;
+
+ priv->idm_base = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(priv->idm_base))
+ return PTR_ERR(priv->idm_base);
+
+ ret = dev_read_resource_byname(pdev, "iproc-ext", &res);
+ if (ret)
+ return ret;
+
+ priv->ext_base = devm_ioremap(dev, res.start, resource_size(&res));
+ if (IS_ERR(priv->ext_base))
+ return PTR_ERR(priv->ext_base);
+
+ soc->ctlrdy_ack = iproc_nand_intc_ack;
+ soc->ctlrdy_set_enabled = iproc_nand_intc_set;
+ soc->prepare_data_bus = iproc_nand_apb_access;
+
+ return brcmnand_probe(pdev, soc);
+}
+
+static const struct udevice_id iproc_nand_dt_ids[] = {
+ {
+ .compatible = "brcm,nand-iproc",
+ },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(iproc_nand) = {
+ .name = "iproc-nand",
+ .id = UCLASS_MTD,
+ .of_match = iproc_nand_dt_ids,
+ .probe = iproc_nand_probe,
+ .priv_auto = sizeof(struct iproc_nand_soc),
+};
+
+void board_nand_init(void)
+{
+ struct udevice *dev;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_MTD,
+ DM_DRIVER_GET(iproc_nand), &dev);
+ if (ret && ret != -ENODEV)
+ pr_err("Failed to initialize %s. (error %d)\n", dev->name,
+ ret);
+}
package/boot/uboot-bcm53xx/patches/0002-mtd-rawnand-nand_base-Handle-algorithm-selection.patch 0 → 100644
浏览文件 @ 1b15cb21
From d75483f8892f3a0dfb8f5aa4147e72c02c8b034c Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Fri, 7 Apr 2023 15:40:05 +0200
Subject: [PATCH 2/5] mtd: rawnand: nand_base: Handle algorithm selection
For BRCMNAND with 1-bit BCH ECC (BCH-1) such as used on the
D-Link DIR-885L and DIR-890L routers, we need to explicitly
select the ECC like this in the device tree:
nand-ecc-algo = "bch";
nand-ecc-strength = <1>;
nand-ecc-step-size = <512>;
This is handled by the Linux kernel but U-Boot core does
not respect this. Fix it up by parsing the algorithm and
preserve the behaviour using this property to select
software BCH as far as possible.
Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Tested-by: Tom Rini <trini@konsulko.com> [am335x_evm]
Link: https://lore.kernel.org/all/20230407134008.1939717-3-linus.walleij@linaro.org/
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
---
drivers/mtd/nand/raw/nand_base.c | 29 +++++++++++++++++++++++++----
1 file changed, 25 insertions(+), 4 deletions(-)
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -4487,6 +4487,7 @@ EXPORT_SYMBOL(nand_detect);
static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, ofnode node)
{
int ret, ecc_mode = -1, ecc_strength, ecc_step;
+ int ecc_algo = NAND_ECC_UNKNOWN;
const char *str;
ret = ofnode_read_s32_default(node, "nand-bus-width", -1);
@@ -4512,10 +4513,22 @@ static int nand_dt_init(struct mtd_info
ecc_mode = NAND_ECC_SOFT_BCH;
}
- if (ecc_mode == NAND_ECC_SOFT) {
- str = ofnode_read_string(node, "nand-ecc-algo");
- if (str && !strcmp(str, "bch"))
- ecc_mode = NAND_ECC_SOFT_BCH;
+ str = ofnode_read_string(node, "nand-ecc-algo");
+ if (str) {
+ /*
+ * If we are in NAND_ECC_SOFT mode, just alter the
+ * soft mode to BCH here. No change of algorithm.
+ */
+ if (ecc_mode == NAND_ECC_SOFT) {
+ if (!strcmp(str, "bch"))
+ ecc_mode = NAND_ECC_SOFT_BCH;
+ } else {
+ if (!strcmp(str, "bch")) {
+ ecc_algo = NAND_ECC_BCH;
+ } else if (!strcmp(str, "hamming")) {
+ ecc_algo = NAND_ECC_HAMMING;
+ }
+ }
}
ecc_strength = ofnode_read_s32_default(node,
@@ -4529,6 +4542,14 @@ static int nand_dt_init(struct mtd_info
return -EINVAL;
}
+ /*
+ * Chip drivers may have assigned default algorithms here,
+ * onlt override it if we have found something explicitly
+ * specified in the device tree.
+ */
+ if (ecc_algo != NAND_ECC_UNKNOWN)
+ chip->ecc.algo = ecc_algo;
+
if (ecc_mode >= 0)
chip->ecc.mode = ecc_mode;
package/boot/uboot-bcm53xx/patches/0003-arm-dts-Import-device-tree-for-Broadcom-Northstar.patch 0 → 100644
浏览文件 @ 1b15cb21
From 3d6098a662b7ff5b80c4b75c54fcd1b2baf9f150 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Mon, 24 Apr 2023 09:38:28 +0200
Subject: [PATCH 3/5] arm: dts: Import device tree for Broadcom Northstar
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This brings in the main SoC device tree used by the
Broadcom Northstar chipset, i.e. BCM4709x and BCM5301x.
This is taken from the v6.3 Linux kernel.
Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/dts/bcm5301x.dtsi | 581 ++++++++++++++++++++++++++++
include/dt-bindings/clock/bcm-nsp.h | 51 +++
2 files changed, 632 insertions(+)
create mode 100644 arch/arm/dts/bcm5301x.dtsi
create mode 100644 include/dt-bindings/clock/bcm-nsp.h
--- /dev/null
+++ b/arch/arm/dts/bcm5301x.dtsi
@@ -0,0 +1,581 @@
+/*
+ * Broadcom BCM470X / BCM5301X ARM platform code.
+ * Generic DTS part for all BCM53010, BCM53011, BCM53012, BCM53014, BCM53015,
+ * BCM53016, BCM53017, BCM53018, BCM4707, BCM4708 and BCM4709 SoCs
+ *
+ * Copyright 2013-2014 Hauke Mehrtens <hauke@hauke-m.de>
+ *
+ * Licensed under the GNU/GPL. See COPYING for details.
+ */
+
+#include <dt-bindings/clock/bcm-nsp.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ chipcommon-a-bus@18000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0x18000000 0x00001000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ uart0: serial@300 {
+ compatible = "ns16550";
+ reg = <0x0300 0x100>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&iprocslow>;
+ status = "disabled";
+ };
+
+ uart1: serial@400 {
+ compatible = "ns16550";
+ reg = <0x0400 0x100>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&iprocslow>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinmux_uart1>;
+ status = "disabled";
+ };
+ };
+
+ mpcore-bus@19000000 {
+ compatible = "simple-bus";
+ ranges = <0x00000000 0x19000000 0x00023000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ a9pll: arm_clk@0 {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x00000 0x1000>;
+ };
+
+ scu@20000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x20000 0x100>;
+ };
+
+ timer@20200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x20200 0x100>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&periph_clk>;
+ };
+
+ timer@20600 {
+ compatible = "arm,cortex-a9-twd-timer";
+ reg = <0x20600 0x20>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
+ clocks = <&periph_clk>;
+ };
+
+ watchdog@20620 {
+ compatible = "arm,cortex-a9-twd-wdt";
+ reg = <0x20620 0x20>;
+ interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_EDGE_RISING)>;
+ clocks = <&periph_clk>;
+ };
+
+ gic: interrupt-controller@21000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
+ };
+
+ L2: cache-controller@22000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x22000 0x1000>;
+ cache-unified;
+ arm,shared-override;
+ prefetch-data = <1>;
+ prefetch-instr = <1>;
+ cache-level = <2>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts =
+ <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ osc: oscillator {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ periph_clk: periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&a9pll>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+ };
+
+ axi@18000000 {
+ compatible = "brcm,bus-axi";
+ reg = <0x18000000 0x1000>;
+ ranges = <0x00000000 0x18000000 0x00100000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0x000fffff 0xffff>;
+ interrupt-map =
+ /* ChipCommon */
+ <0x00000000 0 &gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Switch Register Access Block */
+ <0x00007000 0 &gic GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 1 &gic GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 2 &gic GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 3 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 4 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 5 &gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 6 &gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 7 &gic GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 8 &gic GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 9 &gic GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 10 &gic GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 11 &gic GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00007000 12 &gic GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* PCIe Controller 0 */
+ <0x00012000 0 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00012000 1 &gic GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00012000 2 &gic GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00012000 3 &gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00012000 4 &gic GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00012000 5 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* PCIe Controller 1 */
+ <0x00013000 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00013000 1 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00013000 2 &gic GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00013000 3 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00013000 4 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00013000 5 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* PCIe Controller 2 */
+ <0x00014000 0 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00014000 1 &gic GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00014000 2 &gic GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00014000 3 &gic GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00014000 4 &gic GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00014000 5 &gic GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* USB 2.0 Controller */
+ <0x00021000 0 &gic GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* USB 3.0 Controller */
+ <0x00023000 0 &gic GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Ethernet Controller 0 */
+ <0x00024000 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Ethernet Controller 1 */
+ <0x00025000 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Ethernet Controller 2 */
+ <0x00026000 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* Ethernet Controller 3 */
+ <0x00027000 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+
+ /* NAND Controller */
+ <0x00028000 0 &gic GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 1 &gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 2 &gic GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 3 &gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 4 &gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 5 &gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 6 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
+ <0x00028000 7 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+
+ chipcommon: chipcommon@0 {
+ reg = <0x00000000 0x1000>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcie0: pcie@12000 {
+ reg = <0x00012000 0x1000>;
+ };
+
+ pcie1: pcie@13000 {
+ reg = <0x00013000 0x1000>;
+ };
+
+ pcie2: pcie@14000 {
+ reg = <0x00014000 0x1000>;
+ };
+
+ usb2: usb2@21000 {
+ reg = <0x00021000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupt-parent = <&gic>;
+
+ ehci: usb@21000 {
+ #usb-cells = <0>;
+
+ compatible = "generic-ehci";
+ reg = <0x00021000 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb2_phy>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ehci_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ ehci_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+ };
+
+ ohci: usb@22000 {
+ #usb-cells = <0>;
+
+ compatible = "generic-ohci";
+ reg = <0x00022000 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ohci_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+
+ ohci_port2: port@2 {
+ reg = <2>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ usb3: usb3@23000 {
+ reg = <0x00023000 0x1000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ interrupt-parent = <&gic>;
+
+ xhci: usb@23000 {
+ #usb-cells = <0>;
+
+ compatible = "generic-xhci";
+ reg = <0x00023000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy>;
+ phy-names = "usb";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ xhci_port1: port@1 {
+ reg = <1>;
+ #trigger-source-cells = <0>;
+ };
+ };
+ };
+
+ gmac0: ethernet@24000 {
+ reg = <0x24000 0x800>;
+ };
+
+ gmac1: ethernet@25000 {
+ reg = <0x25000 0x800>;
+ };
+
+ gmac2: ethernet@26000 {
+ reg = <0x26000 0x800>;
+ };
+
+ gmac3: ethernet@27000 {
+ reg = <0x27000 0x800>;
+ };
+ };
+
+ pwm: pwm@18002000 {
+ compatible = "brcm,iproc-pwm";
+ reg = <0x18002000 0x28>;
+ clocks = <&osc>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ mdio: mdio@18003000 {
+ compatible = "brcm,iproc-mdio";
+ reg = <0x18003000 0x8>;
+ #size-cells = <0>;
+ #address-cells = <1>;
+ };
+
+ mdio-mux@18003000 {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ mdio-parent-bus = <&mdio>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x18003000 0x4>;
+ mux-mask = <0x200>;
+
+ mdio@0 {
+ reg = <0x0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ usb3_phy: usb3-phy@10 {
+ compatible = "brcm,ns-ax-usb3-phy";
+ reg = <0x10>;
+ usb3-dmp-syscon = <&usb3_dmp>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+ };
+ };
+
+ usb3_dmp: syscon@18105000 {
+ reg = <0x18105000 0x1000>;
+ };
+
+ uart2: serial@18008000 {
+ compatible = "ns16550a";
+ reg = <0x18008000 0x20>;
+ clocks = <&iprocslow>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@18009000 {
+ compatible = "brcm,iproc-i2c";
+ reg = <0x18009000 0x50>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ dmu-bus@1800c000 {
+ compatible = "simple-bus";
+ ranges = <0 0x1800c000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cru-bus@100 {
+ compatible = "brcm,ns-cru", "simple-mfd";
+ reg = <0x100 0x1a4>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ lcpll0: clock-controller@100 {
+ #clock-cells = <1>;
+ compatible = "brcm,nsp-lcpll0";
+ reg = <0x100 0x14>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll0", "pcie_phy",
+ "sdio", "ddr_phy";
+ };
+
+ genpll: clock-controller@140 {
+ #clock-cells = <1>;
+ compatible = "brcm,nsp-genpll";
+ reg = <0x140 0x24>;
+ clocks = <&osc>;
+ clock-output-names = "genpll", "phy",
+ "ethernetclk",
+ "usbclk", "iprocfast",
+ "sata1", "sata2";
+ };
+
+ usb2_phy: phy@164 {
+ compatible = "brcm,ns-usb2-phy";
+ reg = <0x164 0x4>;
+ brcm,syscon-clkset = <&cru_clkset>;
+ clocks = <&genpll BCM_NSP_GENPLL_USB_PHY_REF_CLK>;
+ clock-names = "phy-ref-clk";
+ #phy-cells = <0>;
+ };
+
+ cru_clkset: syscon@180 {
+ compatible = "brcm,cru-clkset", "syscon";
+ reg = <0x180 0x4>;
+ };
+
+ pinctrl: pinctrl@1c0 {
+ compatible = "brcm,bcm4708-pinmux";
+ reg = <0x1c0 0x24>;
+ reg-names = "cru_gpio_control";
+
+ spi-pins {
+ groups = "spi_grp";
+ function = "spi";
+ };
+
+ pinmux_i2c: i2c-pins {
+ groups = "i2c_grp";
+ function = "i2c";
+ };
+
+ pinmux_pwm: pwm-pins {
+ groups = "pwm0_grp", "pwm1_grp",
+ "pwm2_grp", "pwm3_grp";
+ function = "pwm";
+ };
+
+ pinmux_uart1: uart1-pins {
+ groups = "uart1_grp";
+ function = "uart1";
+ };
+ };
+
+ thermal: thermal@2c0 {
+ compatible = "brcm,ns-thermal";
+ reg = <0x2c0 0x10>;
+ #thermal-sensor-cells = <0>;
+ };
+ };
+ };
+
+ srab: ethernet-switch@18007000 {
+ compatible = "brcm,bcm53011-srab", "brcm,bcm5301x-srab";
+ reg = <0x18007000 0x1000>;
+
+ status = "disabled";
+
+ /* ports are defined in board DTS */
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ rng: rng@18004000 {
+ compatible = "brcm,bcm5301x-rng";
+ reg = <0x18004000 0x14>;
+ };
+
+ nand_controller: nand-controller@18028000 {
+ compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1", "brcm,brcmnand";
+ reg = <0x18028000 0x600>, <0x1811a408 0x600>, <0x18028f00 0x20>;
+ reg-names = "nand", "iproc-idm", "iproc-ext";
+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcm,nand-has-wp;
+ };
+
+ spi@18029200 {
+ compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";
+ reg = <0x18029200 0x184>,
+ <0x18029000 0x124>,
+ <0x1811b408 0x004>,
+ <0x180293a0 0x01c>;
+ reg-names = "mspi", "bspi", "intr_regs", "intr_status_reg";
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "mspi_done",
+ "mspi_halted",
+ "spi_lr_fullness_reached",
+ "spi_lr_session_aborted",
+ "spi_lr_impatient",
+ "spi_lr_session_done",
+ "spi_lr_overread";
+ clocks = <&iprocmed>;
+ clock-names = "iprocmed";
+ num-cs = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spi_nor: flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ status = "disabled";
+
+ partitions {
+ compatible = "brcm,bcm947xx-cfe-partitions";
+ };
+ };
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <1000>;
+ coefficients = <(-556) 418000>;
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <125000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+};
--- /dev/null
+++ b/include/dt-bindings/clock/bcm-nsp.h
@@ -0,0 +1,51 @@
+/*
+ * BSD LICENSE
+ *
+ * Copyright(c) 2015 Broadcom Corporation. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Broadcom Corporation nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _CLOCK_BCM_NSP_H
+#define _CLOCK_BCM_NSP_H
+
+/* GENPLL clock channel ID */
+#define BCM_NSP_GENPLL 0
+#define BCM_NSP_GENPLL_PHY_CLK 1
+#define BCM_NSP_GENPLL_ENET_SW_CLK 2
+#define BCM_NSP_GENPLL_USB_PHY_REF_CLK 3
+#define BCM_NSP_GENPLL_IPROCFAST_CLK 4
+#define BCM_NSP_GENPLL_SATA1_CLK 5
+#define BCM_NSP_GENPLL_SATA2_CLK 6
+
+/* LCPLL0 clock channel ID */
+#define BCM_NSP_LCPLL0 0
+#define BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK 1
+#define BCM_NSP_LCPLL0_SDIO_CLK 2
+#define BCM_NSP_LCPLL0_DDR_PHY_CLK 3
+
+#endif /* _CLOCK_BCM_NSP_H */
package/boot/uboot-bcm53xx/patches/0004-arm-Add-support-for-the-Broadcom-Northstar-SoCs.patch 0 → 100644
浏览文件 @ 1b15cb21
From b81ea0a64b01ae42e8b41d2a8b9a3fabffe97489 Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Mon, 24 Apr 2023 09:38:29 +0200
Subject: [PATCH 4/5] arm: Add support for the Broadcom Northstar SoCs
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The original Northstar is an ARM SoC series that comprise
BCM4709x and BCM5301x and uses a dual-core Cortex A9, the
global timer and a few other things.
This series should not be confused with North Star Plus
(NSP) which is partly supported by U-Boot already.
The SoC is well supported by the Linux kernel and OpenWrt
as it is used in many routers.
Since we currently don't need any chip-specific quirks
and can get the system up from just the device tree, a
mach-* directory doesn't even need to be added, just
some small Kconfig fragments.
Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/Kconfig | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -357,7 +357,7 @@ config SYS_ARM_ARCH
choice
prompt "Select the ARM data write cache policy"
- default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
+ default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || TARGET_BCMNS || RZA1
default SYS_ARM_CACHE_WRITEBACK
config SYS_ARM_CACHE_WRITEBACK
@@ -670,6 +670,25 @@ config TARGET_BCMCYGNUS
imply HASH_VERIFY
imply NETDEVICES
+config TARGET_BCMNS
+ bool "Support Broadcom Northstar"
+ select CPU_V7A
+ select DM
+ select DM_GPIO
+ select DM_SERIAL
+ select OF_CONTROL
+ select TIMER
+ select SYS_NS16550
+ select ARM_GLOBAL_TIMER
+ imply SYS_THUMB_BUILD
+ imply MTD_RAW_NAND
+ imply NAND_BRCMNAND
+ imply NAND_BRCMNAND_IPROC
+ help
+ Support for Broadcom Northstar SoCs. NS is a dual-core 32-bit
+ ARMv7 Cortex-A9 SoC family including BCM4708, BCM47094,
+ BCM5301x etc.
+
config TARGET_BCMNS2
bool "Support Broadcom Northstar2"
select ARM64
package/boot/uboot-bcm53xx/patches/0005-board-Add-new-Broadcom-Northstar-board.patch 0 → 100644
浏览文件 @ 1b15cb21
From 652a6fa45b6c9d52dd9685fc12ad662e54a9092e Mon Sep 17 00:00:00 2001
From: Linus Walleij <linus.walleij@linaro.org>
Date: Mon, 24 Apr 2023 09:38:30 +0200
Subject: [PATCH 5/5] board: Add new Broadcom Northstar board
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
This adds a simple Northstar "BRCMNS" board to be used with
the BCM4708x and BCM5301x chips.
The main intention is to use this with the D-Link DIR-890L
and DIR-885L routers for loading the kernel into RAM from
NAND memory using the BCH-1 ECC and using the separately
submitted SEAMA load command, so we are currently not adding
support for things such as networking.
The DTS file is a multiplatform NorthStar board, designed to
be usable with several NorthStar designs by avoiding any
particulars not related to the operation of U-Boot.
If other board need other ECC for example, they need to
create a separate DTS file and augment the code, but I don't
know if any other users will turn up.
Cc: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
arch/arm/Kconfig | 1 +
arch/arm/dts/Makefile | 2 ++
arch/arm/dts/ns-board.dts | 57 ++++++++++++++++++++++++++++++
board/broadcom/bcmns/Kconfig | 12 +++++++
board/broadcom/bcmns/MAINTAINERS | 6 ++++
board/broadcom/bcmns/Makefile | 2 ++
board/broadcom/bcmns/ns.c | 60 ++++++++++++++++++++++++++++++++
configs/bcmns_defconfig | 41 ++++++++++++++++++++++
doc/board/broadcom/index.rst | 1 +
doc/board/broadcom/northstar.rst | 44 +++++++++++++++++++++++
include/configs/bcmns.h | 49 ++++++++++++++++++++++++++
11 files changed, 275 insertions(+)
create mode 100644 arch/arm/dts/ns-board.dts
create mode 100644 board/broadcom/bcmns/Kconfig
create mode 100644 board/broadcom/bcmns/MAINTAINERS
create mode 100644 board/broadcom/bcmns/Makefile
create mode 100644 board/broadcom/bcmns/ns.c
create mode 100644 configs/bcmns_defconfig
create mode 100644 doc/board/broadcom/northstar.rst
create mode 100644 include/configs/bcmns.h
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2286,6 +2286,7 @@ source "board/Marvell/octeontx2/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
+source "board/broadcom/bcmns/Kconfig"
source "board/broadcom/bcmns3/Kconfig"
source "board/cavium/thunderx/Kconfig"
source "board/eets/pdu001/Kconfig"
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1185,6 +1185,8 @@ dtb-$(CONFIG_ARCH_BCM283X) += \
bcm2837-rpi-cm3-io3.dtb \
bcm2711-rpi-4-b.dtb
+dtb-$(CONFIG_TARGET_BCMNS) += ns-board.dtb
+
dtb-$(CONFIG_TARGET_BCMNS3) += ns3-board.dtb
dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
--- /dev/null
+++ b/arch/arm/dts/ns-board.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/dts-v1/;
+
+#include "bcm5301x.dtsi"
+
+/ {
+ /*
+ * The Northstar does not have a proper fallback compatible, but
+ * these basic chips will suffice.
+ */
+ model = "Northstar model";
+ compatible = "brcm,bcm47094", "brcm,bcm4708";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x08000000>,
+ <0x88000000 0x08000000>;
+ };
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ nand-controller@18028000 {
+ nandcs: nand@0 {
+ compatible = "brcm,nandcs";
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /*
+ * Same as using the bcm5301x-nand-cs0-bch1.dtsi
+ * include from the Linux kernel.
+ */
+ nand-ecc-algo = "bch";
+ nand-ecc-strength = <1>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "brcm,bcm947xx-cfe-partitions";
+ };
+ };
+ };
+};
+
+&uart0 {
+ clock-frequency = <125000000>;
+ status = "okay";
+};
--- /dev/null
+++ b/board/broadcom/bcmns/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_BCMNS
+
+config SYS_BOARD
+ default "bcmns"
+
+config SYS_VENDOR
+ default "broadcom"
+
+config SYS_CONFIG_NAME
+ default "bcmns"
+
+endif
--- /dev/null
+++ b/board/broadcom/bcmns/MAINTAINERS
@@ -0,0 +1,6 @@
+BCMNS BOARD
+M: Linus Walleij <linus.walleij@linaro.org>
+S: Maintained
+F: board/broadcom/bcmnsp/
+F: configs/bcmnsp_defconfig
+F: include/configs/bcmnsp.h
--- /dev/null
+++ b/board/broadcom/bcmns/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+obj-y := ns.o
--- /dev/null
+++ b/board/broadcom/bcmns/ns.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Broadcom Northstar generic board set-up code
+ * Copyright (C) 2023 Linus Walleij <linus.walleij@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <init.h>
+#include <log.h>
+#include <ram.h>
+#include <serial.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/armv7m.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+ return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void)
+{
+ return fdtdec_setup_memory_banksize();
+}
+
+int board_late_init(void)
+{
+ /* LEDs etc can be initialized here */
+ return 0;
+}
+
+int board_init(void)
+{
+ return 0;
+}
+
+void reset_cpu(void)
+{
+}
+
+int print_cpuinfo(void)
+{
+ printf("BCMNS Northstar SoC\n");
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+
+int ft_board_setup(void *fdt, struct bd_info *bd)
+{
+ printf("Northstar board setup: DTB at 0x%08lx\n", (ulong)fdt);
+ return 0;
+}
+
--- /dev/null
+++ b/configs/bcmns_defconfig
@@ -0,0 +1,41 @@
+CONFIG_ARM=y
+CONFIG_TARGET_BCMNS=y
+CONFIG_TEXT_BASE=0x00008000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="ns-board"
+CONFIG_IDENT_STRING="Broadcom Northstar"
+CONFIG_SYS_LOAD_ADDR=0x00008000
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x00100000
+# CONFIG_BOOTSTD is not set
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Boot Northstar system in %d seconds\n"
+CONFIG_BOOTDELAY=1
+CONFIG_USE_BOOTCOMMAND=y
+CONFIG_BOOTCOMMAND="run bootcmd_dlink_dir8xxl"
+CONFIG_SYS_PROMPT="northstar> "
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_SEAMA=y
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_USE_HOSTNAME=y
+CONFIG_HOSTNAME="NS"
+CONFIG_CLK=y
+CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_RAW_NAND=y
+CONFIG_NAND_BRCMNAND=y
+CONFIG_SYS_NAND_ONFI_DETECTION=y
+CONFIG_CMD_NAND=y
+CONFIG_DM_SERIAL=y
+CONFIG_SYS_NS16550=y
+# CONFIG_NET is not set
+# CONFIG_EFI_LOADER is not set
--- a/doc/board/broadcom/index.rst
+++ b/doc/board/broadcom/index.rst
@@ -9,3 +9,4 @@ Broadcom
bcm7xxx
raspberrypi
+ northstar
--- /dev/null
+++ b/doc/board/broadcom/northstar.rst
@@ -0,0 +1,44 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. Copyright (C) 2023 Linus Walleij <linus.walleij@linaro.org>
+
+Broadcom Northstar Boards
+=========================
+
+This document describes how to use U-Boot on the Broadcom Northstar
+boards, comprised of the Cortex A9 ARM-based BCM470x and BCM5301x SoCs. These
+were introduced in 2012-2013 and some of them are also called StrataGX.
+
+Northstar is part of the iProc SoC family.
+
+A good overview of these boards can be found in Jon Mason's presentation
+"Enabling New Hardware in U-Boot" where the difference between Northstar
+and Northstar Plus and Northstar 2 (Aarch64) is addressed.
+
+The ROM in the Northstar SoC will typically look into NOR flash memory
+for a boot loader, and the way this works is undocumented. It should be
+possible to execute U-Boot as the first binary from the NOR flash but
+this usage path is unexplored. Please add information if you know more.
+
+D-Link Boards
+-------------
+
+When we use U-Boot with D-Link routers, the NOR flash has a boot loader
+and web server that can re-flash the bigger NAND flash memory for object
+code in the SEAMA format, so on these platforms U-Boot is converted into
+a SEAMA binary and installed in the SoC using the flash tool resident in
+the NOR flash. Details can be found in the OpenWrt project codebase.
+
+Configure
+---------
+
+.. code-block:: console
+
+ $ make CROSS_COMPILE=${CROSS_COMPILE} bcmns_defconfig
+
+Build
+-----
+
+.. code-block:: console
+
+ $ make CROSS_COMPILE=${CROSS_COMPILE}
+ $ ${CROSS_COMPILE}strip u-boot
--- /dev/null
+++ b/include/configs/bcmns.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __BCM_NS_H
+#define __BCM_NS_H
+
+#include <linux/sizes.h>
+
+/* Physical Memory Map */
+#define V2M_BASE 0x00000000
+#define PHYS_SDRAM_1 V2M_BASE
+
+#define CFG_SYS_SDRAM_BASE PHYS_SDRAM_1
+
+/* Called "periph_clk" in Linux, used by the global timer */
+#define CFG_SYS_HZ_CLOCK 500000000
+
+/* Called "iprocslow" in Linux */
+#define CFG_SYS_NS16550_CLK 125000000
+
+/* console configuration */
+#define CONSOLE_ARGS "console_args=console=ttyS0,115200n8\0"
+#define MAX_CPUS "max_cpus=maxcpus=2\0"
+#define EXTRA_ARGS "extra_args=earlycon=uart8250,mmio32,0x18000300\0"
+
+#define BASE_ARGS "${console_args} ${extra_args} ${pcie_args}" \
+ " ${max_cpus} ${log_level} ${reserved_mem}"
+#define SETBOOTARGS "setbootargs=setenv bootargs " BASE_ARGS "\0"
+
+#define KERNEL_LOADADDR_CFG \
+ "loadaddr=0x01000000\0" \
+ "dtb_loadaddr=0x02000000\0"
+
+/*
+ * Hardcoded for the only boards we support, if you add more
+ * boards, add a more clever bootcmd!
+ */
+#define NS_BOOTCMD "bootcmd_dlink_dir8xxl=seama 0x00fe0000; go 0x01000000"
+
+#define ARCH_ENV_SETTINGS \
+ CONSOLE_ARGS \
+ MAX_CPUS \
+ EXTRA_ARGS \
+ KERNEL_LOADADDR_CFG \
+ NS_BOOTCMD
+
+#define CFG_EXTRA_ENV_SETTINGS \
+ ARCH_ENV_SETTINGS
+
+#endif /* __BCM_NS_H */
package/boot/uboot-envtools/Makefile
浏览文件 @ 1b15cb21
......@@ -9,15 +9,15 @@ include $(TOPDIR)/rules.mk
PKG_NAME:=uboot-envtools
PKG_DISTNAME:=u-boot
PKG_VERSION:=2023.04
PKG_RELEASE:=1
PKG_VERSION:=2023.07.02
PKG_RELEASE:=2
PKG_SOURCE:=$(PKG_DISTNAME)-$(PKG_VERSION).tar.bz2
PKG_SOURCE_URL:= \
https://ftp.denx.de/pub/u-boot \
https://mirror.cyberbits.eu/u-boot \
ftp://ftp.denx.de/pub/u-boot
PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341
PKG_HASH:=6b6a48581c14abb0f95bd87c1af4d740922406d7b801002a9f94727fdde021d5
PKG_SOURCE_SUBDIR:=$(PKG_DISTNAME)-$(PKG_VERSION)
PKG_BUILD_DIR:=$(BUILD_DIR)/$(PKG_DISTNAME)-$(PKG_VERSION)
......@@ -45,18 +45,19 @@ define Package/uboot-envtools/description
endef
define Build/Configure
touch $(PKG_BUILD_DIR)/include/config.h
mkdir -p $(PKG_BUILD_DIR)/include/config
touch $(PKG_BUILD_DIR)/include/config/auto.conf
mkdir -p $(PKG_BUILD_DIR)/include/generated
touch $(PKG_BUILD_DIR)/include/generated/autoconf.h
$(call Build/Compile/Default,tools-only_defconfig)
endef
define Build/Compile
$(call Build/Compile/Default,envtools)
endef
# We need to override the ARCH passed by buildsystem as otherwise the defconfig
# for tools-only wont match and the includes for sandbox will be dropped
MAKE_FLAGS += \
ARCH="sandbox" \
TARGET_CFLAGS="$(TARGET_CFLAGS)" \
TARGET_LDFLAGS="$(TARGET_LDFLAGS)" \
no-dot-config-targets=envtools \
envtools
TARGET_LDFLAGS="$(TARGET_LDFLAGS)"
define Package/uboot-envtools/conffiles
/etc/config/ubootenv
......
package/boot/uboot-envtools/files/mediatek_filogic
浏览文件 @ 1b15cb21
......@@ -45,7 +45,7 @@ mercusys,mr90x-v1)
ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x20000" "1"
;;
netgear,wax220)
ubootenv_add_uci_config "/dev/mtd5" "0x0" "0x20000" "0x20000"
ubootenv_add_uci_config "/dev/mtd1" "0x0" "0x20000" "0x20000"
;;
xiaomi,mi-router-wr30u-112m-nmbm|\
xiaomi,mi-router-wr30u-stock|\
......@@ -71,6 +71,9 @@ zyxel,ex5601-t0)
local envdev=/dev/mtd$(find_mtd_index "u-boot-env")
ubootenv_add_uci_config "$envdev" "0x0" "0x20000" "0x40000" "2"
;;
zyxel,ex5700-telenor)
ubootenv_add_uci_config "/dev/ubootenv" "0x0" "0x4000" "0x4000" "1"
;;
esac
config_load ubootenv
......
package/boot/uboot-envtools/files/qualcommax_ipq807x
浏览文件 @ 1b15cb21
......@@ -9,6 +9,7 @@ board=$(board_name)
case "$board" in
dynalink,dl-wrx36|\
netgear,rax120v2|\
netgear,wax218)
idx="$(find_mtd_index 0:appsblenv)"
[ -n "$idx" ] && \
......
package/boot/uboot-envtools/patches/002-Revert-tools-env-use-run-to-store-lockfile.patch 0 → 100644
浏览文件 @ 1b15cb21
Revert "tools: env: use /run to store lockfile"
In OpenWRT we still use /var/lock as default location for lock files and
/run might not even exist. Revert the upstream change and restore the
previous default path.
This reverts upstream commit
https://source.denx.de/u-boot/u-boot/-/commit/aeb40f1166e072856f865d26d42a4bea1ec3a514
---
tools/env/fw_env_main.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tools/env/fw_env_main.c b/tools/env/fw_env_main.c
index 0b201b9e62..1d193bd437 100644
--- a/tools/env/fw_env_main.c
+++ b/tools/env/fw_env_main.c
@@ -73,7 +73,7 @@ void usage_printenv(void)
" -c, --config configuration file, default:" CONFIG_FILE "\n"
#endif
" -n, --noheader do not repeat variable name in output\n"
- " -l, --lock lock node, default:/run\n"
+ " -l, --lock lock node, default:/var/lock\n"
"\n");
}
@@ -88,7 +88,7 @@ void usage_env_set(void)
#ifdef CONFIG_FILE
" -c, --config configuration file, default:" CONFIG_FILE "\n"
#endif
- " -l, --lock lock node, default:/run\n"
+ " -l, --lock lock node, default:/var/lock\n"
" -s, --script batch mode to minimize writes\n"
"\n"
"Examples:\n"
@@ -206,7 +206,7 @@ int parse_setenv_args(int argc, char *argv[])
int main(int argc, char *argv[])
{
- char *lockname = "/run/" CMD_PRINTENV ".lock";
+ char *lockname = "/var/lock/" CMD_PRINTENV ".lock";
int lockfd = -1;
int retval = EXIT_SUCCESS;
char *_cmdname;
package/boot/uboot-mediatek/Makefile
浏览文件 @ 1b15cb21
......@@ -124,10 +124,34 @@ define U-Boot/mt7622_bananapi_bpi-r64-snand
DEPENDS:=+trusted-firmware-a-mt7622-snand-2ddr
endef
define U-Boot/mt7622_ubnt_unifi-6-lr
define U-Boot/mt7622_ubnt_unifi-6-lr-v1
NAME:=Ubiquiti UniFi 6 LR
UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr
BUILD_DEVICES:=ubnt_unifi-6-lr-v1-ubootmod ubnt_unifi-6-lr-v2-ubootmod
UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr-v1
BUILD_DEVICES:=ubnt_unifi-6-lr-v1-ubootmod
BUILD_SUBTARGET:=mt7622
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=nor
BL2_DDRBLOB:=2
DEPENDS:=+trusted-firmware-a-mt7622-nor-2ddr
FIP_COMPRESS:=1
endef
define U-Boot/mt7622_ubnt_unifi-6-lr-v2
NAME:=Ubiquiti UniFi 6 LR v2
UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr-v2
BUILD_DEVICES:=ubnt_unifi-6-lr-v2-ubootmod
BUILD_SUBTARGET:=mt7622
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=nor
BL2_DDRBLOB:=2
DEPENDS:=+trusted-firmware-a-mt7622-nor-2ddr
FIP_COMPRESS:=1
endef
define U-Boot/mt7622_ubnt_unifi-6-lr-v3
NAME:=Ubiquiti UniFi 6 LR v3
UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr-v3
BUILD_DEVICES:=ubnt_unifi-6-lr-v3-ubootmod
BUILD_SUBTARGET:=mt7622
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=nor
......@@ -324,61 +348,62 @@ endef
define U-Boot/mt7988_rfb-spim-nand
NAME:=MT7988 Reference Board
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=mediatek_mt7988a-rfb-nand
BUILD_DEVICES:=mediatek_mt7988a-rfb
UBOOT_CONFIG:=mt7988_rfb
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=spim-nand
BL2_SOC:=mt7988
BL2_DDRTYPE:=ddr4
DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ddr4
BL2_DDRTYPE:=comb
DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-comb
endef
define U-Boot/mt7988_rfb-snand
NAME:=MT7988 Reference Board
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=mediatek_mt7988a-rfb-nand
BUILD_DEVICES:=mediatek_mt7988a-rfb
UBOOT_CONFIG:=mt7988_rfb
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=snand
BL2_SOC:=mt7988
BL2_DDRTYPE:=ddr4
DEPENDS:=+trusted-firmware-a-mt7988-snand-ddr4
BL2_DDRTYPE:=comb
DEPENDS:=+trusted-firmware-a-mt7988-snand-comb
endef
define U-Boot/mt7988_rfb-nor
NAME:=MT7988 Reference Board
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=mediatek_mt7988a-rfb-nand
BUILD_DEVICES:=mediatek_mt7988a-rfb
UBOOT_CONFIG:=mt7988_rfb
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=nor
BL2_SOC:=mt7988
BL2_DDRTYPE:=ddr4
DEPENDS:=+trusted-firmware-a-mt7988-nor-ddr4
BL2_DDRTYPE:=comb
DEPENDS:=+trusted-firmware-a-mt7988-nor-comb
FIP_COMPRESS:=1
endef
define U-Boot/mt7988_rfb-emmc
NAME:=MT7988 Reference Board
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=mediatek_mt7988a-rfb-nand
BUILD_DEVICES:=mediatek_mt7988a-rfb
UBOOT_CONFIG:=mt7988_rfb
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=emmc
BL2_SOC:=mt7988
BL2_DDRTYPE:=ddr4
DEPENDS:=+trusted-firmware-a-mt7988-emmc-ddr4
BL2_DDRTYPE:=comb
DEPENDS:=+trusted-firmware-a-mt7988-emmc-comb
endef
define U-Boot/mt7988_rfb-sd
NAME:=MT7988 Reference Board
BUILD_SUBTARGET:=filogic
BUILD_DEVICES:=mediatek_mt7988a-rfb-nand
BUILD_DEVICES:=mediatek_mt7988a-rfb
UBOOT_CONFIG:=mt7988_sd_rfb
UBOOT_IMAGE:=u-boot.fip
BL2_BOOTDEV:=sdmmc
BL2_SOC:=mt7988
BL2_DDRTYPE:=ddr4
DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-ddr4
BL2_DDRTYPE:=comb
DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-comb
endef
UBOOT_TARGETS := \
......@@ -391,7 +416,9 @@ UBOOT_TARGETS := \
mt7622_bananapi_bpi-r64-snand \
mt7622_linksys_e8450 \
mt7622_rfb1 \
mt7622_ubnt_unifi-6-lr \
mt7622_ubnt_unifi-6-lr-v1 \
mt7622_ubnt_unifi-6-lr-v2 \
mt7622_ubnt_unifi-6-lr-v3 \
mt7623n_bpir2 \
mt7623a_unielec_u7623 \
mt7628_rfb \
......
package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch
浏览文件 @ 1b15cb21
......@@ -310,3 +310,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
switch (key) {
case BKEY_PLUS:
--- a/boot/bootflow_menu.c
+++ b/boot/bootflow_menu.c
@@ -231,7 +231,7 @@ int bootflow_menu_run(struct bootstd_pri
key = 0;
if (ichar) {
- key = bootmenu_conv_key(ichar);
+ key = bootmenu_conv_key(NULL, ichar, NULL);
if (key == BKEY_NONE)
key = ichar;
}
package/boot/uboot-mediatek/patches/101-29-board-mediatek-add-MT7988-reference-boards.patch
浏览文件 @ 1b15cb21
......@@ -411,7 +411,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+CONFIG_TARGET_MT7988=y
+CONFIG_DEBUG_UART_BASE=0x11000000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_DEBUG_UART=y
+# CONFIG_AUTOBOOT is not set
+CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
......@@ -497,7 +497,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
+CONFIG_TARGET_MT7988=y
+CONFIG_DEBUG_UART_BASE=0x11000000
+CONFIG_DEBUG_UART_CLOCK=40000000
+CONFIG_SYS_LOAD_ADDR=0x46000000
+CONFIG_SYS_LOAD_ADDR=0x50000000
+CONFIG_DEBUG_UART=y
+# CONFIG_AUTOBOOT is not set
+CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
......
package/boot/uboot-mediatek/patches/104-configs-set-CONFIG_LMB_MAX_REGIONS-64-for-MT7988-boards.patch 0 → 100644
浏览文件 @ 1b15cb21
From patchwork Mon Aug 21 19:38:23 2023
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X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
X-Patchwork-Id: 1823742
X-Patchwork-Delegate: trini@ti.com
Return-Path: <u-boot-bounces@lists.denx.de>
X-Original-To: incoming@patchwork.ozlabs.org
Delivered-To: patchwork-incoming@legolas.ozlabs.org
Date: Mon, 21 Aug 2023 20:38:23 +0100
From: Daniel Golle <daniel@makrotopia.org>
To: Sam Shih <sam.shih@mediatek.com>, Weijie Gao <weijie.gao@mediatek.com>,
Lorenzo Bianconi <lorenzo@kernel.org>, u-boot@lists.denx.de
Subject: [PATCH] configs: set CONFIG_LMB_MAX_REGIONS=64 for MT7988 boards
Message-ID:
<568a8030acf9056266b5c96055cea54f810496c9.1692646620.git.daniel@makrotopia.org>
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Similar to MT7981 and MT7986 also MT7988 can have a high number of
reserved-memory regions used by the various hardware offloading
subsystems.
Raise CONFIG_LMB_MAX_REGIONS to 64 to avoid errors when trying to boot
Linux with more then 6 reserved regions:
ERROR: reserving fdt memory region failed (addr=4f700000 size=240000 flags=4)
ERROR: reserving fdt memory region failed (addr=15194000 size=1000 flags=4)
ERROR: reserving fdt memory region failed (addr=15294000 size=1000 flags=4)
ERROR: reserving fdt memory region failed (addr=15394000 size=1000 flags=4)
ERROR: Failed to allocate 0xb161 bytes below 0x80000000.
device tree - allocation error
Fixes: bc4adc97cfb ("board: mediatek: add MT7988 reference boards")
Reported-by: Lorenzo Bianconi <lorenzo@kernel.org>
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
configs/mt7988_rfb_defconfig | 1 +
configs/mt7988_sd_rfb_defconfig | 1 +
2 files changed, 2 insertions(+)
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
@@ -81,3 +81,4 @@ CONFIG_MTK_SPIM=y
CONFIG_LZO=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
+CONFIG_LMB_MAX_REGIONS=64
--- a/configs/mt7988_sd_rfb_defconfig
+++ b/configs/mt7988_sd_rfb_defconfig
@@ -69,3 +69,4 @@ CONFIG_MTK_SPIM=y
CONFIG_LZO=y
CONFIG_HEXDUMP=y
# CONFIG_EFI_LOADER is not set
+CONFIG_LMB_MAX_REGIONS=64
package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch 0 → 100644
浏览文件 @ 1b15cb21
--- a/configs/mt7988_sd_rfb_defconfig
+++ b/configs/mt7988_sd_rfb_defconfig
@@ -12,6 +12,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_DEBUG_UART=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_GPIO_HOG=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_FIT=y
+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_SPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_NAND_BOOT=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb"
CONFIG_LOGLEVEL=7
@@ -22,15 +40,118 @@ CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-# CONFIG_CMD_ELF is not set
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_BOOTP=y
+CONFIG_CMD_BUTTON=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_ELF=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ENV_READMEM=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FDT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_PWM=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PING=y
+CONFIG_CMD_SF=y
CONFIG_CMD_SMC=y
+CONFIG_CMD_TFTPBOOT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
+CONFIG_CMD_UBIFS=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_UUID=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DM_MMC=y
+CONFIG_DM_MTD=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_USB=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_PARTITION_UUIDS=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SCSI=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PCI=y
+CONFIG_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
+# CONFIG_MTD_RAW_NAND is not set
+CONFIG_DM_PCI=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPI_NAND=y
+CONFIG_MTK_SPI_NAND_MTD=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_MTK=y
+CONFIG_LZO=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_RANDOM_UUID=y
+CONFIG_REGEX=y
+CONFIG_USB=y
+CONFIG_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_OFFSET_REDUND=0x440000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE_REDUND=0x40000
CONFIG_DOS_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
@@ -46,6 +167,9 @@ CONFIG_PROT_TCP=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
+CONFIG_MMC=y
+CONFIG_MMC_DEFAULT_DEV=1
+CONFIG_MMC_SUPPORTS_TUNING=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
@@ -12,6 +12,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000
CONFIG_DEBUG_UART_CLOCK=40000000
CONFIG_SYS_LOAD_ADDR=0x50000000
CONFIG_DEBUG_UART=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_CFB_CONSOLE_ANSI=y
+CONFIG_BOARD_LATE_INIT=y
+CONFIG_BUTTON=y
+CONFIG_BUTTON_GPIO=y
+CONFIG_GPIO_HOG=y
+CONFIG_CMD_ENV_FLAGS=y
+CONFIG_FIT=y
+CONFIG_FIT_ENABLE_SHA256_SUPPORT=y
+CONFIG_LED=y
+CONFIG_LED_BLINK=y
+CONFIG_LED_GPIO=y
+CONFIG_SPI_BOOT=y
+CONFIG_SD_BOOT=y
+CONFIG_NAND_BOOT=y
+CONFIG_BOOTSTD_DEFAULTS=y
+CONFIG_BOOTSTD_FULL=y
# CONFIG_AUTOBOOT is not set
CONFIG_DEFAULT_FDT_FILE="mt7988-rfb"
CONFIG_LOGLEVEL=7
@@ -22,15 +40,118 @@ CONFIG_SYS_PBSIZE=1049
# CONFIG_BOOTM_PLAN9 is not set
# CONFIG_BOOTM_RTEMS is not set
# CONFIG_BOOTM_VXWORKS is not set
-# CONFIG_CMD_ELF is not set
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_BOOTP=y
+CONFIG_CMD_BUTTON=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_CDP=y
+CONFIG_CMD_CPU=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_DM=y
+CONFIG_CMD_ELF=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_ECHO=y
+CONFIG_CMD_ENV_READMEM=y
+CONFIG_CMD_ERASEENV=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FDT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_CMD_FS_UUID=y
CONFIG_CMD_CLK=y
CONFIG_CMD_DM=y
CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_HASH=y
+CONFIG_CMD_ITEST=y
+CONFIG_CMD_LED=y
+CONFIG_CMD_LICENSE=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_CMD_NAND=y
+CONFIG_CMD_NAND_TRIMFFS=y
+CONFIG_CMD_PCI=y
+CONFIG_CMD_PSTORE=y
+CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_PXE=y
CONFIG_CMD_PWM=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
CONFIG_CMD_PING=y
+CONFIG_CMD_SF=y
CONFIG_CMD_SMC=y
+CONFIG_CMD_TFTPBOOT=y
+CONFIG_CMD_TFTPSRV=y
+CONFIG_CMD_UBI=y
+CONFIG_CMD_UBI_RENAME=y
+CONFIG_CMD_UBIFS=y
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_RARP=y
+CONFIG_CMD_SETEXPR=y
+CONFIG_CMD_SLEEP=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_SOURCE=y
+CONFIG_CMD_STRINGS=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_UUID=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DM_MMC=y
+CONFIG_DM_MTD=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_DM_USB=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MTK=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_PARTITION_UUIDS=y
+CONFIG_NETCONSOLE=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_SCSI=y
+CONFIG_PHY=y
+CONFIG_PHY_MTK_TPHY=y
+CONFIG_PCI=y
+CONFIG_MTD=y
+CONFIG_MTD_UBI_FASTMAP=y
+# CONFIG_MTD_RAW_NAND is not set
+CONFIG_DM_PCI=y
+CONFIG_PCIE_MEDIATEK=y
+CONFIG_PINCTRL_MT7988=y
+CONFIG_PRE_CONSOLE_BUFFER=y
+CONFIG_PRE_CON_BUF_ADDR=0x4007EF00
+CONFIG_RAM=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SPI_NAND=y
+CONFIG_MTK_SPI_NAND_MTD=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_WDT_MTK=y
+CONFIG_LZO=y
+CONFIG_ZSTD=y
+CONFIG_HEXDUMP=y
+CONFIG_RANDOM_UUID=y
+CONFIG_REGEX=y
+CONFIG_USB=y
+CONFIG_USB_HOST=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MTK=y
+CONFIG_USB_STORAGE=y
+CONFIG_OF_EMBED=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_ENV_OFFSET_REDUND=0x440000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_ENV_SIZE_REDUND=0x40000
CONFIG_DOS_PARTITION=y
CONFIG_EFI_PARTITION=y
CONFIG_PARTITION_TYPE_GUID=y
@@ -46,6 +167,9 @@ CONFIG_PROT_TCP=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_CLK=y
+CONFIG_MMC=y
+CONFIG_MMC_DEFAULT_DEV=1
+CONFIG_MMC_SUPPORTS_TUNING=y
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_MTK=y
CONFIG_MTD=y
package/boot/uboot-rockchip/Makefile
浏览文件 @ 1b15cb21
......@@ -66,6 +66,20 @@ define U-Boot/roc-cc-rk3328
firefly_roc-rk3328-cc
endef
define U-Boot/rock64-rk3328
$(U-Boot/rk3328/Default)
NAME:=Rock64
BUILD_DEVICES:= \
pine64_rock64
endef
define U-Boot/rock-pi-e-rk3328
$(U-Boot/rk3328/Default)
NAME:=ROCK Pi E
BUILD_DEVICES:= \
radxa_rock-pi-e
endef
# RK3399 boards
define U-Boot/rk3399/Default
......@@ -111,7 +125,9 @@ UBOOT_TARGETS := \
nanopi-r2s-rk3328 \
orangepi-r1-plus-rk3328 \
orangepi-r1-plus-lts-rk3328 \
roc-cc-rk3328
roc-cc-rk3328 \
rock64-rk3328 \
rock-pi-e-rk3328
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
......
package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-decl.h 0 → 100644
浏览文件 @ 1b15cb21
/*
* DO NOT MODIFY
*
* Declares externs for all device/uclass instances.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
/* driver declarations - these allow DM_DRIVER_GET() to be used */
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(ns16550_serial);
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
extern UCLASS_DRIVER(clk);
extern UCLASS_DRIVER(mmc);
extern UCLASS_DRIVER(ram);
extern UCLASS_DRIVER(serial);
extern UCLASS_DRIVER(syscon);
package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-plat.c 0 → 100644
浏览文件 @ 1b15cb21
/*
* DO NOT MODIFY
*
* Declares the U_BOOT_DRIVER() records and platform data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
/* Allow use of U_BOOT_DRVINFO() in this file */
#define DT_PLAT_C
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
/*
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
*
* idx driver_info driver
* --- -------------------- --------------------
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
* 1: dmc rockchip_rk3328_dmc
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
* 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc
* 4: serial_at_ff130000 ns16550_serial
* 5: syscon_at_ff100000 rockchip_rk3328_grf
* --- -------------------- --------------------
*/
/*
* Node /clock-controller@ff440000 index 0
* driver rockchip_rk3328_cru parent None
*/
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
.reg = {0xff440000, 0x1000},
.rockchip_grf = 0x38,
};
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
.name = "rockchip_rk3328_cru",
.plat = &dtv_clock_controller_at_ff440000,
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
.parent_idx = -1,
};
/*
* Node /dmc index 1
* driver rockchip_rk3328_dmc parent None
*/
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
0xff720000, 0x1000, 0xff798000, 0x1000},
.rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
0x10, 0x10, 0x0, 0x9028b189, 0x0, 0x21, 0x482, 0x15,
0x222, 0xff, 0x14d, 0x3, 0x1, 0x0, 0x0, 0x0,
0x43041001, 0x64, 0x28003b, 0xd0, 0x20053, 0xd4, 0x20000, 0xd8,
0x100, 0xdc, 0x3200000, 0xe0, 0x0, 0xe4, 0x90000, 0xf4,
0xf011f, 0x100, 0x7090b06, 0x104, 0x50209, 0x108, 0x3030407, 0x10c,
0x202006, 0x110, 0x3020204, 0x114, 0x3030202, 0x120, 0x903, 0x180,
0x800020, 0x184, 0x0, 0x190, 0x7010001, 0x198, 0x5001100, 0x1a0,
0xc0400003, 0x240, 0x6000604, 0x244, 0x201, 0x250, 0xf00, 0x490,
0x1, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xa, 0x28, 0x6, 0x2c,
0x0, 0x30, 0x5, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
0x77, 0x77, 0x79, 0x9},
};
U_BOOT_DRVINFO(dmc) = {
.name = "rockchip_rk3328_dmc",
.plat = &dtv_dmc,
.plat_size = sizeof(dtv_dmc),
.parent_idx = -1,
};
/*
* Node /mmc@ff500000 index 2
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
.bus_width = 0x4,
.cap_mmc_highspeed = true,
.cap_sd_highspeed = true,
.card_detect_delay = 0xc8,
.clocks = {
{0, {317}},
{0, {33}},
{0, {74}},
{0, {78}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xc, 0x4},
.max_frequency = 0x8f0d180,
.num_slots = 0x1,
.pinctrl_0 = {0x45, 0x46, 0x47, 0x48},
.pinctrl_names = "default",
.reg = {0xff500000, 0x4000},
.supports_sd = true,
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x49,
};
U_BOOT_DRVINFO(mmc_at_ff500000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff500000,
.plat_size = sizeof(dtv_mmc_at_ff500000),
.parent_idx = -1,
};
/*
* Node /mmc@ff520000 index 3
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = {
.bus_width = 0x8,
.cap_mmc_highspeed = true,
.clocks = {
{0, {319}},
{0, {35}},
{0, {76}},
{0, {80}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xe, 0x4},
.max_frequency = 0x8f0d180,
.mmc_hs200_1_8v = true,
.non_removable = true,
.num_slots = 0x1,
.pinctrl_0 = {0x4a, 0x4b, 0x4c, 0x0},
.pinctrl_names = "default",
.reg = {0xff520000, 0x4000},
.supports_emmc = true,
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x1c,
.vqmmc_supply = 0x1d,
};
U_BOOT_DRVINFO(mmc_at_ff520000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff520000,
.plat_size = sizeof(dtv_mmc_at_ff520000),
.parent_idx = -1,
};
/*
* Node /serial@ff130000 index 4
* driver ns16550_serial parent None
*/
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
.clock_frequency = 0x16e3600,
.clocks = {
{0, {40}},
{0, {212}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x6, 0x10, 0x7},
.interrupts = {0x0, 0x39, 0x4},
.pinctrl_0 = 0x24,
.pinctrl_names = "default",
.reg = {0xff130000, 0x100},
.reg_io_width = 0x4,
.reg_shift = 0x2,
};
U_BOOT_DRVINFO(serial_at_ff130000) = {
.name = "ns16550_serial",
.plat = &dtv_serial_at_ff130000,
.plat_size = sizeof(dtv_serial_at_ff130000),
.parent_idx = -1,
};
/*
* Node /syscon@ff100000 index 5
* driver rockchip_rk3328_grf parent None
*/
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
.reg = {0xff100000, 0x1000},
};
U_BOOT_DRVINFO(syscon_at_ff100000) = {
.name = "rockchip_rk3328_grf",
.plat = &dtv_syscon_at_ff100000,
.plat_size = sizeof(dtv_syscon_at_ff100000),
.parent_idx = -1,
};
package/boot/uboot-rockchip/src/of-platdata/rock-pi-e-rk3328/dt-structs-gen.h 0 → 100644
浏览文件 @ 1b15cb21
/*
* DO NOT MODIFY
*
* Defines the structs used to hold devicetree data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <stdbool.h>
#include <linux/libfdt.h>
struct dtd_ns16550_serial {
fdt32_t clock_frequency;
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0;
const char * pinctrl_names;
fdt64_t reg[2];
fdt32_t reg_io_width;
fdt32_t reg_shift;
};
struct dtd_rockchip_rk3288_dw_mshc {
fdt32_t bus_width;
bool cap_mmc_highspeed;
bool cap_sd_highspeed;
fdt32_t card_detect_delay;
struct phandle_1_arg clocks[4];
bool disable_wp;
fdt32_t fifo_depth;
fdt32_t interrupts[3];
fdt32_t max_frequency;
bool mmc_hs200_1_8v;
bool non_removable;
fdt32_t num_slots;
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
bool supports_emmc;
bool supports_sd;
bool u_boot_spl_fifo_mode;
fdt32_t vmmc_supply;
fdt32_t vqmmc_supply;
};
struct dtd_rockchip_rk3328_cru {
fdt64_t reg[2];
fdt32_t rockchip_grf;
};
struct dtd_rockchip_rk3328_dmc {
fdt64_t reg[12];
fdt32_t rockchip_sdram_params[196];
};
struct dtd_rockchip_rk3328_grf {
fdt64_t reg[2];
};
package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-decl.h 0 → 100644
浏览文件 @ 1b15cb21
/*
* DO NOT MODIFY
*
* Declares externs for all device/uclass instances.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <dm/device-internal.h>
#include <dm/uclass-internal.h>
/* driver declarations - these allow DM_DRIVER_GET() to be used */
extern U_BOOT_DRIVER(rockchip_rk3328_cru);
extern U_BOOT_DRIVER(rockchip_rk3328_dmc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(rockchip_rk3288_dw_mshc);
extern U_BOOT_DRIVER(ns16550_serial);
extern U_BOOT_DRIVER(rockchip_rk3328_spi);
extern U_BOOT_DRIVER(jedec_spi_nor);
extern U_BOOT_DRIVER(rockchip_rk3328_grf);
/* uclass driver declarations - needed for DM_UCLASS_DRIVER_REF() */
extern UCLASS_DRIVER(clk);
extern UCLASS_DRIVER(mmc);
extern UCLASS_DRIVER(ram);
extern UCLASS_DRIVER(serial);
extern UCLASS_DRIVER(spi_flash);
extern UCLASS_DRIVER(syscon);
package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-plat.c 0 → 100644
浏览文件 @ 1b15cb21
/*
* DO NOT MODIFY
*
* Declares the U_BOOT_DRIVER() records and platform data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
/* Allow use of U_BOOT_DRVINFO() in this file */
#define DT_PLAT_C
#include <common.h>
#include <dm.h>
#include <dt-structs.h>
/*
* driver_info declarations, ordered by 'struct driver_info' linker_list idx:
*
* idx driver_info driver
* --- -------------------- --------------------
* 0: clock_controller_at_ff440000 rockchip_rk3328_cru
* 1: dmc rockchip_rk3328_dmc
* 2: mmc_at_ff500000 rockchip_rk3288_dw_mshc
* 3: mmc_at_ff520000 rockchip_rk3288_dw_mshc
* 4: serial_at_ff130000 ns16550_serial
* 5: spi_at_ff190000 rockchip_rk3328_spi
* 6: spiflash_at_0 jedec_spi_nor
* 7: syscon_at_ff100000 rockchip_rk3328_grf
* --- -------------------- --------------------
*/
/*
* Node /clock-controller@ff440000 index 0
* driver rockchip_rk3328_cru parent None
*/
static struct dtd_rockchip_rk3328_cru dtv_clock_controller_at_ff440000 = {
.reg = {0xff440000, 0x1000},
.rockchip_grf = 0x3b,
};
U_BOOT_DRVINFO(clock_controller_at_ff440000) = {
.name = "rockchip_rk3328_cru",
.plat = &dtv_clock_controller_at_ff440000,
.plat_size = sizeof(dtv_clock_controller_at_ff440000),
.parent_idx = -1,
};
/*
* Node /dmc index 1
* driver rockchip_rk3328_dmc parent None
*/
static struct dtd_rockchip_rk3328_dmc dtv_dmc = {
.reg = {0xff400000, 0x1000, 0xff780000, 0x3000, 0xff100000, 0x1000, 0xff440000, 0x1000,
0xff720000, 0x1000, 0xff798000, 0x1000},
.rockchip_sdram_params = {0x1, 0xc, 0x3, 0x1, 0x0, 0x0, 0x10, 0x10,
0x10, 0x10, 0x0, 0x98899459, 0x0, 0x2e, 0x544, 0x15,
0x432, 0xff, 0x320, 0x6, 0x1, 0x0, 0x1, 0x0,
0x43041008, 0x64, 0x300054, 0xd0, 0x500002, 0xd4, 0x10000, 0xd8,
0xe03, 0xdc, 0x43001a, 0xe0, 0x10000, 0xe4, 0xe0005, 0xf4,
0xf011f, 0x100, 0xb141b11, 0x104, 0x3031a, 0x108, 0x3060809, 0x10c,
0x606000, 0x110, 0x8020409, 0x114, 0x1010606, 0x118, 0x2020004, 0x120,
0x404, 0x138, 0x58, 0x180, 0x900024, 0x184, 0x1400000, 0x190,
0x7050002, 0x198, 0x5001100, 0x1a0, 0xc0400003, 0x240, 0xa020b28, 0x244,
0x101, 0x250, 0xf00, 0x490, 0x1, 0xffffffff, 0xffffffff, 0xffffffff,
0xffffffff, 0xffffffff, 0xffffffff, 0x4, 0xb, 0x28, 0xc, 0x2c,
0x0, 0x30, 0x6, 0xffffffff, 0xffffffff, 0x77, 0x88, 0x79,
0x79, 0x87, 0x97, 0x87, 0x78, 0x77, 0x78, 0x87,
0x88, 0x87, 0x87, 0x77, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x69, 0x9, 0x77,
0x78, 0x77, 0x78, 0x77, 0x78, 0x77, 0x78, 0x77,
0x79, 0x9, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x78, 0x78, 0x69, 0x9, 0x77, 0x78, 0x77,
0x77, 0x77, 0x77, 0x77, 0x77, 0x77, 0x79, 0x9,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78,
0x78, 0x69, 0x9, 0x77, 0x78, 0x77, 0x78, 0x77,
0x78, 0x77, 0x78, 0x77, 0x79, 0x9, 0x78, 0x78,
0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x78, 0x69,
0x9, 0x77, 0x78, 0x77, 0x77, 0x77, 0x77, 0x77,
0x77, 0x77, 0x79, 0x9},
};
U_BOOT_DRVINFO(dmc) = {
.name = "rockchip_rk3328_dmc",
.plat = &dtv_dmc,
.plat_size = sizeof(dtv_dmc),
.parent_idx = -1,
};
/*
* Node /mmc@ff500000 index 2
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff500000 = {
.bus_width = 0x4,
.cap_mmc_highspeed = true,
.cap_sd_highspeed = true,
.clocks = {
{0, {317}},
{0, {33}},
{0, {74}},
{0, {78}},},
.disable_wp = true,
.fifo_depth = 0x100,
.interrupts = {0x0, 0xc, 0x4},
.max_frequency = 0x8f0d180,
.pinctrl_0 = {0x4a, 0x4b, 0x4c, 0x4d},
.pinctrl_names = "default",
.reg = {0xff500000, 0x4000},
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x4e,
};
U_BOOT_DRVINFO(mmc_at_ff500000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff500000,
.plat_size = sizeof(dtv_mmc_at_ff500000),
.parent_idx = -1,
};
/*
* Node /mmc@ff520000 index 3
* driver rockchip_rk3288_dw_mshc parent None
*/
static struct dtd_rockchip_rk3288_dw_mshc dtv_mmc_at_ff520000 = {
.bus_width = 0x8,
.cap_mmc_highspeed = true,
.clocks = {
{0, {319}},
{0, {35}},
{0, {76}},
{0, {80}},},
.fifo_depth = 0x100,
.interrupts = {0x0, 0xe, 0x4},
.max_frequency = 0x8f0d180,
.mmc_hs200_1_8v = true,
.non_removable = true,
.pinctrl_0 = {0x4f, 0x50, 0x51, 0x0},
.pinctrl_names = "default",
.reg = {0xff520000, 0x4000},
.u_boot_spl_fifo_mode = true,
.vmmc_supply = 0x1e,
.vqmmc_supply = 0x1f,
};
U_BOOT_DRVINFO(mmc_at_ff520000) = {
.name = "rockchip_rk3288_dw_mshc",
.plat = &dtv_mmc_at_ff520000,
.plat_size = sizeof(dtv_mmc_at_ff520000),
.parent_idx = -1,
};
/*
* Node /serial@ff130000 index 4
* driver ns16550_serial parent None
*/
static struct dtd_ns16550_serial dtv_serial_at_ff130000 = {
.clock_frequency = 0x16e3600,
.clocks = {
{0, {40}},
{0, {212}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x6, 0x10, 0x7},
.interrupts = {0x0, 0x39, 0x4},
.pinctrl_0 = 0x27,
.pinctrl_names = "default",
.reg = {0xff130000, 0x100},
.reg_io_width = 0x4,
.reg_shift = 0x2,
};
U_BOOT_DRVINFO(serial_at_ff130000) = {
.name = "ns16550_serial",
.plat = &dtv_serial_at_ff130000,
.plat_size = sizeof(dtv_serial_at_ff130000),
.parent_idx = -1,
};
/* Node /spi@ff190000 index 5 */
static struct dtd_rockchip_rk3328_spi dtv_spi_at_ff190000 = {
.clocks = {
{0, {32}},
{0, {209}},},
.dma_names = {"tx", "rx"},
.dmas = {0x10, 0x8, 0x10, 0x9},
.interrupts = {0x0, 0x31, 0x4},
.pinctrl_0 = {0x2f, 0x30, 0x31, 0x32},
.pinctrl_names = "default",
.reg = {0xff190000, 0x1000},
};
U_BOOT_DRVINFO(spi_at_ff190000) = {
.name = "rockchip_rk3328_spi",
.plat = &dtv_spi_at_ff190000,
.plat_size = sizeof(dtv_spi_at_ff190000),
.parent_idx = -1,
};
/*
* Node /spi@ff190000/spiflash@0 index 6
* driver jedec_spi_nor parent None
*/
static struct dtd_jedec_spi_nor dtv_spiflash_at_0 = {
.reg = {0x0},
.spi_max_frequency = 0x2faf080,
};
U_BOOT_DRVINFO(spiflash_at_0) = {
.name = "jedec_spi_nor",
.plat = &dtv_spiflash_at_0,
.plat_size = sizeof(dtv_spiflash_at_0),
.parent_idx = 5,
};
/*
* Node /syscon@ff100000 index 7
* driver rockchip_rk3328_grf parent None
*/
static struct dtd_rockchip_rk3328_grf dtv_syscon_at_ff100000 = {
.reg = {0xff100000, 0x1000},
};
U_BOOT_DRVINFO(syscon_at_ff100000) = {
.name = "rockchip_rk3328_grf",
.plat = &dtv_syscon_at_ff100000,
.plat_size = sizeof(dtv_syscon_at_ff100000),
.parent_idx = -1,
};
package/boot/uboot-rockchip/src/of-platdata/rock64-rk3328/dt-structs-gen.h 0 → 100644
浏览文件 @ 1b15cb21
/*
* DO NOT MODIFY
*
* Defines the structs used to hold devicetree data.
* This was generated by dtoc from a .dtb (device tree binary) file.
*/
#include <stdbool.h>
#include <linux/libfdt.h>
struct dtd_jedec_spi_nor {
fdt32_t reg[1];
fdt32_t spi_max_frequency;
};
struct dtd_ns16550_serial {
fdt32_t clock_frequency;
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0;
const char * pinctrl_names;
fdt64_t reg[2];
fdt32_t reg_io_width;
fdt32_t reg_shift;
};
struct dtd_rockchip_rk3288_dw_mshc {
fdt32_t bus_width;
bool cap_mmc_highspeed;
bool cap_sd_highspeed;
struct phandle_1_arg clocks[4];
bool disable_wp;
fdt32_t fifo_depth;
fdt32_t interrupts[3];
fdt32_t max_frequency;
bool mmc_hs200_1_8v;
bool non_removable;
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
bool u_boot_spl_fifo_mode;
fdt32_t vmmc_supply;
fdt32_t vqmmc_supply;
};
struct dtd_rockchip_rk3328_cru {
fdt64_t reg[2];
fdt32_t rockchip_grf;
};
struct dtd_rockchip_rk3328_dmc {
fdt64_t reg[12];
fdt32_t rockchip_sdram_params[196];
};
struct dtd_rockchip_rk3328_grf {
fdt64_t reg[2];
};
struct dtd_rockchip_rk3328_spi {
struct phandle_1_arg clocks[2];
const char * dma_names[2];
fdt32_t dmas[4];
fdt32_t interrupts[3];
fdt32_t pinctrl_0[4];
const char * pinctrl_names;
fdt64_t reg[2];
};
package/boot/uboot-sunxi/Makefile
浏览文件 @ 1b15cb21
......@@ -9,9 +9,9 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2020.07
PKG_VERSION:=2023.04
PKG_HASH:=c1f5bf9ee6bb6e648edbf19ce2ca9452f614b08a9f886f1a566aa42e8cf05f6a
PKG_HASH:=e31cac91545ff41b71cec5d8c22afd695645cd6e2a442ccdacacd60534069341
PKG_MAINTAINER:=Zoltan HERPAI <wigyori@uid0.hu>
......@@ -392,7 +392,7 @@ UBOOT_TARGETS := \
UBOOT_CONFIGURE_VARS += USE_PRIVATE_LIBGCC=yes
UBOOT_MAKE_FLAGS += \
BL31=$(STAGING_DIR_IMAGE)/bl31_sunxi-$(ATF).bin
BL31=$(STAGING_DIR_IMAGE)/bl31_sunxi-$(ATF).bin SCP=/dev/null
define Build/InstallDev
$(INSTALL_DIR) $(STAGING_DIR_IMAGE)
......
package/boot/uboot-sunxi/patches/003-add-theobroma-a31-pangolin.patch 已删除 100644 → 0
浏览文件 @ 497012ab
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -475,6 +475,7 @@ dtb-$(CONFIG_MACH_SUN6I) += \
sun6i-a31-m9.dtb \
sun6i-a31-mele-a1000g-quad.dtb \
sun6i-a31-mixtile-loftq.dtb \
+ sun6i-a31-pangolin.dtb \
sun6i-a31s-colorfly-e708-q1.dtb \
sun6i-a31s-cs908.dtb \
sun6i-a31s-inet-q972.dtb \
--- a/arch/arm/dts/sun6i-a31.dtsi
+++ b/arch/arm/dts/sun6i-a31.dtsi
@@ -641,6 +641,11 @@
function = "lcd0";
};
+ i2c3_pins_a: i2c3@0 {
+ allwinner,pins = "PB5", "PB6";
+ allwinner,function = "i2c3";
+ };
+
mmc0_pins_a: mmc0@0 {
pins = "PF0", "PF1", "PF2",
"PF3", "PF4", "PF5";
--- /dev/null
+++ b/arch/arm/dts/sun6i-a31-pangolin.dts
@@ -0,0 +1,292 @@
+/*
+ * Copyright 2015, Theobroma Systems Design und Consulting GmbH
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun6i-a31.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Theobroma Systems A31 Pangolin";
+ compatible = "tsd,a31-pangolin", "allwinner,sun6i-a31";
+
+ aliases {
+ serial0 = &uart0;
+ serial2 = &uart2;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ };
+
+ chosen {
+ stdout-path = "serial2:115200n8";
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+&ohci0 {
+ status = "okay";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&gmac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac_pins_rgmii_a>;
+ phy = <&phy1>;
+ phy-mode = "rgmii";
+ snps,reset-gpio = <&pio 0 7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 10000 30000>;
+ status = "okay";
+
+ phy1: ethernet-phy@4 {
+ reg = <4>;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins_a>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins_a>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins_a>;
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_pins_a>;
+ status = "okay";
+
+ rtc_twi: rtc@6f {
+ compatible = "isil,isl1208";
+ reg = <0x6f>;
+ };
+ fan: fan@18 {
+ compatible = "ti,amc6821";
+ reg = <0x18>;
+ cooling-min-state = <0>;
+ cooling-max-state = <9>;
+ #cooling-cells = <2>;
+ };
+};
+
+&spi0 {
+ status = "okay";
+
+ flash: flash@0 {
+ compatible = "spansion,m25p40";
+ spi-max-frequency = <16000000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&ir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ir_pins_a>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_pangolin>;
+ vmmc-supply = <&reg_vcc3v0>;
+ bus-width = <4>;
+ cd-gpios = <&pio 2 19 GPIO_ACTIVE_LOW>; /* PC19 */
+ status = "okay";
+};
+
+&mmc0_pins_a {
+ /* external pull-ups missing for some pins */
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <&reg_vcc3v0>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&pio {
+ mmc0_cd_pin_pangolin: mmc0_cd_pin@0 {
+ allwinner,pins = "PC19";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
+ };
+
+ leds_pins_pangolin: led_pins@0 {
+ allwinner,pins = "PH7", "PC16";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_20_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ mmc2_pins_a: mmc2@0 {
+ allwinner,pins = "PC6","PC7","PC8","PC9","PC10","PC11",
+ "PC12","PC13","PC14","PC15";
+ allwinner,function = "mmc2";
+ allwinner,drive = <SUN4I_PINCTRL_30_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&p2wi {
+ status = "okay";
+
+ axp221: pmic@68 {
+ compatible = "x-powers,axp221";
+ reg = <0x68>;
+ interrupt-parent = <&nmi_intc>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ dcdc1-supply = <&vcc_3v0>;
+ dcdc5-supply = <&vcc_dram>;
+
+ regulators {
+ x-powers,dcdc-freq = <3000>;
+
+ vcc_3v0: dcdc1 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "vcc-3v0";
+ };
+
+ vdd_cpu: dcdc2 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-cpu";
+ };
+
+ vdd_gpu: dcdc3 {
+ regulator-always-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-name = "vdd-gpu";
+ };
+
+ vdd_sys_dll: dcdc4 {
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-name = "vdd-sys-dll";
+ };
+
+ vcc_dram: dcdc5 {
+ regulator-always-on;
+ regulator-min-microvolt = <1500000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vcc-dram";
+ };
+
+ vcc_wifi: aldo1 {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc_wifi";
+ };
+
+ avcc: aldo3 {
+ regulator-always-on;
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ regulator-name = "avcc";
+ };
+ };
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usb1_vbus_pin_a {
+ allwinner,pins = "PD23";
+};
+
+&reg_usb1_vbus {
+ gpio = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD 23 */
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+ usb1_vbus-supply = <&reg_usb1_vbus>;
+};
--- /dev/null
+++ b/configs/pangolin_defconfig
@@ -0,0 +1,36 @@
+CONFIG_SUNXI_PANGOLIN=y
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="USB_EHCI,SUNXI_GMAC,RGMII"
+CONFIG_DEFAULT_DEVICE_TREE="sun6i-a31-pangolin"
+CONFIG_VIDEO_VGA_VIA_LCD=y
+CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25"
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_MACH_SUN6I=y
+CONFIG_DRAM_CHANNELS=1
+CONFIG_DRAM_CLK=360
+CONFIG_DRAM_ZQ=70
+CONFIG_AXP_DCDC1_VOLT=3300
+CONFIG_AXP_ALDO1_VOLT=0
+CONFIG_AXP_ALDO2_VOLT=1800
+CONFIG_AXP_ALDO3_VOLT=3000
+CONFIG_AXP_DLDO4_VOLT=3300
+CONFIG_AXP_ELDO1_VOLT=1200
+CONFIG_AXP_ELDO2_VOLT=2500
+CONFIG_AXP_ELDO3_VOLT=3300
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+CONFIG_CONS_INDEX=3
+# Vbus gpio for usb1
+CONFIG_USB1_VBUS_PIN=""
+# No Vbus gpio for usb2
+CONFIG_USB2_VBUS_PIN=""
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_EHCI=y
+CONFIG_USB_KEYBOARD=y
+CONFIG_DM_ETH=y
+CONFIG_CMD_IMLS=n
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_DM_SPI=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SUNXI_SPI=y
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -896,6 +896,14 @@ config VIDEO_LCD_PANEL_I2C_SCL
Set the SCL pin for the LCD i2c interface. This takes a string in the
format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
+choice
+ prompt "Sunxi Board Variant"
+ optional
+
+config SUNXI_PANGOLIN
+ bool "Theobroma A31 uQ7 Board"
+
+endchoice
# Note only one of these may be selected at a time! But hidden choices are
# not supported by Kconfig
package/boot/uboot-sunxi/patches/062-A20-improve-gmac-upload.patch
浏览文件 @ 1b15cb21
......@@ -2,7 +2,7 @@
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -23,6 +23,7 @@ CONFIG_ETH_DESIGNWARE=y
@@ -26,6 +26,7 @@ CONFIG_ETH_DESIGNWARE=y
CONFIG_RGMII=y
CONFIG_MII=y
CONFIG_SUN7I_GMAC=y
......
package/boot/uboot-sunxi/patches/063-fix-lime2-revK-add-micrel-PHY.patch 已删除 100644 → 0
浏览文件 @ 497012ab
--- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig
+++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig
@@ -8,6 +8,8 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SATAPWR="PC3"
CONFIG_SPL_SPI_SUNXI=y
CONFIG_AHCI=y
--- a/configs/A20-OLinuXino-Lime2_defconfig
+++ b/configs/A20-OLinuXino-Lime2_defconfig
@@ -7,6 +7,8 @@ CONFIG_MMC0_CD_PIN="PH1"
CONFIG_USB0_VBUS_PIN="PC17"
CONFIG_USB0_VBUS_DET="PH5"
CONFIG_I2C1_ENABLE=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_SATAPWR="PC3"
CONFIG_AHCI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
--- a/drivers/net/phy/micrel_ksz90x1.c
+++ b/drivers/net/phy/micrel_ksz90x1.c
@@ -14,6 +14,8 @@
#include <errno.h>
#include <micrel.h>
#include <phy.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
/*
* KSZ9021 - KSZ9031 common
@@ -344,6 +346,10 @@ static int ksz9031_phy_extwrite(struct p
static int ksz9031_config(struct phy_device *phydev)
{
int ret;
+ struct sunxi_ccm_reg *const ccm =
+ (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+
+ setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_DELAY(4));
ret = ksz9031_of_config(phydev);
if (ret)
package/boot/uboot-sunxi/patches/091-sun6i-sync-PLL1-multdiv-with-Boot1.patch
浏览文件 @ 1b15cb21
......@@ -14,7 +14,7 @@ More specifically, the following settings are now used:
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -114,11 +114,12 @@ void clock_set_pll1(unsigned int clk)
@@ -131,11 +131,12 @@ void clock_set_pll1(unsigned int clk)
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
const int p = 0;
......
package/boot/uboot-sunxi/patches/093-sun6i-fix-PLL-LDO-voltselect.patch
浏览文件 @ 1b15cb21
......@@ -18,7 +18,7 @@ required setting for the PLL LDO is 1.37v as per the A31 manual.
--- a/arch/arm/mach-sunxi/clock_sun6i.c
+++ b/arch/arm/mach-sunxi/clock_sun6i.c
@@ -27,13 +27,26 @@ void clock_init_safe(void)
@@ -28,13 +28,26 @@ void clock_init_safe(void)
struct sunxi_prcm_reg * const prcm =
(struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
......@@ -47,8 +47,8 @@ required setting for the PLL LDO is 1.37v as per the A31 manual.
#endif
#if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
--- a/arch/arm/include/asm/arch-sunxi/prcm.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm.h
--- a/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/prcm_sun6i.h
@@ -110,13 +110,13 @@
#define PRCM_PLL_CTRL_LDO_OUT_MASK \
__PRCM_PLL_CTRL_LDO_OUT(0x7)
......
package/boot/uboot-sunxi/patches/100-sun6i-alternate-on-UART2.patch 已删除 100644 → 0
浏览文件 @ 497012ab
From d7311b6e7cdd1fc0e92665188e650934718cb2b1 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 16 Jun 2015 10:52:01 +0200
Subject: sun6i: define alternate-function for UART2 on GPG
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -190,6 +190,7 @@ enum sunxi_gpio_number {
#define SUN6I_GPG_SDC1 2
#define SUN8I_GPG_SDC1 2
#define SUN6I_GPG_TWI3 2
+#define SUN6I_GPG_UART2 2
#define SUN5I_GPG_UART1 4
#define SUN6I_GPH_PWM 2
package/boot/uboot-sunxi/patches/101-sun6i-support-console-on-UART2.patch 已删除 100644 → 0
浏览文件 @ 497012ab
From c058dfb69136d62f88ae8b121104bdb7ce2df03f Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 16 Jun 2015 10:53:11 +0200
Subject: ARM: sun6i: Support console on UART2 (GPG6/GPG7)
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -132,6 +132,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN6I)
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(6), SUN6I_GPG_UART2);
+ sunxi_gpio_set_cfgpin(SUNXI_GPG(7), SUN6I_GPG_UART2);
+ sunxi_gpio_set_pull(SUNXI_GPG(7), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
--- a/include/configs/sunxi-common.h
+++ b/include/configs/sunxi-common.h
@@ -244,6 +244,8 @@ extern int soft_i2c_gpio_scl;
#endif
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28400:115200"
+#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN6I)
+#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200"
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
#define OF_STDOUT_PATH "/soc@01c00000/serial@01c28800:115200"
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
package/boot/uboot-sunxi/patches/102-sunxi-make_CONS_INDEX-configurable.patch 已删除 100644 → 0
浏览文件 @ 497012ab
From 78d5fab8e345b1273ec8c22d06f1a1d27670b518 Mon Sep 17 00:00:00 2001
From: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Date: Tue, 16 Jun 2015 10:59:38 +0200
Subject: ARM: sunxi: Make CONS_INDEX configurable
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -559,6 +559,14 @@ config SYS_BOARD
config SYS_SOC
default "sunxi"
+config CONS_INDEX
+ int "UART used for console"
+ range 1 5
+ default 1
+ ---help---
+ Defines the UART port used for serial output. It starts at 1 so UART0 is 1,
+ UART1 is 2 and so on.
+
config UART0_PORT_F
bool "UART0 on MicroSD breakout board"
default n
package/boot/uboot-sunxi/patches/200-mkimage-check-environment-for-dtc-binary-location.patch
浏览文件 @ 1b15cb21
......@@ -17,7 +17,7 @@ Cc: Simon Glass <sjg@chromium.org>
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -751,9 +751,14 @@ static int fit_handle_file(struct image_
@@ -754,9 +754,14 @@ static int fit_handle_file(struct image_
}
*cmd = '\0';
} else if (params->datafile) {
......
package/boot/uboot-sunxi/patches/210-sunxi-deactivate-binman.patch 已删除 100644 → 0
浏览文件 @ 497012ab
From def280c4792262a368c8861312dc6b376181021f Mon Sep 17 00:00:00 2001
From: Hauke Mehrtens <hauke@hauke-m.de>
Date: Mon, 1 Jan 2018 23:10:56 +0100
Subject: sunxi: deactivate binman
Use the old way to generate the images instead of binman.
binman needs python with swig to avoid this host tool dependency use the
old way of generating images.
---
Makefile | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
--- a/Makefile
+++ b/Makefile
@@ -1607,8 +1607,10 @@ endif
ifneq ($(CONFIG_ARCH_SUNXI),)
ifeq ($(CONFIG_ARM64),)
-u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img u-boot.dtb FORCE
- $(call if_changed,binman)
+OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \
+ --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff
+u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE
+ $(call if_changed,pad_cat)
else
u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.itb FORCE
$(call if_changed,cat)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -995,7 +995,6 @@ config ARCH_SOCFPGA
config ARCH_SUNXI
bool "Support sunxi (Allwinner) SoCs"
- select BINMAN
select CMD_GPIO
select CMD_MMC if MMC
select CMD_USB if DISTRO_DEFAULTS
package/boot/uboot-sunxi/patches/230-disable-axp209-on-a13-olinuxino.diff 已删除 100644 → 0
浏览文件 @ 497012ab
--- a/configs/A13-OLinuXino_defconfig
+++ b/configs/A13-OLinuXino_defconfig
@@ -7,7 +7,6 @@ CONFIG_DRAM_EMR1=0
CONFIG_MMC0_CD_PIN="PG0"
CONFIG_USB0_VBUS_DET="PG1"
CONFIG_USB1_VBUS_PIN="PG11"
-CONFIG_AXP_GPIO=y
# CONFIG_VIDEO_HDMI is not set
CONFIG_VIDEO_VGA_VIA_LCD=y
CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y
@@ -20,7 +19,7 @@ CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_DEFAULT_DEVICE_TREE="sun5i-a13-olinuxino"
CONFIG_DFU_RAM=y
CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
-CONFIG_AXP_ALDO3_VOLT=3300
+CONFIG_SUNXI_NO_PMIC=y
CONFIG_CONS_INDEX=2
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_OHCI_HCD=y
package/boot/uboot-sunxi/patches/250-sun8i-h3-add-support-for-zeropi.patch 已删除 100644 → 0
浏览文件 @ 497012ab
From 2527b24f39d8f27ba2fd922ca27a1f14119cfa1b Mon Sep 17 00:00:00 2001
From: Yu-Tung Chang <mtwget@gmail.com>
Date: Sat, 19 Jun 2021 16:16:45 +0800
Subject: [PATCH] sunxi: h3: Add initial ZeroPi support
ZeroPi is a new board of high performance with low cost
designed by FriendlyElec., using the Allwinner H3 SOC.
ZeroPi features
- Allwinner H3, Quad-core Cortex-A7@1.2GHz
- 256MB/512MB DDR3 RAM
- microsd slot
- 10/100/1000Mbps Ethernet
- Debug Serial Port
- DC 5V/2A power-supply
Signed-off-by: Yu-Tung Chang <mtwget@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
---
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -560,7 +560,8 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-orangepi-plus.dtb \
sun8i-h3-orangepi-plus2e.dtb \
sun8i-h3-orangepi-zero-plus2.dtb \
- sun8i-h3-rervision-dvk.dtb
+ sun8i-h3-rervision-dvk.dtb \
+ sun8i-h3-zeropi.dtb
dtb-$(CONFIG_MACH_SUN8I_R40) += \
sun8i-r40-bananapi-m2-ultra.dtb \
sun8i-v40-bananapi-m2-berry.dtb
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-zeropi.dts
@@ -0,0 +1,85 @@
+/*
+ * Copyright (C) 2020 Yu-Tung Chang <mtwget@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyARM ZeroPi";
+ compatible = "friendlyarm,zeropi", "allwinner,sun8i-h3";
+
+ aliases {
+ ethernet0 = &emac;
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; /* PD6 */
+ };
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+
+ allwinner,leds-active-low;
+ status = "okay";
+};
+
+&usb_otg {
+ status = "okay";
+ dr_mode = "host";
+};
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -508,3 +508,9 @@ YONES TOPTECH BS1078 V2 BOARD
M: Peter Korsgaard <peter@korsgaard.com>
S: Maintained
F: configs/Yones_Toptech_BS1078_V2_defconfig
+
+ZEROPI BOARD
+M: Yu-Tung Chang <mtwget@gmail.com>
+S: Maintained
+F: configs/zeropi_defconfig
+F: arch/arm/dts/sun8i-h3-zeropi.dts
--- /dev/null
+++ b/configs/zeropi_defconfig
@@ -0,0 +1,13 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_DEFAULT_DEVICE_TREE="sun8i-h3-zeropi"
+CONFIG_SPL=y
+CONFIG_MACH_SUN8I_H3=y
+CONFIG_DRAM_CLK=408
+CONFIG_MACPWR="PD6"
+# CONFIG_VIDEO_DE2 is not set
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_CONSOLE_MUX=y
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
package/boot/uboot-sunxi/patches/252-sunxi-h3-add-support-for-nanopi-r1.patch
浏览文件 @ 1b15cb21
......@@ -12,165 +12,6 @@ Signed-off-by: Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
create mode 100644 arch/arm/dts/sun8i-h3-nanopi-r1.dts
create mode 100644 configs/nanopi_r1_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -551,6 +551,7 @@ dtb-$(CONFIG_MACH_SUN8I_H3) += \
sun8i-h3-nanopi-m1-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-nanopi-neo-air.dtb \
+ sun8i-h3-nanopi-r1.dtb \
sun8i-h3-orangepi-2.dtb \
sun8i-h3-orangepi-lite.dtb \
sun8i-h3-orangepi-one.dtb \
--- /dev/null
+++ b/arch/arm/dts/sun8i-h3-nanopi-r1.dts
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Igor Pecovnik <igor@armbian.com>
+ * Copyright (C) 2020 Jayantajit Gogoi <jayanta.gogoi525@gmail.com>
+ */
+
+/* NanoPi R1 is based on the NanoPi-H3 design from FriendlyARM */
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyARM NanoPi R1";
+ compatible = "friendlyarm,nanopi-r1", "allwinner,sun8i-h3";
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ pinctrl-names = "default";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>;
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <1100000 0x0
+ 1300000 0x1>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ pinctrl-names = "default";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
+ };
+
+ leds {
+ /delete-node/ pwr;
+ status {
+ label = "nanopi:red:status";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ wan {
+ label = "nanopi:green:wan";
+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+
+ lan {
+ label = "nanopi:green:lan";
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r_gpio_keys {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_npi>;
+
+ /delete-node/ k1;
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ sdio_wifi: sdio_wifi@1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ interrupt-parent = <&pio>;
+ interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_8bit_pins>;
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ bus-width = <8>;
+ non-removable;
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&r_pio {
+ sw_r_npi: key_pins {
+ pins = "PL3";
+ function = "gpio_in";
+ };
+};
--- /dev/null
+++ b/configs/nanopi_r1_defconfig
@@ -0,0 +1,21 @@
......
package/boot/uboot-sunxi/patches/253-sunxi-h5-add-support-for-nanopi-r1s-h5.patch 已删除 100644 → 0
浏览文件 @ 497012ab
From e7510d24cab4741f72489b9d67c2d42b18fe5374 Mon Sep 17 00:00:00 2001
From: Chukun Pan <amadeus@jmu.edu.cn>
Date: Sun, 10 Oct 2021 21:36:57 +0800
Subject: [PATCH] sunxi: Add support for FriendlyARM NanoPi R1S H5
This adds support for the NanoPi R1S H5 board.
Allwinner H5 SoC
512MB DDR3 RAM
10/100/1000M Ethernet x 2
RTL8189ETV WiFi 802.11b/g/n
USB 2.0 host port (A)
MicroSD Slot
Reset button
Serial Debug Port
WAN - LAN - SYS LED
Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts | 195 +++++++++++++++++++++++
board/sunxi/MAINTAINERS | 5 +
configs/nanopi_r1s_h5_defconfig | 14 ++
4 files changed, 215 insertions(+)
create mode 100644 arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
create mode 100644 configs/nanopi_r1s_h5_defconfig
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -575,6 +575,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \
sun50i-h5-libretech-all-h5-cc.dtb \
sun50i-h5-nanopi-neo2.dtb \
sun50i-h5-nanopi-neo-plus2.dtb \
+ sun50i-h5-nanopi-r1s-h5.dtb \
sun50i-h5-orangepi-zero-plus.dtb \
sun50i-h5-orangepi-pc2.dtb \
sun50i-h5-orangepi-prime.dtb \
--- /dev/null
+++ b/arch/arm/dts/sun50i-h5-nanopi-r1s-h5.dts
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Chukun Pan <amadeus@jmu.edu.cn>
+ *
+ * Based on sun50i-h5-nanopi-neo-plus2.dts, which is:
+ * Copyright (C) 2017 Antony Antony <antony@phenome.org>
+ * Copyright (C) 2016 ARM Ltd.
+ */
+
+/dts-v1/;
+#include "sun50i-h5.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "FriendlyARM NanoPi R1S H5";
+ compatible = "friendlyarm,nanopi-r1s-h5", "allwinner,sun50i-h5";
+
+ aliases {
+ ethernet0 = &emac;
+ ethernet1 = &rtl8189etv;
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ sys {
+ label = "nanopi:red:sys";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ lan {
+ label = "nanopi:green:lan";
+ gpios = <&pio 0 9 GPIO_ACTIVE_HIGH>;
+ };
+
+ wan {
+ label = "nanopi:green:wan";
+ gpios = <&pio 6 11 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ r-gpio-keys {
+ compatible = "gpio-keys";
+
+ reset {
+ label = "reset";
+ linux,code = <KEY_RESTART>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ reg_gmac_3v3: gmac-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "gmac-3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ startup-delay-us = <100000>;
+ enable-active-high;
+ gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>;
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ reg_usb0_vbus: usb0-vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb0-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ enable-active-high;
+ gpio = <&r_pio 0 2 GPIO_ACTIVE_HIGH>; /* PL2 */
+ status = "okay";
+ };
+
+ vdd_cpux: gpio-regulator {
+ compatible = "regulator-gpio";
+ regulator-name = "vdd-cpux";
+ regulator-type = "voltage";
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-ramp-delay = <50>; /* 4ms */
+ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>;
+ gpios-states = <0x1>;
+ states = <1100000 0x0>, <1300000 0x1>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>; /* PL7 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpux>;
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&emac {
+ pinctrl-names = "default";
+ pinctrl-0 = <&emac_rgmii_pins>;
+ phy-supply = <&reg_gmac_3v3>;
+ phy-handle = <&ext_rgmii_phy>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&external_mdio {
+ ext_rgmii_phy: ethernet-phy@7 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <7>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ eeprom@51 {
+ compatible = "microchip,24c02";
+ reg = <0x51>;
+ pagesize = <16>;
+ };
+};
+
+&mmc0 {
+ vmmc-supply = <&reg_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
+
+&mmc1 {
+ vmmc-supply = <&reg_vcc3v3>;
+ vqmmc-supply = <&reg_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ rtl8189etv: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pa_pins>;
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ /* USB Type-A port's VBUS is always on */
+ usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
+ usb0_vbus-supply = <&reg_usb0_vbus>;
+ status = "okay";
+};
--- a/board/sunxi/MAINTAINERS
+++ b/board/sunxi/MAINTAINERS
@@ -358,6 +358,11 @@ M: Jelle van der Waa <jelle@vdwaa.nl>
S: Maintained
F: configs/nanopi_neo_air_defconfig
+NANOPI-R1S-H5 BOARD
+M: Chukun Pan <amadeus@jmu.edu.cn>
+S: Maintained
+F: configs/nanopi_r1s_h5_defconfig
+
NANOPI-A64 BOARD
M: Jagan Teki <jagan@amarulasolutions.com>
S: Maintained
--- /dev/null
+++ b/configs/nanopi_r1s_h5_defconfig
@@ -0,0 +1,14 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SUNXI=y
+CONFIG_SPL=y
+CONFIG_MACH_SUN50I_H5=y
+CONFIG_DRAM_CLK=672
+CONFIG_DRAM_ZQ=3881977
+# CONFIG_DRAM_ODT_EN is not set
+CONFIG_MACPWR="PD6"
+CONFIG_MMC_SUNXI_SLOT_EXTRA=2
+# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
+CONFIG_DEFAULT_DEVICE_TREE="sun50i-h5-nanopi-r1s-h5"
+CONFIG_SUN8I_EMAC=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
package/boot/uboot-sunxi/patches/270-arm-sunxi-increase-SYS_MALLOC_F_LEN.patch 已删除 100644 → 0
浏览文件 @ 497012ab
From 20abdd7feefbb4fccef5c653e045911670237e8b Mon Sep 17 00:00:00 2001
From: Stijn Tintel <stijn@linux-ipv6.be>
Date: Thu, 22 Dec 2022 00:35:07 +0200
Subject: [PATCH] arm: sunxi: increase SYS_MALLOC_F_LEN
Version 2020.10 throws the following output after loading bl31:
alloc space exhausted
This has been fixed in v2022.07, but the change is too intrusive to
backport. Instead, just modify the default for ARCH_SUNXI for now.
See e05689242238 ("Kconfig: Change SYS_MALLOC_F_LEN default to 0x2000").
Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
---
Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/Kconfig
+++ b/Kconfig
@@ -146,7 +146,7 @@ config SYS_MALLOC_F_LEN
default 0x2000 if (ARCH_IMX8 || ARCH_IMX8M || ARCH_MX7 || \
ARCH_MX7ULP || ARCH_MX6 || ARCH_MX5 || \
ARCH_LS1012A || ARCH_LS1021A || ARCH_LS1043A || \
- ARCH_LS1046A || ARCH_QEMU)
+ ARCH_LS1046A || ARCH_QEMU || ARCH_SUNXI)
default 0x400
help
Before relocation, memory is very limited on many platforms. Still,
package/boot/uboot-sunxi/patches/300-force-pylibfdt-build.patch 0 → 100644
浏览文件 @ 1b15cb21
--- a/Makefile
+++ b/Makefile
@@ -2000,26 +2000,7 @@ endif
# Check dtc and pylibfdt, if DTC is provided, else build them
PHONY += scripts_dtc
scripts_dtc: scripts_basic
- $(Q)if test "$(DTC)" = "$(DTC_INTREE)"; then \
- $(MAKE) $(build)=scripts/dtc; \
- else \
- if ! $(DTC) -v >/dev/null; then \
- echo '*** Failed to check dtc version: $(DTC)'; \
- false; \
- else \
- if test "$(call dtc-version)" -lt $(DTC_MIN_VERSION); then \
- echo '*** Your dtc is too old, please upgrade to dtc $(DTC_MIN_VERSION) or newer'; \
- false; \
- else \
- if [ -n "$(CONFIG_PYLIBFDT)" ]; then \
- if ! echo "import libfdt" | $(PYTHON3) 2>/dev/null; then \
- echo '*** pylibfdt does not seem to be available with $(PYTHON3)'; \
- false; \
- fi; \
- fi; \
- fi; \
- fi; \
- fi
+ $(MAKE) $(build)=scripts/dtc
# ---------------------------------------------------------------------------
quiet_cmd_cpp_lds = LDS $@
package/firmware/ipq-wifi/Makefile
浏览文件 @ 1b15cb21
......@@ -33,6 +33,7 @@ ALLWIFIBOARDS:= \
dynalink_dl-wrx36 \
edgecore_eap102 \
edimax_cax1800 \
netgear_rax120v2 \
netgear_wax218 \
prpl_haze \
qnap_301w \
......@@ -121,6 +122,7 @@ $(eval $(call generate-ipq-wifi-package,compex_wpq873,Compex WPQ-873))
$(eval $(call generate-ipq-wifi-package,dynalink_dl-wrx36,Dynalink DL-WRX36))
$(eval $(call generate-ipq-wifi-package,edgecore_eap102,Edgecore EAP102))
$(eval $(call generate-ipq-wifi-package,edimax_cax1800,Edimax CAX1800))
$(eval $(call generate-ipq-wifi-package,netgear_rax120v2,Netgear RAX120v2))
$(eval $(call generate-ipq-wifi-package,netgear_wax218,Netgear WAX218))
$(eval $(call generate-ipq-wifi-package,qnap_301w,QNAP 301w))
$(eval $(call generate-ipq-wifi-package,prpl_haze,prpl Haze))
......
package/firmware/wireless-regdb/Makefile
浏览文件 @ 1b15cb21
include $(TOPDIR)/rules.mk
PKG_NAME:=wireless-regdb
PKG_VERSION:=2023.05.03
PKG_VERSION:=2023.09.01
PKG_RELEASE:=1
PKG_SOURCE:=$(PKG_NAME)-$(PKG_VERSION).tar.xz
PKG_SOURCE_URL:=@KERNEL/software/network/wireless-regdb/
PKG_HASH:=f254d08ab3765aeae2b856222e11a95d44aef519a6663877c71ef68fae4c8c12
PKG_HASH:=26d4c2a727cc59239b84735aad856b7c7d0b04e30aa5c235c4f7f47f5f053491
PKG_MAINTAINER:=Felix Fietkau <nbd@nbd.name>
......
package/kernel/lantiq/ltq-ifxos/patches/100-compat.patch
浏览文件 @ 1b15cb21
......@@ -90,3 +90,17 @@
return ret;
}
--- a/src/linux/ifxos_linux_thread_drv.c
+++ b/src/linux/ifxos_linux_thread_drv.c
@@ -154,7 +154,11 @@ IFXOS_STATIC int IFXOS_KernelThreadStart
retVal = pThrCntrl->pThrFct(&pThrCntrl->thrParams);
pThrCntrl->thrParams.bRunning = IFX_FALSE;
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0))
+ kthread_complete_and_exit(&pThrCntrl->thrCompletion, (long)retVal);
+#else
complete_and_exit(&pThrCntrl->thrCompletion, (long)retVal);
+#endif
IFXOS_PRN_USR_DBG_NL( IFXOS, IFXOS_PRN_LEVEL_NORMAL,
("EXIT - Kernel Thread Startup <%s>" IFXOS_CRLF,
package/kernel/lantiq/ltq-vdsl-vr11-mei/patches/100-compat.patch
浏览文件 @ 1b15cb21
......@@ -8,3 +8,16 @@
MODULE_LICENSE ("GPL");
#endif /* #ifdef MODULE*/
--- a/src/drv_mei_cpe_linux.h
+++ b/src/drv_mei_cpe_linux.h
@@ -110,6 +110,10 @@ typedef irqreturn_t (*usedIsrHandler_t)(
# endif
#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0))
+#define PDE_DATA pde_data
+#endif
+
/**
Function typedef for the Linux request_threaded_irq()
*/
package/kernel/lantiq/ltq-vdsl-vr11-mei/patches/122-cp_linux-fix-compilation-warning.patch
浏览文件 @ 1b15cb21
--- a/src/drv_mei_cpe_linux.c
--- a/src/drv_mei_cpe_linux.c
+++ b/src/drv_mei_cpe_linux.c
@@ -1267,7 +1267,9 @@ static long MEI_Ioctl( struct file *filp,
@@ -1267,7 +1267,9 @@ static long MEI_Ioctl( struct file *filp
MEI_IOCTL_RETURN:
local_args.drv_ioctl.retCode = ret;
......
package/kernel/lantiq/vrx518_ep/patches/100-compat.patch
浏览文件 @ 1b15cb21
......@@ -42,6 +42,25 @@
dev_err(&pdev->dev,
"%s: Failed to enable MSI interrupts error code: %d\n",
__func__, err);
@@ -589,15 +589,15 @@ static int dc_ep_probe(struct pci_dev *p
/* Target structures have a limit of 32 bit DMA pointers.
* DMA pointers can be wider than 32 bits by default on some systems.
*/
- ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
+ ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
if (ret) {
dev_err(&pdev->dev, "32-bit DMA not available: %d\n", ret);
goto err_region;
}
- ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
+ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
if (ret) {
- dev_err(&pdev->dev, "cannot enable 32-bit consistent DMA\n");
+ dev_err(&pdev->dev, "cannot enable 32-bit coherent DMA\n");
goto err_region;
}
@@ -654,7 +654,7 @@ static int dc_ep_probe(struct pci_dev *p
goto err_iomap;
......
package/kernel/lantiq/vrx518_tc/patches/200-swplat.patch
浏览文件 @ 1b15cb21
......@@ -79,7 +79,7 @@ This replaces it by a basic working implementation.
tc_dbg(priv->tc_priv, MSG_TX, "ATM: TX fail\n");
--- a/dcdp/ptm_tc.c
+++ b/dcdp/ptm_tc.c
@@ -497,6 +497,7 @@ static int ptm_xmit(struct sk_buff *skb,
@@ -506,6 +506,7 @@ static int ptm_xmit(struct sk_buff *skb,
struct ptm_priv *ptm_tc = netdev_priv(dev);
int qid;
enum tc_pkt_type type;
......@@ -87,7 +87,7 @@ This replaces it by a basic working implementation.
if (!showtime_stat(ptm_tc->tc_priv))
goto PTM_XMIT_DROP;
@@ -510,11 +511,13 @@ static int ptm_xmit(struct sk_buff *skb,
@@ -519,11 +520,13 @@ static int ptm_xmit(struct sk_buff *skb,
type = ptm_tc->tc_priv->tc_mode == TC_PTM_BND_MODE
? PTM_BOND_PKT : PTM_SL_PKT;
......@@ -102,7 +102,7 @@ This replaces it by a basic working implementation.
}
return 0;
@@ -631,7 +634,7 @@ static int ptm_dev_init(struct tc_priv *
@@ -640,7 +643,7 @@ static int ptm_dev_init(struct tc_priv *
const char macaddr[ETH_ALEN]
= {0xAC, 0x9A, 0x96, 0x11, 0x22, 0x33};
......@@ -111,7 +111,7 @@ This replaces it by a basic working implementation.
if (!dev) {
tc_dbg(tc_priv, MSG_INIT, "Cannot alloc net device\n");
return -ENOMEM;
@@ -2324,7 +2327,11 @@ static void ptm_aca_init(struct ptm_ep_p
@@ -2337,7 +2340,11 @@ static void ptm_aca_init(struct ptm_ep_p
cfg = &priv->tc_priv->cfg;
txin = &param.aca_txin;
......@@ -123,7 +123,7 @@ This replaces it by a basic working implementation.
txin->hd_size_in_dw = cfg->txin.soc_desc_dwsz;
txin->pd_desc_base = SB_XBAR_ADDR(__ACA_TX_IN_PD_LIST_BASE);
txin->pd_desc_num = __ACA_TX_IN_PD_LIST_NUM;
@@ -2347,7 +2354,11 @@ static void ptm_aca_init(struct ptm_ep_p
@@ -2360,7 +2367,11 @@ static void ptm_aca_init(struct ptm_ep_p
txin->soc_cmlt_cnt_addr);
txout = &param.aca_txout;
......@@ -135,7 +135,7 @@ This replaces it by a basic working implementation.
txout->hd_size_in_dw = cfg->txout.soc_desc_dwsz;
if (priv->tc_priv->param.cdma_desc_loc == LOC_IN_FPI)
txout->pd_desc_base = sb_r32(__TX_OUT_SHADOW_PTR) - phybase;
@@ -2373,7 +2384,11 @@ static void ptm_aca_init(struct ptm_ep_p
@@ -2386,7 +2397,11 @@ static void ptm_aca_init(struct ptm_ep_p
txout->soc_cmlt_cnt_addr);
rxout = &param.aca_rxout;
......@@ -147,7 +147,7 @@ This replaces it by a basic working implementation.
rxout->hd_size_in_dw = cfg->rxout.soc_desc_dwsz;
if (priv->tc_priv->param.cdma_desc_loc == LOC_IN_FPI)
rxout->pd_desc_base = sb_r32(__RX_OUT_SHADOW_PTR) - phybase;
@@ -2399,7 +2414,11 @@ static void ptm_aca_init(struct ptm_ep_p
@@ -2412,7 +2427,11 @@ static void ptm_aca_init(struct ptm_ep_p
rxout->soc_cmlt_cnt_addr);
rxin = &param.aca_rxin;
......
package/kernel/lantiq/vrx518_tc/patches/202-napi.patch
浏览文件 @ 1b15cb21
......@@ -334,7 +334,7 @@
int (*umt_init)(u32 umt_id, u32 umt_period, u32 umt_dst);
--- a/dcdp/ptm_tc.c
+++ b/dcdp/ptm_tc.c
@@ -141,7 +141,11 @@ static int ptm_open(struct net_device *d
@@ -146,7 +146,11 @@ static int ptm_open(struct net_device *d
struct ptm_priv *ptm_tc = netdev_priv(dev);
tc_info(ptm_tc->tc_priv, MSG_EVENT, "ptm open\n");
......@@ -346,7 +346,7 @@
#ifdef CONFIG_SOC_TYPE_XWAY
xet_phy_wan_port(7, NULL, 1, 1);
if (ppa_hook_ppa_phys_port_add_fn)
@@ -158,7 +162,11 @@ static int ptm_stop(struct net_device *d
@@ -163,7 +167,11 @@ static int ptm_stop(struct net_device *d
struct ptm_priv *ptm_tc = netdev_priv(dev);
tc_info(ptm_tc->tc_priv, MSG_EVENT, "ptm stop\n");
......@@ -358,7 +358,7 @@
#ifdef CONFIG_SOC_TYPE_XWAY
if (ppa_drv_datapath_mac_entry_setting)
ppa_drv_datapath_mac_entry_setting(dev->dev_addr, 0, 6, 10, 1, 2);
@@ -555,7 +563,7 @@ static void ptm_rx(struct net_device *de
@@ -564,7 +572,7 @@ static void ptm_rx(struct net_device *de
ptm_tc->stats64.rx_packets++;
ptm_tc->stats64.rx_bytes += skb->len;
......@@ -367,17 +367,22 @@
ptm_tc->stats64.rx_dropped++;
return;
@@ -651,6 +659,9 @@ static int ptm_dev_init(struct tc_priv *
@@ -664,6 +672,14 @@ static int ptm_dev_init(struct tc_priv *
memcpy(ptm_tc->outq_map, def_outq_map, sizeof(def_outq_map));
SET_NETDEV_DEV(ptm_tc->dev, tc_priv->ep_dev[id].dev);
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(5,17,0))
+ netif_napi_add(ptm_tc->dev, &ptm_tc->napi_rx, tc_priv->tc_ops.napi_rx);
+ netif_napi_add_tx(ptm_tc->dev, &ptm_tc->napi_tx, tc_priv->tc_ops.napi_tx);
+#else
+ netif_napi_add(ptm_tc->dev, &ptm_tc->napi_rx, tc_priv->tc_ops.napi_rx, NAPI_POLL_WEIGHT);
+ netif_tx_napi_add(ptm_tc->dev, &ptm_tc->napi_tx, tc_priv->tc_ops.napi_tx, NAPI_POLL_WEIGHT);
+
+#endif
err = register_netdev(ptm_tc->dev);
if (err)
goto err1;
@@ -2605,7 +2616,9 @@ static int ptm_ring_init(struct ptm_ep_p
@@ -2618,7 +2634,9 @@ static int ptm_ring_init(struct ptm_ep_p
{
ptm_aca_ring_config_init(priv, id, bonding);
return priv->tc_priv->tc_ops.dev_reg(priv->ptm_tc->dev,
......@@ -388,7 +393,7 @@
}
/**
@@ -2960,7 +2973,9 @@ void ptm_tc_unload(enum dsl_tc_mode tc_m
@@ -2973,7 +2991,9 @@ void ptm_tc_unload(enum dsl_tc_mode tc_m
/* unregister device */
if (ptm_tc->tc_priv->tc_ops.dev_unreg != NULL)
ptm_tc->tc_priv->tc_ops.dev_unreg(ptm_tc->dev,
......@@ -399,7 +404,7 @@
/* remove PTM callback function */
ptm_cb_setup(ptm_tc, 0);
@@ -2978,6 +2993,10 @@ void ptm_exit(void)
@@ -2991,6 +3011,10 @@ void ptm_exit(void)
if (!priv)
return;
......
package/kernel/lantiq/vrx518_tc/patches/205-dcdp-ptm_tc-dynamically-alloc-mib.patch
浏览文件 @ 1b15cb21
--- a/dcdp/ptm_tc.c
+++ b/dcdp/ptm_tc.c
@@ -298,15 +298,19 @@ static int ptm_tc_get_stats(struct ptm_e
@@ -307,15 +307,19 @@ static int ptm_tc_get_stats(struct ptm_e
)
{
struct rtnl_link_stats64 *stat;
......@@ -21,7 +21,7 @@
if (bonding)
stats->tc_info = TC_PTM_BND_MODE;
else
@@ -340,11 +344,11 @@ static int ptm_tc_get_stats(struct ptm_e
@@ -349,11 +353,11 @@ static int ptm_tc_get_stats(struct ptm_e
? cur_cnt - last_cnt
: cur_cnt + ((unsigned int)(-1) - last_cnt);
......@@ -36,7 +36,7 @@
cur_cnt = tc_r32(GIF0_RX_CRC_ERR_CNT);
last_cnt = priv->ptm_mib.rx_crc_err_pdu[0];
@@ -358,7 +362,7 @@ static int ptm_tc_get_stats(struct ptm_e
@@ -367,7 +371,7 @@ static int ptm_tc_get_stats(struct ptm_e
? cur_cnt - last_cnt
: cur_cnt + ((unsigned int)(-1) - last_cnt);
......@@ -45,7 +45,7 @@
cur_cnt = sb_r32(__US_TC_LOCAL_Q_CFG_CTXT_BASE +
offsetof(desq_cfg_ctxt_t, deq_pkt_cnt) / 4);
last_cnt = priv->ptm_mib.tx_total_pdu[0];
@@ -376,90 +380,108 @@ static int ptm_tc_get_stats(struct ptm_e
@@ -385,90 +389,108 @@ static int ptm_tc_get_stats(struct ptm_e
/* For bonding information */
if (bonding) {
int i;
......
package/kernel/mac80211/ath.mk
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package/kernel/mt76/Makefile
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package/kernel/ubootenv-nvram/Makefile 0 → 100644
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package/utils/nvram/Makefile
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scripts/download.pl
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