Skip to content

H
hdl4se

饶先宏 / hdl4se

通知 12
Star 1
Fork 0
H
hdl4se

前往新版Gitcode，体验更适合开发者的 AI 搜索 >>

提交 6f8db5d8 编写于 作者: 饶先宏's avatar 饶先宏
浏览文件
操作

202109050658

上级 5f3252a2
展开全部 隐藏空白更改
内联 并排
Showing with 8261 addition and 6549 deletion
examples/hdl4se_riscv/de2/.qsys_edit/layout.xml 0 → 100644
浏览文件 @ 6f8db5d8
此差异已折叠。
examples/hdl4se_riscv/de2/.qsys_edit/preferences.xml
浏览文件 @ 6f8db5d8
......@@ -3,7 +3,7 @@
<debug showDebugMenu="0" />
<systemtable>
<columns>
<connections preferredWidth="79" />
<connections preferredWidth="47" />
<irq preferredWidth="34" />
</columns>
</systemtable>
......@@ -15,5 +15,5 @@
</columns>
</clocktable>
<window width="1100" height="800" x="1187" y="706" />
<library expandedCategories="Project,Library,Library/PLL" />
<library expandedCategories="Library,Project" />
</preferences>
examples/hdl4se_riscv/de2/PLLJ_PLLSPE_INFO.txt
浏览文件 @ 6f8db5d8
PLL_Name pllqsys:clk100|pllqsys_altpll_0:altpll_0|pllqsys_altpll_0_altpll_r342:sd1|pll7
PLL_Name pllqsys:comb_9|pllqsys_altpll_0:altpll_0|pllqsys_altpll_0_altpll_m342:sd1|pll7
PLLJITTER 30
PLLSPEmax 84
PLLSPEmin -53
......
examples/hdl4se_riscv/de2/de2_riscv_v4.qsf
浏览文件 @ 6f8db5d8
......@@ -5,7 +5,7 @@
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY "de2_riscv_v4"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.0"
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0
set_global_assignment -name LAST_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:51:38 SEPTEMBER 01,2021"
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
......@@ -1013,6 +1013,9 @@ set_global_assignment -name VERILOG_FILE ../verilog/uart/uart_ctrl.v
set_global_assignment -name VERILOG_FILE ../verilog/uart/hdl4se_uart.v
set_global_assignment -name VERILOG_FILE de2_riscv_v4.v
set_global_assignment -name SDC_FILE de2_riscv_v4.SDC
set_global_assignment -name QIP_FILE ../de1/clk/clk100M.qip
set_global_assignment -name SIP_FILE ../de1/clk/clk100M.sip
set_global_assignment -name QIP_FILE ../verilog/altera/alu/mulsu.qip
set_global_assignment -name QIP_FILE ../verilog/altera/alu/mult.qip
set_global_assignment -name QIP_FILE ../verilog/altera/alu/mult_s.qip
set_global_assignment -name QIP_FILE ../verilog/altera/alu/div.qip
set_global_assignment -name QIP_FILE ../verilog/altera/alu/div_s.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
examples/hdl4se_riscv/de2/de2_riscv_v4.v
浏览文件 @ 6f8db5d8
......@@ -3,7 +3,7 @@
// This code is generated by Terasic System Builder
//=======================================================
`define USECLOCK50
`define USECLOCK50__
module de2_riscv_v4(
//////////// CLOCK //////////
......@@ -376,17 +376,21 @@ inout [35:0] GPIO;
`ifdef USECLOCK50
wire wClk = CLOCK_50;
wire nwReset = KEY[3];
`else
wire clk100MHz, clk75MHz, clklocked;
clk100M clk100(.refclk(CLOCK_50),
.rst(~KEY[3]),
.outclk_0(clk100MHz),
.outclk_1(clk75MHz),
.locked(clklocked));
wire clk100MHz;
wire nwReset = KEY[3];
pllqsys (
.clk_clk(CLOCK_50), // clk.clk
.reset_reset_n(nwReset), // reset.reset_n
.altpll_0_c0_clk(clk100MHz), // altpll_0_c0.clk
.altpll_0_areset_conduit_export(1'b0), // altpll_0_areset_conduit.export
.altpll_0_inclk_interface_reset_reset(~nwReset) // altpll_0_inclk_interface_reset.reset
);
wire wClk = clk100MHz;
`endif
wire nwReset = KEY[3];
wire wWrite, wRead;
wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey, bReadDataUart;
......
examples/hdl4se_riscv/de2/qsys/.qsys_edit/pllqsys.xml
浏览文件 @ 6f8db5d8
......@@ -553,14 +553,13 @@
</child>
</children>
</root>
<root name="ccontrol south">
<root name="external">
<layout factory="predefined">
<replacement id="rootccontrol south"/>
<replacement id="rootexternal"/>
<delegate id="delegate_CommonDockStationFactory">
<id>ccontrol south</id>
<id>external</id>
<root>true</root>
<content delegate="flap dock">
<window auto="true" direction="SOUTH"/>
<content delegate="screen dock">
<placeholders>
<version>0</version>
<format>dock.PlaceholderList</format>
......@@ -570,7 +569,7 @@
</layout>
<adjacent>
<layout factory="dock.RootStationAdjacentFactory">
<type>dock.CContentArea.minimize</type>
<type>dock.CExternalizeArea</type>
</layout>
</adjacent>
<children ignore="false"/>
......@@ -597,13 +596,14 @@
</adjacent>
<children ignore="false"/>
</root>
<root name="external">
<root name="ccontrol south">
<layout factory="predefined">
<replacement id="rootexternal"/>
<replacement id="rootccontrol south"/>
<delegate id="delegate_CommonDockStationFactory">
<id>external</id>
<id>ccontrol south</id>
<root>true</root>
<content delegate="screen dock">
<content delegate="flap dock">
<window auto="true" direction="SOUTH"/>
<placeholders>
<version>0</version>
<format>dock.PlaceholderList</format>
......@@ -613,7 +613,7 @@
</layout>
<adjacent>
<layout factory="dock.RootStationAdjacentFactory">
<type>dock.CExternalizeArea</type>
<type>dock.CContentArea.minimize</type>
</layout>
</adjacent>
<children ignore="false"/>
......@@ -761,7 +761,7 @@
<fullscreen-action>false</fullscreen-action>
<node nodeId="1372710005721" orientation="HORIZONTAL" divider="0.22181146025878004">
<node nodeId="1375985011088" orientation="VERTICAL" divider="0.504054054054054">
<leaf id="2" nodeId="1375985003630">
<leaf id="0" nodeId="1375985003630">
<placeholders>
<placeholder>dock.single.Library</placeholder>
</placeholders>
......@@ -770,7 +770,7 @@
<format>dock.PlaceholderList</format>
</placeholder-map>
</leaf>
<leaf id="3" nodeId="1375985011087">
<leaf id="2" nodeId="1375985011087">
<placeholders>
<placeholder>dock.single.Hierarchy</placeholder>
</placeholders>
......@@ -795,9 +795,9 @@
<placeholder>dock.single.Instance\ Parameters</placeholder>
<placeholder>dock.single.Clock\ Domains\ \-\ Beta</placeholder>
<placeholder>dock.single.Data\ Path</placeholder>
<placeholder>dock.single.Data\ Path\ \-\ Beta</placeholder>
<placeholder>dock.single.Instrumentation</placeholder>
<placeholder>dock.single.Domains</placeholder>
<placeholder>dock.single.Instrumentation</placeholder>
<placeholder>dock.single.Data\ Path\ \-\ Beta</placeholder>
<placeholder>dock.single.HDL\ Example</placeholder>
</placeholders>
<placeholder-map>
......@@ -825,7 +825,7 @@
</leaf>
</node>
</node>
<leaf id="0" nodeId="1372710005745">
<leaf id="3" nodeId="1372710005745">
<placeholders>
<placeholder>dock.single.Messages</placeholder>
</placeholders>
......@@ -846,10 +846,10 @@
</adjacent>
<children ignore="false">
<child>
<layout factory="predefined" placeholder="dock.single.Messages">
<replacement id="dockablesingle Messages"/>
<layout factory="predefined" placeholder="dock.single.Library">
<replacement id="dockablesingle Library"/>
<delegate id="delegate_ccontrol backup factory id">
<id>Messages</id>
<id>Library</id>
<area/>
</delegate>
</layout>
......@@ -979,20 +979,20 @@
</children>
</child>
<child>
<layout factory="predefined" placeholder="dock.single.Library">
<replacement id="dockablesingle Library"/>
<layout factory="predefined" placeholder="dock.single.Hierarchy">
<replacement id="dockablesingle Hierarchy"/>
<delegate id="delegate_ccontrol backup factory id">
<id>Library</id>
<id>Hierarchy</id>
<area/>
</delegate>
</layout>
<children ignore="false"/>
</child>
<child>
<layout factory="predefined" placeholder="dock.single.Hierarchy">
<replacement id="dockablesingle Hierarchy"/>
<layout factory="predefined" placeholder="dock.single.Messages">
<replacement id="dockablesingle Messages"/>
<delegate id="delegate_ccontrol backup factory id">
<id>Hierarchy</id>
<id>Messages</id>
<area/>
</delegate>
</layout>
......
examples/hdl4se_riscv/de2/qsys/.qsys_edit/preferences.xml
浏览文件 @ 6f8db5d8
......@@ -15,5 +15,5 @@
</columns>
</clocktable>
<window width="1100" height="1020" x="1187" y="706" />
<library expandedCategories="Project,Library/PLL,Library" />
<library expandedCategories="Library,Project" />
</preferences>
examples/hdl4se_riscv/de2/qsys/pllqsys.html
浏览文件 @ 6f8db5d8
......@@ -67,7 +67,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</table>
<table class="blueBar">
<tr>
<td class="l">2021.09.02.06:19:52</td>
<td class="l">2021.09.04.17:30:36</td>
<td class="r">Datasheet</td>
</tr>
</table>
......@@ -311,7 +311,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">CLK0_MULTIPLY_BY</td>
<td class="parametervalue">3</td>
<td class="parametervalue">2</td>
</tr>
<tr>
<td class="parametername">CLK1_MULTIPLY_BY</td>
......@@ -367,7 +367,7 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">CLK0_DIVIDE_BY</td>
<td class="parametervalue">5</td>
<td class="parametervalue">1</td>
</tr>
<tr>
<td class="parametername">CLK1_DIVIDE_BY</td>
......@@ -807,11 +807,11 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</tr>
<tr>
<td class="parametername">HIDDEN_CONSTANTS</td>
<td class="parametervalue">CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 3 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 5 CT#PORT_LOCKED PORT_USED</td>
<td class="parametervalue">CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#PORT_LOCKED PORT_USED</td>
</tr>
<tr>
<td class="parametername">HIDDEN_PRIVATES</td>
<td class="parametervalue">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 30.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 30.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1630534604000345.mif PT#ACTIVECLK_CHECK 0</td>
<td class="parametervalue">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1630534604000345.mif PT#ACTIVECLK_CHECK 0</td>
</tr>
<tr>
<td class="parametername">HIDDEN_USED_PORTS</td>
......@@ -862,8 +862,8 @@ div.greydiv { vertical-align:top ; text-align:center ; background:#eeeeee ; bord
</div>
<table class="blueBar">
<tr>
<td class="l">generation took 0.00 seconds</td>
<td class="r">rendering took 0.02 seconds</td>
<td class="l">generation took 0.01 seconds</td>
<td class="r">rendering took 0.03 seconds</td>
</tr>
</table>
</body>
......
examples/hdl4se_riscv/de2/qsys/pllqsys.qsys
浏览文件 @ 6f8db5d8
......@@ -6,9 +6,12 @@
version="1.0"
description=""
tags=""
categories="" />
categories="System" />
<parameter name="bonusData"><![CDATA[bonusData
{
element $${FILENAME}
{
}
element altpll_0
{
datum _sortIndex
......@@ -95,7 +98,7 @@
<parameter name="DOWN_SPREAD" value="" />
<parameter name="SELF_RESET_ON_GATED_LOSS_LOCK" value="" />
<parameter name="SELF_RESET_ON_LOSS_LOCK" value="" />
<parameter name="CLK0_MULTIPLY_BY" value="3" />
<parameter name="CLK0_MULTIPLY_BY" value="2" />
<parameter name="CLK1_MULTIPLY_BY" value="" />
<parameter name="CLK2_MULTIPLY_BY" value="" />
<parameter name="CLK3_MULTIPLY_BY" value="" />
......@@ -109,7 +112,7 @@
<parameter name="EXTCLK1_MULTIPLY_BY" value="" />
<parameter name="EXTCLK2_MULTIPLY_BY" value="" />
<parameter name="EXTCLK3_MULTIPLY_BY" value="" />
<parameter name="CLK0_DIVIDE_BY" value="5" />
<parameter name="CLK0_DIVIDE_BY" value="1" />
<parameter name="CLK1_DIVIDE_BY" value="" />
<parameter name="CLK2_DIVIDE_BY" value="" />
<parameter name="CLK3_DIVIDE_BY" value="" />
......@@ -219,8 +222,8 @@
<parameter name="USING_FBMIMICBIDIR_PORT" value="" />
<parameter name="SCAN_CHAIN_MIF_FILE" value="" />
<parameter name="AVALON_USE_SEPARATE_SYSCLK" value="NO" />
<parameter name="HIDDEN_CONSTANTS">CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 3 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 5 CT#PORT_LOCKED PORT_USED</parameter>
<parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 30.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 30.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1630534604000345.mif PT#ACTIVECLK_CHECK 0</parameter>
<parameter name="HIDDEN_CONSTANTS">CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#PORT_LOCKED PORT_USED</parameter>
<parameter name="HIDDEN_PRIVATES">PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1630534604000345.mif PT#ACTIVECLK_CHECK 0</parameter>
<parameter name="HIDDEN_USED_PORTS">UP#locked used UP#c0 used UP#areset used UP#inclk0 used</parameter>
<parameter name="HIDDEN_IS_NUMERIC">IN#WIDTH_CLOCK 1 IN#CLK0_DUTY_CYCLE 1 IN#PLL_TARGET_HARCOPY_CHECK 1 IN#SWITCHOVER_COUNT_EDIT 1 IN#INCLK0_INPUT_FREQUENCY 1 IN#PLL_LVDS_PLL_CHECK 1 IN#PLL_AUTOPLL_CHECK 1 IN#PLL_FASTPLL_CHECK 1 IN#PLL_ENHPLL_CHECK 1 IN#DIV_FACTOR0 1 IN#LVDS_MODE_DATA_RATE_DIRTY 1 IN#GLOCK_COUNTER_EDIT 1 IN#CLK0_DIVIDE_BY 1 IN#MULT_FACTOR0 1 IN#CLK0_MULTIPLY_BY 1 IN#USE_MIL_SPEED_GRADE 1</parameter>
<parameter name="HIDDEN_MF_PORTS">MF#areset 1 MF#clk 1 MF#locked 1 MF#inclk 1</parameter>
......
examples/hdl4se_riscv/de2/qsys/pllqsys.sopcinfo
浏览文件 @ 6f8db5d8
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="pllqsys" kind="pllqsys" version="1.0" fabric="QSYS">
<!-- Format version 13.1 162 (Future versions may contain additional information.) -->
<!-- 2021.09.02.06:19:52 -->
<!-- 2021.09.04.17:30:36 -->
<!-- A collection of modules and connections -->
<parameter name="AUTO_GENERATION_ID">
<type>java.lang.Integer</type>
<value>1630534792</value>
<value>1630747835</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
......@@ -638,7 +638,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="CLK0_MULTIPLY_BY">
<type>java.lang.String</type>
<value>3</value>
<value>2</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
......@@ -750,7 +750,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="CLK0_DIVIDE_BY">
<type>java.lang.String</type>
<value>5</value>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
......@@ -1630,7 +1630,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="HIDDEN_CONSTANTS">
<type>java.lang.String</type>
<value>CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 3 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 5 CT#PORT_LOCKED PORT_USED</value>
<value>CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#PORT_LOCKED PORT_USED</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
......@@ -1638,7 +1638,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="HIDDEN_PRIVATES">
<type>java.lang.String</type>
<value>PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 30.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 30.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1630534604000345.mif PT#ACTIVECLK_CHECK 0</value>
<value>PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1630534604000345.mif PT#ACTIVECLK_CHECK 0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
......@@ -2193,7 +2193,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="clockRate">
<type>long</type>
<value>30000000</value>
<value>100000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
......@@ -2413,18 +2413,18 @@ parameters are a RESULT of the module parameters. -->
</connection>
<plugin>
<instanceCount>1</instanceCount>
<name>clock_source</name>
<name>avalon_slave</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Clock Source</displayName>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Avalon Memory Mapped Slave</displayName>
<version>13.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>reset_sink</name>
<name>clock</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Input</displayName>
<subtype>com.altera.entityinterfaces.IConnection</subtype>
<displayName>Clock Connection</displayName>
<version>13.1</version>
</plugin>
<plugin>
......@@ -2437,10 +2437,10 @@ parameters are a RESULT of the module parameters. -->
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>clock</name>
<name>reset_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IConnection</subtype>
<displayName>Clock Connection</displayName>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Output</displayName>
<version>13.1</version>
</plugin>
<plugin>
......@@ -2452,11 +2452,11 @@ parameters are a RESULT of the module parameters. -->
<version>13.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>altpll</name>
<instanceCount>3</instanceCount>
<name>conduit_end</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Avalon ALTPLL</displayName>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Conduit</displayName>
<version>13.1</version>
</plugin>
<plugin>
......@@ -2477,34 +2477,34 @@ parameters are a RESULT of the module parameters. -->
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>avalon_slave</name>
<name>clock_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Avalon Memory Mapped Slave</displayName>
<displayName>Clock Output</displayName>
<version>13.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>clock_source</name>
<name>altpll</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Clock Output</displayName>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Avalon ALTPLL</displayName>
<version>13.1</version>
</plugin>
<plugin>
<instanceCount>3</instanceCount>
<name>conduit_end</name>
<instanceCount>1</instanceCount>
<name>clock_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Conduit</displayName>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Clock Source</displayName>
<version>13.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>reset_source</name>
<name>reset_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Output</displayName>
<displayName>Reset Input</displayName>
<version>13.1</version>
</plugin>
<reportVersion>13.1 162</reportVersion>
......
examples/hdl4se_riscv/de2/qsys/pllqsys/synthesis/pllqsys.debuginfo
浏览文件 @ 6f8db5d8
<?xml version="1.0" encoding="UTF-8"?>
<EnsembleReport name="pllqsys" kind="system" version="13.1" fabric="QSYS">
<!-- Format version 13.1 162 (Future versions may contain additional information.) -->
<!-- 2021.09.02.06:19:54 -->
<!-- 2021.09.04.17:30:58 -->
<!-- A collection of modules and connections -->
<parameter name="clockCrossingAdapter">
<type>com.altera.sopcmodel.ensemble.EClockAdapter</type>
......@@ -53,7 +53,7 @@
</parameter>
<parameter name="generationId">
<type>int</type>
<value>1630534792</value>
<value>1630747835</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
......@@ -686,7 +686,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="CLK0_MULTIPLY_BY">
<type>java.lang.String</type>
<value>3</value>
<value>2</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
......@@ -798,7 +798,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="CLK0_DIVIDE_BY">
<type>java.lang.String</type>
<value>5</value>
<value>1</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
......@@ -1678,7 +1678,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="HIDDEN_CONSTANTS">
<type>java.lang.String</type>
<value>CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 3 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 5 CT#PORT_LOCKED PORT_USED</value>
<value>CT#PORT_clk5 PORT_UNUSED CT#PORT_clk4 PORT_UNUSED CT#PORT_clk3 PORT_UNUSED CT#PORT_clk2 PORT_UNUSED CT#PORT_clk1 PORT_UNUSED CT#PORT_clk0 PORT_USED CT#CLK0_MULTIPLY_BY 2 CT#PORT_SCANWRITE PORT_UNUSED CT#PORT_SCANACLR PORT_UNUSED CT#PORT_PFDENA PORT_UNUSED CT#PORT_PLLENA PORT_UNUSED CT#PORT_SCANDATA PORT_UNUSED CT#PORT_SCANCLKENA PORT_UNUSED CT#WIDTH_CLOCK 5 CT#PORT_SCANDATAOUT PORT_UNUSED CT#LPM_TYPE altpll CT#PLL_TYPE AUTO CT#CLK0_PHASE_SHIFT 0 CT#PORT_PHASEDONE PORT_UNUSED CT#OPERATION_MODE NORMAL CT#PORT_CONFIGUPDATE PORT_UNUSED CT#COMPENSATE_CLOCK CLK0 CT#PORT_CLKSWITCH PORT_UNUSED CT#INCLK0_INPUT_FREQUENCY 20000 CT#PORT_SCANDONE PORT_UNUSED CT#PORT_CLKLOSS PORT_UNUSED CT#PORT_INCLK1 PORT_UNUSED CT#AVALON_USE_SEPARATE_SYSCLK NO CT#PORT_INCLK0 PORT_USED CT#PORT_clkena5 PORT_UNUSED CT#PORT_clkena4 PORT_UNUSED CT#PORT_clkena3 PORT_UNUSED CT#PORT_clkena2 PORT_UNUSED CT#PORT_clkena1 PORT_UNUSED CT#PORT_clkena0 PORT_UNUSED CT#PORT_ARESET PORT_USED CT#BANDWIDTH_TYPE AUTO CT#INTENDED_DEVICE_FAMILY {Cyclone IV E} CT#PORT_SCANREAD PORT_UNUSED CT#PORT_PHASESTEP PORT_UNUSED CT#PORT_SCANCLK PORT_UNUSED CT#PORT_CLKBAD1 PORT_UNUSED CT#PORT_CLKBAD0 PORT_UNUSED CT#PORT_FBIN PORT_UNUSED CT#PORT_PHASEUPDOWN PORT_UNUSED CT#PORT_extclk3 PORT_UNUSED CT#PORT_extclk2 PORT_UNUSED CT#PORT_extclk1 PORT_UNUSED CT#PORT_PHASECOUNTERSELECT PORT_UNUSED CT#PORT_extclk0 PORT_UNUSED CT#PORT_ACTIVECLOCK PORT_UNUSED CT#CLK0_DUTY_CYCLE 50 CT#CLK0_DIVIDE_BY 1 CT#PORT_LOCKED PORT_USED</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
......@@ -1686,7 +1686,7 @@ the requested settings for a module instance. -->
</parameter>
<parameter name="HIDDEN_PRIVATES">
<type>java.lang.String</type>
<value>PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 30.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 30.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1630534604000345.mif PT#ACTIVECLK_CHECK 0</value>
<value>PT#GLOCKED_FEATURE_ENABLED 0 PT#SPREAD_FEATURE_ENABLED 0 PT#BANDWIDTH_FREQ_UNIT MHz PT#CUR_DEDICATED_CLK c0 PT#INCLK0_FREQ_EDIT 50.000 PT#BANDWIDTH_PRESET Low PT#PLL_LVDS_PLL_CHECK 0 PT#BANDWIDTH_USE_PRESET 0 PT#AVALON_USE_SEPARATE_SYSCLK NO PT#PLL_ENHPLL_CHECK 0 PT#OUTPUT_FREQ_UNIT0 MHz PT#PHASE_RECONFIG_FEATURE_ENABLED 1 PT#CREATE_CLKBAD_CHECK 0 PT#CLKSWITCH_CHECK 0 PT#INCLK1_FREQ_EDIT 100.000 PT#NORMAL_MODE_RADIO 1 PT#SRC_SYNCH_COMP_RADIO 0 PT#PLL_ARESET_CHECK 1 PT#LONG_SCAN_RADIO 1 PT#SCAN_FEATURE_ENABLED 1 PT#PHASE_RECONFIG_INPUTS_CHECK 0 PT#USE_CLK0 1 PT#PRIMARY_CLK_COMBO inclk0 PT#BANDWIDTH 1.000 PT#GLOCKED_COUNTER_EDIT_CHANGED 1 PT#PLL_FASTPLL_CHECK 0 PT#SPREAD_FREQ_UNIT KHz PT#PLL_AUTOPLL_CHECK 1 PT#LVDS_PHASE_SHIFT_UNIT0 deg PT#SWITCHOVER_FEATURE_ENABLED 0 PT#MIG_DEVICE_SPEED_GRADE Any PT#OUTPUT_FREQ_MODE0 1 PT#BANDWIDTH_FEATURE_ENABLED 1 PT#INCLK0_FREQ_UNIT_COMBO MHz PT#ZERO_DELAY_RADIO 0 PT#OUTPUT_FREQ0 100.00000000 PT#SHORT_SCAN_RADIO 0 PT#LVDS_MODE_DATA_RATE_DIRTY 0 PT#CUR_FBIN_CLK c0 PT#PLL_ADVANCED_PARAM_CHECK 0 PT#CLKBAD_SWITCHOVER_CHECK 0 PT#PHASE_SHIFT_STEP_ENABLED_CHECK 0 PT#DEVICE_SPEED_GRADE Any PT#PLL_FBMIMIC_CHECK 0 PT#LVDS_MODE_DATA_RATE {Not Available} PT#LOCKED_OUTPUT_CHECK 1 PT#SPREAD_PERCENT 0.500 PT#PHASE_SHIFT0 0.00000000 PT#DIV_FACTOR0 1 PT#CNX_NO_COMPENSATE_RADIO 0 PT#USE_CLKENA0 0 PT#CREATE_INCLK1_CHECK 0 PT#GLOCK_COUNTER_EDIT 1048575 PT#INCLK1_FREQ_UNIT_COMBO MHz PT#EFF_OUTPUT_FREQ_VALUE0 100.000000 PT#SPREAD_FREQ 50.000 PT#USE_MIL_SPEED_GRADE 0 PT#EXPLICIT_SWITCHOVER_COUNTER 0 PT#STICKY_CLK0 1 PT#EXT_FEEDBACK_RADIO 0 PT#MIRROR_CLK0 0 PT#SWITCHOVER_COUNT_EDIT 1 PT#SELF_RESET_LOCK_LOSS 0 PT#PLL_PFDENA_CHECK 0 PT#INT_FEEDBACK__MODE_RADIO 1 PT#INCLK1_FREQ_EDIT_CHANGED 1 PT#CLKLOSS_CHECK 0 PT#SYNTH_WRAPPER_GEN_POSTFIX 0 PT#PHASE_SHIFT_UNIT0 deg PT#BANDWIDTH_USE_AUTO 1 PT#HAS_MANUAL_SWITCHOVER 1 PT#MULT_FACTOR0 1 PT#SPREAD_USE 0 PT#GLOCKED_MODE_CHECK 0 PT#SACN_INPUTS_CHECK 0 PT#DUTY_CYCLE0 50.00000000 PT#INTENDED_DEVICE_FAMILY {Cyclone IV E} PT#PLL_TARGET_HARCOPY_CHECK 0 PT#INCLK1_FREQ_UNIT_CHANGED 1 PT#RECONFIG_FILE ALTPLL1630534604000345.mif PT#ACTIVECLK_CHECK 0</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>false</visible>
......@@ -2241,7 +2241,7 @@ parameters are a RESULT of the module parameters. -->
</parameter>
<parameter name="clockRate">
<type>long</type>
<value>30000000</value>
<value>100000000</value>
<derived>false</derived>
<enabled>true</enabled>
<visible>true</visible>
......@@ -2461,18 +2461,18 @@ parameters are a RESULT of the module parameters. -->
</connection>
<plugin>
<instanceCount>1</instanceCount>
<name>clock_source</name>
<name>avalon_slave</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Clock Source</displayName>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Avalon Memory Mapped Slave</displayName>
<version>13.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>reset_sink</name>
<name>clock</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Input</displayName>
<subtype>com.altera.entityinterfaces.IConnection</subtype>
<displayName>Clock Connection</displayName>
<version>13.1</version>
</plugin>
<plugin>
......@@ -2485,10 +2485,10 @@ parameters are a RESULT of the module parameters. -->
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>clock</name>
<name>reset_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IConnection</subtype>
<displayName>Clock Connection</displayName>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Output</displayName>
<version>13.1</version>
</plugin>
<plugin>
......@@ -2500,11 +2500,11 @@ parameters are a RESULT of the module parameters. -->
<version>13.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>altpll</name>
<instanceCount>3</instanceCount>
<name>conduit_end</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Avalon ALTPLL</displayName>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Conduit</displayName>
<version>13.1</version>
</plugin>
<plugin>
......@@ -2525,36 +2525,36 @@ parameters are a RESULT of the module parameters. -->
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>avalon_slave</name>
<name>clock_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Avalon Memory Mapped Slave</displayName>
<displayName>Clock Output</displayName>
<version>13.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>clock_source</name>
<name>altpll</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Clock Output</displayName>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Avalon ALTPLL</displayName>
<version>13.1</version>
</plugin>
<plugin>
<instanceCount>3</instanceCount>
<name>conduit_end</name>
<instanceCount>1</instanceCount>
<name>clock_source</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Conduit</displayName>
<subtype>com.altera.entityinterfaces.IModule</subtype>
<displayName>Clock Source</displayName>
<version>13.1</version>
</plugin>
<plugin>
<instanceCount>1</instanceCount>
<name>reset_source</name>
<name>reset_sink</name>
<type>com.altera.entityinterfaces.IElementClass</type>
<subtype>com.altera.entityinterfaces.IMutableConnectionPoint</subtype>
<displayName>Reset Output</displayName>
<displayName>Reset Input</displayName>
<version>13.1</version>
</plugin>
<reportVersion>13.1 162</reportVersion>
<uniqueIdentifier>5C61994ACABB0000017BA3727638</uniqueIdentifier>
<uniqueIdentifier>5C61994ACABB0000017BB0253F5E</uniqueIdentifier>
</EnsembleReport>
examples/hdl4se_riscv/de2/qsys/pllqsys/synthesis/pllqsys.qip
浏览文件 @ 6f8db5d8
......@@ -2,7 +2,7 @@ set_global_assignment -entity "pllqsys" -library "pllqsys" -name IP_TOOL_NAME "Q
set_global_assignment -entity "pllqsys" -library "pllqsys" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "pllqsys" -library "pllqsys" -name IP_TOOL_ENV "Qsys"
set_global_assignment -library "pllqsys" -name SOPCINFO_FILE [file join $::quartus(qip_path) "../../pllqsys.sopcinfo"]
set_global_assignment -entity "pllqsys" -library "pllqsys" -name SLD_INFO "QSYS_NAME pllqsys HAS_SOPCINFO 1 GENERATION_ID 1630534792"
set_global_assignment -entity "pllqsys" -library "pllqsys" -name SLD_INFO "QSYS_NAME pllqsys HAS_SOPCINFO 1 GENERATION_ID 1630747835"
set_global_assignment -library "pllqsys" -name MISC_FILE [file join $::quartus(qip_path) "../../pllqsys.cmp"]
set_global_assignment -library "pllqsys" -name SLD_FILE [file join $::quartus(qip_path) "pllqsys.debuginfo"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
......
examples/hdl4se_riscv/de2/qsys/pllqsys/synthesis/pllqsys.v
浏览文件 @ 6f8db5d8
// pllqsys.v
// Generated using ACDS version 13.1 162 at 2021.09.02.06:19:52
// Generated using ACDS version 13.1 162 at 2021.09.04.17:30:36
`timescale 1 ps / 1 ps
module pllqsys (
......
examples/hdl4se_riscv/de2/qsys/pllqsys/synthesis/submodules/pllqsys_altpll_0.v
浏览文件 @ 6f8db5d8
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=5 clk0_duty_cycle=50 clk0_multiply_by=3 clk0_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//altpll_avalon avalon_use_separate_sysclk="NO" CBX_SINGLE_OUTPUT_FILE="ON" CBX_SUBMODULE_USED_PORTS="altpll:areset,clk,locked,inclk" address areset c0 clk locked phasedone read readdata reset write writedata bandwidth_type="AUTO" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5
//VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:24:09:15:20:SJ cbx_altiobuf_bidir 2013:10:24:09:15:20:SJ cbx_altiobuf_in 2013:10:24:09:15:20:SJ cbx_altiobuf_out 2013:10:24:09:15:20:SJ cbx_altpll 2013:10:24:09:15:20:SJ cbx_altpll_avalon 2013:10:24:09:15:20:SJ cbx_cycloneii 2013:10:24:09:15:20:SJ cbx_lpm_add_sub 2013:10:24:09:15:20:SJ cbx_lpm_compare 2013:10:24:09:15:20:SJ cbx_lpm_counter 2013:10:24:09:15:20:SJ cbx_lpm_decode 2013:10:24:09:15:20:SJ cbx_lpm_mux 2013:10:24:09:15:20:SJ cbx_lpm_shiftreg 2013:10:24:09:15:20:SJ cbx_mgl 2013:10:24:09:16:30:SJ cbx_stratix 2013:10:24:09:15:20:SJ cbx_stratixii 2013:10:24:09:15:20:SJ cbx_stratixiii 2013:10:24:09:15:20:SJ cbx_stratixv 2013:10:24:09:15:20:SJ cbx_util_mgl 2013:10:24:09:15:20:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
......@@ -119,7 +119,7 @@ module pllqsys_altpll_0_stdsync_sv6
endmodule //pllqsys_altpll_0_stdsync_sv6
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=5 clk0_duty_cycle=50 clk0_multiply_by=3 clk0_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//altpll bandwidth_type="AUTO" CBX_SINGLE_OUTPUT_FILE="ON" clk0_divide_by=1 clk0_duty_cycle=50 clk0_multiply_by=2 clk0_phase_shift="0" compensate_clock="CLK0" device_family="CYCLONEIVE" inclk0_input_frequency=20000 intended_device_family="Cyclone IV E" operation_mode="normal" pll_type="AUTO" port_clk0="PORT_USED" port_clk1="PORT_UNUSED" port_clk2="PORT_UNUSED" port_clk3="PORT_UNUSED" port_clk4="PORT_UNUSED" port_clk5="PORT_UNUSED" port_extclk0="PORT_UNUSED" port_extclk1="PORT_UNUSED" port_extclk2="PORT_UNUSED" port_extclk3="PORT_UNUSED" port_inclk1="PORT_UNUSED" port_phasecounterselect="PORT_UNUSED" port_phasedone="PORT_UNUSED" port_scandata="PORT_UNUSED" port_scandataout="PORT_UNUSED" width_clock=5 areset clk inclk locked
//VERSION_BEGIN 13.1 cbx_altclkbuf 2013:10:24:09:15:20:SJ cbx_altiobuf_bidir 2013:10:24:09:15:20:SJ cbx_altiobuf_in 2013:10:24:09:15:20:SJ cbx_altiobuf_out 2013:10:24:09:15:20:SJ cbx_altpll 2013:10:24:09:15:20:SJ cbx_cycloneii 2013:10:24:09:15:20:SJ cbx_lpm_add_sub 2013:10:24:09:15:20:SJ cbx_lpm_compare 2013:10:24:09:15:20:SJ cbx_lpm_counter 2013:10:24:09:15:20:SJ cbx_lpm_decode 2013:10:24:09:15:20:SJ cbx_lpm_mux 2013:10:24:09:15:20:SJ cbx_mgl 2013:10:24:09:16:30:SJ cbx_stratix 2013:10:24:09:15:20:SJ cbx_stratixii 2013:10:24:09:15:20:SJ cbx_stratixiii 2013:10:24:09:15:20:SJ cbx_stratixv 2013:10:24:09:15:20:SJ cbx_util_mgl 2013:10:24:09:15:20:SJ VERSION_END
//synthesis_resources = cycloneive_pll 1 reg 1
......@@ -127,7 +127,7 @@ endmodule //pllqsys_altpll_0_stdsync_sv6
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"SUPPRESS_DA_RULE_INTERNAL=C104;SUPPRESS_DA_RULE_INTERNAL=R101"} *)
module pllqsys_altpll_0_altpll_r342
module pllqsys_altpll_0_altpll_m342
(
areset,
clk,
......@@ -192,9 +192,9 @@ module pllqsys_altpll_0_altpll_r342
);
defparam
pll7.bandwidth_type = "auto",
pll7.clk0_divide_by = 5,
pll7.clk0_divide_by = 1,
pll7.clk0_duty_cycle = 50,
pll7.clk0_multiply_by = 3,
pll7.clk0_multiply_by = 2,
pll7.clk0_phase_shift = "0",
pll7.compensate_clock = "clk0",
pll7.inclk0_input_frequency = 20000,
......@@ -204,7 +204,7 @@ module pllqsys_altpll_0_altpll_r342
assign
clk = {wire_pll7_clk[4:0]},
locked = (wire_pll7_locked & pll_lock_sync);
endmodule //pllqsys_altpll_0_altpll_r342
endmodule //pllqsys_altpll_0_altpll_m342
//synthesis_resources = cycloneive_pll 1 reg 6
//synopsys translate_off
......@@ -256,7 +256,7 @@ module pllqsys_altpll_0
.din(wire_sd1_locked),
.dout(wire_stdsync2_dout),
.reset_n((~ reset)));
pllqsys_altpll_0_altpll_r342 sd1
pllqsys_altpll_0_altpll_m342 sd1
(
.areset((w_pll_areset_in | areset)),
.clk(wire_sd1_clk),
......
examples/hdl4se_riscv/test_code/console.c
浏览文件 @ 6f8db5d8
#define UARTADDRESS (unsigned int *)0xf0000100
#define REFFREQ 50000000
#define REFFREQ 100000000
static volatile unsigned int* _uartaddr = UARTADDRESS;
static volatile unsigned int _uartstate;
......@@ -65,13 +65,7 @@ static int _gets(char* s, int buflen)
do {
ch = _getchar();
if (ch != -1) {
if (ch == '\b') {
if (ind > 0)
ind--;
}
else {
s[ind++] = ch;
}
s[ind++] = ch;
while(_putchar(ch) == -1) /* 回显 */
;
if (ind >= buflen - 1)
......@@ -294,7 +288,7 @@ static void dispmem()
for (i = 0; i < 16; i++) {
unsigned char* disp = (unsigned char*)startaddr;
char temp[2];
if (disp[i] > 0x20 && disp[i] < 0x7f) {
if (disp[i] >= 0x20 && disp[i] < 0x7f) {
temp[0] = disp[i];
}
else {
......@@ -366,9 +360,9 @@ static void printhelp()
{
_puts(" d <addr> -- display memory \n");
_puts(" b <baudrate> -- set baudrate \n");
_puts(" r <addr> <width> \n");
_puts(" w <addr> <value> <width> \n");
_puts(" width=1,2 or 4\n");
_puts(" r <addr> <width> -- read memory word\n");
_puts(" w <addr> <value> <width> -- write memory word\n");
_puts(" width=1, 2 or 4\n");
}
int main(int argc, char* argv[])
......@@ -376,17 +370,13 @@ int main(int argc, char* argv[])
volatile unsigned int* ledkey = (unsigned int*)0xF0000000;
volatile unsigned int* leddata = (unsigned int*)0xf0000010;
unsigned char ledd[20];
unsigned int test = 0;
unsigned int count0;
unsigned int count1;
unsigned int ctemp;
const unsigned char testdata[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10};
const char* hello = "Hello, World\n";
unsigned int ctemp;
_buadrateset(115200);
*(unsigned int*)(&testdata[1]) = 0x99887766;
test = *(unsigned int*)(&testdata[2]);
if (_canputchar())
_puts(hello);
count0 = 0;
count1 = 0;
do {
......@@ -409,6 +399,7 @@ int main(int argc, char* argv[])
_gets(buf, 255);
break;
}
#if 0
count0++;
if (count0 > 10000) {
count1++;
......@@ -418,6 +409,7 @@ int main(int argc, char* argv[])
ledd[1] = num2seg(ctemp / 10);
ledd[2] = num2seg(ctemp / 100);
ledd[3] = num2seg(ctemp / 1000);
/*
ctemp /= 10000;
ledd[4] = num2seg(ctemp);
ledd[5] = num2seg(ctemp / 10);
......@@ -428,22 +420,21 @@ int main(int argc, char* argv[])
ledd[9] = num2seg(ctemp / 10);
ledd[10] = num2seg(ctemp / 100);
ledd[11] = num2seg(ctemp / 1000);
*/
leddata[0] = *(unsigned int*)&ledd[0];
//leddata[1] = *(unsigned int*)&ledd[4];
//leddata[2] = *(unsigned int*)&ledd[8];
}
else {
unsigned int count = cycle()>>10;
ledd[0] = num2seg(count);
ledd[0] = num2seg(count0);
ledd[1] = num2seg(count1 / 10);
ledd[2] = num2seg(count1 / 100);
ledd[3] = num2seg(count1 / 1000);
leddata[0] = *(unsigned int*)&ledd[0];
}
#endif
} while (1);
_puts(":");
_puts("\n\r:");
_puts(buf);
_puts("\n\r");
if (_strncmp(buf, "help ", 4) == 0) {
......
examples/hdl4se_riscv/test_code/test.info
浏览文件 @ 6f8db5d8
......@@ -10,7 +10,7 @@ ELF Header:
Version: 0x1
Entry point address: 0x8c
Start of program headers: 52 (bytes into file)
Start of section headers: 20440 (bytes into file)
Start of section headers: 20312 (bytes into file)
Flags: 0x0
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
......@@ -22,28 +22,28 @@ ELF Header:
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .text PROGBITS 00000074 000074 001db0 00 AX 0 0 4
[ 2] .rodata PROGBITS 00001e24 001e24 000228 00 A 0 0 4
[ 3] .eh_frame PROGBITS 0000304c 00204c 00002c 00 WA 0 0 4
[ 4] .init_array INIT_ARRAY 00003078 002078 000008 04 WA 0 0 4
[ 5] .fini_array FINI_ARRAY 00003080 002080 000004 04 WA 0 0 4
[ 6] .data PROGBITS 00003088 002088 000428 00 WA 0 0 8
[ 7] .sdata PROGBITS 000034b0 0024b0 00000c 00 WA 0 0 4
[ 8] .sbss NOBITS 000034bc 0024bc 000008 00 WA 0 0 4
[ 9] .bss NOBITS 000034c4 0024bc 00001c 00 WA 0 0 4
[10] .comment PROGBITS 00000000 0024bc 000012 01 MS 0 0 1
[11] .riscv.attributes RISCV_ATTRIBUTE 00000000 0024ce 000025 00 0 0 1
[12] .debug_aranges PROGBITS 00000000 0024f3 000038 00 0 0 1
[13] .debug_info PROGBITS 00000000 00252b 000839 00 0 0 1
[14] .debug_abbrev PROGBITS 00000000 002d64 000216 00 0 0 1
[15] .debug_line PROGBITS 00000000 002f7a 000766 00 0 0 1
[16] .debug_str PROGBITS 00000000 0036e0 000296 01 MS 0 0 1
[17] .debug_line_str PROGBITS 00000000 003976 0000b0 01 MS 0 0 1
[18] .debug_loclists PROGBITS 00000000 003a26 000a99 00 0 0 1
[19] .debug_rnglists PROGBITS 00000000 0044bf 000111 00 0 0 1
[20] .symtab SYMTAB 00000000 0045d0 0005f0 10 21 72 4
[21] .strtab STRTAB 00000000 004bc0 000329 00 0 0 1
[22] .shstrtab STRTAB 00000000 004ee9 0000ee 00 0 0 1
[ 1] .text PROGBITS 00000074 000074 001a5c 00 AX 0 0 4
[ 2] .rodata PROGBITS 00001ad0 001ad0 000210 00 A 0 0 4
[ 3] .eh_frame PROGBITS 00002000 002000 00002c 00 WA 0 0 4
[ 4] .init_array INIT_ARRAY 0000202c 00202c 000008 04 WA 0 0 4
[ 5] .fini_array FINI_ARRAY 00002034 002034 000004 04 WA 0 0 4
[ 6] .data PROGBITS 00002038 002038 000428 00 WA 0 0 8
[ 7] .sdata PROGBITS 00002460 002460 00000c 00 WA 0 0 4
[ 8] .sbss NOBITS 0000246c 00246c 000008 00 WA 0 0 4
[ 9] .bss NOBITS 00002474 00246c 00001c 00 WA 0 0 4
[10] .comment PROGBITS 00000000 00246c 000012 01 MS 0 0 1
[11] .riscv.attributes RISCV_ATTRIBUTE 00000000 00247e 000025 00 0 0 1
[12] .debug_aranges PROGBITS 00000000 0024a3 000038 00 0 0 1
[13] .debug_info PROGBITS 00000000 0024db 000839 00 0 0 1
[14] .debug_abbrev PROGBITS 00000000 002d14 000216 00 0 0 1
[15] .debug_line PROGBITS 00000000 002f2a 000766 00 0 0 1
[16] .debug_str PROGBITS 00000000 003690 000296 01 MS 0 0 1
[17] .debug_line_str PROGBITS 00000000 003926 0000b0 01 MS 0 0 1
[18] .debug_loclists PROGBITS 00000000 0039d6 000a99 00 0 0 1
[19] .debug_rnglists PROGBITS 00000000 00446f 000111 00 0 0 1
[20] .symtab SYMTAB 00000000 004580 0005d0 10 21 71 4
[21] .strtab STRTAB 00000000 004b50 000319 00 0 0 1
[22] .shstrtab STRTAB 00000000 004e69 0000ee 00 0 0 1
Key to Flags:
W (write), A (alloc), X (execute), M (merge), S (strings), I (info),
L (link order), O (extra OS processing required), G (group), T (TLS),
......@@ -54,8 +54,8 @@ There are no section groups in this file.
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000000 0x00000000 0x00000000 0x0204c 0x0204c R E 0x1000
LOAD 0x00204c 0x0000304c 0x0000304c 0x00470 0x00494 RW 0x1000
LOAD 0x000000 0x00000000 0x00000000 0x01ce0 0x01ce0 R E 0x1000
LOAD 0x002000 0x00002000 0x00002000 0x0046c 0x00490 RW 0x1000
Section to Segment mapping:
Segment Sections...
......@@ -68,18 +68,18 @@ There are no relocations in this file.
The decoding of unwind sections for machine type RISC-V is not currently supported.
Symbol table '.symtab' contains 95 entries:
Symbol table '.symtab' contains 93 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000074 0 SECTION LOCAL DEFAULT 1 .text
2: 00001e24 0 SECTION LOCAL DEFAULT 2 .rodata
3: 0000304c 0 SECTION LOCAL DEFAULT 3 .eh_frame
4: 00003078 0 SECTION LOCAL DEFAULT 4 .init_array
5: 00003080 0 SECTION LOCAL DEFAULT 5 .fini_array
6: 00003088 0 SECTION LOCAL DEFAULT 6 .data
7: 000034b0 0 SECTION LOCAL DEFAULT 7 .sdata
8: 000034bc 0 SECTION LOCAL DEFAULT 8 .sbss
9: 000034c4 0 SECTION LOCAL DEFAULT 9 .bss
2: 00001ad0 0 SECTION LOCAL DEFAULT 2 .rodata
3: 00002000 0 SECTION LOCAL DEFAULT 3 .eh_frame
4: 0000202c 0 SECTION LOCAL DEFAULT 4 .init_array
5: 00002034 0 SECTION LOCAL DEFAULT 5 .fini_array
6: 00002038 0 SECTION LOCAL DEFAULT 6 .data
7: 00002460 0 SECTION LOCAL DEFAULT 7 .sdata
8: 0000246c 0 SECTION LOCAL DEFAULT 8 .sbss
9: 00002474 0 SECTION LOCAL DEFAULT 9 .bss
10: 00000000 0 SECTION LOCAL DEFAULT 10 .comment
11: 00000000 0 SECTION LOCAL DEFAULT 11 .riscv.attributes
12: 00000000 0 SECTION LOCAL DEFAULT 12 .debug_aranges
......@@ -93,78 +93,76 @@ Symbol table '.symtab' contains 95 entries:
20: 00000000 0 FILE LOCAL DEFAULT ABS __call_atexit.c
21: 00000074 24 FUNC LOCAL DEFAULT 1 register_fini
22: 00000000 0 FILE LOCAL DEFAULT ABS crtstuff.c
23: 0000304c 0 OBJECT LOCAL DEFAULT 3 __EH_FRAME_BEGIN__
23: 00002000 0 OBJECT LOCAL DEFAULT 3 __EH_FRAME_BEGIN__
24: 000000d8 0 FUNC LOCAL DEFAULT 1 __do_global_dtors_aux
25: 000034c4 1 OBJECT LOCAL DEFAULT 9 completed.1
26: 00003080 0 OBJECT LOCAL DEFAULT 5 __do_global_dtor[...]
25: 00002474 1 OBJECT LOCAL DEFAULT 9 completed.1
26: 00002034 0 OBJECT LOCAL DEFAULT 5 __do_global_dtor[...]
27: 0000011c 0 FUNC LOCAL DEFAULT 1 frame_dummy
28: 000034c8 24 OBJECT LOCAL DEFAULT 9 object.0
29: 0000307c 0 OBJECT LOCAL DEFAULT 4 __frame_dummy_in[...]
28: 00002478 24 OBJECT LOCAL DEFAULT 9 object.0
29: 00002030 0 OBJECT LOCAL DEFAULT 4 __frame_dummy_in[...]
30: 00000000 0 FILE LOCAL DEFAULT ABS console.c
31: 000034b4 4 OBJECT LOCAL DEFAULT 7 _uartaddr
32: 000034bc 4 OBJECT LOCAL DEFAULT 8 _uartstate
31: 00002464 4 OBJECT LOCAL DEFAULT 7 _uartaddr
32: 0000246c 4 OBJECT LOCAL DEFAULT 8 _uartstate
33: 0000013c 60 FUNC LOCAL DEFAULT 1 _canputchar
34: 00000178 64 FUNC LOCAL DEFAULT 1 _haschar
35: 000001b8 88 FUNC LOCAL DEFAULT 1 _putchar
36: 00000210 76 FUNC LOCAL DEFAULT 1 _getchar
37: 0000025c 104 FUNC LOCAL DEFAULT 1 _puts
38: 000002c4 252 FUNC LOCAL DEFAULT 1 _gets
39: 000003c0 348 FUNC LOCAL DEFAULT 1 _d2s
40: 0000051c 424 FUNC LOCAL DEFAULT 1 _h2s
41: 000006c4 252 FUNC LOCAL DEFAULT 1 _s2d
42: 000007c0 312 FUNC LOCAL DEFAULT 1 _s2h
43: 000008f8 140 FUNC LOCAL DEFAULT 1 _strcat
44: 00000984 152 FUNC LOCAL DEFAULT 1 _strncmp
45: 00000a1c 64 FUNC LOCAL DEFAULT 1 _buadrateset
46: 000034c0 4 OBJECT LOCAL DEFAULT 8 displayaddr
47: 00000a5c 628 FUNC LOCAL DEFAULT 1 dispmem
48: 00000cd0 64 FUNC LOCAL DEFAULT 1 num2seg
49: 00000d10 124 FUNC LOCAL DEFAULT 1 cycle
50: 00000d8c 124 FUNC LOCAL DEFAULT 1 instrcount
51: 00000e08 96 FUNC LOCAL DEFAULT 1 printhelp
52: 00000000 0 FILE LOCAL DEFAULT ABS libgcc2.c
53: 00000000 0 FILE LOCAL DEFAULT ABS exit.c
54: 00000000 0 FILE LOCAL DEFAULT ABS init.c
55: 00000000 0 FILE LOCAL DEFAULT ABS fini.c
56: 00000000 0 FILE LOCAL DEFAULT ABS atexit.c
57: 00000000 0 FILE LOCAL DEFAULT ABS __atexit.c
58: 00000000 0 FILE LOCAL DEFAULT ABS sys_exit.c
59: 00000000 0 FILE LOCAL DEFAULT ABS errno.c
60: 00000000 0 FILE LOCAL DEFAULT ABS libgcc2.c
61: 00000000 0 FILE LOCAL DEFAULT ABS crtstuff.c
62: 00003074 0 OBJECT LOCAL DEFAULT 3 __FRAME_END__
63: 00000000 0 FILE LOCAL DEFAULT ABS impure.c
64: 00003088 1064 OBJECT LOCAL DEFAULT 6 impure_data
65: 00000000 0 FILE LOCAL DEFAULT ABS
66: 00003084 0 NOTYPE LOCAL DEFAULT 5 __fini_array_end
67: 00003080 0 NOTYPE LOCAL DEFAULT 5 __fini_array_start
68: 00003080 0 NOTYPE LOCAL DEFAULT 4 __init_array_end
69: 00003078 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_end
70: 00003078 0 NOTYPE LOCAL DEFAULT 4 __init_array_start
71: 00003078 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_start
72: 00003888 0 NOTYPE GLOBAL DEFAULT ABS __global_pointer$
73: 00001f24 40 OBJECT GLOBAL DEFAULT 2 segcode
74: 00001e1c 8 FUNC GLOBAL DEFAULT 1 __errno
75: 000034b0 0 NOTYPE GLOBAL DEFAULT 7 __SDATA_BEGIN__
76: 000034b0 4 OBJECT GLOBAL DEFAULT 7 _global_impure_ptr
77: 00001a4c 156 FUNC GLOBAL DEFAULT 1 __libc_init_array
78: 000015ec 1072 FUNC GLOBAL HIDDEN 1 __udivdi3
79: 00001ce4 92 FUNC GLOBAL DEFAULT 1 __libc_fini_array
80: 00001bc4 288 FUNC GLOBAL DEFAULT 1 __call_exitprocs
81: 0000008c 76 FUNC GLOBAL DEFAULT 1 _start
82: 00001d54 152 FUNC GLOBAL DEFAULT 1 __register_exitproc
83: 000034e0 0 NOTYPE GLOBAL DEFAULT 9 __BSS_END__
84: 000034bc 0 NOTYPE GLOBAL DEFAULT 8 __bss_start
85: 00001ae8 220 FUNC GLOBAL DEFAULT 1 memset
86: 00000e68 1924 FUNC GLOBAL DEFAULT 1 main
87: 00001f4c 256 OBJECT GLOBAL HIDDEN 2 __clz_tab
88: 00001d40 20 FUNC GLOBAL DEFAULT 1 atexit
89: 000034b8 4 OBJECT GLOBAL DEFAULT 7 _impure_ptr
90: 00003088 0 NOTYPE GLOBAL DEFAULT 6 __DATA_BEGIN__
91: 000034bc 0 NOTYPE GLOBAL DEFAULT 7 _edata
92: 000034e0 0 NOTYPE GLOBAL DEFAULT 9 _end
93: 00001a1c 48 FUNC GLOBAL DEFAULT 1 exit
94: 00001dec 48 FUNC GLOBAL DEFAULT 1 _exit
38: 000002c4 216 FUNC LOCAL DEFAULT 1 _gets
39: 0000039c 348 FUNC LOCAL DEFAULT 1 _d2s
40: 000004f8 424 FUNC LOCAL DEFAULT 1 _h2s
41: 000006a0 252 FUNC LOCAL DEFAULT 1 _s2d
42: 0000079c 312 FUNC LOCAL DEFAULT 1 _s2h
43: 000008d4 140 FUNC LOCAL DEFAULT 1 _strcat
44: 00000960 152 FUNC LOCAL DEFAULT 1 _strncmp
45: 000009f8 64 FUNC LOCAL DEFAULT 1 _buadrateset
46: 00002470 4 OBJECT LOCAL DEFAULT 8 displayaddr
47: 00000a38 628 FUNC LOCAL DEFAULT 1 dispmem
48: 00000cac 124 FUNC LOCAL DEFAULT 1 cycle
49: 00000d28 124 FUNC LOCAL DEFAULT 1 instrcount
50: 00000da4 96 FUNC LOCAL DEFAULT 1 printhelp
51: 00000000 0 FILE LOCAL DEFAULT ABS libgcc2.c
52: 00000000 0 FILE LOCAL DEFAULT ABS exit.c
53: 00000000 0 FILE LOCAL DEFAULT ABS init.c
54: 00000000 0 FILE LOCAL DEFAULT ABS fini.c
55: 00000000 0 FILE LOCAL DEFAULT ABS atexit.c
56: 00000000 0 FILE LOCAL DEFAULT ABS __atexit.c
57: 00000000 0 FILE LOCAL DEFAULT ABS sys_exit.c
58: 00000000 0 FILE LOCAL DEFAULT ABS errno.c
59: 00000000 0 FILE LOCAL DEFAULT ABS libgcc2.c
60: 00000000 0 FILE LOCAL DEFAULT ABS crtstuff.c
61: 00002028 0 OBJECT LOCAL DEFAULT 3 __FRAME_END__
62: 00000000 0 FILE LOCAL DEFAULT ABS impure.c
63: 00002038 1064 OBJECT LOCAL DEFAULT 6 impure_data
64: 00000000 0 FILE LOCAL DEFAULT ABS
65: 00002038 0 NOTYPE LOCAL DEFAULT 5 __fini_array_end
66: 00002034 0 NOTYPE LOCAL DEFAULT 5 __fini_array_start
67: 00002034 0 NOTYPE LOCAL DEFAULT 4 __init_array_end
68: 0000202c 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_end
69: 0000202c 0 NOTYPE LOCAL DEFAULT 4 __init_array_start
70: 0000202c 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_start
71: 00002838 0 NOTYPE GLOBAL DEFAULT ABS __global_pointer$
72: 00001ac8 8 FUNC GLOBAL DEFAULT 1 __errno
73: 00002460 0 NOTYPE GLOBAL DEFAULT 7 __SDATA_BEGIN__
74: 00002460 4 OBJECT GLOBAL DEFAULT 7 _global_impure_ptr
75: 000016f8 156 FUNC GLOBAL DEFAULT 1 __libc_init_array
76: 00001298 1072 FUNC GLOBAL HIDDEN 1 __udivdi3
77: 00001990 92 FUNC GLOBAL DEFAULT 1 __libc_fini_array
78: 00001870 288 FUNC GLOBAL DEFAULT 1 __call_exitprocs
79: 0000008c 76 FUNC GLOBAL DEFAULT 1 _start
80: 00001a00 152 FUNC GLOBAL DEFAULT 1 __register_exitproc
81: 00002490 0 NOTYPE GLOBAL DEFAULT 9 __BSS_END__
82: 0000246c 0 NOTYPE GLOBAL DEFAULT 8 __bss_start
83: 00001794 220 FUNC GLOBAL DEFAULT 1 memset
84: 00000e04 1172 FUNC GLOBAL DEFAULT 1 main
85: 00001be0 256 OBJECT GLOBAL HIDDEN 2 __clz_tab
86: 000019ec 20 FUNC GLOBAL DEFAULT 1 atexit
87: 00002468 4 OBJECT GLOBAL DEFAULT 7 _impure_ptr
88: 00002038 0 NOTYPE GLOBAL DEFAULT 6 __DATA_BEGIN__
89: 0000246c 0 NOTYPE GLOBAL DEFAULT 7 _edata
90: 00002490 0 NOTYPE GLOBAL DEFAULT 9 _end
91: 000016c8 48 FUNC GLOBAL DEFAULT 1 exit
92: 00001a98 48 FUNC GLOBAL DEFAULT 1 _exit
No version information found in this file.
Attribute Section: riscv
......
examples/hdl4se_riscv/verilog/altera/alu/div.v
浏览文件 @ 6f8db5d8
......@@ -64,9 +64,9 @@ module div (
.clken (1'b1));
defparam
LPM_DIVIDE_component.lpm_drepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
LPM_DIVIDE_component.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE",
LPM_DIVIDE_component.lpm_nrepresentation = "UNSIGNED",
LPM_DIVIDE_component.lpm_pipeline = 12,
LPM_DIVIDE_component.lpm_pipeline = 32,
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 32,
LPM_DIVIDE_component.lpm_widthn = 32;
......@@ -79,16 +79,16 @@ endmodule
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "6"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "12"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "32"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
......
examples/hdl4se_riscv/verilog/altera/alu/div_bb.v
浏览文件 @ 6f8db5d8
......@@ -51,16 +51,16 @@ endmodule
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "6"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "12"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "32"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
......
examples/hdl4se_riscv/verilog/altera/alu/div_s.v
浏览文件 @ 6f8db5d8
......@@ -64,9 +64,9 @@ module div_s (
.clken (1'b1));
defparam
LPM_DIVIDE_component.lpm_drepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE",
LPM_DIVIDE_component.lpm_hint = "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE",
LPM_DIVIDE_component.lpm_nrepresentation = "SIGNED",
LPM_DIVIDE_component.lpm_pipeline = 12,
LPM_DIVIDE_component.lpm_pipeline = 32,
LPM_DIVIDE_component.lpm_type = "LPM_DIVIDE",
LPM_DIVIDE_component.lpm_widthd = 32,
LPM_DIVIDE_component.lpm_widthn = 32;
......@@ -79,16 +79,16 @@ endmodule
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "6"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "12"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "32"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
......
examples/hdl4se_riscv/verilog/altera/alu/div_s_bb.v
浏览文件 @ 6f8db5d8
......@@ -51,16 +51,16 @@ endmodule
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: PRIVATE_LPM_REMAINDERPOSITIVE STRING "TRUE"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "-1"
// Retrieval info: PRIVATE: PRIVATE_MAXIMIZE_SPEED NUMERIC "6"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USING_PIPELINE NUMERIC "1"
// Retrieval info: PRIVATE: VERSION_NUMBER NUMERIC "2"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_DREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_HINT STRING "LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE"
// Retrieval info: CONSTANT: LPM_NREPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "12"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "32"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_DIVIDE"
// Retrieval info: CONSTANT: LPM_WIDTHD NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHN NUMERIC "32"
......
examples/hdl4se_riscv/verilog/altera/alu/mulsu.v
浏览文件 @ 6f8db5d8
......@@ -37,10 +37,12 @@
`timescale 1 ps / 1 ps
// synopsys translate_on
module mulsu (
clock,
dataa,
datab,
result);
input clock;
input [31:0] dataa;
input [39:0] datab;
output [71:0] result;
......@@ -49,15 +51,16 @@ module mulsu (
wire [71:0] result = sub_wire0[71:0];
lpm_mult lpm_mult_component (
.clock (clock),
.dataa (dataa),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0),
.sum (1'b0));
defparam
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_pipeline = 4,
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 32,
......@@ -74,8 +77,8 @@ endmodule
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "4"
// Retrieval info: PRIVATE: Latency NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
......@@ -89,14 +92,17 @@ endmodule
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "40"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "72"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 40 0 INPUT NODEFVAL "datab[39..0]"
// Retrieval info: USED_PORT: result 0 0 72 0 OUTPUT NODEFVAL "result[71..0]"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 40 0 datab 0 0 40 0
// Retrieval info: CONNECT: result 0 0 72 0 @result 0 0 72 0
......
examples/hdl4se_riscv/verilog/greybox_tmp/cbx_args.txt 0 → 100644
浏览文件 @ 6f8db5d8
LPM_DREPRESENTATION=SIGNED
LPM_HINT=MAXIMIZE_SPEED=6,LPM_REMAINDERPOSITIVE=TRUE
LPM_NREPRESENTATION=SIGNED
LPM_PIPELINE=32
LPM_TYPE=LPM_DIVIDE
LPM_WIDTHD=32
LPM_WIDTHN=32
DEVICE_FAMILY="Cyclone V"
clock
denom
numer
quotient
remain
Markdown is supported
0% 或 .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑！
想要评论请 注册 或