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提交 50cd4628 编写于 作者: 饶先宏's avatar 饶先宏
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202106211844

上级 b2bacf07
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Showing with 1220 addition and 881 deletion
examples/terris/include/terrisengine1.h
浏览文件 @ 50cd4628
......@@ -169,15 +169,11 @@ enum {
ST_FLUSHTODISP,
ST_CHECKKEY,
ST_CHECKBLOCKCANSETTO,
ST_MOVEDOWN,
ST_BLOCKWRITE,
ST_CHECKLINE,
ST_COPYLINES,
};
static int BlockCanSetTo_x;
static int BlockCanSetTo_y;
static int BlockCanSetTo_res;
static int state_after_BlockCanSetTo;
static int param_after_BlockCanSet;
//static unsigned long terrisPanel[PANELHEIGHT][PANELWIDTH];
static int terrisBlockCanSetTo(TerrisBlock * pBlock, int x, int y);
static int terrisGenNewBlock(TerrisBlock * pBlock);
......
examples/terris/src/terisctrl_1.c
浏览文件 @ 50cd4628
......@@ -49,9 +49,9 @@
1: input nwReset,
2: output wWrite,
3: output[5:0] bWriteAddr,
4: output[31:0] bWriteData,
4: output[63:0] bWriteData,
5: output[5:0] bReadAddr,
6: input[31:0] bReadData,
6: input[63:0] bReadData,
7: input[31:0] bKeyData,
8: input wStateComplete,
9: output wStateChange,
......@@ -78,7 +78,6 @@ struct _sTerrisCtrl1 {
IHDL4SEUnit** readdata_unit;
int readdata_index;
IBigNumber** readdata;
IBigNumber** lastreaddata;
IHDL4SEUnit** keydata_unit;
IBigNumber** keydata;
......@@ -90,25 +89,28 @@ struct _sTerrisCtrl1 {
unsigned int write;
unsigned int writeaddr;
unsigned int writedata;
unsigned long long writedata;
unsigned int readaddr;
unsigned int write_reg;
unsigned int writeaddr_reg;
unsigned long long writedata_reg;
unsigned int readaddr_reg;
struct tagInitContext {
struct tagGenContext {
int index;
}initContext;
struct tagBlockMoveDownContext {
int index;
int state; /*0 -- movedown, 1 -- checkline*/
}blockMoveDownContext;
int complete;
int count;
int startindex;
}genContext;
struct tagBlockCanSetToContext {
int laststate;
int nextstate;
int param;
int result;
int index;
int x;
int y;
int complete;
void (*BlockCanSetToPro)(sTerrisCtrl1 * pobj);
}blockCanSetToContext;
......@@ -153,8 +155,7 @@ static int terrisctrl1Create(const PARAMITEM* pParams, int paramcount, HOBJECT*
pobj->statecomplete_unit = NULL;
pobj->statecompletedata = bigintegerCreate(1);
pobj->readdata_unit = NULL;
pobj->readdata = bigintegerCreate(32);
pobj->lastreaddata = bigintegerCreate(32);
pobj->readdata = bigintegerCreate(64);
for (i = 0; i < paramcount; i++) {
if (pParams[i].name == PARAMID_HDL4SE_UNIT_NAME) {
if (pobj->name != NULL)
......@@ -165,7 +166,7 @@ static int terrisctrl1Create(const PARAMITEM* pParams, int paramcount, HOBJECT*
pobj->parent = (IHDL4SEModule **)pParams[i].pvalue;
}
}
pobj->initContext.index = 0;
pobj->genContext.index = 0;
pobj->write = 0;
pobj->state = ST_INIT;
pobj->laststate = ST_INIT;
......@@ -246,16 +247,16 @@ static int terrisctrl1_hdl4se_unit_GetValue(HOBJECT object, int index, int width
sTerrisCtrl1* pobj;
pobj = (sTerrisCtrl1*)objectThis(object);
if (index == 2) {
objectCall1(value, AssignUint32, pobj->write);
objectCall1(value, AssignUint32, pobj->write_reg);
}
else if (index == 3) {
objectCall1(value, AssignUint32, pobj->writeaddr);
objectCall1(value, AssignUint32, pobj->writeaddr_reg);
}
else if (index == 4) {
objectCall1(value, AssignUint32, pobj->writedata);
objectCall1(value, AssignUint64, pobj->writedata_reg);
}
else if (index == 5) {
objectCall1(value, AssignUint32, pobj->readaddr);
objectCall1(value, AssignUint32, pobj->readaddr_reg);
}
else if (index == 9) {
objectCall1(value, AssignUint32, pobj->state != pobj->laststate);
......@@ -317,27 +318,26 @@ static void terrisctrl1_hdl4se_unit_PressKeyPro(sTerrisCtrl1* pobj)
currentblock.posx++;
break;
case TK_TURNLEFT:/*逆时针1*/
terrisBlockRotate(&currentblock, 1);
if (pobj->blockCanSetToContext.result == 0)
terrisBlockRotate(&currentblock, 0);
break;
case TK_TURNRIGHT:/*顺时针0*/
terrisBlockRotate(&currentblock, 0);
if (pobj->blockCanSetToContext.result == 0)
terrisBlockRotate(&currentblock, 1);
break;
}
}
static void terrisctrl1_hdl4se_unit_MoveDownPro2(sTerrisCtrl1* pobj)
static void terrisctrl1_hdl4se_unit_AfterCheckLine(sTerrisCtrl1* pobj)
{
if (pobj->blockCanSetToContext.result == 0) {
terrisInit();
pobj->initContext.index = 0;
pobj->genContext.index = 0;
pobj->state = ST_INIT;
}
else {
terrisGenNewBlock(&nextblock);
pobj->state = ST_FLUSHTODISP;
}
}
......@@ -348,51 +348,127 @@ static void terrisctrl1_hdl4se_unit_MoveDownPro(sTerrisCtrl1* pobj)
currentblock.posy++;
}
else {
pobj->blockMoveDownContext.state = 0;
pobj->blockMoveDownContext.index = 0;
pobj->genContext.index = 0;
pobj->state = ST_BLOCKWRITE;
}
return;
}
static void terrisctrl1_hdl4se_unit_BlockWrite(sTerrisCtrl1* pobj)
{
/*先读后写*/
int i, x, y;
i = pobj->genContext.index;
y = currentblock.posy - BLOCKSIZE / 2 + i+1;
pobj->readaddr = YCOUNT-1-y;
pobj->write = 0;
pobj->genContext.complete = 0;
if (pobj->genContext.index > 1) {
unsigned long long line;
unsigned long long blockline;
i = pobj->genContext.index - 2; /*数据比索引晚两拍*/
y = currentblock.posy - BLOCKSIZE / 2 + i+1;
x = currentblock.posx - BLOCKSIZE / 2;
if (y < YCOUNT && y>=0) {
blockline = currentblock.subblock[i][3] & 0xF;
blockline <<= 4;
blockline |= currentblock.subblock[i][2] & 0xF;
blockline <<= 4;
blockline |= currentblock.subblock[i][1] & 0xF;
blockline <<= 4;
blockline |= currentblock.subblock[i][0] & 0xF;
pobj->writeaddr = YCOUNT - 1 - y;
pobj->write = 1;
objectCall3(pobj->readdata_unit, GetValue, pobj->readdata_index, 64, pobj->readdata);
objectCall1(pobj->readdata, GetUint64, &line);
if (x < 0)
pobj->writedata = line | (blockline >> (-x * 4));
else
pobj->writedata = line | (blockline << (x * 4));
}
}
pobj->genContext.index++;
if (pobj->genContext.index > BLOCKSIZE + 1) {
pobj->genContext.complete = 1;
}
}
static void terrisctrl1_hdl4se_unit_CopyLines(sTerrisCtrl1* pobj)
{
pobj->readaddr = pobj->genContext.index + 1;
pobj->write = 0;
if (pobj->genContext.index - pobj->genContext.startindex > 1) {
int index = pobj->genContext.index - 1;
unsigned long long line;
if (index == YCOUNT-1) {
line = 0;
}
else {
objectCall3(pobj->readdata_unit, GetValue, pobj->readdata_index, 64, pobj->readdata);
objectCall1(pobj->readdata, GetUint64, &line);
}
if (index < YCOUNT) {
pobj->write = 1;
pobj->writeaddr = index;
pobj->writedata = line;
}
if (index >= YCOUNT || line == 0) {
pobj->genContext.index = 0;
pobj->state = ST_CHECKLINE;
return;
}
}
pobj->genContext.index++;
}
static void terrisctrl1_hdl4se_unit_CheckLine(sTerrisCtrl1* pobj)
{
pobj->readaddr = pobj->genContext.index;
pobj->genContext.complete = 0;
if (pobj->genContext.index > 1) {
unsigned long long line = 0;
int i;
int j;
for (i = 0; i < BLOCKSIZE; i++)
{
for (j = 0; j < BLOCKSIZE; j++)
{
if (currentblock.subblock[i][j] != 0)
{
int xx, yy;
xx = currentblock.posx - BLOCKSIZE / 2 + j;
yy = currentblock.posy - BLOCKSIZE / 2 + i;
if (yy < 0)
continue;
if (yy >= PANELHEIGHT)
continue;
if (xx < 0)
continue;
if (xx >= PANELWIDTH)
continue;
//if (terrisPanel[yy][xx] != 0)
// continue;
//terrisPanel[yy][xx] = currentblock.subblock[i][j];
}
}
objectCall3(pobj->readdata_unit, GetValue, pobj->readdata_index, 64, pobj->readdata);
objectCall1(pobj->readdata, GetUint64, &line);
for (i = 0; i < XCOUNT; i++) {
if ((line & 0xf) == 0)
break;
line >>= 4;
}
terrisCheckLine();
if (i == XCOUNT) {
pobj->genContext.index -= 2;
pobj->genContext.startindex = pobj->genContext.index;
pobj->readaddr = pobj->genContext.index + 1;
pobj->state = ST_COPYLINES;
pobj->genContext.count++;
return;
}
}
if (pobj->genContext.index >= YCOUNT + 1) {
pobj->genContext.complete = 1;
}
pobj->genContext.index++;
if (pobj->genContext.complete) {
memcpy(&currentblock, &nextblock, sizeof(currentblock));
pobj->blockCanSetToContext.laststate = ST_MOVEDOWN;
pobj->blockCanSetToContext.nextstate = ST_FLUSHTODISP;
pobj->blockCanSetToContext.param = 0;
pobj->blockCanSetToContext.result = 0;
pobj->blockCanSetToContext.complete = 0;
pobj->blockCanSetToContext.index = 0;
pobj->blockCanSetToContext.BlockCanSetToPro = terrisctrl1_hdl4se_unit_MoveDownPro2;
pobj->blockCanSetToContext.BlockCanSetToPro = terrisctrl1_hdl4se_unit_AfterCheckLine;
pobj->blockCanSetToContext.x = currentblock.posx;
pobj->blockCanSetToContext.y = currentblock.posy;
pobj->state = ST_CHECKBLOCKCANSETTO;
}
}
static int terrisctrl1_hdl4se_unit_MoveDown(sTerrisCtrl1* pobj)
{
pobj->blockCanSetToContext.laststate = ST_MOVEDOWN;
pobj->blockCanSetToContext.nextstate = ST_FLUSHTODISP;
pobj->blockCanSetToContext.param = 0;
pobj->blockCanSetToContext.result = 0;
pobj->blockCanSetToContext.complete = 0;
pobj->blockCanSetToContext.index = 0;
pobj->blockCanSetToContext.BlockCanSetToPro = terrisctrl1_hdl4se_unit_MoveDownPro;
pobj->blockCanSetToContext.x = currentblock.posx;
......@@ -413,11 +489,12 @@ static int terrisctrl1_hdl4se_unit_Tick(sTerrisCtrl1* pobj)
}
static int terrisctrl1_hdl4se_unit_PressKeyStart(sTerrisCtrl1* pobj, int key)
static void terrisctrl1_hdl4se_unit_PressKeyStart(sTerrisCtrl1* pobj, int key)
{
pobj->blockCanSetToContext.laststate = ST_FLUSHTODISP;
pobj->blockCanSetToContext.nextstate = ST_FLUSHTODISP;
pobj->blockCanSetToContext.param = key;
pobj->blockCanSetToContext.result = 0;
pobj->blockCanSetToContext.complete = 0;
pobj->blockCanSetToContext.index = 0;
pobj->blockCanSetToContext.BlockCanSetToPro = terrisctrl1_hdl4se_unit_PressKeyPro;
pobj->state = ST_CHECKBLOCKCANSETTO;
......@@ -453,11 +530,83 @@ static int terrisctrl1_hdl4se_unit_PressKeyStart(sTerrisCtrl1* pobj, int key)
currenttick = 0;
if (gameScore < 0) {
terrisInit();
pobj->initContext.index = 0;
pobj->genContext.index = 0;
pobj->state = ST_INIT;
}
}
static void terrisctrl1_hdl4se_unit_BlockCanSetTo(sTerrisCtrl1* pobj, TerrisBlock* pBlock, int x, int y)
{
#define RETURNRESULT(res) \
do { \
pobj->blockCanSetToContext.result = res; \
pobj->blockCanSetToContext.complete = 1; \
goto BlockCanSetTo_return; \
} while (0)
int i;
int j;
int yy;
i = pobj->blockCanSetToContext.index / BLOCKSIZE;
yy = y - BLOCKSIZE / 2 + i + 1;
pobj->readaddr = YCOUNT - 1 - yy;
pobj->write = 0;
pobj->blockCanSetToContext.complete = 0;
if (pobj->blockCanSetToContext.index > 1) {
/*从进入这个状态的第二个周期开始进行判断，此时数据已经读入到端口上*/
i = (pobj->blockCanSetToContext.index-2) / BLOCKSIZE;
j = (pobj->blockCanSetToContext.index-2) % BLOCKSIZE;
if (pBlock->subblock[i][j] != 0) {
int xx, yy;
unsigned long long line;
xx = x - BLOCKSIZE / 2 + j;
yy = y - BLOCKSIZE / 2 + i;
if (yy < 0)
goto BlockCanSetTo_return;
if (yy >= PANELHEIGHT-1)
RETURNRESULT(0);
if (xx < 0)
RETURNRESULT(0);
if (xx >= PANELWIDTH)
RETURNRESULT(0);
objectCall3(pobj->readdata_unit, GetValue, pobj->readdata_index, 64, pobj->readdata);
objectCall1(pobj->readdata, GetUint64, &line);
line >>= xx * 4;
line &= 0xF;
if (line != 0)
RETURNRESULT(0);
}
}
if (pobj->blockCanSetToContext.index > BLOCKSIZE * BLOCKSIZE) {
pobj->blockCanSetToContext.complete = 1;
pobj->blockCanSetToContext.result = 1;
}
BlockCanSetTo_return :
pobj->blockCanSetToContext.index++;
return;
}
static void terrisctrl1_hdl4se_unit_Init(sTerrisCtrl1* pobj)
{
if (pobj->genContext.index < YCOUNT) {
int i;
unsigned long long data = 0;
for (i = 0; i < 16; i++) {
int c;
c = ((pobj->genContext.index * (pobj->genContext.index + 2 + i)) % 14) + 2;
data <<= 4;
data |= c;
}
pobj->write = 1;
pobj->writeaddr = pobj->genContext.index;
pobj->writedata = 0;
pobj->genContext.index++;
pobj->genContext.complete = 0;
}
else {
pobj->genContext.complete = 1;
}
}
static int terrisctrl1_hdl4se_unit_ClkTick(HOBJECT object)
{
sTerrisCtrl1* pobj;
......@@ -468,13 +617,8 @@ static int terrisctrl1_hdl4se_unit_ClkTick(HOBJECT object)
pobj->write = 0;
if (pobj->state == ST_INIT) {
if (pobj->initContext.index < YCOUNT * 2) {
pobj->write = 1;
pobj->writeaddr = pobj->initContext.index;
pobj->writedata = 0;
pobj->initContext.index++;
}
else {
terrisctrl1_hdl4se_unit_Init(pobj);
if (pobj->genContext.complete) {
pobj->state = ST_FLUSHTODISP;
}
}
......@@ -503,12 +647,26 @@ static int terrisctrl1_hdl4se_unit_ClkTick(HOBJECT object)
}
}
else if (pobj->state == ST_CHECKBLOCKCANSETTO) {
pobj->state = pobj->blockCanSetToContext.laststate;
pobj->blockCanSetToContext.result = terrisBlockCanSetTo(&currentblock, pobj->blockCanSetToContext.x, pobj->blockCanSetToContext.y);
pobj->blockCanSetToContext.BlockCanSetToPro(pobj);
terrisctrl1_hdl4se_unit_BlockCanSetTo(pobj, &currentblock, pobj->blockCanSetToContext.x, pobj->blockCanSetToContext.y);
if (pobj->blockCanSetToContext.complete) {
pobj->state = pobj->blockCanSetToContext.nextstate;
pobj->blockCanSetToContext.BlockCanSetToPro(pobj);
}
}
else if (pobj->state == ST_MOVEDOWN) {
pobj->state = ST_FLUSHTODISP;
else if (pobj->state == ST_BLOCKWRITE) {
terrisctrl1_hdl4se_unit_BlockWrite(pobj);
if (pobj->genContext.complete) {
pobj->state = ST_CHECKLINE;
pobj->genContext.complete = 0;
pobj->genContext.index = 0;
pobj->genContext.count = 0;
}
}
else if (pobj->state == ST_CHECKLINE) {
terrisctrl1_hdl4se_unit_CheckLine(pobj);
}
else if (pobj->state == ST_COPYLINES) {
terrisctrl1_hdl4se_unit_CopyLines(pobj);
}
else {
pobj->state = ST_FLUSHTODISP;
......@@ -521,6 +679,10 @@ static int terrisctrl1_hdl4se_unit_Setup(HOBJECT object)
sTerrisCtrl1* pobj;
pobj = (sTerrisCtrl1*)objectThis(object);
pobj->laststate = pobj->state;
pobj->write_reg = pobj->write;
pobj->writeaddr_reg = pobj->writeaddr;
pobj->writedata_reg = pobj->writedata;
pobj->readaddr_reg = pobj->readaddr;
return 0;
}
examples/terris/src/topmodule.c
浏览文件 @ 50cd4628
此差异已折叠。
examples/terris/verilog/main_1.v
浏览文件 @ 50cd4628
......@@ -45,9 +45,9 @@ module teris_ctrl
input nwReset,
output wWrite,
output [5:0] bWriteAddr,
output [31:0] bWriteData,
output [63:0] bWriteData,
output [5:0] bReadAddr,
input [31:0] bReadData,
input [63:0] bReadData,
input [31:0] bKeyData,
input wStateComplete,
output wStateChange,
......@@ -64,58 +64,22 @@ endmodule
`define ST_INIT 0
`define ST_FLUSHTODISP 1
module main(
input wClk, nwReset,
output wWrite,
output [31:0] bWriteAddr,
output [31:0] bWriteData,
output [3:0] bWriteMask,
output wRead,
output [31:0] bReadAddr,
input [31:0] bReadData);
/*
wire wClk, nwReset;
wire wWrite;
wire [31:0] bWriteAddr, bWriteData;
wire [3:0] bWriteMask;
wire wRead;
wire [31:0] bReadAddr;
wire [31:0] bReadData;
*/
wire wram_Write;
wire [5:0] bram_WriteAddr;
wire [31:0] bram_WriteData;
wire [5:0] bram_ReadAddr;
wire [31:0] bram_ReadData;
/* 帧存存储器 */
hdl4se_ram1p #(32, 6) ram_0(
wClk,
wram_Write,
bram_WriteAddr,
bram_WriteData,
bram_ReadAddr,
bram_ReadData
);
/* 游戏控制器 */
wire wCtrlWrite;
wire [5:0] bCtrlWriteAddr;
wire [31:0] bCtrlWriteData;
wire [5:0] bCtrlReadAddr;
wire [31:0] bCtrlReadData;
wire [31:0] bCtrlKeyData;
wire wCtrlStateComplete;
wire wCtrlStateChange;
wire [3:0] bCtrlState;
wire [31:0] bCtrlSpeed;
wire [31:0] bCtrlLevel;
wire [31:0] bCtrlScore;
wire [63:0] bNextBlock;
wire [63:0] bCurBlock;
wire [15:0] bCurBlockPos;
module flushtodisp(
input wClk,
input [3:0] bCtrlState,
output wCtrlStateComplete,
output [5:0] bFlushReadAddr,
input [63:0] bFlushReadData,
output wWrite,
output [31:0] bWriteAddr,
output [31:0] bWriteData,
input [31:0] bCtrlSpeed,
input [31:0] bCtrlLevel,
input [31:0] bCtrlScore,
input [63:0] bNextBlock,
input [63:0] bCurBlock,
input [15:0] bCurBlockPos
);
wire [31:0] bNextBlockLo = bNextBlock[31:0];
wire [31:0] bNextBlockHi = bNextBlock[63:32];
......@@ -124,29 +88,13 @@ module main(
wire [4:0] bCurBlockX = bCurBlockPos[4:0];
wire [4:0] bCurBlockY = bCurBlockPos[12:8];
teris_ctrl ctrl(wClk, nwReset, wCtrlWrite, bCtrlWriteAddr, bCtrlWriteData,
bCtrlReadAddr,bCtrlReadData, bCtrlKeyData,
wCtrlStateComplete, wCtrlStateChange, bCtrlState,
bCtrlScore, bCtrlSpeed, bCtrlLevel,
bNextBlock, bCurBlock, bCurBlockPos);
assign wram_Write = (bCtrlState == `ST_FLUSHTODISP) ? 1'b0 : wCtrlWrite; /*刷新模块不写ram*/
assign bram_WriteAddr = (bCtrlState == `ST_FLUSHTODISP) ? 6'b0 : bCtrlWriteAddr;
assign bram_WriteData = (bCtrlState == `ST_FLUSHTODISP) ? 32'b0 : bCtrlWriteData;
assign bram_ReadAddr = (bCtrlState == `ST_FLUSHTODISP) ? bFlushReadAddr : bCtrlReadAddr;
assign bCtrlReadData = bram_ReadData;
assign bFlushReadData = bram_ReadData;
wire [5:0] bFlushReadAddr;
wire [31:0] bFlushReadData;
/* 目前编译器还不支持reg和always块，因此直接用基本单元来做寄存器 */
wire [6:0] wirein_readaddr, wireout_readaddr, wireout_readaddr_delay_1;
wire [7:0] wirein_readaddr, wireout_readaddr, wireout_readaddr_delay_1;
wire[31:0] wireout_readaddr2;
hdl4se_reg #(6) ramreadaddr(wClk, wirein_readaddr, wireout_readaddr);
hdl4se_reg #(6) ramreadaddr_delay_1(wClk, wireout_readaddr, wireout_readaddr_delay_1);
assign wirein_readaddr = (bCtrlState == `ST_FLUSHTODISP) ? wireout_readaddr + 1 : 6'b0;
assign bFlushReadAddr = wireout_readaddr;
assign bFlushReadAddr = wireout_readaddr[6:1];
assign wCtrlStateComplete = wireout_readaddr == 6'd60;
assign bWriteAddr = 32'hf000_0010 + wireout_readaddr_delay_1 * 4;
assign wWrite = (bCtrlState == `ST_FLUSHTODISP) ? 1 : 0;
......@@ -159,7 +107,7 @@ module main(
58 : speed --> 6
*/
wire [4:0] line = wireout_readaddr_delay_1[5:1];
wire right = wireout_readaddr_delay_1[0:0];
wire right = wireout_readaddr_delay_1[0];
wire [15:0] line3 = ((line + 2) == bCurBlockY) ? 16'hffff:16'b0;
wire [15:0] line2 = ((line + 1) == bCurBlockY) ? 16'hffff:16'b0;
wire [15:0] line1 = (line == bCurBlockY) ? 16'hffff:16'b0;
......@@ -171,8 +119,20 @@ module main(
hdl4se_bind2 #(16, 16) curlinebind(curblockline, selecteddata[31:16], curline);
wire [31:0] leftline_0_15;
wire [31:0] leftline = bCurBlockX[5:4]?selecteddata:leftline_0_15;
wire [31:0] leftline = bCurBlockX[5:4]?selecteddata:(leftline_0_15 | selecteddata);
wire [31:0] leftline_1, leftline0, leftline1, leftline2, leftline3, leftline4, leftline5, leftline6, leftline7, leftline8, leftline9;
hdl4se_bind2 #(4, 28) leftline0_gen(curblockline[15:12], 28'b0, leftline_1);
hdl4se_bind2 #(8, 24) leftline0_gen(curblockline[15:8], 24'b0, leftline0);
hdl4se_bind2 #(12, 20) leftline1_gen(curblockline[15:4], 20'b0, leftline1);
hdl4se_bind2 #(16, 16) leftline2_gen(curblockline[15:0], 16'b0, leftline2);
hdl4se_bind3 #(4, 16, 12) leftline3_gen(4'b0, curblockline[15:0], 12'b0, leftline3);
hdl4se_bind3 #(8, 16, 8) leftline4_gen(8'b0, curblockline[15:0], 8'b0, leftline4);
hdl4se_bind3 #(12,16, 4) leftline5_gen(12'b0, curblockline[15:0], 4'b0, leftline5);
hdl4se_bind2 #(16, 16) leftline6_gen(16'b0, curblockline[15:0], leftline6);
hdl4se_bind2 #(20, 12) leftline7_gen(20'b0, curblockline[11:0], leftline7);
hdl4se_bind2 #(24, 8) leftline8_gen(24'b0, curblockline[7:0], leftline8);
hdl4se_bind2 #(28, 4) leftline9_gen(28'b0, curblockline[3:0], leftline9);
/*
hdl4se_bind2 #(4, 28) leftline0_gen(curblockline[15:12], selecteddata[27:0], leftline_1);
hdl4se_bind2 #(8, 24) leftline0_gen(curblockline[15:8], selecteddata[23:0], leftline0);
hdl4se_bind2 #(12, 20) leftline1_gen(curblockline[15:4], selecteddata[19:0], leftline1);
......@@ -184,7 +144,7 @@ module main(
hdl4se_bind2 #(20, 12) leftline7_gen(selecteddata[31:12], curblockline[11:0], leftline7);
hdl4se_bind2 #(24, 8) leftline8_gen(selecteddata[31:8], curblockline[7:0], leftline8);
hdl4se_bind2 #(28, 4) leftline9_gen(selecteddata[31:4], curblockline[3:0], leftline9);
*/
hdl4se_mux16 #(32) selectleftline(
bCurBlockX[3:0],
leftline_1,
......@@ -207,19 +167,32 @@ module main(
);
wire [31:0] rightline_3_18;
wire [31:0] rightline = (bCurBlockX[5:0]>=3)?rightline_3_18:selecteddata;
wire [31:0] rightline = (bCurBlockX[5:0]>=3)?(rightline_3_18|selecteddata):selecteddata;
wire [31:0] rightline0, rightline1, rightline2, rightline3, rightline4, rightline5, rightline6, rightline7, rightline8, rightline9, rightline10;
hdl4se_bind2 #(4, 28) rightline0_gen(curblockline[15:12], selecteddata[27:0], rightline0);
hdl4se_bind2 #(8, 24) rightline1_gen(curblockline[15:8], selecteddata[23:0], rightline1);
hdl4se_bind2 #(12, 20) rightline2_gen(curblockline[15:4], selecteddata[19:0], rightline2);
hdl4se_bind2 #(16, 16) rightline3_gen(curblockline[15:0], selecteddata[15:0], rightline3);
hdl4se_bind3 #(4, 16, 12) rightline4_gen(selecteddata[31:28], curblockline[15:0], selecteddata[11:0], rightline4);
hdl4se_bind3 #(8, 16, 8) rightline5_gen(selecteddata[31:24], curblockline[15:0], selecteddata[7:0], rightline5);
hdl4se_bind3 #(12, 16, 4) rightline6_gen(selecteddata[31:20], curblockline[15:0], selecteddata[3:0], rightline6);
hdl4se_bind2 #(16, 16) rightline7_gen(selecteddata[31:16], curblockline[15:0], rightline7);
hdl4se_bind2 #(20, 12) rightline8_gen(selecteddata[31:12], curblockline[11:0], rightline8);
hdl4se_bind2 #(24, 8) rightline9_gen(selecteddata[31:8], curblockline[7:0], rightline9);
hdl4se_bind2 #(28, 4) rightline10_gen(selecteddata[31:4], curblockline[3:0], rightline10);
/*
hdl4se_bind2 #(4, 28) rightline0_gen(curblockline[15:12], 28'b0 | selecteddata[31:28], selecteddata[27:0], rightline0);
hdl4se_bind2 #(8, 24) rightline1_gen(curblockline[15:8] | selecteddata[31:24], selecteddata[23:0], rightline1);
hdl4se_bind2 #(12, 20) rightline2_gen(curblockline[15:4] | selecteddata[31:20], selecteddata[19:0], rightline2);
hdl4se_bind2 #(16, 16) rightline3_gen(curblockline[15:0] | selecteddata[31:16], selecteddata[15:0], rightline3);
hdl4se_bind3 #(4, 16, 12) rightline4_gen(selecteddata[31:28], curblockline[15:0] | selecteddata[27:12], selecteddata[11:0], rightline4);
hdl4se_bind3 #(8, 16, 8) rightline5_gen(selecteddata[31:24], curblockline[15:0] | selecteddata[23:8], selecteddata[7:0], rightline5);
hdl4se_bind3 #(12, 16, 4) rightline6_gen(selecteddata[31:20], curblockline[15:0] | selecteddata[19:4], selecteddata[3:0], rightline6);
hdl4se_bind2 #(16, 16) rightline7_gen(selecteddata[31:16], curblockline[15:0] | selecteddata[15:0], rightline7);
hdl4se_bind2 #(20, 12) rightline8_gen(selecteddata[31:12], curblockline[11:0] | selecteddata[11:0], rightline8);
hdl4se_bind2 #(24, 8) rightline9_gen(selecteddata[31:8], curblockline[7:0] | selecteddata[7:0], rightline9);
hdl4se_bind2 #(28, 4) rightline10_gen(selecteddata[31:4], curblockline[3:0] | selecteddata[3:0], rightline10);
*/
hdl4se_bind2 #(4, 28) rightline0_gen(curblockline[15:12], 28'b0, rightline0);
hdl4se_bind2 #(8, 24) rightline1_gen(curblockline[15:8], 24'b0, rightline1);
hdl4se_bind2 #(12, 20) rightline2_gen(curblockline[15:4], 20'b0, rightline2);
hdl4se_bind2 #(16, 16) rightline3_gen(curblockline[15:0], 16'b0,rightline3);
hdl4se_bind3 #(4, 16, 12) rightline4_gen(4'b0, curblockline[15:0], 12'b0, rightline4);
hdl4se_bind3 #(8, 16, 8) rightline5_gen(8'b0, curblockline[15:0], 8'b0, rightline5);
hdl4se_bind3 #(12, 16, 4) rightline6_gen(12'b0, curblockline[15:0], 4'b0, rightline6);
hdl4se_bind2 #(16, 16) rightline7_gen(16'b0, curblockline[15:0], rightline7);
hdl4se_bind2 #(20, 12) rightline8_gen(20'b0, curblockline[11:0], rightline8);
hdl4se_bind2 #(24, 8) rightline9_gen(24'b0, curblockline[7:0], rightline9);
hdl4se_bind2 #(28, 4) rightline10_gen(28'b0, curblockline[3:0], rightline10);
wire [5:0] blockx_3 = bCurBlockX[5:0] - 6'd3;
hdl4se_mux16 #(32) selectrightline(
blockx_3[3:0],
......@@ -252,9 +225,78 @@ module main(
bCtrlScore,
bCtrlLevel,
bCtrlSpeed,
bram_ReadData,
right?bFlushReadData[63:32]:bFlushReadData[31:0],
selecteddata
);
endmodule
module main(
input wClk, nwReset,
output wWrite,
output [31:0] bWriteAddr,
output [31:0] bWriteData,
output [3:0] bWriteMask,
output wRead,
output [31:0] bReadAddr,
input [31:0] bReadData);
wire wram_Write;
wire [5:0] bram_WriteAddr;
wire [63:0] bram_WriteData;
wire [5:0] bram_ReadAddr;
wire [63:0] bram_ReadData;
/* 帧存存储器 */
hdl4se_ram1p #(64, 6) ram_0(
wClk,
wram_Write,
bram_WriteAddr,
bram_WriteData,
bram_ReadAddr,
bram_ReadData
);
/* 游戏控制器 */
wire wCtrlWrite;
wire [5:0] bCtrlWriteAddr;
wire [63:0] bCtrlWriteData;
wire [5:0] bCtrlReadAddr;
wire [63:0] bCtrlReadData;
wire [31:0] bCtrlKeyData;
wire wCtrlStateComplete;
wire wCtrlStateChange;
wire [3:0] bCtrlState;
wire [31:0] bCtrlSpeed;
wire [31:0] bCtrlLevel;
wire [31:0] bCtrlScore;
wire [63:0] bNextBlock;
wire [63:0] bCurBlock;
wire [15:0] bCurBlockPos;
teris_ctrl ctrl(wClk, nwReset, wCtrlWrite, bCtrlWriteAddr, bCtrlWriteData,
bCtrlReadAddr,bCtrlReadData, bCtrlKeyData,
wCtrlStateComplete, wCtrlStateChange, bCtrlState,
bCtrlScore, bCtrlSpeed, bCtrlLevel,
bNextBlock, bCurBlock, bCurBlockPos);
wire [5:0] bFlushReadAddr;
wire [63:0] bFlushReadData;
/* 屏幕刷新 */
flushtodisp flusher(wClk,
bCtrlState, wCtrlStateComplete,
bFlushReadAddr, bFlushReadData,
wWrite, bWriteAddr, bWriteData,
bCtrlSpeed, bCtrlLevel, bCtrlScore,
bNextBlock, bCurBlock, bCurBlockPos);
/* ram读写口仲裁 */
assign wram_Write = (bCtrlState == `ST_FLUSHTODISP) ? 1'b0 : wCtrlWrite; /*刷新模块不写ram*/
assign bram_WriteAddr = (bCtrlState == `ST_FLUSHTODISP) ? 6'b0 : bCtrlWriteAddr;
assign bram_WriteData = (bCtrlState == `ST_FLUSHTODISP) ? 64'b0 : bCtrlWriteData;
assign bram_ReadAddr = (bCtrlState == `ST_FLUSHTODISP) ? bFlushReadAddr : bCtrlReadAddr;
assign bCtrlReadData = bram_ReadData;
assign bFlushReadData = bram_ReadData;
/*我们一直在读按键的状态*/
assign wRead = 1'b1;
......
examples/terris/verilog/main_asm.v
浏览文件 @ 50cd4628
......@@ -434,9 +434,9 @@ module teris_ctrl
input nwReset,
output wWrite,
output [5:0] bWriteAddr,
output [31:0] bWriteData,
output [63:0] bWriteData,
output [5:0] bReadAddr,
input [31:0] bReadData,
input [63:0] bReadData,
input [31:0] bKeyData,
input wStateComplete,
output wStateChange,
......@@ -452,50 +452,33 @@ module teris_ctrl
endmodule
module main
module flushtodisp
(
input wClk,
input nwReset,
input [3:0] bCtrlState,
output wCtrlStateComplete,
output [5:0] bFlushReadAddr,
input [63:0] bFlushReadData,
output wWrite,
output [31:0] bWriteAddr,
output [31:0] bWriteData,
output [3:0] bWriteMask,
output wRead,
output [31:0] bReadAddr,
input [31:0] bReadData
input [31:0] bCtrlSpeed,
input [31:0] bCtrlLevel,
input [31:0] bCtrlScore,
input [63:0] bNextBlock,
input [63:0] bCurBlock,
input [15:0] bCurBlockPos
)
;
wire wram_Write;
wire [5:0] bram_WriteAddr;
wire [31:0] bram_WriteData;
wire [5:0] bram_ReadAddr;
wire [31:0] bram_ReadData;
wire wCtrlWrite;
wire [5:0] bCtrlWriteAddr;
wire [31:0] bCtrlWriteData;
wire [5:0] bCtrlReadAddr;
wire [31:0] bCtrlReadData;
wire [31:0] bCtrlKeyData;
wire wCtrlStateComplete;
wire wCtrlStateChange;
wire [3:0] bCtrlState;
wire [31:0] bCtrlSpeed;
wire [31:0] bCtrlLevel;
wire [31:0] bCtrlScore;
wire [63:0] bNextBlock;
wire [63:0] bCurBlock;
wire [15:0] bCurBlockPos;
wire [31:0] bNextBlockLo;
wire [31:0] bNextBlockHi;
wire [31:0] bCurBlockLo;
wire [31:0] bCurBlockHi;
wire [4:0] bCurBlockX;
wire [4:0] bCurBlockY;
wire [5:0] bFlushReadAddr;
wire [31:0] bFlushReadData;
wire [6:0] wirein_readaddr;
wire [6:0] wireout_readaddr;
wire [6:0] wireout_readaddr_delay_1;
wire [7:0] wirein_readaddr;
wire [7:0] wireout_readaddr;
wire [7:0] wireout_readaddr_delay_1;
wire [31:0] wireout_readaddr2;
wire [2:0] bWriteDataSel;
wire [4:0] line;
......@@ -534,21 +517,12 @@ module main
wire [31:0] rightline9;
wire [31:0] rightline10;
wire [5:0] blockx_3;
assign wram_Write = bCtrlState==1?1'b0:wCtrlWrite;
assign bram_WriteAddr = bCtrlState==1?6'b0:bCtrlWriteAddr;
assign bram_WriteData = bCtrlState==1?32'b0:bCtrlWriteData;
assign bram_ReadAddr = bCtrlState==1?bFlushReadAddr:bCtrlReadAddr;
assign bCtrlReadData = bram_ReadData;
assign bFlushReadData = bram_ReadData;
assign wirein_readaddr = bCtrlState==1?wireout_readaddr+1:6'b0;
assign bFlushReadAddr = wireout_readaddr;
assign bFlushReadAddr = wireout_readaddr [6:1] ;
assign wCtrlStateComplete = wireout_readaddr==6'd60;
assign bWriteAddr = 32'hf0000010+wireout_readaddr_delay_1*4;
assign wWrite = bCtrlState==1?1:0;
assign bWriteData = curblockline!=16'b0?right?rightline:leftline:selecteddata;
assign wRead = 32'h1;
assign bReadAddr = 32'hf0000000;
assign bCtrlKeyData = bReadData;
assign bNextBlockLo = bNextBlock [31:0] ;
assign bNextBlockHi = bNextBlock [63:32] ;
assign bCurBlockLo = bCurBlock [31:0] ;
......@@ -557,54 +531,104 @@ module main
assign bCurBlockY = bCurBlockPos [12:8] ;
assign bWriteDataSel = wireout_readaddr_delay_1<6'd52?3'd7:wireout_readaddr_delay_1-6'd52;
assign line = wireout_readaddr_delay_1 [5:1] ;
assign right = wireout_readaddr_delay_1 [0:0] ;
assign right = wireout_readaddr_delay_1 [0] ;
assign line3 = line+2==bCurBlockY?16'hffff:16'b0;
assign line2 = line+1==bCurBlockY?16'hffff:16'b0;
assign line1 = line==bCurBlockY?16'hffff:16'b0;
assign line0 = line==bCurBlockY+1?16'hffff:16'b0;
assign curblockline = line0&bCurBlock [15:0] |line1&bCurBlock [31:16] |line2&bCurBlock [47:32] |line3&bCurBlock [63:48] ;
assign leftline = bCurBlockX [5:4] ?selecteddata:leftline_0_15;
assign rightline = bCurBlockX [5:0] >=3?rightline_3_18:selecteddata;
assign leftline = bCurBlockX [5:4] ?selecteddata:leftline_0_15|selecteddata;
assign rightline = bCurBlockX [5:0] >=3?rightline_3_18|selecteddata:selecteddata;
assign blockx_3 = bCurBlockX [5:0] -6'd3;
hdl4se_ram1p #( 32, 6 ) ram_0( wClk, wram_Write, bram_WriteAddr, bram_WriteData, bram_ReadAddr, bram_ReadData
);
teris_ctrl ctrl( wClk, nwReset, wCtrlWrite, bCtrlWriteAddr, bCtrlWriteData, bCtrlReadAddr
, bCtrlReadData, bCtrlKeyData, wCtrlStateComplete, wCtrlStateChange, bCtrlState
, bCtrlScore, bCtrlSpeed, bCtrlLevel, bNextBlock, bCurBlock
, bCurBlockPos );
hdl4se_reg #( 6 ) ramreadaddr( wClk, wirein_readaddr, wireout_readaddr );
hdl4se_reg #( 6 ) ramreadaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 );
hdl4se_bind2 #( 16, 16 ) curlinebind( curblockline, selecteddata [31:16] , curline );
hdl4se_bind2 #( 4, 28 ) leftline0_gen( curblockline [15:12] , selecteddata [27:0] , leftline_1 );
hdl4se_bind2 #( 8, 24 ) leftline0_gen( curblockline [15:8] , selecteddata [23:0] , leftline0 );
hdl4se_bind2 #( 12, 20 ) leftline1_gen( curblockline [15:4] , selecteddata [19:0] , leftline1 );
hdl4se_bind2 #( 16, 16 ) leftline2_gen( curblockline [15:0] , selecteddata [15:0] , leftline2 );
hdl4se_bind3 #( 4, 16, 12 ) leftline3_gen( selecteddata [31:28] , curblockline [15:0] , selecteddata [11:0] , leftline3 );
hdl4se_bind3 #( 8, 16, 8 ) leftline4_gen( selecteddata [31:24] , curblockline [15:0] , selecteddata [7:0] , leftline4 );
hdl4se_bind3 #( 12, 16, 4 ) leftline5_gen( selecteddata [31:20] , curblockline [15:0] , selecteddata [3:0] , leftline5 );
hdl4se_bind2 #( 16, 16 ) leftline6_gen( selecteddata [31:16] , curblockline [15:0] , leftline6 );
hdl4se_bind2 #( 20, 12 ) leftline7_gen( selecteddata [31:12] , curblockline [11:0] , leftline7 );
hdl4se_bind2 #( 24, 8 ) leftline8_gen( selecteddata [31:8] , curblockline [7:0] , leftline8 );
hdl4se_bind2 #( 28, 4 ) leftline9_gen( selecteddata [31:4] , curblockline [3:0] , leftline9 );
hdl4se_bind2 #( 4, 28 ) leftline0_gen( curblockline [15:12] , 32'h0, leftline_1 );
hdl4se_bind2 #( 8, 24 ) leftline0_gen( curblockline [15:8] , 32'h0, leftline0 );
hdl4se_bind2 #( 12, 20 ) leftline1_gen( curblockline [15:4] , 32'h0, leftline1 );
hdl4se_bind2 #( 16, 16 ) leftline2_gen( curblockline [15:0] , 32'h0, leftline2 );
hdl4se_bind3 #( 4, 16, 12 ) leftline3_gen( 32'h0, curblockline [15:0] , 32'h0, leftline3 );
hdl4se_bind3 #( 8, 16, 8 ) leftline4_gen( 32'h0, curblockline [15:0] , 32'h0, leftline4 );
hdl4se_bind3 #( 12, 16, 4 ) leftline5_gen( 32'h0, curblockline [15:0] , 32'h0, leftline5 );
hdl4se_bind2 #( 16, 16 ) leftline6_gen( 32'h0, curblockline [15:0] , leftline6 );
hdl4se_bind2 #( 20, 12 ) leftline7_gen( 32'h0, curblockline [11:0] , leftline7 );
hdl4se_bind2 #( 24, 8 ) leftline8_gen( 32'h0, curblockline [7:0] , leftline8 );
hdl4se_bind2 #( 28, 4 ) leftline9_gen( 32'h0, curblockline [3:0] , leftline9 );
hdl4se_mux16 #( 32 ) selectleftline( bCurBlockX [3:0] , leftline_1, leftline0, leftline1, leftline2, leftline3
, leftline4, leftline5, leftline6, leftline7, leftline8
, leftline9, selecteddata, selecteddata, selecteddata, selecteddata
, selecteddata, leftline_0_15 );
hdl4se_bind2 #( 4, 28 ) rightline0_gen( curblockline [15:12] , selecteddata [27:0] , rightline0 );
hdl4se_bind2 #( 8, 24 ) rightline1_gen( curblockline [15:8] , selecteddata [23:0] , rightline1 );
hdl4se_bind2 #( 12, 20 ) rightline2_gen( curblockline [15:4] , selecteddata [19:0] , rightline2 );
hdl4se_bind2 #( 16, 16 ) rightline3_gen( curblockline [15:0] , selecteddata [15:0] , rightline3 );
hdl4se_bind3 #( 4, 16, 12 ) rightline4_gen( selecteddata [31:28] , curblockline [15:0] , selecteddata [11:0] , rightline4 );
hdl4se_bind3 #( 8, 16, 8 ) rightline5_gen( selecteddata [31:24] , curblockline [15:0] , selecteddata [7:0] , rightline5 );
hdl4se_bind3 #( 12, 16, 4 ) rightline6_gen( selecteddata [31:20] , curblockline [15:0] , selecteddata [3:0] , rightline6 );
hdl4se_bind2 #( 16, 16 ) rightline7_gen( selecteddata [31:16] , curblockline [15:0] , rightline7 );
hdl4se_bind2 #( 20, 12 ) rightline8_gen( selecteddata [31:12] , curblockline [11:0] , rightline8 );
hdl4se_bind2 #( 24, 8 ) rightline9_gen( selecteddata [31:8] , curblockline [7:0] , rightline9 );
hdl4se_bind2 #( 28, 4 ) rightline10_gen( selecteddata [31:4] , curblockline [3:0] , rightline10 );
hdl4se_bind2 #( 4, 28 ) rightline0_gen( curblockline [15:12] , 32'h0, rightline0 );
hdl4se_bind2 #( 8, 24 ) rightline1_gen( curblockline [15:8] , 32'h0, rightline1 );
hdl4se_bind2 #( 12, 20 ) rightline2_gen( curblockline [15:4] , 32'h0, rightline2 );
hdl4se_bind2 #( 16, 16 ) rightline3_gen( curblockline [15:0] , 32'h0, rightline3 );
hdl4se_bind3 #( 4, 16, 12 ) rightline4_gen( 32'h0, curblockline [15:0] , 32'h0, rightline4 );
hdl4se_bind3 #( 8, 16, 8 ) rightline5_gen( 32'h0, curblockline [15:0] , 32'h0, rightline5 );
hdl4se_bind3 #( 12, 16, 4 ) rightline6_gen( 32'h0, curblockline [15:0] , 32'h0, rightline6 );
hdl4se_bind2 #( 16, 16 ) rightline7_gen( 32'h0, curblockline [15:0] , rightline7 );
hdl4se_bind2 #( 20, 12 ) rightline8_gen( 32'h0, curblockline [11:0] , rightline8 );
hdl4se_bind2 #( 24, 8 ) rightline9_gen( 32'h0, curblockline [7:0] , rightline9 );
hdl4se_bind2 #( 28, 4 ) rightline10_gen( 32'h0, curblockline [3:0] , rightline10 );
hdl4se_mux16 #( 32 ) selectrightline( blockx_3 [3:0] , selecteddata, selecteddata, selecteddata, selecteddata, selecteddata
, rightline0, rightline1, rightline2, rightline3, rightline4
, rightline5, rightline6, rightline7, rightline8, rightline9
, rightline10, rightline_3_18 );
hdl4se_mux8 #( 32 ) writedatasel( bWriteDataSel, bNextBlockLo, bNextBlockHi, 32'h0, 32'h0, bCtrlScore
, bCtrlLevel, bCtrlSpeed, bram_ReadData, selecteddata );
, bCtrlLevel, bCtrlSpeed, right?bFlushReadData [63:32] :bFlushReadData [31:0] , selecteddata );
endmodule
module main
(
input wClk,
input nwReset,
output wWrite,
output [31:0] bWriteAddr,
output [31:0] bWriteData,
output [3:0] bWriteMask,
output wRead,
output [31:0] bReadAddr,
input [31:0] bReadData
)
;
wire wram_Write;
wire [5:0] bram_WriteAddr;
wire [63:0] bram_WriteData;
wire [5:0] bram_ReadAddr;
wire [63:0] bram_ReadData;
wire wCtrlWrite;
wire [5:0] bCtrlWriteAddr;
wire [63:0] bCtrlWriteData;
wire [5:0] bCtrlReadAddr;
wire [63:0] bCtrlReadData;
wire [31:0] bCtrlKeyData;
wire wCtrlStateComplete;
wire wCtrlStateChange;
wire [3:0] bCtrlState;
wire [31:0] bCtrlSpeed;
wire [31:0] bCtrlLevel;
wire [31:0] bCtrlScore;
wire [63:0] bNextBlock;
wire [63:0] bCurBlock;
wire [15:0] bCurBlockPos;
wire [5:0] bFlushReadAddr;
wire [63:0] bFlushReadData;
assign wram_Write = bCtrlState==1?1'b0:wCtrlWrite;
assign bram_WriteAddr = bCtrlState==1?6'b0:bCtrlWriteAddr;
assign bram_WriteData = bCtrlState==1?64'b0:bCtrlWriteData;
assign bram_ReadAddr = bCtrlState==1?bFlushReadAddr:bCtrlReadAddr;
assign bCtrlReadData = bram_ReadData;
assign bFlushReadData = bram_ReadData;
assign wRead = 32'h1;
assign bReadAddr = 32'hf0000000;
assign bCtrlKeyData = bReadData;
hdl4se_ram1p #( 64, 6 ) ram_0( wClk, wram_Write, bram_WriteAddr, bram_WriteData, bram_ReadAddr, bram_ReadData
);
teris_ctrl ctrl( wClk, nwReset, wCtrlWrite, bCtrlWriteAddr, bCtrlWriteData, bCtrlReadAddr
, bCtrlReadData, bCtrlKeyData, wCtrlStateComplete, wCtrlStateChange, bCtrlState
, bCtrlScore, bCtrlSpeed, bCtrlLevel, bNextBlock, bCurBlock
, bCurBlockPos );
flushtodisp flusher( wClk, bCtrlState, wCtrlStateComplete, bFlushReadAddr, bFlushReadData, wWrite
, bWriteAddr, bWriteData, bCtrlSpeed, bCtrlLevel, bCtrlScore
, bNextBlock, bCurBlock, bCurBlockPos );
endmodule
parser/verilog_expr.c
浏览文件 @ 50cd4628
......@@ -747,35 +747,43 @@ static int expr_verilognode_procheck(HOBJECT object, HOBJECT module, void * para
pobj->data.isconst = 0;
IBigNumber** left = NULL;
IBigNumber** right = NULL;
verilogExpr* pexpr;
verilogExpr* pexpr0;
verilogExpr* pexpr1;
if (1 != objectCall2(pobj->data.expr0, procheck, module, param))
return 0;
if (1 != objectCall2(pobj->data.expr1, procheck, module, param))
return 0;
left = bigintegerCreate(32);
pexpr = verilogExprGetData(pobj->data.expr0);
if (pexpr == NULL)
pexpr0 = verilogExprGetData(pobj->data.expr0);
if (pexpr0 == NULL)
goto endofbinop;
pobj->data.width = pexpr->width;
if (pexpr->exprtype != EXPRTYPE_BIGNUMBER)
pobj->data.width = pexpr0->width;
pexpr1 = verilogExprGetData(pobj->data.expr1);
if (pexpr1 == NULL)
goto endofbinop;
if (0 != objectCall1(left, Clone, pexpr->bignumber))
if (pobj->data.width < pexpr1->width)
pobj->data.width = pexpr1->width;
if (pexpr0->exprtype != EXPRTYPE_BIGNUMBER)
goto endofbinop;
right = bigintegerCreate(32);
pexpr = verilogExprGetData(pobj->data.expr1);
if (pexpr == NULL)
left = bigintegerCreate(32);
if (0 != objectCall1(left, Clone, pexpr0->bignumber))
goto endofbinop;
if (pobj->data.width < pexpr->width)
pobj->data.width = pexpr->width;
if (pexpr->exprtype != EXPRTYPE_BIGNUMBER)
if (pexpr1->exprtype != EXPRTYPE_BIGNUMBER)
goto endofbinop;
if (0 != objectCall1(right, Clone, pexpr->bignumber))
right = bigintegerCreate(32);
if (0 != objectCall1(right, Clone, pexpr1->bignumber))
goto endofbinop;
if (0 != expr_calc_binop(pobj->data.op, left, left, right))
goto endofbinop;
if (0 != expr_setto_number(pobj, left)) {
goto endofbinop;
}
pobj->data.isconst = 1;
endofbinop:
objectRelease(left);
......@@ -813,7 +821,70 @@ static int expr_verilognode_procheck(HOBJECT object, HOBJECT module, void * para
}
break;
case EXPRTYPE_IFOP:
break;
{
pobj->data.isconst = 0;
IBigNumber** cond = NULL;
IBigNumber** yes = NULL;
IBigNumber** no = NULL;
verilogExpr* expr_cond;
verilogExpr* expr_yes;
verilogExpr* expr_no;
if (1 != objectCall2(pobj->data.expr0, procheck, module, param))
return 0;
if (1 != objectCall2(pobj->data.expr1, procheck, module, param))
return 0;
expr_cond = verilogExprGetData(pobj->data.expr0);
if (expr_cond == NULL)
goto endofifop;
expr_yes = verilogExprGetData(pobj->data.expr1);
if (expr_yes == NULL)
goto endofifop;
pobj->data.width = expr_yes->width;
expr_no = verilogExprGetData(pobj->data.expr2);
if (expr_no == NULL)
goto endofifop;
pobj->data.width = expr_yes->width;
if (expr_cond->exprtype != EXPRTYPE_BIGNUMBER)
goto endofifop;
cond = bigintegerCreate(32);
if (0 != objectCall1(cond, Clone, expr_cond->bignumber))
goto endofifop;
if (expr_yes->exprtype != EXPRTYPE_BIGNUMBER)
goto endofifop;
yes = bigintegerCreate(32);
if (0 != objectCall1(yes, Clone, expr_yes->bignumber))
goto endofifop;
if (expr_no->exprtype != EXPRTYPE_BIGNUMBER)
goto endofifop;
no = bigintegerCreate(32);
if (0 != objectCall1(no, Clone, expr_no->bignumber))
goto endofifop;
if (objectCall0(cond, IsZero)) {
if (0 != expr_setto_number(pobj, no)) {
goto endofifop;
}
}
else {
if (0 != expr_setto_number(pobj, yes)) {
goto endofifop;
}
}
pobj->data.isconst = 1;
endofifop:
objectRelease(cond);
objectRelease(yes);
objectRelease(no);
return pobj->data.isconst;
}
break;
case EXPRTYPE_HIERARCHICAL_IDENT:
break;
default:
......@@ -844,6 +915,7 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module
expr_result->index = varindex;
expr_result->portindex = 0;
expr_result->width = width;
pobj->data.width = expr_result->width;
return 0;
}
if (verilogparseIsConstExpr(pobj, module)) {
......@@ -867,6 +939,7 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module
expr_result->portindex = 0;
expr_result->type = EXPR_RESULT_TYPE_TEMPVAR;
expr_result->width = 64; /*fixed me*/
pobj->data.width = expr_result->width;
return 0;
}
switch (pobj->data.exprtype) {
......@@ -884,6 +957,7 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module
expr_result->portindex = index;
expr_result->type = EXPR_RESULT_TYPE_PORT;
expr_result->width = 32;/*fixed me*/
pobj->data.width = expr_result->width;
return 0;
}
index = verilogModuleGetNetIndex(module, select->name->string);
......@@ -892,11 +966,43 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module
expr_result->portindex = 0;
expr_result->type = EXPR_RESULT_TYPE_NET;
expr_result->width = 32;/*fixed me*/
pobj->data.width = expr_result->width;
return 0;
}
}
else if (select->range_type == RANGE_TYPE_BITSELECT) {
verilogExpr * msb;
int msbindex;
expr_verilognode_procheck(select->range_msb, module, param);
msb = verilogExprGetData(select->range_msb);
if (msb->exprtype == EXPRTYPE_BIGNUMBER) {
objectCall1(msb->bignumber, GetInt32, &msbindex);
int varindex = moduleinfo->tempvarindex++;
fprintf(pFile, "\tIHDL4SEUnit** tempvar_%d = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, \"%d, %d, %d\", \"tempvar_%d\");\n",
varindex,
msbindex + 1, /*fixed me*/
1,
msbindex,
varindex);
expr_result->index = varindex;
expr_result->portindex = 1;
expr_result->type = EXPR_RESULT_TYPE_TEMPVAR;
expr_result->width = 1;
pobj->data.width = expr_result->width;
index = verilogModuleGetPortIndex(module, select->name->string);
if (index >= 0) {
fprintf(pFile, "\tobjectCall3(tempvar_%d, Connect, 0, unit, %d);\n", varindex, index);
return 0;
}
index = verilogModuleGetNetIndex(module, select->name->string);
if (index >= 0) {
fprintf(pFile, "\tobjectCall3(tempvar_%d, Connect, 0, nets[%d], 0);\n", varindex, index);
return 0;
}
}
else {
fprintf(pFile, "#error only support constant bit select\n");
}
}
else if (select->range_type == RANGE_TYPE_PARTSELECT) {
verilogExpr* lsb, * msb;
......@@ -920,6 +1026,7 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module
expr_result->portindex = 1;
expr_result->type = EXPR_RESULT_TYPE_TEMPVAR;
expr_result->width = msbindex - lsbindex + 1;
pobj->data.width = expr_result->width;
index = verilogModuleGetPortIndex(module, select->name->string);
if (index >= 0) {
fprintf(pFile, "\tobjectCall3(tempvar_%d, Connect, 0, unit, %d);\n", varindex, index);
......@@ -974,7 +1081,8 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module
fprintf(pFile, "unit, %d);\n", expr_results[i].portindex);
}
}
pobj->data.width = reswidth;
expr_result->width = reswidth;
expr_result->index = varindex;
expr_result->portindex = 2;
expr_result->type = EXPR_RESULT_TYPE_TEMPVAR;
......@@ -1009,7 +1117,8 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module
fprintf(pFile, "unit, %d);\n", expr_results[i].portindex);
}
}
pobj->data.width = reswidth;
expr_result->width = reswidth;
expr_result->index = varindex;
expr_result->portindex = 1;
expr_result->type = EXPR_RESULT_TYPE_TEMPVAR;
......@@ -1045,6 +1154,8 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module
fprintf(pFile, "unit, %d);\n", expr_results[i].portindex);
}
}
pobj->data.width = reswidth;
expr_result->width = reswidth;
expr_result->index = varindex;
expr_result->portindex = 3;
expr_result->type = EXPR_RESULT_TYPE_TEMPVAR;
......@@ -1055,46 +1166,6 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module
return -1;
}
#if 0
HOBJECT verilogparseCreateExpr(
int exprtype,
IConstStringVar* value,
HOBJECT range0,
HOBJECT range1,
int op,
HOBJECT expr0,
HOBJECT expr1,
HOBJECT expr2,
IDListVarPtr attributes,
IDListVarPtr elementselect
)
{
HOBJECT expr = NULL;
sExpr * pobj;
A_u_t_o_registor_expr();
objectCreate(CLSID_VERILOG_EXPR, NULL, 0, &expr);
if (expr == NULL)
return NULL;
pobj = (sExpr *)objectThis(expr);
objectQueryInterface(value, IID_CONSTSTRING, (void**)&pobj->data.value);
pobj->data.exprtype = exprtype;
pobj->data.op = op;
pobj->data.attributes = attributes;
pobj->data.elementselect = elementselect;
objectQueryInterface(expr0, IID_VERILOG_NODE, (void**)&pobj->data.expr0);
objectRelease(expr0);
objectQueryInterface(expr1, IID_VERILOG_NODE, (void**)&pobj->data.expr1);
objectRelease(expr1);
objectQueryInterface(expr2, IID_VERILOG_NODE, (void**)&pobj->data.expr2);
objectRelease(expr2);
objectQueryInterface(range0, IID_VERILOG_NODE, (void**)&pobj->data.range0);
objectRelease(range0);
objectQueryInterface(range1, IID_VERILOG_NODE, (void**)&pobj->data.range1);
objectRelease(range1);
return expr;
}
#endif
static sExpr* verilogparseCreateGeneralExpr(int exprtype, IDListVarPtr attributes)
{
HOBJECT expr = NULL;
......
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