From 50cd46288fc23d571564e21823307d27612314b2 Mon Sep 17 00:00:00 2001 From: m0_56903617 Date: Mon, 21 Jun 2021 18:45:02 +0800 Subject: [PATCH] 202106211844 --- examples/terris/include/terrisengine1.h | 10 +- examples/terris/src/terisctrl_1.c | 296 ++++-- examples/terris/src/topmodule.c | 1216 ++++++++++++----------- examples/terris/verilog/main_1.v | 218 ++-- examples/terris/verilog/main_asm.v | 174 ++-- parser/verilog_expr.c | 187 ++-- 6 files changed, 1220 insertions(+), 881 deletions(-) diff --git a/examples/terris/include/terrisengine1.h b/examples/terris/include/terrisengine1.h index 0e3b352..f160520 100644 --- a/examples/terris/include/terrisengine1.h +++ b/examples/terris/include/terrisengine1.h @@ -169,15 +169,11 @@ enum { ST_FLUSHTODISP, ST_CHECKKEY, ST_CHECKBLOCKCANSETTO, - ST_MOVEDOWN, + ST_BLOCKWRITE, + ST_CHECKLINE, + ST_COPYLINES, }; -static int BlockCanSetTo_x; -static int BlockCanSetTo_y; -static int BlockCanSetTo_res; -static int state_after_BlockCanSetTo; -static int param_after_BlockCanSet; -//static unsigned long terrisPanel[PANELHEIGHT][PANELWIDTH]; static int terrisBlockCanSetTo(TerrisBlock * pBlock, int x, int y); static int terrisGenNewBlock(TerrisBlock * pBlock); diff --git a/examples/terris/src/terisctrl_1.c b/examples/terris/src/terisctrl_1.c index c1cfff3..6afe5bb 100644 --- a/examples/terris/src/terisctrl_1.c +++ b/examples/terris/src/terisctrl_1.c @@ -49,9 +49,9 @@ 1: input nwReset, 2: output wWrite, 3: output[5:0] bWriteAddr, -4: output[31:0] bWriteData, +4: output[63:0] bWriteData, 5: output[5:0] bReadAddr, -6: input[31:0] bReadData, +6: input[63:0] bReadData, 7: input[31:0] bKeyData, 8: input wStateComplete, 9: output wStateChange, @@ -78,7 +78,6 @@ struct _sTerrisCtrl1 { IHDL4SEUnit** readdata_unit; int readdata_index; IBigNumber** readdata; - IBigNumber** lastreaddata; IHDL4SEUnit** keydata_unit; IBigNumber** keydata; @@ -90,25 +89,28 @@ struct _sTerrisCtrl1 { unsigned int write; unsigned int writeaddr; - unsigned int writedata; + unsigned long long writedata; unsigned int readaddr; + unsigned int write_reg; + unsigned int writeaddr_reg; + unsigned long long writedata_reg; + unsigned int readaddr_reg; - struct tagInitContext { + struct tagGenContext { int index; - }initContext; - - struct tagBlockMoveDownContext { - int index; - int state; /*0 -- movedown, 1 -- checkline*/ - }blockMoveDownContext; + int complete; + int count; + int startindex; + }genContext; struct tagBlockCanSetToContext { - int laststate; + int nextstate; int param; int result; int index; int x; int y; + int complete; void (*BlockCanSetToPro)(sTerrisCtrl1 * pobj); }blockCanSetToContext; @@ -153,8 +155,7 @@ static int terrisctrl1Create(const PARAMITEM* pParams, int paramcount, HOBJECT* pobj->statecomplete_unit = NULL; pobj->statecompletedata = bigintegerCreate(1); pobj->readdata_unit = NULL; - pobj->readdata = bigintegerCreate(32); - pobj->lastreaddata = bigintegerCreate(32); + pobj->readdata = bigintegerCreate(64); for (i = 0; i < paramcount; i++) { if (pParams[i].name == PARAMID_HDL4SE_UNIT_NAME) { if (pobj->name != NULL) @@ -165,7 +166,7 @@ static int terrisctrl1Create(const PARAMITEM* pParams, int paramcount, HOBJECT* pobj->parent = (IHDL4SEModule **)pParams[i].pvalue; } } - pobj->initContext.index = 0; + pobj->genContext.index = 0; pobj->write = 0; pobj->state = ST_INIT; pobj->laststate = ST_INIT; @@ -246,16 +247,16 @@ static int terrisctrl1_hdl4se_unit_GetValue(HOBJECT object, int index, int width sTerrisCtrl1* pobj; pobj = (sTerrisCtrl1*)objectThis(object); if (index == 2) { - objectCall1(value, AssignUint32, pobj->write); + objectCall1(value, AssignUint32, pobj->write_reg); } else if (index == 3) { - objectCall1(value, AssignUint32, pobj->writeaddr); + objectCall1(value, AssignUint32, pobj->writeaddr_reg); } else if (index == 4) { - objectCall1(value, AssignUint32, pobj->writedata); + objectCall1(value, AssignUint64, pobj->writedata_reg); } else if (index == 5) { - objectCall1(value, AssignUint32, pobj->readaddr); + objectCall1(value, AssignUint32, pobj->readaddr_reg); } else if (index == 9) { objectCall1(value, AssignUint32, pobj->state != pobj->laststate); @@ -317,27 +318,26 @@ static void terrisctrl1_hdl4se_unit_PressKeyPro(sTerrisCtrl1* pobj) currentblock.posx++; break; case TK_TURNLEFT:/*逆时针1*/ - terrisBlockRotate(¤tblock, 1); if (pobj->blockCanSetToContext.result == 0) terrisBlockRotate(¤tblock, 0); break; case TK_TURNRIGHT:/*顺时针0*/ - terrisBlockRotate(¤tblock, 0); if (pobj->blockCanSetToContext.result == 0) terrisBlockRotate(¤tblock, 1); break; } } -static void terrisctrl1_hdl4se_unit_MoveDownPro2(sTerrisCtrl1* pobj) +static void terrisctrl1_hdl4se_unit_AfterCheckLine(sTerrisCtrl1* pobj) { if (pobj->blockCanSetToContext.result == 0) { terrisInit(); - pobj->initContext.index = 0; + pobj->genContext.index = 0; pobj->state = ST_INIT; } else { terrisGenNewBlock(&nextblock); + pobj->state = ST_FLUSHTODISP; } } @@ -348,51 +348,127 @@ static void terrisctrl1_hdl4se_unit_MoveDownPro(sTerrisCtrl1* pobj) currentblock.posy++; } else { - pobj->blockMoveDownContext.state = 0; - pobj->blockMoveDownContext.index = 0; + pobj->genContext.index = 0; + pobj->state = ST_BLOCKWRITE; + } + return; +} + +static void terrisctrl1_hdl4se_unit_BlockWrite(sTerrisCtrl1* pobj) +{ + /*先读后写*/ + int i, x, y; + i = pobj->genContext.index; + y = currentblock.posy - BLOCKSIZE / 2 + i+1; + pobj->readaddr = YCOUNT-1-y; + pobj->write = 0; + pobj->genContext.complete = 0; + if (pobj->genContext.index > 1) { + unsigned long long line; + unsigned long long blockline; + i = pobj->genContext.index - 2; /*数据比索引晚两拍*/ + y = currentblock.posy - BLOCKSIZE / 2 + i+1; + x = currentblock.posx - BLOCKSIZE / 2; + if (y < YCOUNT && y>=0) { + blockline = currentblock.subblock[i][3] & 0xF; + blockline <<= 4; + blockline |= currentblock.subblock[i][2] & 0xF; + blockline <<= 4; + blockline |= currentblock.subblock[i][1] & 0xF; + blockline <<= 4; + blockline |= currentblock.subblock[i][0] & 0xF; + pobj->writeaddr = YCOUNT - 1 - y; + pobj->write = 1; + objectCall3(pobj->readdata_unit, GetValue, pobj->readdata_index, 64, pobj->readdata); + objectCall1(pobj->readdata, GetUint64, &line); + if (x < 0) + pobj->writedata = line | (blockline >> (-x * 4)); + else + pobj->writedata = line | (blockline << (x * 4)); + } + } + pobj->genContext.index++; + if (pobj->genContext.index > BLOCKSIZE + 1) { + pobj->genContext.complete = 1; + } +} + +static void terrisctrl1_hdl4se_unit_CopyLines(sTerrisCtrl1* pobj) +{ + pobj->readaddr = pobj->genContext.index + 1; + pobj->write = 0; + if (pobj->genContext.index - pobj->genContext.startindex > 1) { + int index = pobj->genContext.index - 1; + unsigned long long line; + if (index == YCOUNT-1) { + line = 0; + } + else { + objectCall3(pobj->readdata_unit, GetValue, pobj->readdata_index, 64, pobj->readdata); + objectCall1(pobj->readdata, GetUint64, &line); + } + if (index < YCOUNT) { + pobj->write = 1; + pobj->writeaddr = index; + pobj->writedata = line; + } + if (index >= YCOUNT || line == 0) { + pobj->genContext.index = 0; + pobj->state = ST_CHECKLINE; + return; + } + } + pobj->genContext.index++; +} + +static void terrisctrl1_hdl4se_unit_CheckLine(sTerrisCtrl1* pobj) +{ + pobj->readaddr = pobj->genContext.index; + pobj->genContext.complete = 0; + if (pobj->genContext.index > 1) { + unsigned long long line = 0; int i; - int j; - for (i = 0; i < BLOCKSIZE; i++) - { - for (j = 0; j < BLOCKSIZE; j++) - { - if (currentblock.subblock[i][j] != 0) - { - int xx, yy; - xx = currentblock.posx - BLOCKSIZE / 2 + j; - yy = currentblock.posy - BLOCKSIZE / 2 + i; - if (yy < 0) - continue; - if (yy >= PANELHEIGHT) - continue; - if (xx < 0) - continue; - if (xx >= PANELWIDTH) - continue; - //if (terrisPanel[yy][xx] != 0) - // continue; - //terrisPanel[yy][xx] = currentblock.subblock[i][j]; - } - } + objectCall3(pobj->readdata_unit, GetValue, pobj->readdata_index, 64, pobj->readdata); + objectCall1(pobj->readdata, GetUint64, &line); + for (i = 0; i < XCOUNT; i++) { + if ((line & 0xf) == 0) + break; + line >>= 4; } - terrisCheckLine(); + if (i == XCOUNT) { + pobj->genContext.index -= 2; + pobj->genContext.startindex = pobj->genContext.index; + pobj->readaddr = pobj->genContext.index + 1; + pobj->state = ST_COPYLINES; + pobj->genContext.count++; + return; + } + } + if (pobj->genContext.index >= YCOUNT + 1) { + pobj->genContext.complete = 1; + } + pobj->genContext.index++; + if (pobj->genContext.complete) { memcpy(¤tblock, &nextblock, sizeof(currentblock)); - pobj->blockCanSetToContext.laststate = ST_MOVEDOWN; + pobj->blockCanSetToContext.nextstate = ST_FLUSHTODISP; pobj->blockCanSetToContext.param = 0; pobj->blockCanSetToContext.result = 0; + pobj->blockCanSetToContext.complete = 0; pobj->blockCanSetToContext.index = 0; - pobj->blockCanSetToContext.BlockCanSetToPro = terrisctrl1_hdl4se_unit_MoveDownPro2; + pobj->blockCanSetToContext.BlockCanSetToPro = terrisctrl1_hdl4se_unit_AfterCheckLine; pobj->blockCanSetToContext.x = currentblock.posx; pobj->blockCanSetToContext.y = currentblock.posy; pobj->state = ST_CHECKBLOCKCANSETTO; } } + static int terrisctrl1_hdl4se_unit_MoveDown(sTerrisCtrl1* pobj) { - pobj->blockCanSetToContext.laststate = ST_MOVEDOWN; + pobj->blockCanSetToContext.nextstate = ST_FLUSHTODISP; pobj->blockCanSetToContext.param = 0; pobj->blockCanSetToContext.result = 0; + pobj->blockCanSetToContext.complete = 0; pobj->blockCanSetToContext.index = 0; pobj->blockCanSetToContext.BlockCanSetToPro = terrisctrl1_hdl4se_unit_MoveDownPro; pobj->blockCanSetToContext.x = currentblock.posx; @@ -413,11 +489,12 @@ static int terrisctrl1_hdl4se_unit_Tick(sTerrisCtrl1* pobj) } -static int terrisctrl1_hdl4se_unit_PressKeyStart(sTerrisCtrl1* pobj, int key) +static void terrisctrl1_hdl4se_unit_PressKeyStart(sTerrisCtrl1* pobj, int key) { - pobj->blockCanSetToContext.laststate = ST_FLUSHTODISP; + pobj->blockCanSetToContext.nextstate = ST_FLUSHTODISP; pobj->blockCanSetToContext.param = key; pobj->blockCanSetToContext.result = 0; + pobj->blockCanSetToContext.complete = 0; pobj->blockCanSetToContext.index = 0; pobj->blockCanSetToContext.BlockCanSetToPro = terrisctrl1_hdl4se_unit_PressKeyPro; pobj->state = ST_CHECKBLOCKCANSETTO; @@ -453,11 +530,83 @@ static int terrisctrl1_hdl4se_unit_PressKeyStart(sTerrisCtrl1* pobj, int key) currenttick = 0; if (gameScore < 0) { terrisInit(); - pobj->initContext.index = 0; + pobj->genContext.index = 0; pobj->state = ST_INIT; } } +static void terrisctrl1_hdl4se_unit_BlockCanSetTo(sTerrisCtrl1* pobj, TerrisBlock* pBlock, int x, int y) +{ +#define RETURNRESULT(res) \ +do { \ + pobj->blockCanSetToContext.result = res; \ + pobj->blockCanSetToContext.complete = 1; \ + goto BlockCanSetTo_return; \ +} while (0) + int i; + int j; + int yy; + i = pobj->blockCanSetToContext.index / BLOCKSIZE; + yy = y - BLOCKSIZE / 2 + i + 1; + pobj->readaddr = YCOUNT - 1 - yy; + pobj->write = 0; + pobj->blockCanSetToContext.complete = 0; + if (pobj->blockCanSetToContext.index > 1) { + /*从进入这个状态的第二个周期开始进行判断，此时数据已经读入到端口上*/ + i = (pobj->blockCanSetToContext.index-2) / BLOCKSIZE; + j = (pobj->blockCanSetToContext.index-2) % BLOCKSIZE; + if (pBlock->subblock[i][j] != 0) { + int xx, yy; + unsigned long long line; + xx = x - BLOCKSIZE / 2 + j; + yy = y - BLOCKSIZE / 2 + i; + if (yy < 0) + goto BlockCanSetTo_return; + if (yy >= PANELHEIGHT-1) + RETURNRESULT(0); + if (xx < 0) + RETURNRESULT(0); + if (xx >= PANELWIDTH) + RETURNRESULT(0); + objectCall3(pobj->readdata_unit, GetValue, pobj->readdata_index, 64, pobj->readdata); + objectCall1(pobj->readdata, GetUint64, &line); + line >>= xx * 4; + line &= 0xF; + if (line != 0) + RETURNRESULT(0); + } + } + if (pobj->blockCanSetToContext.index > BLOCKSIZE * BLOCKSIZE) { + pobj->blockCanSetToContext.complete = 1; + pobj->blockCanSetToContext.result = 1; + } +BlockCanSetTo_return : + pobj->blockCanSetToContext.index++; + return; +} + +static void terrisctrl1_hdl4se_unit_Init(sTerrisCtrl1* pobj) +{ + if (pobj->genContext.index < YCOUNT) { + int i; + unsigned long long data = 0; + for (i = 0; i < 16; i++) { + int c; + c = ((pobj->genContext.index * (pobj->genContext.index + 2 + i)) % 14) + 2; + data <<= 4; + data |= c; + } + pobj->write = 1; + pobj->writeaddr = pobj->genContext.index; + pobj->writedata = 0; + pobj->genContext.index++; + pobj->genContext.complete = 0; + } + else { + pobj->genContext.complete = 1; + } +} + static int terrisctrl1_hdl4se_unit_ClkTick(HOBJECT object) { sTerrisCtrl1* pobj; @@ -468,13 +617,8 @@ static int terrisctrl1_hdl4se_unit_ClkTick(HOBJECT object) pobj->write = 0; if (pobj->state == ST_INIT) { - if (pobj->initContext.index < YCOUNT * 2) { - pobj->write = 1; - pobj->writeaddr = pobj->initContext.index; - pobj->writedata = 0; - pobj->initContext.index++; - } - else { + terrisctrl1_hdl4se_unit_Init(pobj); + if (pobj->genContext.complete) { pobj->state = ST_FLUSHTODISP; } } @@ -503,12 +647,26 @@ static int terrisctrl1_hdl4se_unit_ClkTick(HOBJECT object) } } else if (pobj->state == ST_CHECKBLOCKCANSETTO) { - pobj->state = pobj->blockCanSetToContext.laststate; - pobj->blockCanSetToContext.result = terrisBlockCanSetTo(¤tblock, pobj->blockCanSetToContext.x, pobj->blockCanSetToContext.y); - pobj->blockCanSetToContext.BlockCanSetToPro(pobj); + terrisctrl1_hdl4se_unit_BlockCanSetTo(pobj, ¤tblock, pobj->blockCanSetToContext.x, pobj->blockCanSetToContext.y); + if (pobj->blockCanSetToContext.complete) { + pobj->state = pobj->blockCanSetToContext.nextstate; + pobj->blockCanSetToContext.BlockCanSetToPro(pobj); + } } - else if (pobj->state == ST_MOVEDOWN) { - pobj->state = ST_FLUSHTODISP; + else if (pobj->state == ST_BLOCKWRITE) { + terrisctrl1_hdl4se_unit_BlockWrite(pobj); + if (pobj->genContext.complete) { + pobj->state = ST_CHECKLINE; + pobj->genContext.complete = 0; + pobj->genContext.index = 0; + pobj->genContext.count = 0; + } + } + else if (pobj->state == ST_CHECKLINE) { + terrisctrl1_hdl4se_unit_CheckLine(pobj); + } + else if (pobj->state == ST_COPYLINES) { + terrisctrl1_hdl4se_unit_CopyLines(pobj); } else { pobj->state = ST_FLUSHTODISP; @@ -521,6 +679,10 @@ static int terrisctrl1_hdl4se_unit_Setup(HOBJECT object) sTerrisCtrl1* pobj; pobj = (sTerrisCtrl1*)objectThis(object); pobj->laststate = pobj->state; + pobj->write_reg = pobj->write; + pobj->writeaddr_reg = pobj->writeaddr; + pobj->writedata_reg = pobj->writedata; + pobj->readaddr_reg = pobj->readaddr; return 0; } diff --git a/examples/terris/src/topmodule.c b/examples/terris/src/topmodule.c index 4dc281a..19177a8 100644 --- a/examples/terris/src/topmodule.c +++ b/examples/terris/src/topmodule.c @@ -31,7 +31,7 @@ /* -* Created by HDL4SE @ Sun Jun 20 20:43:11 2021 +* Created by HDL4SE @ Mon Jun 21 15:12:52 2021 * Don't edit it. */ @@ -48,11 +48,571 @@ IHDL4SEUnit** hdl4seCreate_0011(IHDL4SEModule** parent, const char* instanceparam, const char* name) +{ /* module flushtodisp */ + IHDL4SEModule** module; + IHDL4SEUnit** unit; + IHDL4SEUnit** nets[47]; + IHDL4SEUnit** modules[28]; + + /* 生成模块对象 */ + unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); + /* 得到对象的IHDL4SEModule 接口 */ + objectQueryInterface(unit, IID_HDL4SEMODULE, (void**)&module); + + /* 端口 */ + /* 0*/ objectCall4(module, AddPort, "wClk", 1, 1, PORT_DIRECT_INPUT ); + /* 1*/ objectCall4(module, AddPort, "bCtrlState", 4, 1, PORT_DIRECT_INPUT ); + /* 2*/ objectCall4(module, AddPort, "wCtrlStateComplete", 1, 1, PORT_DIRECT_OUTPUT); + /* 3*/ objectCall4(module, AddPort, "bFlushReadAddr", 6, 1, PORT_DIRECT_OUTPUT); + /* 4*/ objectCall4(module, AddPort, "bFlushReadData", 64, 1, PORT_DIRECT_INPUT ); + /* 5*/ objectCall4(module, AddPort, "wWrite", 1, 1, PORT_DIRECT_OUTPUT); + /* 6*/ objectCall4(module, AddPort, "bWriteAddr", 32, 1, PORT_DIRECT_OUTPUT); + /* 7*/ objectCall4(module, AddPort, "bWriteData", 32, 1, PORT_DIRECT_OUTPUT); + /* 8*/ objectCall4(module, AddPort, "bCtrlSpeed", 32, 1, PORT_DIRECT_INPUT ); + /* 9*/ objectCall4(module, AddPort, "bCtrlLevel", 32, 1, PORT_DIRECT_INPUT ); + /* 10*/ objectCall4(module, AddPort, "bCtrlScore", 32, 1, PORT_DIRECT_INPUT ); + /* 11*/ objectCall4(module, AddPort, "bNextBlock", 64, 1, PORT_DIRECT_INPUT ); + /* 12*/ objectCall4(module, AddPort, "bCurBlock", 64, 1, PORT_DIRECT_INPUT ); + /* 13*/ objectCall4(module, AddPort, "bCurBlockPos", 16, 1, PORT_DIRECT_INPUT ); + + /* 线网 */ + nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bNextBlockLo"); + nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bNextBlockHi"); + nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCurBlockLo"); + nets[ 3] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCurBlockHi"); + nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 5", "bCurBlockX"); + nets[ 5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 5", "bCurBlockY"); + nets[ 6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wirein_readaddr"); + nets[ 7] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_readaddr"); + nets[ 8] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 8", "wireout_readaddr_delay_1"); + nets[ 9] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wireout_readaddr2"); + nets[ 10] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 3", "bWriteDataSel"); + nets[ 11] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 5", "line"); + nets[ 12] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "right"); + nets[ 13] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "line3"); + nets[ 14] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "line2"); + nets[ 15] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "line1"); + nets[ 16] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "line0"); + nets[ 17] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "curblockline"); + nets[ 18] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "curline"); + nets[ 19] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "selecteddata"); + nets[ 20] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline_0_15"); + nets[ 21] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline"); + nets[ 22] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline_1"); + nets[ 23] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline0"); + nets[ 24] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline1"); + nets[ 25] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline2"); + nets[ 26] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline3"); + nets[ 27] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline4"); + nets[ 28] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline5"); + nets[ 29] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline6"); + nets[ 30] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline7"); + nets[ 31] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline8"); + nets[ 32] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline9"); + nets[ 33] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline_3_18"); + nets[ 34] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline"); + nets[ 35] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline0"); + nets[ 36] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline1"); + nets[ 37] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline2"); + nets[ 38] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline3"); + nets[ 39] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline4"); + nets[ 40] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline5"); + nets[ 41] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline6"); + nets[ 42] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline7"); + nets[ 43] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline8"); + nets[ 44] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline9"); + nets[ 45] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline10"); + nets[ 46] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "blockx_3"); + +/* 模块实例化 */ + modules[ 0] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "ramreadaddr"); + objectCall3(modules[0], Connect, 0, unit, 0); + objectCall3(modules[0], Connect, 1, nets[6], 0); + objectCall3(nets[7], Connect, 0, modules[0], 2); + modules[ 1] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "ramreadaddr_delay_1"); + objectCall3(modules[1], Connect, 0, unit, 0); + objectCall3(modules[1], Connect, 1, nets[7], 0); + objectCall3(nets[8], Connect, 0, modules[1], 2); + modules[ 2] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "16, 16", "curlinebind"); + objectCall3(modules[2], Connect, 0, nets[17], 0); + IHDL4SEUnit** tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 16, 16", "tempvar_0"); + objectCall3(tempvar_0, Connect, 0, nets[19], 0); + objectCall3(modules[2], Connect, 1, tempvar_0, 1); + objectCall3(nets[18], Connect, 0, modules[2], 2); + modules[ 3] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "4, 28", "leftline0_gen"); + IHDL4SEUnit** tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 4, 12", "tempvar_1"); + objectCall3(tempvar_1, Connect, 0, nets[17], 0); + objectCall3(modules[3], Connect, 0, tempvar_1, 1); + IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_2"); + objectCall3(modules[3], Connect, 1, tempvar_2, 0); + objectCall3(nets[22], Connect, 0, modules[3], 2); + modules[ 4] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "8, 24", "leftline0_gen"); + IHDL4SEUnit** tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 8, 8", "tempvar_3"); + objectCall3(tempvar_3, Connect, 0, nets[17], 0); + objectCall3(modules[4], Connect, 0, tempvar_3, 1); + IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_4"); + objectCall3(modules[4], Connect, 1, tempvar_4, 0); + objectCall3(nets[23], Connect, 0, modules[4], 2); + modules[ 5] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "12, 20", "leftline1_gen"); + IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 12, 4", "tempvar_5"); + objectCall3(tempvar_5, Connect, 0, nets[17], 0); + objectCall3(modules[5], Connect, 0, tempvar_5, 1); + IHDL4SEUnit** tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_6"); + objectCall3(modules[5], Connect, 1, tempvar_6, 0); + objectCall3(nets[24], Connect, 0, modules[5], 2); + modules[ 6] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "16, 16", "leftline2_gen"); + IHDL4SEUnit** tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_7"); + objectCall3(tempvar_7, Connect, 0, nets[17], 0); + objectCall3(modules[6], Connect, 0, tempvar_7, 1); + IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_8"); + objectCall3(modules[6], Connect, 1, tempvar_8, 0); + objectCall3(nets[25], Connect, 0, modules[6], 2); + modules[ 7] = hdl4seCreateUnit2(module, "D1F303E2-3ED1-42FD-8762-3AA623DA901E", "4, 16, 12", "leftline3_gen"); + IHDL4SEUnit** tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_9"); + objectCall3(modules[7], Connect, 0, tempvar_9, 0); + IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_10"); + objectCall3(tempvar_10, Connect, 0, nets[17], 0); + objectCall3(modules[7], Connect, 1, tempvar_10, 1); + IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_11"); + objectCall3(modules[7], Connect, 2, tempvar_11, 0); + objectCall3(nets[26], Connect, 0, modules[7], 3); + modules[ 8] = hdl4seCreateUnit2(module, "D1F303E2-3ED1-42FD-8762-3AA623DA901E", "8, 16, 8", "leftline4_gen"); + IHDL4SEUnit** tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_12"); + objectCall3(modules[8], Connect, 0, tempvar_12, 0); + IHDL4SEUnit** tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_13"); + objectCall3(tempvar_13, Connect, 0, nets[17], 0); + objectCall3(modules[8], Connect, 1, tempvar_13, 1); + IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_14"); + objectCall3(modules[8], Connect, 2, tempvar_14, 0); + objectCall3(nets[27], Connect, 0, modules[8], 3); + modules[ 9] = hdl4seCreateUnit2(module, "D1F303E2-3ED1-42FD-8762-3AA623DA901E", "12, 16, 4", "leftline5_gen"); + IHDL4SEUnit** tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_15"); + objectCall3(modules[9], Connect, 0, tempvar_15, 0); + IHDL4SEUnit** tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_16"); + objectCall3(tempvar_16, Connect, 0, nets[17], 0); + objectCall3(modules[9], Connect, 1, tempvar_16, 1); + IHDL4SEUnit** tempvar_17 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_17"); + objectCall3(modules[9], Connect, 2, tempvar_17, 0); + objectCall3(nets[28], Connect, 0, modules[9], 3); + modules[ 10] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "16, 16", "leftline6_gen"); + IHDL4SEUnit** tempvar_18 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_18"); + objectCall3(modules[10], Connect, 0, tempvar_18, 0); + IHDL4SEUnit** tempvar_19 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_19"); + objectCall3(tempvar_19, Connect, 0, nets[17], 0); + objectCall3(modules[10], Connect, 1, tempvar_19, 1); + objectCall3(nets[29], Connect, 0, modules[10], 2); + modules[ 11] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "20, 12", "leftline7_gen"); + IHDL4SEUnit** tempvar_20 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_20"); + objectCall3(modules[11], Connect, 0, tempvar_20, 0); + IHDL4SEUnit** tempvar_21 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "12, 12, 0", "tempvar_21"); + objectCall3(tempvar_21, Connect, 0, nets[17], 0); + objectCall3(modules[11], Connect, 1, tempvar_21, 1); + objectCall3(nets[30], Connect, 0, modules[11], 2); + modules[ 12] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "24, 8", "leftline8_gen"); + IHDL4SEUnit** tempvar_22 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_22"); + objectCall3(modules[12], Connect, 0, tempvar_22, 0); + IHDL4SEUnit** tempvar_23 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "8, 8, 0", "tempvar_23"); + objectCall3(tempvar_23, Connect, 0, nets[17], 0); + objectCall3(modules[12], Connect, 1, tempvar_23, 1); + objectCall3(nets[31], Connect, 0, modules[12], 2); + modules[ 13] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "28, 4", "leftline9_gen"); + IHDL4SEUnit** tempvar_24 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_24"); + objectCall3(modules[13], Connect, 0, tempvar_24, 0); + IHDL4SEUnit** tempvar_25 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "4, 4, 0", "tempvar_25"); + objectCall3(tempvar_25, Connect, 0, nets[17], 0); + objectCall3(modules[13], Connect, 1, tempvar_25, 1); + objectCall3(nets[32], Connect, 0, modules[13], 2); + modules[ 14] = hdl4seCreateUnit2(module, "69B4A095-0644-4B9E-9CF0-295474D7C243", "32", "selectleftline"); + IHDL4SEUnit** tempvar_26 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "4, 4, 0", "tempvar_26"); + objectCall3(tempvar_26, Connect, 0, nets[4], 0); + objectCall3(modules[14], Connect, 0, tempvar_26, 1); + objectCall3(modules[14], Connect, 1, nets[22], 0); + objectCall3(modules[14], Connect, 2, nets[23], 0); + objectCall3(modules[14], Connect, 3, nets[24], 0); + objectCall3(modules[14], Connect, 4, nets[25], 0); + objectCall3(modules[14], Connect, 5, nets[26], 0); + objectCall3(modules[14], Connect, 6, nets[27], 0); + objectCall3(modules[14], Connect, 7, nets[28], 0); + objectCall3(modules[14], Connect, 8, nets[29], 0); + objectCall3(modules[14], Connect, 9, nets[30], 0); + objectCall3(modules[14], Connect, 10, nets[31], 0); + objectCall3(modules[14], Connect, 11, nets[32], 0); + objectCall3(modules[14], Connect, 12, nets[19], 0); + objectCall3(modules[14], Connect, 13, nets[19], 0); + objectCall3(modules[14], Connect, 14, nets[19], 0); + objectCall3(modules[14], Connect, 15, nets[19], 0); + objectCall3(modules[14], Connect, 16, nets[19], 0); + objectCall3(nets[20], Connect, 0, modules[14], 17); + modules[ 15] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "4, 28", "rightline0_gen"); + IHDL4SEUnit** tempvar_27 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 4, 12", "tempvar_27"); + objectCall3(tempvar_27, Connect, 0, nets[17], 0); + objectCall3(modules[15], Connect, 0, tempvar_27, 1); + IHDL4SEUnit** tempvar_28 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_28"); + objectCall3(modules[15], Connect, 1, tempvar_28, 0); + objectCall3(nets[35], Connect, 0, modules[15], 2); + modules[ 16] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "8, 24", "rightline1_gen"); + IHDL4SEUnit** tempvar_29 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 8, 8", "tempvar_29"); + objectCall3(tempvar_29, Connect, 0, nets[17], 0); + objectCall3(modules[16], Connect, 0, tempvar_29, 1); + IHDL4SEUnit** tempvar_30 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_30"); + objectCall3(modules[16], Connect, 1, tempvar_30, 0); + objectCall3(nets[36], Connect, 0, modules[16], 2); + modules[ 17] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "12, 20", "rightline2_gen"); + IHDL4SEUnit** tempvar_31 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 12, 4", "tempvar_31"); + objectCall3(tempvar_31, Connect, 0, nets[17], 0); + objectCall3(modules[17], Connect, 0, tempvar_31, 1); + IHDL4SEUnit** tempvar_32 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_32"); + objectCall3(modules[17], Connect, 1, tempvar_32, 0); + objectCall3(nets[37], Connect, 0, modules[17], 2); + modules[ 18] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "16, 16", "rightline3_gen"); + IHDL4SEUnit** tempvar_33 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_33"); + objectCall3(tempvar_33, Connect, 0, nets[17], 0); + objectCall3(modules[18], Connect, 0, tempvar_33, 1); + IHDL4SEUnit** tempvar_34 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_34"); + objectCall3(modules[18], Connect, 1, tempvar_34, 0); + objectCall3(nets[38], Connect, 0, modules[18], 2); + modules[ 19] = hdl4seCreateUnit2(module, "D1F303E2-3ED1-42FD-8762-3AA623DA901E", "4, 16, 12", "rightline4_gen"); + IHDL4SEUnit** tempvar_35 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_35"); + objectCall3(modules[19], Connect, 0, tempvar_35, 0); + IHDL4SEUnit** tempvar_36 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_36"); + objectCall3(tempvar_36, Connect, 0, nets[17], 0); + objectCall3(modules[19], Connect, 1, tempvar_36, 1); + IHDL4SEUnit** tempvar_37 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_37"); + objectCall3(modules[19], Connect, 2, tempvar_37, 0); + objectCall3(nets[39], Connect, 0, modules[19], 3); + modules[ 20] = hdl4seCreateUnit2(module, "D1F303E2-3ED1-42FD-8762-3AA623DA901E", "8, 16, 8", "rightline5_gen"); + IHDL4SEUnit** tempvar_38 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_38"); + objectCall3(modules[20], Connect, 0, tempvar_38, 0); + IHDL4SEUnit** tempvar_39 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_39"); + objectCall3(tempvar_39, Connect, 0, nets[17], 0); + objectCall3(modules[20], Connect, 1, tempvar_39, 1); + IHDL4SEUnit** tempvar_40 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_40"); + objectCall3(modules[20], Connect, 2, tempvar_40, 0); + objectCall3(nets[40], Connect, 0, modules[20], 3); + modules[ 21] = hdl4seCreateUnit2(module, "D1F303E2-3ED1-42FD-8762-3AA623DA901E", "12, 16, 4", "rightline6_gen"); + IHDL4SEUnit** tempvar_41 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_41"); + objectCall3(modules[21], Connect, 0, tempvar_41, 0); + IHDL4SEUnit** tempvar_42 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_42"); + objectCall3(tempvar_42, Connect, 0, nets[17], 0); + objectCall3(modules[21], Connect, 1, tempvar_42, 1); + IHDL4SEUnit** tempvar_43 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_43"); + objectCall3(modules[21], Connect, 2, tempvar_43, 0); + objectCall3(nets[41], Connect, 0, modules[21], 3); + modules[ 22] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "16, 16", "rightline7_gen"); + IHDL4SEUnit** tempvar_44 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_44"); + objectCall3(modules[22], Connect, 0, tempvar_44, 0); + IHDL4SEUnit** tempvar_45 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_45"); + objectCall3(tempvar_45, Connect, 0, nets[17], 0); + objectCall3(modules[22], Connect, 1, tempvar_45, 1); + objectCall3(nets[42], Connect, 0, modules[22], 2); + modules[ 23] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "20, 12", "rightline8_gen"); + IHDL4SEUnit** tempvar_46 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_46"); + objectCall3(modules[23], Connect, 0, tempvar_46, 0); + IHDL4SEUnit** tempvar_47 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "12, 12, 0", "tempvar_47"); + objectCall3(tempvar_47, Connect, 0, nets[17], 0); + objectCall3(modules[23], Connect, 1, tempvar_47, 1); + objectCall3(nets[43], Connect, 0, modules[23], 2); + modules[ 24] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "24, 8", "rightline9_gen"); + IHDL4SEUnit** tempvar_48 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_48"); + objectCall3(modules[24], Connect, 0, tempvar_48, 0); + IHDL4SEUnit** tempvar_49 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "8, 8, 0", "tempvar_49"); + objectCall3(tempvar_49, Connect, 0, nets[17], 0); + objectCall3(modules[24], Connect, 1, tempvar_49, 1); + objectCall3(nets[44], Connect, 0, modules[24], 2); + modules[ 25] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "28, 4", "rightline10_gen"); + IHDL4SEUnit** tempvar_50 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_50"); + objectCall3(modules[25], Connect, 0, tempvar_50, 0); + IHDL4SEUnit** tempvar_51 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "4, 4, 0", "tempvar_51"); + objectCall3(tempvar_51, Connect, 0, nets[17], 0); + objectCall3(modules[25], Connect, 1, tempvar_51, 1); + objectCall3(nets[45], Connect, 0, modules[25], 2); + modules[ 26] = hdl4seCreateUnit2(module, "69B4A095-0644-4B9E-9CF0-295474D7C243", "32", "selectrightline"); + IHDL4SEUnit** tempvar_52 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "4, 4, 0", "tempvar_52"); + objectCall3(tempvar_52, Connect, 0, nets[46], 0); + objectCall3(modules[26], Connect, 0, tempvar_52, 1); + objectCall3(modules[26], Connect, 1, nets[19], 0); + objectCall3(modules[26], Connect, 2, nets[19], 0); + objectCall3(modules[26], Connect, 3, nets[19], 0); + objectCall3(modules[26], Connect, 4, nets[19], 0); + objectCall3(modules[26], Connect, 5, nets[19], 0); + objectCall3(modules[26], Connect, 6, nets[35], 0); + objectCall3(modules[26], Connect, 7, nets[36], 0); + objectCall3(modules[26], Connect, 8, nets[37], 0); + objectCall3(modules[26], Connect, 9, nets[38], 0); + objectCall3(modules[26], Connect, 10, nets[39], 0); + objectCall3(modules[26], Connect, 11, nets[40], 0); + objectCall3(modules[26], Connect, 12, nets[41], 0); + objectCall3(modules[26], Connect, 13, nets[42], 0); + objectCall3(modules[26], Connect, 14, nets[43], 0); + objectCall3(modules[26], Connect, 15, nets[44], 0); + objectCall3(modules[26], Connect, 16, nets[45], 0); + objectCall3(nets[33], Connect, 0, modules[26], 17); + modules[ 27] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "32", "writedatasel"); + objectCall3(modules[27], Connect, 0, nets[10], 0); + objectCall3(modules[27], Connect, 1, nets[0], 0); + objectCall3(modules[27], Connect, 2, nets[1], 0); + IHDL4SEUnit** tempvar_53 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_53"); + objectCall3(modules[27], Connect, 3, tempvar_53, 0); + IHDL4SEUnit** tempvar_54 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_54"); + objectCall3(modules[27], Connect, 4, tempvar_54, 0); + objectCall3(modules[27], Connect, 5, unit, 10); + objectCall3(modules[27], Connect, 6, unit, 9); + objectCall3(modules[27], Connect, 7, unit, 8); + IHDL4SEUnit** tempvar_56 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "64, 32, 32", "tempvar_56"); + objectCall3(tempvar_56, Connect, 0, unit, 4); + IHDL4SEUnit** tempvar_57 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 32, 0", "tempvar_57"); + objectCall3(tempvar_57, Connect, 0, unit, 4); + IHDL4SEUnit **tempvar_55 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_55"); + objectCall3(tempvar_55, Connect, 0, nets[12], 0); + objectCall3(tempvar_55, Connect, 1, tempvar_57, 1); + objectCall3(tempvar_55, Connect, 2, tempvar_56, 1); + objectCall3(modules[27], Connect, 8, tempvar_55, 3); + objectCall3(nets[19], Connect, 0, modules[27], 9); + + /* 持续性赋值 */ + /* assign wirein_readaddr = bCtrlState==1?wireout_readaddr+1:6'b0; */ + IHDL4SEUnit** tempvar_60 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_60"); + IHDL4SEUnit **tempvar_59 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_59"); + objectCall3(tempvar_59, Connect, 0, unit, 1); + objectCall3(tempvar_59, Connect, 1, tempvar_60, 0); + IHDL4SEUnit** tempvar_62 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_62"); + IHDL4SEUnit **tempvar_61 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 0", "tempvar_61"); + objectCall3(tempvar_61, Connect, 0, nets[7], 0); + objectCall3(tempvar_61, Connect, 1, tempvar_62, 0); + IHDL4SEUnit** tempvar_63 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_63"); + IHDL4SEUnit **tempvar_58 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_58"); + objectCall3(tempvar_58, Connect, 0, tempvar_59, 2); + objectCall3(tempvar_58, Connect, 1, tempvar_63, 0); + objectCall3(tempvar_58, Connect, 2, tempvar_61, 2); + objectCall3(nets[6], Connect, 0, tempvar_58, 3); + /* assign bFlushReadAddr = wireout_readaddr [6:1] ; */ + IHDL4SEUnit** tempvar_64 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "7, 6, 1", "tempvar_64"); + objectCall3(tempvar_64, Connect, 0, nets[7], 0); + objectCall3(unit, Connect, 3, tempvar_64, 1); + /* assign wCtrlStateComplete = wireout_readaddr==6'd60; */ + IHDL4SEUnit** tempvar_66 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h3c", "tempvar_66"); + IHDL4SEUnit **tempvar_65 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_65"); + objectCall3(tempvar_65, Connect, 0, nets[7], 0); + objectCall3(tempvar_65, Connect, 1, tempvar_66, 0); + objectCall3(unit, Connect, 2, tempvar_65, 2); + /* assign bWriteAddr = 32'hf0000010+wireout_readaddr_delay_1*4; */ + IHDL4SEUnit** tempvar_68 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hf0000010", "tempvar_68"); + IHDL4SEUnit** tempvar_70 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 4", "tempvar_70"); + IHDL4SEUnit **tempvar_69 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 2", "tempvar_69"); + objectCall3(tempvar_69, Connect, 0, nets[8], 0); + objectCall3(tempvar_69, Connect, 1, tempvar_70, 0); + IHDL4SEUnit **tempvar_67 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 0", "tempvar_67"); + objectCall3(tempvar_67, Connect, 0, tempvar_68, 0); + objectCall3(tempvar_67, Connect, 1, tempvar_69, 2); + objectCall3(unit, Connect, 6, tempvar_67, 2); + /* assign wWrite = bCtrlState==1?1:0; */ + IHDL4SEUnit** tempvar_73 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_73"); + IHDL4SEUnit **tempvar_72 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_72"); + objectCall3(tempvar_72, Connect, 0, unit, 1); + objectCall3(tempvar_72, Connect, 1, tempvar_73, 0); + IHDL4SEUnit** tempvar_74 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_74"); + IHDL4SEUnit** tempvar_75 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_75"); + IHDL4SEUnit **tempvar_71 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "1", "tempvar_71"); + objectCall3(tempvar_71, Connect, 0, tempvar_72, 2); + objectCall3(tempvar_71, Connect, 1, tempvar_75, 0); + objectCall3(tempvar_71, Connect, 2, tempvar_74, 0); + objectCall3(unit, Connect, 5, tempvar_71, 3); + /* assign bWriteData = curblockline!=16'b0?right?rightline:leftline:selecteddata; */ + IHDL4SEUnit** tempvar_78 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_78"); + IHDL4SEUnit **tempvar_77 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 5", "tempvar_77"); + objectCall3(tempvar_77, Connect, 0, nets[17], 0); + objectCall3(tempvar_77, Connect, 1, tempvar_78, 0); + IHDL4SEUnit **tempvar_79 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_79"); + objectCall3(tempvar_79, Connect, 0, nets[12], 0); + objectCall3(tempvar_79, Connect, 1, nets[21], 0); + objectCall3(tempvar_79, Connect, 2, nets[34], 0); + IHDL4SEUnit **tempvar_76 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_76"); + objectCall3(tempvar_76, Connect, 0, tempvar_77, 2); + objectCall3(tempvar_76, Connect, 1, nets[19], 0); + objectCall3(tempvar_76, Connect, 2, tempvar_79, 3); + objectCall3(unit, Connect, 7, tempvar_76, 3); + /* assign bNextBlockLo = bNextBlock [31:0] ; */ + IHDL4SEUnit** tempvar_80 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 32, 0", "tempvar_80"); + objectCall3(tempvar_80, Connect, 0, unit, 11); + objectCall3(nets[0], Connect, 0, tempvar_80, 1); + /* assign bNextBlockHi = bNextBlock [63:32] ; */ + IHDL4SEUnit** tempvar_81 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "64, 32, 32", "tempvar_81"); + objectCall3(tempvar_81, Connect, 0, unit, 11); + objectCall3(nets[1], Connect, 0, tempvar_81, 1); + /* assign bCurBlockLo = bCurBlock [31:0] ; */ + IHDL4SEUnit** tempvar_82 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 32, 0", "tempvar_82"); + objectCall3(tempvar_82, Connect, 0, unit, 12); + objectCall3(nets[2], Connect, 0, tempvar_82, 1); + /* assign bCurBlockHi = bCurBlock [63:32] ; */ + IHDL4SEUnit** tempvar_83 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "64, 32, 32", "tempvar_83"); + objectCall3(tempvar_83, Connect, 0, unit, 12); + objectCall3(nets[3], Connect, 0, tempvar_83, 1); + /* assign bCurBlockX = bCurBlockPos [4:0] ; */ + IHDL4SEUnit** tempvar_84 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "5, 5, 0", "tempvar_84"); + objectCall3(tempvar_84, Connect, 0, unit, 13); + objectCall3(nets[4], Connect, 0, tempvar_84, 1); + /* assign bCurBlockY = bCurBlockPos [12:8] ; */ + IHDL4SEUnit** tempvar_85 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "13, 5, 8", "tempvar_85"); + objectCall3(tempvar_85, Connect, 0, unit, 13); + objectCall3(nets[5], Connect, 0, tempvar_85, 1); + /* assign bWriteDataSel = wireout_readaddr_delay_1<6'd52?3'd7:wireout_readaddr_delay_1-6'd52; */ + IHDL4SEUnit** tempvar_88 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h34", "tempvar_88"); + IHDL4SEUnit **tempvar_87 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 6", "tempvar_87"); + objectCall3(tempvar_87, Connect, 0, nets[8], 0); + objectCall3(tempvar_87, Connect, 1, tempvar_88, 0); + IHDL4SEUnit** tempvar_89 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h7", "tempvar_89"); + IHDL4SEUnit** tempvar_91 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h34", "tempvar_91"); + IHDL4SEUnit **tempvar_90 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 1", "tempvar_90"); + objectCall3(tempvar_90, Connect, 0, nets[8], 0); + objectCall3(tempvar_90, Connect, 1, tempvar_91, 0); + IHDL4SEUnit **tempvar_86 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_86"); + objectCall3(tempvar_86, Connect, 0, tempvar_87, 2); + objectCall3(tempvar_86, Connect, 1, tempvar_90, 2); + objectCall3(tempvar_86, Connect, 2, tempvar_89, 0); + objectCall3(nets[10], Connect, 0, tempvar_86, 3); + /* assign line = wireout_readaddr_delay_1 [5:1] ; */ + IHDL4SEUnit** tempvar_92 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "6, 5, 1", "tempvar_92"); + objectCall3(tempvar_92, Connect, 0, nets[8], 0); + objectCall3(nets[11], Connect, 0, tempvar_92, 1); + /* assign right = wireout_readaddr_delay_1 [0] ; */ + IHDL4SEUnit** tempvar_93 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "1, 1, 0", "tempvar_93"); + objectCall3(tempvar_93, Connect, 0, nets[8], 0); + objectCall3(nets[12], Connect, 0, tempvar_93, 1); + /* assign line3 = line+2==bCurBlockY?16'hffff:16'b0; */ + IHDL4SEUnit** tempvar_97 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 2", "tempvar_97"); + IHDL4SEUnit **tempvar_96 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 0", "tempvar_96"); + objectCall3(tempvar_96, Connect, 0, nets[11], 0); + objectCall3(tempvar_96, Connect, 1, tempvar_97, 0); + IHDL4SEUnit **tempvar_95 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_95"); + objectCall3(tempvar_95, Connect, 0, tempvar_96, 2); + objectCall3(tempvar_95, Connect, 1, nets[5], 0); + IHDL4SEUnit** tempvar_98 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hffff", "tempvar_98"); + IHDL4SEUnit** tempvar_99 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_99"); + IHDL4SEUnit **tempvar_94 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_94"); + objectCall3(tempvar_94, Connect, 0, tempvar_95, 2); + objectCall3(tempvar_94, Connect, 1, tempvar_99, 0); + objectCall3(tempvar_94, Connect, 2, tempvar_98, 0); + objectCall3(nets[13], Connect, 0, tempvar_94, 3); + /* assign line2 = line+1==bCurBlockY?16'hffff:16'b0; */ + IHDL4SEUnit** tempvar_103 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_103"); + IHDL4SEUnit **tempvar_102 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 0", "tempvar_102"); + objectCall3(tempvar_102, Connect, 0, nets[11], 0); + objectCall3(tempvar_102, Connect, 1, tempvar_103, 0); + IHDL4SEUnit **tempvar_101 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_101"); + objectCall3(tempvar_101, Connect, 0, tempvar_102, 2); + objectCall3(tempvar_101, Connect, 1, nets[5], 0); + IHDL4SEUnit** tempvar_104 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hffff", "tempvar_104"); + IHDL4SEUnit** tempvar_105 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_105"); + IHDL4SEUnit **tempvar_100 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_100"); + objectCall3(tempvar_100, Connect, 0, tempvar_101, 2); + objectCall3(tempvar_100, Connect, 1, tempvar_105, 0); + objectCall3(tempvar_100, Connect, 2, tempvar_104, 0); + objectCall3(nets[14], Connect, 0, tempvar_100, 3); + /* assign line1 = line==bCurBlockY?16'hffff:16'b0; */ + IHDL4SEUnit **tempvar_107 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_107"); + objectCall3(tempvar_107, Connect, 0, nets[11], 0); + objectCall3(tempvar_107, Connect, 1, nets[5], 0); + IHDL4SEUnit** tempvar_108 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hffff", "tempvar_108"); + IHDL4SEUnit** tempvar_109 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_109"); + IHDL4SEUnit **tempvar_106 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_106"); + objectCall3(tempvar_106, Connect, 0, tempvar_107, 2); + objectCall3(tempvar_106, Connect, 1, tempvar_109, 0); + objectCall3(tempvar_106, Connect, 2, tempvar_108, 0); + objectCall3(nets[15], Connect, 0, tempvar_106, 3); + /* assign line0 = line==bCurBlockY+1?16'hffff:16'b0; */ + IHDL4SEUnit** tempvar_113 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_113"); + IHDL4SEUnit **tempvar_112 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 0", "tempvar_112"); + objectCall3(tempvar_112, Connect, 0, nets[5], 0); + objectCall3(tempvar_112, Connect, 1, tempvar_113, 0); + IHDL4SEUnit **tempvar_111 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_111"); + objectCall3(tempvar_111, Connect, 0, nets[11], 0); + objectCall3(tempvar_111, Connect, 1, tempvar_112, 2); + IHDL4SEUnit** tempvar_114 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hffff", "tempvar_114"); + IHDL4SEUnit** tempvar_115 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_115"); + IHDL4SEUnit **tempvar_110 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_110"); + objectCall3(tempvar_110, Connect, 0, tempvar_111, 2); + objectCall3(tempvar_110, Connect, 1, tempvar_115, 0); + objectCall3(tempvar_110, Connect, 2, tempvar_114, 0); + objectCall3(nets[16], Connect, 0, tempvar_110, 3); + /* assign curblockline = line0&bCurBlock [15:0] |line1&bCurBlock [31:16] |line2&bCurBlock [47:32] |line3&bCurBlock [63:48] ; */ + IHDL4SEUnit** tempvar_118 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_118"); + objectCall3(tempvar_118, Connect, 0, unit, 12); + IHDL4SEUnit **tempvar_117 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 10", "tempvar_117"); + objectCall3(tempvar_117, Connect, 0, nets[16], 0); + objectCall3(tempvar_117, Connect, 1, tempvar_118, 1); + IHDL4SEUnit** tempvar_121 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 16, 16", "tempvar_121"); + objectCall3(tempvar_121, Connect, 0, unit, 12); + IHDL4SEUnit **tempvar_120 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 10", "tempvar_120"); + objectCall3(tempvar_120, Connect, 0, nets[15], 0); + objectCall3(tempvar_120, Connect, 1, tempvar_121, 1); + IHDL4SEUnit** tempvar_124 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "48, 16, 32", "tempvar_124"); + objectCall3(tempvar_124, Connect, 0, unit, 12); + IHDL4SEUnit **tempvar_123 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 10", "tempvar_123"); + objectCall3(tempvar_123, Connect, 0, nets[14], 0); + objectCall3(tempvar_123, Connect, 1, tempvar_124, 1); + IHDL4SEUnit** tempvar_126 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "64, 16, 48", "tempvar_126"); + objectCall3(tempvar_126, Connect, 0, unit, 12); + IHDL4SEUnit **tempvar_125 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 10", "tempvar_125"); + objectCall3(tempvar_125, Connect, 0, nets[13], 0); + objectCall3(tempvar_125, Connect, 1, tempvar_126, 1); + IHDL4SEUnit **tempvar_122 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 11", "tempvar_122"); + objectCall3(tempvar_122, Connect, 0, tempvar_123, 2); + objectCall3(tempvar_122, Connect, 1, tempvar_125, 2); + IHDL4SEUnit **tempvar_119 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 11", "tempvar_119"); + objectCall3(tempvar_119, Connect, 0, tempvar_120, 2); + objectCall3(tempvar_119, Connect, 1, tempvar_122, 2); + IHDL4SEUnit **tempvar_116 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 11", "tempvar_116"); + objectCall3(tempvar_116, Connect, 0, tempvar_117, 2); + objectCall3(tempvar_116, Connect, 1, tempvar_119, 2); + objectCall3(nets[17], Connect, 0, tempvar_116, 2); + /* assign leftline = bCurBlockX [5:4] ?selecteddata:leftline_0_15|selecteddata; */ + IHDL4SEUnit** tempvar_128 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "6, 2, 4", "tempvar_128"); + objectCall3(tempvar_128, Connect, 0, nets[4], 0); + IHDL4SEUnit **tempvar_129 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 11", "tempvar_129"); + objectCall3(tempvar_129, Connect, 0, nets[20], 0); + objectCall3(tempvar_129, Connect, 1, nets[19], 0); + IHDL4SEUnit **tempvar_127 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_127"); + objectCall3(tempvar_127, Connect, 0, tempvar_128, 1); + objectCall3(tempvar_127, Connect, 1, tempvar_129, 2); + objectCall3(tempvar_127, Connect, 2, nets[19], 0); + objectCall3(nets[21], Connect, 0, tempvar_127, 3); + /* assign rightline = bCurBlockX [5:0] >=3?rightline_3_18|selecteddata:selecteddata; */ + IHDL4SEUnit** tempvar_132 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "6, 6, 0", "tempvar_132"); + objectCall3(tempvar_132, Connect, 0, nets[4], 0); + IHDL4SEUnit** tempvar_133 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 3", "tempvar_133"); + IHDL4SEUnit **tempvar_131 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "6, 6, 1, 8", "tempvar_131"); + objectCall3(tempvar_131, Connect, 0, tempvar_132, 1); + objectCall3(tempvar_131, Connect, 1, tempvar_133, 0); + IHDL4SEUnit **tempvar_134 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 11", "tempvar_134"); + objectCall3(tempvar_134, Connect, 0, nets[33], 0); + objectCall3(tempvar_134, Connect, 1, nets[19], 0); + IHDL4SEUnit **tempvar_130 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_130"); + objectCall3(tempvar_130, Connect, 0, tempvar_131, 2); + objectCall3(tempvar_130, Connect, 1, nets[19], 0); + objectCall3(tempvar_130, Connect, 2, tempvar_134, 2); + objectCall3(nets[34], Connect, 0, tempvar_130, 3); + /* assign blockx_3 = bCurBlockX [5:0] -6'd3; */ + IHDL4SEUnit** tempvar_136 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "6, 6, 0", "tempvar_136"); + objectCall3(tempvar_136, Connect, 0, nets[4], 0); + IHDL4SEUnit** tempvar_137 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h3", "tempvar_137"); + IHDL4SEUnit **tempvar_135 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 1", "tempvar_135"); + objectCall3(tempvar_135, Connect, 0, tempvar_136, 1); + objectCall3(tempvar_135, Connect, 1, tempvar_137, 0); + objectCall3(nets[46], Connect, 0, tempvar_135, 2); + + /*释放module接口*/ + objectRelease(module); + /*返回unit接口*/ + return unit; +} + + +IHDL4SEUnit** hdl4seCreate_0012(IHDL4SEModule** parent, const char* instanceparam, const char* name) { /* module main */ IHDL4SEModule** module; IHDL4SEUnit** unit; - IHDL4SEUnit** nets[69]; - IHDL4SEUnit** modules[30]; + IHDL4SEUnit** nets[22]; + IHDL4SEUnit** modules[3]; /* 生成模块对象 */ unit = hdl4seCreateUnit(parent, CLSID_HDL4SE_MODULE, instanceparam, name); @@ -73,14 +633,14 @@ IHDL4SEUnit** hdl4seCreate_0011(IHDL4SEModule** parent, const char* instancepara /* 线网 */ nets[ 0] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wram_Write"); nets[ 1] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bram_WriteAddr"); - nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bram_WriteData"); + nets[ 2] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bram_WriteData"); nets[ 3] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bram_ReadAddr"); - nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bram_ReadData"); + nets[ 4] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bram_ReadData"); nets[ 5] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCtrlWrite"); nets[ 6] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bCtrlWriteAddr"); - nets[ 7] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlWriteData"); + nets[ 7] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bCtrlWriteData"); nets[ 8] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bCtrlReadAddr"); - nets[ 9] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlReadData"); + nets[ 9] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bCtrlReadData"); nets[ 10] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCtrlKeyData"); nets[ 11] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCtrlStateComplete"); nets[ 12] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "wCtrlStateChange"); @@ -91,58 +651,11 @@ IHDL4SEUnit** hdl4seCreate_0011(IHDL4SEModule** parent, const char* instancepara nets[ 17] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bNextBlock"); nets[ 18] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bCurBlock"); nets[ 19] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "bCurBlockPos"); - nets[ 20] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bNextBlockLo"); - nets[ 21] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bNextBlockHi"); - nets[ 22] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCurBlockLo"); - nets[ 23] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bCurBlockHi"); - nets[ 24] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 5", "bCurBlockX"); - nets[ 25] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 5", "bCurBlockY"); - nets[ 26] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bFlushReadAddr"); - nets[ 27] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "bFlushReadData"); - nets[ 28] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 7", "wirein_readaddr"); - nets[ 29] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 7", "wireout_readaddr"); - nets[ 30] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 7", "wireout_readaddr_delay_1"); - nets[ 31] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "wireout_readaddr2"); - nets[ 32] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 3", "bWriteDataSel"); - nets[ 33] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 5", "line"); - nets[ 34] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 1", "right"); - nets[ 35] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "line3"); - nets[ 36] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "line2"); - nets[ 37] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "line1"); - nets[ 38] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "line0"); - nets[ 39] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 16", "curblockline"); - nets[ 40] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "curline"); - nets[ 41] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "selecteddata"); - nets[ 42] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline_0_15"); - nets[ 43] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline"); - nets[ 44] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline_1"); - nets[ 45] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline0"); - nets[ 46] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline1"); - nets[ 47] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline2"); - nets[ 48] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline3"); - nets[ 49] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline4"); - nets[ 50] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline5"); - nets[ 51] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline6"); - nets[ 52] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline7"); - nets[ 53] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline8"); - nets[ 54] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "leftline9"); - nets[ 55] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline_3_18"); - nets[ 56] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline"); - nets[ 57] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline0"); - nets[ 58] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline1"); - nets[ 59] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline2"); - nets[ 60] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline3"); - nets[ 61] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline4"); - nets[ 62] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline5"); - nets[ 63] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline6"); - nets[ 64] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline7"); - nets[ 65] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline8"); - nets[ 66] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline9"); - nets[ 67] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 32", "rightline10"); - nets[ 68] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "blockx_3"); + nets[ 20] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 6", "bFlushReadAddr"); + nets[ 21] = hdl4seCreateUnit(module, CLSID_HDL4SE_WIRE, " 64", "bFlushReadData"); /* 模块实例化 */ - modules[ 0] = hdl4seCreateUnit2(module, "dffb1080-8b92-4b42-a607-d1b377c27bb1", "32, 6", "ram_0"); + modules[ 0] = hdl4seCreateUnit2(module, "dffb1080-8b92-4b42-a607-d1b377c27bb1", "64, 6", "ram_0"); objectCall3(modules[0], Connect, 0, unit, 0); objectCall3(modules[0], Connect, 1, nets[0], 0); objectCall3(modules[0], Connect, 2, nets[1], 0); @@ -167,547 +680,78 @@ IHDL4SEUnit** hdl4seCreate_0011(IHDL4SEModule** parent, const char* instancepara objectCall3(nets[17], Connect, 0, modules[1], 14); objectCall3(nets[18], Connect, 0, modules[1], 15); objectCall3(nets[19], Connect, 0, modules[1], 16); - modules[ 2] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "ramreadaddr"); + modules[ 2] = hdl4seCreate_0011(module, "", "flusher"); objectCall3(modules[2], Connect, 0, unit, 0); - objectCall3(modules[2], Connect, 1, nets[28], 0); - objectCall3(nets[29], Connect, 0, modules[2], 2); - modules[ 3] = hdl4seCreateUnit2(module, "76FBFD4B-FEAD-45fd-AA27-AFC58AC241C2", "6", "ramreadaddr_delay_1"); - objectCall3(modules[3], Connect, 0, unit, 0); - objectCall3(modules[3], Connect, 1, nets[29], 0); - objectCall3(nets[30], Connect, 0, modules[3], 2); - modules[ 4] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "16, 16", "curlinebind"); - objectCall3(modules[4], Connect, 0, nets[39], 0); - IHDL4SEUnit** tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 16, 16", "tempvar_0"); - objectCall3(tempvar_0, Connect, 0, nets[41], 0); - objectCall3(modules[4], Connect, 1, tempvar_0, 1); - objectCall3(nets[40], Connect, 0, modules[4], 2); - modules[ 5] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "4, 28", "leftline0_gen"); - IHDL4SEUnit** tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 4, 12", "tempvar_1"); - objectCall3(tempvar_1, Connect, 0, nets[39], 0); - objectCall3(modules[5], Connect, 0, tempvar_1, 1); - IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "28, 28, 0", "tempvar_2"); - objectCall3(tempvar_2, Connect, 0, nets[41], 0); - objectCall3(modules[5], Connect, 1, tempvar_2, 1); - objectCall3(nets[44], Connect, 0, modules[5], 2); - modules[ 6] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "8, 24", "leftline0_gen"); - IHDL4SEUnit** tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 8, 8", "tempvar_3"); - objectCall3(tempvar_3, Connect, 0, nets[39], 0); - objectCall3(modules[6], Connect, 0, tempvar_3, 1); - IHDL4SEUnit** tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "24, 24, 0", "tempvar_4"); - objectCall3(tempvar_4, Connect, 0, nets[41], 0); - objectCall3(modules[6], Connect, 1, tempvar_4, 1); - objectCall3(nets[45], Connect, 0, modules[6], 2); - modules[ 7] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "12, 20", "leftline1_gen"); - IHDL4SEUnit** tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 12, 4", "tempvar_5"); - objectCall3(tempvar_5, Connect, 0, nets[39], 0); - objectCall3(modules[7], Connect, 0, tempvar_5, 1); - IHDL4SEUnit** tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "20, 20, 0", "tempvar_6"); - objectCall3(tempvar_6, Connect, 0, nets[41], 0); - objectCall3(modules[7], Connect, 1, tempvar_6, 1); - objectCall3(nets[46], Connect, 0, modules[7], 2); - modules[ 8] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "16, 16", "leftline2_gen"); - IHDL4SEUnit** tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_7"); - objectCall3(tempvar_7, Connect, 0, nets[39], 0); - objectCall3(modules[8], Connect, 0, tempvar_7, 1); - IHDL4SEUnit** tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_8"); - objectCall3(tempvar_8, Connect, 0, nets[41], 0); - objectCall3(modules[8], Connect, 1, tempvar_8, 1); - objectCall3(nets[47], Connect, 0, modules[8], 2); - modules[ 9] = hdl4seCreateUnit2(module, "D1F303E2-3ED1-42FD-8762-3AA623DA901E", "4, 16, 12", "leftline3_gen"); - IHDL4SEUnit** tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 4, 28", "tempvar_9"); - objectCall3(tempvar_9, Connect, 0, nets[41], 0); - objectCall3(modules[9], Connect, 0, tempvar_9, 1); - IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_10"); - objectCall3(tempvar_10, Connect, 0, nets[39], 0); - objectCall3(modules[9], Connect, 1, tempvar_10, 1); - IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "12, 12, 0", "tempvar_11"); - objectCall3(tempvar_11, Connect, 0, nets[41], 0); - objectCall3(modules[9], Connect, 2, tempvar_11, 1); - objectCall3(nets[48], Connect, 0, modules[9], 3); - modules[ 10] = hdl4seCreateUnit2(module, "D1F303E2-3ED1-42FD-8762-3AA623DA901E", "8, 16, 8", "leftline4_gen"); - IHDL4SEUnit** tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 8, 24", "tempvar_12"); - objectCall3(tempvar_12, Connect, 0, nets[41], 0); - objectCall3(modules[10], Connect, 0, tempvar_12, 1); - IHDL4SEUnit** tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_13"); - objectCall3(tempvar_13, Connect, 0, nets[39], 0); - objectCall3(modules[10], Connect, 1, tempvar_13, 1); - IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "8, 8, 0", "tempvar_14"); - objectCall3(tempvar_14, Connect, 0, nets[41], 0); - objectCall3(modules[10], Connect, 2, tempvar_14, 1); - objectCall3(nets[49], Connect, 0, modules[10], 3); - modules[ 11] = hdl4seCreateUnit2(module, "D1F303E2-3ED1-42FD-8762-3AA623DA901E", "12, 16, 4", "leftline5_gen"); - IHDL4SEUnit** tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 12, 20", "tempvar_15"); - objectCall3(tempvar_15, Connect, 0, nets[41], 0); - objectCall3(modules[11], Connect, 0, tempvar_15, 1); - IHDL4SEUnit** tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_16"); - objectCall3(tempvar_16, Connect, 0, nets[39], 0); - objectCall3(modules[11], Connect, 1, tempvar_16, 1); - IHDL4SEUnit** tempvar_17 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "4, 4, 0", "tempvar_17"); - objectCall3(tempvar_17, Connect, 0, nets[41], 0); - objectCall3(modules[11], Connect, 2, tempvar_17, 1); - objectCall3(nets[50], Connect, 0, modules[11], 3); - modules[ 12] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "16, 16", "leftline6_gen"); - IHDL4SEUnit** tempvar_18 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 16, 16", "tempvar_18"); - objectCall3(tempvar_18, Connect, 0, nets[41], 0); - objectCall3(modules[12], Connect, 0, tempvar_18, 1); - IHDL4SEUnit** tempvar_19 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_19"); - objectCall3(tempvar_19, Connect, 0, nets[39], 0); - objectCall3(modules[12], Connect, 1, tempvar_19, 1); - objectCall3(nets[51], Connect, 0, modules[12], 2); - modules[ 13] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "20, 12", "leftline7_gen"); - IHDL4SEUnit** tempvar_20 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 20, 12", "tempvar_20"); - objectCall3(tempvar_20, Connect, 0, nets[41], 0); - objectCall3(modules[13], Connect, 0, tempvar_20, 1); - IHDL4SEUnit** tempvar_21 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "12, 12, 0", "tempvar_21"); - objectCall3(tempvar_21, Connect, 0, nets[39], 0); - objectCall3(modules[13], Connect, 1, tempvar_21, 1); - objectCall3(nets[52], Connect, 0, modules[13], 2); - modules[ 14] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "24, 8", "leftline8_gen"); - IHDL4SEUnit** tempvar_22 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 24, 8", "tempvar_22"); - objectCall3(tempvar_22, Connect, 0, nets[41], 0); - objectCall3(modules[14], Connect, 0, tempvar_22, 1); - IHDL4SEUnit** tempvar_23 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "8, 8, 0", "tempvar_23"); - objectCall3(tempvar_23, Connect, 0, nets[39], 0); - objectCall3(modules[14], Connect, 1, tempvar_23, 1); - objectCall3(nets[53], Connect, 0, modules[14], 2); - modules[ 15] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "28, 4", "leftline9_gen"); - IHDL4SEUnit** tempvar_24 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 28, 4", "tempvar_24"); - objectCall3(tempvar_24, Connect, 0, nets[41], 0); - objectCall3(modules[15], Connect, 0, tempvar_24, 1); - IHDL4SEUnit** tempvar_25 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "4, 4, 0", "tempvar_25"); - objectCall3(tempvar_25, Connect, 0, nets[39], 0); - objectCall3(modules[15], Connect, 1, tempvar_25, 1); - objectCall3(nets[54], Connect, 0, modules[15], 2); - modules[ 16] = hdl4seCreateUnit2(module, "69B4A095-0644-4B9E-9CF0-295474D7C243", "32", "selectleftline"); - IHDL4SEUnit** tempvar_26 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "4, 4, 0", "tempvar_26"); - objectCall3(tempvar_26, Connect, 0, nets[24], 0); - objectCall3(modules[16], Connect, 0, tempvar_26, 1); - objectCall3(modules[16], Connect, 1, nets[44], 0); - objectCall3(modules[16], Connect, 2, nets[45], 0); - objectCall3(modules[16], Connect, 3, nets[46], 0); - objectCall3(modules[16], Connect, 4, nets[47], 0); - objectCall3(modules[16], Connect, 5, nets[48], 0); - objectCall3(modules[16], Connect, 6, nets[49], 0); - objectCall3(modules[16], Connect, 7, nets[50], 0); - objectCall3(modules[16], Connect, 8, nets[51], 0); - objectCall3(modules[16], Connect, 9, nets[52], 0); - objectCall3(modules[16], Connect, 10, nets[53], 0); - objectCall3(modules[16], Connect, 11, nets[54], 0); - objectCall3(modules[16], Connect, 12, nets[41], 0); - objectCall3(modules[16], Connect, 13, nets[41], 0); - objectCall3(modules[16], Connect, 14, nets[41], 0); - objectCall3(modules[16], Connect, 15, nets[41], 0); - objectCall3(modules[16], Connect, 16, nets[41], 0); - objectCall3(nets[42], Connect, 0, modules[16], 17); - modules[ 17] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "4, 28", "rightline0_gen"); - IHDL4SEUnit** tempvar_27 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 4, 12", "tempvar_27"); - objectCall3(tempvar_27, Connect, 0, nets[39], 0); - objectCall3(modules[17], Connect, 0, tempvar_27, 1); - IHDL4SEUnit** tempvar_28 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "28, 28, 0", "tempvar_28"); - objectCall3(tempvar_28, Connect, 0, nets[41], 0); - objectCall3(modules[17], Connect, 1, tempvar_28, 1); - objectCall3(nets[57], Connect, 0, modules[17], 2); - modules[ 18] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "8, 24", "rightline1_gen"); - IHDL4SEUnit** tempvar_29 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 8, 8", "tempvar_29"); - objectCall3(tempvar_29, Connect, 0, nets[39], 0); - objectCall3(modules[18], Connect, 0, tempvar_29, 1); - IHDL4SEUnit** tempvar_30 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "24, 24, 0", "tempvar_30"); - objectCall3(tempvar_30, Connect, 0, nets[41], 0); - objectCall3(modules[18], Connect, 1, tempvar_30, 1); - objectCall3(nets[58], Connect, 0, modules[18], 2); - modules[ 19] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "12, 20", "rightline2_gen"); - IHDL4SEUnit** tempvar_31 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 12, 4", "tempvar_31"); - objectCall3(tempvar_31, Connect, 0, nets[39], 0); - objectCall3(modules[19], Connect, 0, tempvar_31, 1); - IHDL4SEUnit** tempvar_32 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "20, 20, 0", "tempvar_32"); - objectCall3(tempvar_32, Connect, 0, nets[41], 0); - objectCall3(modules[19], Connect, 1, tempvar_32, 1); - objectCall3(nets[59], Connect, 0, modules[19], 2); - modules[ 20] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "16, 16", "rightline3_gen"); - IHDL4SEUnit** tempvar_33 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_33"); - objectCall3(tempvar_33, Connect, 0, nets[39], 0); - objectCall3(modules[20], Connect, 0, tempvar_33, 1); - IHDL4SEUnit** tempvar_34 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_34"); - objectCall3(tempvar_34, Connect, 0, nets[41], 0); - objectCall3(modules[20], Connect, 1, tempvar_34, 1); - objectCall3(nets[60], Connect, 0, modules[20], 2); - modules[ 21] = hdl4seCreateUnit2(module, "D1F303E2-3ED1-42FD-8762-3AA623DA901E", "4, 16, 12", "rightline4_gen"); - IHDL4SEUnit** tempvar_35 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 4, 28", "tempvar_35"); - objectCall3(tempvar_35, Connect, 0, nets[41], 0); - objectCall3(modules[21], Connect, 0, tempvar_35, 1); - IHDL4SEUnit** tempvar_36 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_36"); - objectCall3(tempvar_36, Connect, 0, nets[39], 0); - objectCall3(modules[21], Connect, 1, tempvar_36, 1); - IHDL4SEUnit** tempvar_37 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "12, 12, 0", "tempvar_37"); - objectCall3(tempvar_37, Connect, 0, nets[41], 0); - objectCall3(modules[21], Connect, 2, tempvar_37, 1); - objectCall3(nets[61], Connect, 0, modules[21], 3); - modules[ 22] = hdl4seCreateUnit2(module, "D1F303E2-3ED1-42FD-8762-3AA623DA901E", "8, 16, 8", "rightline5_gen"); - IHDL4SEUnit** tempvar_38 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 8, 24", "tempvar_38"); - objectCall3(tempvar_38, Connect, 0, nets[41], 0); - objectCall3(modules[22], Connect, 0, tempvar_38, 1); - IHDL4SEUnit** tempvar_39 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_39"); - objectCall3(tempvar_39, Connect, 0, nets[39], 0); - objectCall3(modules[22], Connect, 1, tempvar_39, 1); - IHDL4SEUnit** tempvar_40 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "8, 8, 0", "tempvar_40"); - objectCall3(tempvar_40, Connect, 0, nets[41], 0); - objectCall3(modules[22], Connect, 2, tempvar_40, 1); - objectCall3(nets[62], Connect, 0, modules[22], 3); - modules[ 23] = hdl4seCreateUnit2(module, "D1F303E2-3ED1-42FD-8762-3AA623DA901E", "12, 16, 4", "rightline6_gen"); - IHDL4SEUnit** tempvar_41 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 12, 20", "tempvar_41"); - objectCall3(tempvar_41, Connect, 0, nets[41], 0); - objectCall3(modules[23], Connect, 0, tempvar_41, 1); - IHDL4SEUnit** tempvar_42 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_42"); - objectCall3(tempvar_42, Connect, 0, nets[39], 0); - objectCall3(modules[23], Connect, 1, tempvar_42, 1); - IHDL4SEUnit** tempvar_43 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "4, 4, 0", "tempvar_43"); - objectCall3(tempvar_43, Connect, 0, nets[41], 0); - objectCall3(modules[23], Connect, 2, tempvar_43, 1); - objectCall3(nets[63], Connect, 0, modules[23], 3); - modules[ 24] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "16, 16", "rightline7_gen"); - IHDL4SEUnit** tempvar_44 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 16, 16", "tempvar_44"); - objectCall3(tempvar_44, Connect, 0, nets[41], 0); - objectCall3(modules[24], Connect, 0, tempvar_44, 1); - IHDL4SEUnit** tempvar_45 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_45"); - objectCall3(tempvar_45, Connect, 0, nets[39], 0); - objectCall3(modules[24], Connect, 1, tempvar_45, 1); - objectCall3(nets[64], Connect, 0, modules[24], 2); - modules[ 25] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "20, 12", "rightline8_gen"); - IHDL4SEUnit** tempvar_46 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 20, 12", "tempvar_46"); - objectCall3(tempvar_46, Connect, 0, nets[41], 0); - objectCall3(modules[25], Connect, 0, tempvar_46, 1); - IHDL4SEUnit** tempvar_47 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "12, 12, 0", "tempvar_47"); - objectCall3(tempvar_47, Connect, 0, nets[39], 0); - objectCall3(modules[25], Connect, 1, tempvar_47, 1); - objectCall3(nets[65], Connect, 0, modules[25], 2); - modules[ 26] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "24, 8", "rightline9_gen"); - IHDL4SEUnit** tempvar_48 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 24, 8", "tempvar_48"); - objectCall3(tempvar_48, Connect, 0, nets[41], 0); - objectCall3(modules[26], Connect, 0, tempvar_48, 1); - IHDL4SEUnit** tempvar_49 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "8, 8, 0", "tempvar_49"); - objectCall3(tempvar_49, Connect, 0, nets[39], 0); - objectCall3(modules[26], Connect, 1, tempvar_49, 1); - objectCall3(nets[66], Connect, 0, modules[26], 2); - modules[ 27] = hdl4seCreateUnit2(module, "DA8C1494-B6F6-4910-BB2B-C9BCFCB9FAD0", "28, 4", "rightline10_gen"); - IHDL4SEUnit** tempvar_50 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 28, 4", "tempvar_50"); - objectCall3(tempvar_50, Connect, 0, nets[41], 0); - objectCall3(modules[27], Connect, 0, tempvar_50, 1); - IHDL4SEUnit** tempvar_51 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "4, 4, 0", "tempvar_51"); - objectCall3(tempvar_51, Connect, 0, nets[39], 0); - objectCall3(modules[27], Connect, 1, tempvar_51, 1); - objectCall3(nets[67], Connect, 0, modules[27], 2); - modules[ 28] = hdl4seCreateUnit2(module, "69B4A095-0644-4B9E-9CF0-295474D7C243", "32", "selectrightline"); - IHDL4SEUnit** tempvar_52 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "4, 4, 0", "tempvar_52"); - objectCall3(tempvar_52, Connect, 0, nets[68], 0); - objectCall3(modules[28], Connect, 0, tempvar_52, 1); - objectCall3(modules[28], Connect, 1, nets[41], 0); - objectCall3(modules[28], Connect, 2, nets[41], 0); - objectCall3(modules[28], Connect, 3, nets[41], 0); - objectCall3(modules[28], Connect, 4, nets[41], 0); - objectCall3(modules[28], Connect, 5, nets[41], 0); - objectCall3(modules[28], Connect, 6, nets[57], 0); - objectCall3(modules[28], Connect, 7, nets[58], 0); - objectCall3(modules[28], Connect, 8, nets[59], 0); - objectCall3(modules[28], Connect, 9, nets[60], 0); - objectCall3(modules[28], Connect, 10, nets[61], 0); - objectCall3(modules[28], Connect, 11, nets[62], 0); - objectCall3(modules[28], Connect, 12, nets[63], 0); - objectCall3(modules[28], Connect, 13, nets[64], 0); - objectCall3(modules[28], Connect, 14, nets[65], 0); - objectCall3(modules[28], Connect, 15, nets[66], 0); - objectCall3(modules[28], Connect, 16, nets[67], 0); - objectCall3(nets[55], Connect, 0, modules[28], 17); - modules[ 29] = hdl4seCreateUnit2(module, "DD99B7F6-9ED1-45BB-8150-ED78EEF982CA", "32", "writedatasel"); - objectCall3(modules[29], Connect, 0, nets[32], 0); - objectCall3(modules[29], Connect, 1, nets[20], 0); - objectCall3(modules[29], Connect, 2, nets[21], 0); - IHDL4SEUnit** tempvar_53 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_53"); - objectCall3(modules[29], Connect, 3, tempvar_53, 0); - IHDL4SEUnit** tempvar_54 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_54"); - objectCall3(modules[29], Connect, 4, tempvar_54, 0); - objectCall3(modules[29], Connect, 5, nets[16], 0); - objectCall3(modules[29], Connect, 6, nets[15], 0); - objectCall3(modules[29], Connect, 7, nets[14], 0); - objectCall3(modules[29], Connect, 8, nets[4], 0); - objectCall3(nets[41], Connect, 0, modules[29], 9); + objectCall3(modules[2], Connect, 1, nets[13], 0); + objectCall3(nets[11], Connect, 0, modules[2], 2); + objectCall3(nets[20], Connect, 0, modules[2], 3); + objectCall3(modules[2], Connect, 4, nets[21], 0); + objectCall3(unit, Connect, 2, modules[2], 5); + objectCall3(unit, Connect, 3, modules[2], 6); + objectCall3(unit, Connect, 4, modules[2], 7); + objectCall3(modules[2], Connect, 8, nets[14], 0); + objectCall3(modules[2], Connect, 9, nets[15], 0); + objectCall3(modules[2], Connect, 10, nets[16], 0); + objectCall3(modules[2], Connect, 11, nets[17], 0); + objectCall3(modules[2], Connect, 12, nets[18], 0); + objectCall3(modules[2], Connect, 13, nets[19], 0); /* 持续性赋值 */ /* assign wram_Write = bCtrlState==1?1'b0:wCtrlWrite; */ - IHDL4SEUnit** tempvar_57 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_57"); - IHDL4SEUnit **tempvar_56 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_56"); - objectCall3(tempvar_56, Connect, 0, nets[13], 0); - objectCall3(tempvar_56, Connect, 1, tempvar_57, 0); - IHDL4SEUnit** tempvar_58 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_58"); - IHDL4SEUnit **tempvar_55 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_55"); - objectCall3(tempvar_55, Connect, 0, tempvar_56, 2); - objectCall3(tempvar_55, Connect, 1, nets[5], 0); - objectCall3(tempvar_55, Connect, 2, tempvar_58, 0); - objectCall3(nets[0], Connect, 0, tempvar_55, 3); + IHDL4SEUnit** tempvar_2 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_2"); + IHDL4SEUnit **tempvar_1 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_1"); + objectCall3(tempvar_1, Connect, 0, nets[13], 0); + objectCall3(tempvar_1, Connect, 1, tempvar_2, 0); + IHDL4SEUnit** tempvar_3 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_3"); + IHDL4SEUnit **tempvar_0 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_0"); + objectCall3(tempvar_0, Connect, 0, tempvar_1, 2); + objectCall3(tempvar_0, Connect, 1, nets[5], 0); + objectCall3(tempvar_0, Connect, 2, tempvar_3, 0); + objectCall3(nets[0], Connect, 0, tempvar_0, 3); /* assign bram_WriteAddr = bCtrlState==1?6'b0:bCtrlWriteAddr; */ - IHDL4SEUnit** tempvar_61 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_61"); - IHDL4SEUnit **tempvar_60 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_60"); - objectCall3(tempvar_60, Connect, 0, nets[13], 0); - objectCall3(tempvar_60, Connect, 1, tempvar_61, 0); - IHDL4SEUnit** tempvar_62 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_62"); - IHDL4SEUnit **tempvar_59 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_59"); - objectCall3(tempvar_59, Connect, 0, tempvar_60, 2); - objectCall3(tempvar_59, Connect, 1, nets[6], 0); - objectCall3(tempvar_59, Connect, 2, tempvar_62, 0); - objectCall3(nets[1], Connect, 0, tempvar_59, 3); - /* assign bram_WriteData = bCtrlState==1?32'b0:bCtrlWriteData; */ - IHDL4SEUnit** tempvar_65 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_65"); - IHDL4SEUnit **tempvar_64 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_64"); - objectCall3(tempvar_64, Connect, 0, nets[13], 0); - objectCall3(tempvar_64, Connect, 1, tempvar_65, 0); - IHDL4SEUnit** tempvar_66 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_66"); - IHDL4SEUnit **tempvar_63 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_63"); - objectCall3(tempvar_63, Connect, 0, tempvar_64, 2); - objectCall3(tempvar_63, Connect, 1, nets[7], 0); - objectCall3(tempvar_63, Connect, 2, tempvar_66, 0); - objectCall3(nets[2], Connect, 0, tempvar_63, 3); + IHDL4SEUnit** tempvar_6 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_6"); + IHDL4SEUnit **tempvar_5 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_5"); + objectCall3(tempvar_5, Connect, 0, nets[13], 0); + objectCall3(tempvar_5, Connect, 1, tempvar_6, 0); + IHDL4SEUnit** tempvar_7 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_7"); + IHDL4SEUnit **tempvar_4 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_4"); + objectCall3(tempvar_4, Connect, 0, tempvar_5, 2); + objectCall3(tempvar_4, Connect, 1, nets[6], 0); + objectCall3(tempvar_4, Connect, 2, tempvar_7, 0); + objectCall3(nets[1], Connect, 0, tempvar_4, 3); + /* assign bram_WriteData = bCtrlState==1?64'b0:bCtrlWriteData; */ + IHDL4SEUnit** tempvar_10 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_10"); + IHDL4SEUnit **tempvar_9 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_9"); + objectCall3(tempvar_9, Connect, 0, nets[13], 0); + objectCall3(tempvar_9, Connect, 1, tempvar_10, 0); + IHDL4SEUnit** tempvar_11 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_11"); + IHDL4SEUnit **tempvar_8 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_8"); + objectCall3(tempvar_8, Connect, 0, tempvar_9, 2); + objectCall3(tempvar_8, Connect, 1, nets[7], 0); + objectCall3(tempvar_8, Connect, 2, tempvar_11, 0); + objectCall3(nets[2], Connect, 0, tempvar_8, 3); /* assign bram_ReadAddr = bCtrlState==1?bFlushReadAddr:bCtrlReadAddr; */ - IHDL4SEUnit** tempvar_69 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_69"); - IHDL4SEUnit **tempvar_68 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_68"); - objectCall3(tempvar_68, Connect, 0, nets[13], 0); - objectCall3(tempvar_68, Connect, 1, tempvar_69, 0); - IHDL4SEUnit **tempvar_67 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_67"); - objectCall3(tempvar_67, Connect, 0, tempvar_68, 2); - objectCall3(tempvar_67, Connect, 1, nets[8], 0); - objectCall3(tempvar_67, Connect, 2, nets[26], 0); - objectCall3(nets[3], Connect, 0, tempvar_67, 3); + IHDL4SEUnit** tempvar_14 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_14"); + IHDL4SEUnit **tempvar_13 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_13"); + objectCall3(tempvar_13, Connect, 0, nets[13], 0); + objectCall3(tempvar_13, Connect, 1, tempvar_14, 0); + IHDL4SEUnit **tempvar_12 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_12"); + objectCall3(tempvar_12, Connect, 0, tempvar_13, 2); + objectCall3(tempvar_12, Connect, 1, nets[8], 0); + objectCall3(tempvar_12, Connect, 2, nets[20], 0); + objectCall3(nets[3], Connect, 0, tempvar_12, 3); /* assign bCtrlReadData = bram_ReadData; */ objectCall3(nets[9], Connect, 0, nets[4], 0); /* assign bFlushReadData = bram_ReadData; */ - objectCall3(nets[27], Connect, 0, nets[4], 0); - /* assign wirein_readaddr = bCtrlState==1?wireout_readaddr+1:6'b0; */ - IHDL4SEUnit** tempvar_72 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_72"); - IHDL4SEUnit **tempvar_71 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_71"); - objectCall3(tempvar_71, Connect, 0, nets[13], 0); - objectCall3(tempvar_71, Connect, 1, tempvar_72, 0); - IHDL4SEUnit** tempvar_74 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_74"); - IHDL4SEUnit **tempvar_73 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 0", "tempvar_73"); - objectCall3(tempvar_73, Connect, 0, nets[29], 0); - objectCall3(tempvar_73, Connect, 1, tempvar_74, 0); - IHDL4SEUnit** tempvar_75 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_75"); - IHDL4SEUnit **tempvar_70 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_70"); - objectCall3(tempvar_70, Connect, 0, tempvar_71, 2); - objectCall3(tempvar_70, Connect, 1, tempvar_75, 0); - objectCall3(tempvar_70, Connect, 2, tempvar_73, 2); - objectCall3(nets[28], Connect, 0, tempvar_70, 3); - /* assign bFlushReadAddr = wireout_readaddr; */ - objectCall3(nets[26], Connect, 0, nets[29], 0); - /* assign wCtrlStateComplete = wireout_readaddr==6'd60; */ - IHDL4SEUnit** tempvar_77 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h3c", "tempvar_77"); - IHDL4SEUnit **tempvar_76 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_76"); - objectCall3(tempvar_76, Connect, 0, nets[29], 0); - objectCall3(tempvar_76, Connect, 1, tempvar_77, 0); - objectCall3(nets[11], Connect, 0, tempvar_76, 2); - /* assign bWriteAddr = 32'hf0000010+wireout_readaddr_delay_1*4; */ - IHDL4SEUnit** tempvar_79 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hf0000010", "tempvar_79"); - IHDL4SEUnit** tempvar_81 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "3, 4", "tempvar_81"); - IHDL4SEUnit **tempvar_80 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 2", "tempvar_80"); - objectCall3(tempvar_80, Connect, 0, nets[30], 0); - objectCall3(tempvar_80, Connect, 1, tempvar_81, 0); - IHDL4SEUnit **tempvar_78 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 0", "tempvar_78"); - objectCall3(tempvar_78, Connect, 0, tempvar_79, 0); - objectCall3(tempvar_78, Connect, 1, tempvar_80, 2); - objectCall3(unit, Connect, 3, tempvar_78, 2); - /* assign wWrite = bCtrlState==1?1:0; */ - IHDL4SEUnit** tempvar_84 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_84"); - IHDL4SEUnit **tempvar_83 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_83"); - objectCall3(tempvar_83, Connect, 0, nets[13], 0); - objectCall3(tempvar_83, Connect, 1, tempvar_84, 0); - IHDL4SEUnit** tempvar_85 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_85"); - IHDL4SEUnit** tempvar_86 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 0", "tempvar_86"); - IHDL4SEUnit **tempvar_82 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "1", "tempvar_82"); - objectCall3(tempvar_82, Connect, 0, tempvar_83, 2); - objectCall3(tempvar_82, Connect, 1, tempvar_86, 0); - objectCall3(tempvar_82, Connect, 2, tempvar_85, 0); - objectCall3(unit, Connect, 2, tempvar_82, 3); - /* assign bWriteData = curblockline!=16'b0?right?rightline:leftline:selecteddata; */ - IHDL4SEUnit** tempvar_89 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_89"); - IHDL4SEUnit **tempvar_88 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 5", "tempvar_88"); - objectCall3(tempvar_88, Connect, 0, nets[39], 0); - objectCall3(tempvar_88, Connect, 1, tempvar_89, 0); - IHDL4SEUnit **tempvar_90 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_90"); - objectCall3(tempvar_90, Connect, 0, nets[34], 0); - objectCall3(tempvar_90, Connect, 1, nets[43], 0); - objectCall3(tempvar_90, Connect, 2, nets[56], 0); - IHDL4SEUnit **tempvar_87 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_87"); - objectCall3(tempvar_87, Connect, 0, tempvar_88, 2); - objectCall3(tempvar_87, Connect, 1, nets[41], 0); - objectCall3(tempvar_87, Connect, 2, tempvar_90, 3); - objectCall3(unit, Connect, 4, tempvar_87, 3); + objectCall3(nets[21], Connect, 0, nets[4], 0); /* assign wRead = 32'h1; */ - IHDL4SEUnit** tempvar_91 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h1", "tempvar_91"); - objectCall3(unit, Connect, 6, tempvar_91, 0); + IHDL4SEUnit** tempvar_15 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h1", "tempvar_15"); + objectCall3(unit, Connect, 6, tempvar_15, 0); /* assign bReadAddr = 32'hf0000000; */ - IHDL4SEUnit** tempvar_92 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hf0000000", "tempvar_92"); - objectCall3(unit, Connect, 7, tempvar_92, 0); + IHDL4SEUnit** tempvar_16 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hf0000000", "tempvar_16"); + objectCall3(unit, Connect, 7, tempvar_16, 0); /* assign bCtrlKeyData = bReadData; */ objectCall3(nets[10], Connect, 0, unit, 8); - /* assign bNextBlockLo = bNextBlock [31:0] ; */ - IHDL4SEUnit** tempvar_93 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 32, 0", "tempvar_93"); - objectCall3(tempvar_93, Connect, 0, nets[17], 0); - objectCall3(nets[20], Connect, 0, tempvar_93, 1); - /* assign bNextBlockHi = bNextBlock [63:32] ; */ - IHDL4SEUnit** tempvar_94 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "64, 32, 32", "tempvar_94"); - objectCall3(tempvar_94, Connect, 0, nets[17], 0); - objectCall3(nets[21], Connect, 0, tempvar_94, 1); - /* assign bCurBlockLo = bCurBlock [31:0] ; */ - IHDL4SEUnit** tempvar_95 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 32, 0", "tempvar_95"); - objectCall3(tempvar_95, Connect, 0, nets[18], 0); - objectCall3(nets[22], Connect, 0, tempvar_95, 1); - /* assign bCurBlockHi = bCurBlock [63:32] ; */ - IHDL4SEUnit** tempvar_96 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "64, 32, 32", "tempvar_96"); - objectCall3(tempvar_96, Connect, 0, nets[18], 0); - objectCall3(nets[23], Connect, 0, tempvar_96, 1); - /* assign bCurBlockX = bCurBlockPos [4:0] ; */ - IHDL4SEUnit** tempvar_97 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "5, 5, 0", "tempvar_97"); - objectCall3(tempvar_97, Connect, 0, nets[19], 0); - objectCall3(nets[24], Connect, 0, tempvar_97, 1); - /* assign bCurBlockY = bCurBlockPos [12:8] ; */ - IHDL4SEUnit** tempvar_98 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "13, 5, 8", "tempvar_98"); - objectCall3(tempvar_98, Connect, 0, nets[19], 0); - objectCall3(nets[25], Connect, 0, tempvar_98, 1); - /* assign bWriteDataSel = wireout_readaddr_delay_1<6'd52?3'd7:wireout_readaddr_delay_1-6'd52; */ - IHDL4SEUnit** tempvar_101 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h34", "tempvar_101"); - IHDL4SEUnit **tempvar_100 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 6", "tempvar_100"); - objectCall3(tempvar_100, Connect, 0, nets[30], 0); - objectCall3(tempvar_100, Connect, 1, tempvar_101, 0); - IHDL4SEUnit** tempvar_102 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h7", "tempvar_102"); - IHDL4SEUnit** tempvar_104 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h34", "tempvar_104"); - IHDL4SEUnit **tempvar_103 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 1", "tempvar_103"); - objectCall3(tempvar_103, Connect, 0, nets[30], 0); - objectCall3(tempvar_103, Connect, 1, tempvar_104, 0); - IHDL4SEUnit **tempvar_99 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_99"); - objectCall3(tempvar_99, Connect, 0, tempvar_100, 2); - objectCall3(tempvar_99, Connect, 1, tempvar_103, 2); - objectCall3(tempvar_99, Connect, 2, tempvar_102, 0); - objectCall3(nets[32], Connect, 0, tempvar_99, 3); - /* assign line = wireout_readaddr_delay_1 [5:1] ; */ - IHDL4SEUnit** tempvar_105 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "6, 5, 1", "tempvar_105"); - objectCall3(tempvar_105, Connect, 0, nets[30], 0); - objectCall3(nets[33], Connect, 0, tempvar_105, 1); - /* assign right = wireout_readaddr_delay_1 [0:0] ; */ - IHDL4SEUnit** tempvar_106 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "1, 1, 0", "tempvar_106"); - objectCall3(tempvar_106, Connect, 0, nets[30], 0); - objectCall3(nets[34], Connect, 0, tempvar_106, 1); - /* assign line3 = line+2==bCurBlockY?16'hffff:16'b0; */ - IHDL4SEUnit** tempvar_110 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 2", "tempvar_110"); - IHDL4SEUnit **tempvar_109 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 0", "tempvar_109"); - objectCall3(tempvar_109, Connect, 0, nets[33], 0); - objectCall3(tempvar_109, Connect, 1, tempvar_110, 0); - IHDL4SEUnit **tempvar_108 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_108"); - objectCall3(tempvar_108, Connect, 0, tempvar_109, 2); - objectCall3(tempvar_108, Connect, 1, nets[25], 0); - IHDL4SEUnit** tempvar_111 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hffff", "tempvar_111"); - IHDL4SEUnit** tempvar_112 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_112"); - IHDL4SEUnit **tempvar_107 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_107"); - objectCall3(tempvar_107, Connect, 0, tempvar_108, 2); - objectCall3(tempvar_107, Connect, 1, tempvar_112, 0); - objectCall3(tempvar_107, Connect, 2, tempvar_111, 0); - objectCall3(nets[35], Connect, 0, tempvar_107, 3); - /* assign line2 = line+1==bCurBlockY?16'hffff:16'b0; */ - IHDL4SEUnit** tempvar_116 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_116"); - IHDL4SEUnit **tempvar_115 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 0", "tempvar_115"); - objectCall3(tempvar_115, Connect, 0, nets[33], 0); - objectCall3(tempvar_115, Connect, 1, tempvar_116, 0); - IHDL4SEUnit **tempvar_114 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_114"); - objectCall3(tempvar_114, Connect, 0, tempvar_115, 2); - objectCall3(tempvar_114, Connect, 1, nets[25], 0); - IHDL4SEUnit** tempvar_117 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hffff", "tempvar_117"); - IHDL4SEUnit** tempvar_118 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_118"); - IHDL4SEUnit **tempvar_113 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_113"); - objectCall3(tempvar_113, Connect, 0, tempvar_114, 2); - objectCall3(tempvar_113, Connect, 1, tempvar_118, 0); - objectCall3(tempvar_113, Connect, 2, tempvar_117, 0); - objectCall3(nets[36], Connect, 0, tempvar_113, 3); - /* assign line1 = line==bCurBlockY?16'hffff:16'b0; */ - IHDL4SEUnit **tempvar_120 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_120"); - objectCall3(tempvar_120, Connect, 0, nets[33], 0); - objectCall3(tempvar_120, Connect, 1, nets[25], 0); - IHDL4SEUnit** tempvar_121 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hffff", "tempvar_121"); - IHDL4SEUnit** tempvar_122 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_122"); - IHDL4SEUnit **tempvar_119 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_119"); - objectCall3(tempvar_119, Connect, 0, tempvar_120, 2); - objectCall3(tempvar_119, Connect, 1, tempvar_122, 0); - objectCall3(tempvar_119, Connect, 2, tempvar_121, 0); - objectCall3(nets[37], Connect, 0, tempvar_119, 3); - /* assign line0 = line==bCurBlockY+1?16'hffff:16'b0; */ - IHDL4SEUnit** tempvar_126 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "1, 1", "tempvar_126"); - IHDL4SEUnit **tempvar_125 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 0", "tempvar_125"); - objectCall3(tempvar_125, Connect, 0, nets[25], 0); - objectCall3(tempvar_125, Connect, 1, tempvar_126, 0); - IHDL4SEUnit **tempvar_124 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 1, 4", "tempvar_124"); - objectCall3(tempvar_124, Connect, 0, nets[33], 0); - objectCall3(tempvar_124, Connect, 1, tempvar_125, 2); - IHDL4SEUnit** tempvar_127 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'hffff", "tempvar_127"); - IHDL4SEUnit** tempvar_128 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h0", "tempvar_128"); - IHDL4SEUnit **tempvar_123 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_123"); - objectCall3(tempvar_123, Connect, 0, tempvar_124, 2); - objectCall3(tempvar_123, Connect, 1, tempvar_128, 0); - objectCall3(tempvar_123, Connect, 2, tempvar_127, 0); - objectCall3(nets[38], Connect, 0, tempvar_123, 3); - /* assign curblockline = line0&bCurBlock [15:0] |line1&bCurBlock [31:16] |line2&bCurBlock [47:32] |line3&bCurBlock [63:48] ; */ - IHDL4SEUnit** tempvar_131 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "16, 16, 0", "tempvar_131"); - objectCall3(tempvar_131, Connect, 0, nets[18], 0); - IHDL4SEUnit **tempvar_130 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 10", "tempvar_130"); - objectCall3(tempvar_130, Connect, 0, nets[38], 0); - objectCall3(tempvar_130, Connect, 1, tempvar_131, 1); - IHDL4SEUnit** tempvar_134 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "32, 16, 16", "tempvar_134"); - objectCall3(tempvar_134, Connect, 0, nets[18], 0); - IHDL4SEUnit **tempvar_133 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 10", "tempvar_133"); - objectCall3(tempvar_133, Connect, 0, nets[37], 0); - objectCall3(tempvar_133, Connect, 1, tempvar_134, 1); - IHDL4SEUnit** tempvar_137 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "48, 16, 32", "tempvar_137"); - objectCall3(tempvar_137, Connect, 0, nets[18], 0); - IHDL4SEUnit **tempvar_136 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 10", "tempvar_136"); - objectCall3(tempvar_136, Connect, 0, nets[36], 0); - objectCall3(tempvar_136, Connect, 1, tempvar_137, 1); - IHDL4SEUnit** tempvar_139 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "64, 16, 48", "tempvar_139"); - objectCall3(tempvar_139, Connect, 0, nets[18], 0); - IHDL4SEUnit **tempvar_138 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 10", "tempvar_138"); - objectCall3(tempvar_138, Connect, 0, nets[35], 0); - objectCall3(tempvar_138, Connect, 1, tempvar_139, 1); - IHDL4SEUnit **tempvar_135 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 11", "tempvar_135"); - objectCall3(tempvar_135, Connect, 0, tempvar_136, 2); - objectCall3(tempvar_135, Connect, 1, tempvar_138, 2); - IHDL4SEUnit **tempvar_132 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 11", "tempvar_132"); - objectCall3(tempvar_132, Connect, 0, tempvar_133, 2); - objectCall3(tempvar_132, Connect, 1, tempvar_135, 2); - IHDL4SEUnit **tempvar_129 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 11", "tempvar_129"); - objectCall3(tempvar_129, Connect, 0, tempvar_130, 2); - objectCall3(tempvar_129, Connect, 1, tempvar_132, 2); - objectCall3(nets[39], Connect, 0, tempvar_129, 2); - /* assign leftline = bCurBlockX [5:4] ?selecteddata:leftline_0_15; */ - IHDL4SEUnit** tempvar_141 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "6, 2, 4", "tempvar_141"); - objectCall3(tempvar_141, Connect, 0, nets[24], 0); - IHDL4SEUnit **tempvar_140 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_140"); - objectCall3(tempvar_140, Connect, 0, tempvar_141, 1); - objectCall3(tempvar_140, Connect, 1, nets[42], 0); - objectCall3(tempvar_140, Connect, 2, nets[41], 0); - objectCall3(nets[43], Connect, 0, tempvar_140, 3); - /* assign rightline = bCurBlockX [5:0] >=3?rightline_3_18:selecteddata; */ - IHDL4SEUnit** tempvar_144 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "6, 6, 0", "tempvar_144"); - objectCall3(tempvar_144, Connect, 0, nets[24], 0); - IHDL4SEUnit** tempvar_145 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "2, 3", "tempvar_145"); - IHDL4SEUnit **tempvar_143 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "6, 6, 1, 8", "tempvar_143"); - objectCall3(tempvar_143, Connect, 0, tempvar_144, 1); - objectCall3(tempvar_143, Connect, 1, tempvar_145, 0); - IHDL4SEUnit **tempvar_142 = hdl4seCreateUnit(module, CLSID_HDL4SE_MUX2, "32", "tempvar_142"); - objectCall3(tempvar_142, Connect, 0, tempvar_143, 2); - objectCall3(tempvar_142, Connect, 1, nets[41], 0); - objectCall3(tempvar_142, Connect, 2, nets[55], 0); - objectCall3(nets[56], Connect, 0, tempvar_142, 3); - /* assign blockx_3 = bCurBlockX [5:0] -6'd3; */ - IHDL4SEUnit** tempvar_147 = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, "6, 6, 0", "tempvar_147"); - objectCall3(tempvar_147, Connect, 0, nets[24], 0); - IHDL4SEUnit** tempvar_148 = hdl4seCreateUnit(module, CLSID_HDL4SE_CONST, "32, 32'h3", "tempvar_148"); - IHDL4SEUnit **tempvar_146 = hdl4seCreateUnit(module, CLSID_HDL4SE_BINOP, "32, 32, 32, 1", "tempvar_146"); - objectCall3(tempvar_146, Connect, 0, tempvar_147, 1); - objectCall3(tempvar_146, Connect, 1, tempvar_148, 0); - objectCall3(nets[68], Connect, 0, tempvar_146, 2); /*释放module接口*/ objectRelease(module); @@ -718,5 +762,5 @@ IHDL4SEUnit** hdl4seCreate_0011(IHDL4SEModule** parent, const char* instancepara IHDL4SEUnit** hdl4seCreate_main(IHDL4SEModule** parent, const char* instanceparam, const char* name) { - return hdl4seCreate_0011(parent, instanceparam, name); + return hdl4seCreate_0012(parent, instanceparam, name); } diff --git a/examples/terris/verilog/main_1.v b/examples/terris/verilog/main_1.v index f4b7627..26fe0b5 100644 --- a/examples/terris/verilog/main_1.v +++ b/examples/terris/verilog/main_1.v @@ -45,9 +45,9 @@ module teris_ctrl input nwReset, output wWrite, output [5:0] bWriteAddr, - output [31:0] bWriteData, + output [63:0] bWriteData, output [5:0] bReadAddr, - input [31:0] bReadData, + input [63:0] bReadData, input [31:0] bKeyData, input wStateComplete, output wStateChange, @@ -64,58 +64,22 @@ endmodule `define ST_INIT 0 `define ST_FLUSHTODISP 1 -module main( - input wClk, nwReset, - output wWrite, - output [31:0] bWriteAddr, - output [31:0] bWriteData, - output [3:0] bWriteMask, - output wRead, - output [31:0] bReadAddr, - input [31:0] bReadData); - - /* - wire wClk, nwReset; - wire wWrite; - wire [31:0] bWriteAddr, bWriteData; - wire [3:0] bWriteMask; - wire wRead; - wire [31:0] bReadAddr; - wire [31:0] bReadData; - */ - - wire wram_Write; - wire [5:0] bram_WriteAddr; - wire [31:0] bram_WriteData; - wire [5:0] bram_ReadAddr; - wire [31:0] bram_ReadData; - -/* 帧存存储器 */ - hdl4se_ram1p #(32, 6) ram_0( - wClk, - wram_Write, - bram_WriteAddr, - bram_WriteData, - bram_ReadAddr, - bram_ReadData - ); - -/* 游戏控制器 */ - wire wCtrlWrite; - wire [5:0] bCtrlWriteAddr; - wire [31:0] bCtrlWriteData; - wire [5:0] bCtrlReadAddr; - wire [31:0] bCtrlReadData; - wire [31:0] bCtrlKeyData; - wire wCtrlStateComplete; - wire wCtrlStateChange; - wire [3:0] bCtrlState; - wire [31:0] bCtrlSpeed; - wire [31:0] bCtrlLevel; - wire [31:0] bCtrlScore; - wire [63:0] bNextBlock; - wire [63:0] bCurBlock; - wire [15:0] bCurBlockPos; +module flushtodisp( + input wClk, + input [3:0] bCtrlState, + output wCtrlStateComplete, + output [5:0] bFlushReadAddr, + input [63:0] bFlushReadData, + output wWrite, + output [31:0] bWriteAddr, + output [31:0] bWriteData, + input [31:0] bCtrlSpeed, + input [31:0] bCtrlLevel, + input [31:0] bCtrlScore, + input [63:0] bNextBlock, + input [63:0] bCurBlock, + input [15:0] bCurBlockPos +); wire [31:0] bNextBlockLo = bNextBlock[31:0]; wire [31:0] bNextBlockHi = bNextBlock[63:32]; @@ -124,29 +88,13 @@ module main( wire [4:0] bCurBlockX = bCurBlockPos[4:0]; wire [4:0] bCurBlockY = bCurBlockPos[12:8]; - teris_ctrl ctrl(wClk, nwReset, wCtrlWrite, bCtrlWriteAddr, bCtrlWriteData, - bCtrlReadAddr,bCtrlReadData, bCtrlKeyData, - wCtrlStateComplete, wCtrlStateChange, bCtrlState, - bCtrlScore, bCtrlSpeed, bCtrlLevel, - bNextBlock, bCurBlock, bCurBlockPos); - - assign wram_Write = (bCtrlState == `ST_FLUSHTODISP) ? 1'b0 : wCtrlWrite; /*刷新模块不写ram*/ - assign bram_WriteAddr = (bCtrlState == `ST_FLUSHTODISP) ? 6'b0 : bCtrlWriteAddr; - assign bram_WriteData = (bCtrlState == `ST_FLUSHTODISP) ? 32'b0 : bCtrlWriteData; - assign bram_ReadAddr = (bCtrlState == `ST_FLUSHTODISP) ? bFlushReadAddr : bCtrlReadAddr; - assign bCtrlReadData = bram_ReadData; - assign bFlushReadData = bram_ReadData; - - wire [5:0] bFlushReadAddr; - wire [31:0] bFlushReadData; - /* 目前编译器还不支持reg和always块，因此直接用基本单元来做寄存器 */ - wire [6:0] wirein_readaddr, wireout_readaddr, wireout_readaddr_delay_1; + wire [7:0] wirein_readaddr, wireout_readaddr, wireout_readaddr_delay_1; wire[31:0] wireout_readaddr2; hdl4se_reg #(6) ramreadaddr(wClk, wirein_readaddr, wireout_readaddr); hdl4se_reg #(6) ramreadaddr_delay_1(wClk, wireout_readaddr, wireout_readaddr_delay_1); assign wirein_readaddr = (bCtrlState == `ST_FLUSHTODISP) ? wireout_readaddr + 1 : 6'b0; - assign bFlushReadAddr = wireout_readaddr; + assign bFlushReadAddr = wireout_readaddr[6:1]; assign wCtrlStateComplete = wireout_readaddr == 6'd60; assign bWriteAddr = 32'hf000_0010 + wireout_readaddr_delay_1 * 4; assign wWrite = (bCtrlState == `ST_FLUSHTODISP) ? 1 : 0; @@ -159,7 +107,7 @@ module main( 58 : speed --> 6 */ wire [4:0] line = wireout_readaddr_delay_1[5:1]; - wire right = wireout_readaddr_delay_1[0:0]; + wire right = wireout_readaddr_delay_1[0]; wire [15:0] line3 = ((line + 2) == bCurBlockY) ? 16'hffff:16'b0; wire [15:0] line2 = ((line + 1) == bCurBlockY) ? 16'hffff:16'b0; wire [15:0] line1 = (line == bCurBlockY) ? 16'hffff:16'b0; @@ -171,8 +119,20 @@ module main( hdl4se_bind2 #(16, 16) curlinebind(curblockline, selecteddata[31:16], curline); wire [31:0] leftline_0_15; - wire [31:0] leftline = bCurBlockX[5:4]?selecteddata:leftline_0_15; + wire [31:0] leftline = bCurBlockX[5:4]?selecteddata:(leftline_0_15 | selecteddata); wire [31:0] leftline_1, leftline0, leftline1, leftline2, leftline3, leftline4, leftline5, leftline6, leftline7, leftline8, leftline9; + hdl4se_bind2 #(4, 28) leftline0_gen(curblockline[15:12], 28'b0, leftline_1); + hdl4se_bind2 #(8, 24) leftline0_gen(curblockline[15:8], 24'b0, leftline0); + hdl4se_bind2 #(12, 20) leftline1_gen(curblockline[15:4], 20'b0, leftline1); + hdl4se_bind2 #(16, 16) leftline2_gen(curblockline[15:0], 16'b0, leftline2); + hdl4se_bind3 #(4, 16, 12) leftline3_gen(4'b0, curblockline[15:0], 12'b0, leftline3); + hdl4se_bind3 #(8, 16, 8) leftline4_gen(8'b0, curblockline[15:0], 8'b0, leftline4); + hdl4se_bind3 #(12,16, 4) leftline5_gen(12'b0, curblockline[15:0], 4'b0, leftline5); + hdl4se_bind2 #(16, 16) leftline6_gen(16'b0, curblockline[15:0], leftline6); + hdl4se_bind2 #(20, 12) leftline7_gen(20'b0, curblockline[11:0], leftline7); + hdl4se_bind2 #(24, 8) leftline8_gen(24'b0, curblockline[7:0], leftline8); + hdl4se_bind2 #(28, 4) leftline9_gen(28'b0, curblockline[3:0], leftline9); + /* hdl4se_bind2 #(4, 28) leftline0_gen(curblockline[15:12], selecteddata[27:0], leftline_1); hdl4se_bind2 #(8, 24) leftline0_gen(curblockline[15:8], selecteddata[23:0], leftline0); hdl4se_bind2 #(12, 20) leftline1_gen(curblockline[15:4], selecteddata[19:0], leftline1); @@ -184,7 +144,7 @@ module main( hdl4se_bind2 #(20, 12) leftline7_gen(selecteddata[31:12], curblockline[11:0], leftline7); hdl4se_bind2 #(24, 8) leftline8_gen(selecteddata[31:8], curblockline[7:0], leftline8); hdl4se_bind2 #(28, 4) leftline9_gen(selecteddata[31:4], curblockline[3:0], leftline9); - + */ hdl4se_mux16 #(32) selectleftline( bCurBlockX[3:0], leftline_1, @@ -207,19 +167,32 @@ module main( ); wire [31:0] rightline_3_18; - wire [31:0] rightline = (bCurBlockX[5:0]>=3)?rightline_3_18:selecteddata; + wire [31:0] rightline = (bCurBlockX[5:0]>=3)?(rightline_3_18|selecteddata):selecteddata; wire [31:0] rightline0, rightline1, rightline2, rightline3, rightline4, rightline5, rightline6, rightline7, rightline8, rightline9, rightline10; - hdl4se_bind2 #(4, 28) rightline0_gen(curblockline[15:12], selecteddata[27:0], rightline0); - hdl4se_bind2 #(8, 24) rightline1_gen(curblockline[15:8], selecteddata[23:0], rightline1); - hdl4se_bind2 #(12, 20) rightline2_gen(curblockline[15:4], selecteddata[19:0], rightline2); - hdl4se_bind2 #(16, 16) rightline3_gen(curblockline[15:0], selecteddata[15:0], rightline3); - hdl4se_bind3 #(4, 16, 12) rightline4_gen(selecteddata[31:28], curblockline[15:0], selecteddata[11:0], rightline4); - hdl4se_bind3 #(8, 16, 8) rightline5_gen(selecteddata[31:24], curblockline[15:0], selecteddata[7:0], rightline5); - hdl4se_bind3 #(12, 16, 4) rightline6_gen(selecteddata[31:20], curblockline[15:0], selecteddata[3:0], rightline6); - hdl4se_bind2 #(16, 16) rightline7_gen(selecteddata[31:16], curblockline[15:0], rightline7); - hdl4se_bind2 #(20, 12) rightline8_gen(selecteddata[31:12], curblockline[11:0], rightline8); - hdl4se_bind2 #(24, 8) rightline9_gen(selecteddata[31:8], curblockline[7:0], rightline9); - hdl4se_bind2 #(28, 4) rightline10_gen(selecteddata[31:4], curblockline[3:0], rightline10); + /* + hdl4se_bind2 #(4, 28) rightline0_gen(curblockline[15:12], 28'b0 | selecteddata[31:28], selecteddata[27:0], rightline0); + hdl4se_bind2 #(8, 24) rightline1_gen(curblockline[15:8] | selecteddata[31:24], selecteddata[23:0], rightline1); + hdl4se_bind2 #(12, 20) rightline2_gen(curblockline[15:4] | selecteddata[31:20], selecteddata[19:0], rightline2); + hdl4se_bind2 #(16, 16) rightline3_gen(curblockline[15:0] | selecteddata[31:16], selecteddata[15:0], rightline3); + hdl4se_bind3 #(4, 16, 12) rightline4_gen(selecteddata[31:28], curblockline[15:0] | selecteddata[27:12], selecteddata[11:0], rightline4); + hdl4se_bind3 #(8, 16, 8) rightline5_gen(selecteddata[31:24], curblockline[15:0] | selecteddata[23:8], selecteddata[7:0], rightline5); + hdl4se_bind3 #(12, 16, 4) rightline6_gen(selecteddata[31:20], curblockline[15:0] | selecteddata[19:4], selecteddata[3:0], rightline6); + hdl4se_bind2 #(16, 16) rightline7_gen(selecteddata[31:16], curblockline[15:0] | selecteddata[15:0], rightline7); + hdl4se_bind2 #(20, 12) rightline8_gen(selecteddata[31:12], curblockline[11:0] | selecteddata[11:0], rightline8); + hdl4se_bind2 #(24, 8) rightline9_gen(selecteddata[31:8], curblockline[7:0] | selecteddata[7:0], rightline9); + hdl4se_bind2 #(28, 4) rightline10_gen(selecteddata[31:4], curblockline[3:0] | selecteddata[3:0], rightline10); + */ + hdl4se_bind2 #(4, 28) rightline0_gen(curblockline[15:12], 28'b0, rightline0); + hdl4se_bind2 #(8, 24) rightline1_gen(curblockline[15:8], 24'b0, rightline1); + hdl4se_bind2 #(12, 20) rightline2_gen(curblockline[15:4], 20'b0, rightline2); + hdl4se_bind2 #(16, 16) rightline3_gen(curblockline[15:0], 16'b0,rightline3); + hdl4se_bind3 #(4, 16, 12) rightline4_gen(4'b0, curblockline[15:0], 12'b0, rightline4); + hdl4se_bind3 #(8, 16, 8) rightline5_gen(8'b0, curblockline[15:0], 8'b0, rightline5); + hdl4se_bind3 #(12, 16, 4) rightline6_gen(12'b0, curblockline[15:0], 4'b0, rightline6); + hdl4se_bind2 #(16, 16) rightline7_gen(16'b0, curblockline[15:0], rightline7); + hdl4se_bind2 #(20, 12) rightline8_gen(20'b0, curblockline[11:0], rightline8); + hdl4se_bind2 #(24, 8) rightline9_gen(24'b0, curblockline[7:0], rightline9); + hdl4se_bind2 #(28, 4) rightline10_gen(28'b0, curblockline[3:0], rightline10); wire [5:0] blockx_3 = bCurBlockX[5:0] - 6'd3; hdl4se_mux16 #(32) selectrightline( blockx_3[3:0], @@ -252,9 +225,78 @@ module main( bCtrlScore, bCtrlLevel, bCtrlSpeed, - bram_ReadData, + right?bFlushReadData[63:32]:bFlushReadData[31:0], selecteddata ); +endmodule + +module main( + input wClk, nwReset, + output wWrite, + output [31:0] bWriteAddr, + output [31:0] bWriteData, + output [3:0] bWriteMask, + output wRead, + output [31:0] bReadAddr, + input [31:0] bReadData); + + wire wram_Write; + wire [5:0] bram_WriteAddr; + wire [63:0] bram_WriteData; + wire [5:0] bram_ReadAddr; + wire [63:0] bram_ReadData; + +/* 帧存存储器 */ + hdl4se_ram1p #(64, 6) ram_0( + wClk, + wram_Write, + bram_WriteAddr, + bram_WriteData, + bram_ReadAddr, + bram_ReadData + ); + +/* 游戏控制器 */ + wire wCtrlWrite; + wire [5:0] bCtrlWriteAddr; + wire [63:0] bCtrlWriteData; + wire [5:0] bCtrlReadAddr; + wire [63:0] bCtrlReadData; + wire [31:0] bCtrlKeyData; + wire wCtrlStateComplete; + wire wCtrlStateChange; + wire [3:0] bCtrlState; + wire [31:0] bCtrlSpeed; + wire [31:0] bCtrlLevel; + wire [31:0] bCtrlScore; + wire [63:0] bNextBlock; + wire [63:0] bCurBlock; + wire [15:0] bCurBlockPos; + + teris_ctrl ctrl(wClk, nwReset, wCtrlWrite, bCtrlWriteAddr, bCtrlWriteData, + bCtrlReadAddr,bCtrlReadData, bCtrlKeyData, + wCtrlStateComplete, wCtrlStateChange, bCtrlState, + bCtrlScore, bCtrlSpeed, bCtrlLevel, + bNextBlock, bCurBlock, bCurBlockPos); + + wire [5:0] bFlushReadAddr; + wire [63:0] bFlushReadData; + + /* 屏幕刷新 */ + flushtodisp flusher(wClk, + bCtrlState, wCtrlStateComplete, + bFlushReadAddr, bFlushReadData, + wWrite, bWriteAddr, bWriteData, + bCtrlSpeed, bCtrlLevel, bCtrlScore, + bNextBlock, bCurBlock, bCurBlockPos); + + /* ram读写口仲裁 */ + assign wram_Write = (bCtrlState == `ST_FLUSHTODISP) ? 1'b0 : wCtrlWrite; /*刷新模块不写ram*/ + assign bram_WriteAddr = (bCtrlState == `ST_FLUSHTODISP) ? 6'b0 : bCtrlWriteAddr; + assign bram_WriteData = (bCtrlState == `ST_FLUSHTODISP) ? 64'b0 : bCtrlWriteData; + assign bram_ReadAddr = (bCtrlState == `ST_FLUSHTODISP) ? bFlushReadAddr : bCtrlReadAddr; + assign bCtrlReadData = bram_ReadData; + assign bFlushReadData = bram_ReadData; /*我们一直在读按键的状态*/ assign wRead = 1'b1; diff --git a/examples/terris/verilog/main_asm.v b/examples/terris/verilog/main_asm.v index f44a50e..17391c4 100644 --- a/examples/terris/verilog/main_asm.v +++ b/examples/terris/verilog/main_asm.v @@ -434,9 +434,9 @@ module teris_ctrl input nwReset, output wWrite, output [5:0] bWriteAddr, - output [31:0] bWriteData, + output [63:0] bWriteData, output [5:0] bReadAddr, - input [31:0] bReadData, + input [63:0] bReadData, input [31:0] bKeyData, input wStateComplete, output wStateChange, @@ -452,50 +452,33 @@ module teris_ctrl endmodule -module main +module flushtodisp ( input wClk, - input nwReset, + input [3:0] bCtrlState, + output wCtrlStateComplete, + output [5:0] bFlushReadAddr, + input [63:0] bFlushReadData, output wWrite, output [31:0] bWriteAddr, output [31:0] bWriteData, - output [3:0] bWriteMask, - output wRead, - output [31:0] bReadAddr, - input [31:0] bReadData + input [31:0] bCtrlSpeed, + input [31:0] bCtrlLevel, + input [31:0] bCtrlScore, + input [63:0] bNextBlock, + input [63:0] bCurBlock, + input [15:0] bCurBlockPos ) ; - wire wram_Write; - wire [5:0] bram_WriteAddr; - wire [31:0] bram_WriteData; - wire [5:0] bram_ReadAddr; - wire [31:0] bram_ReadData; - wire wCtrlWrite; - wire [5:0] bCtrlWriteAddr; - wire [31:0] bCtrlWriteData; - wire [5:0] bCtrlReadAddr; - wire [31:0] bCtrlReadData; - wire [31:0] bCtrlKeyData; - wire wCtrlStateComplete; - wire wCtrlStateChange; - wire [3:0] bCtrlState; - wire [31:0] bCtrlSpeed; - wire [31:0] bCtrlLevel; - wire [31:0] bCtrlScore; - wire [63:0] bNextBlock; - wire [63:0] bCurBlock; - wire [15:0] bCurBlockPos; wire [31:0] bNextBlockLo; wire [31:0] bNextBlockHi; wire [31:0] bCurBlockLo; wire [31:0] bCurBlockHi; wire [4:0] bCurBlockX; wire [4:0] bCurBlockY; - wire [5:0] bFlushReadAddr; - wire [31:0] bFlushReadData; - wire [6:0] wirein_readaddr; - wire [6:0] wireout_readaddr; - wire [6:0] wireout_readaddr_delay_1; + wire [7:0] wirein_readaddr; + wire [7:0] wireout_readaddr; + wire [7:0] wireout_readaddr_delay_1; wire [31:0] wireout_readaddr2; wire [2:0] bWriteDataSel; wire [4:0] line; @@ -534,21 +517,12 @@ module main wire [31:0] rightline9; wire [31:0] rightline10; wire [5:0] blockx_3; - assign wram_Write = bCtrlState==1?1'b0:wCtrlWrite; - assign bram_WriteAddr = bCtrlState==1?6'b0:bCtrlWriteAddr; - assign bram_WriteData = bCtrlState==1?32'b0:bCtrlWriteData; - assign bram_ReadAddr = bCtrlState==1?bFlushReadAddr:bCtrlReadAddr; - assign bCtrlReadData = bram_ReadData; - assign bFlushReadData = bram_ReadData; assign wirein_readaddr = bCtrlState==1?wireout_readaddr+1:6'b0; - assign bFlushReadAddr = wireout_readaddr; + assign bFlushReadAddr = wireout_readaddr [6:1] ; assign wCtrlStateComplete = wireout_readaddr==6'd60; assign bWriteAddr = 32'hf0000010+wireout_readaddr_delay_1*4; assign wWrite = bCtrlState==1?1:0; assign bWriteData = curblockline!=16'b0?right?rightline:leftline:selecteddata; - assign wRead = 32'h1; - assign bReadAddr = 32'hf0000000; - assign bCtrlKeyData = bReadData; assign bNextBlockLo = bNextBlock [31:0] ; assign bNextBlockHi = bNextBlock [63:32] ; assign bCurBlockLo = bCurBlock [31:0] ; @@ -557,54 +531,104 @@ module main assign bCurBlockY = bCurBlockPos [12:8] ; assign bWriteDataSel = wireout_readaddr_delay_1<6'd52?3'd7:wireout_readaddr_delay_1-6'd52; assign line = wireout_readaddr_delay_1 [5:1] ; - assign right = wireout_readaddr_delay_1 [0:0] ; + assign right = wireout_readaddr_delay_1 [0] ; assign line3 = line+2==bCurBlockY?16'hffff:16'b0; assign line2 = line+1==bCurBlockY?16'hffff:16'b0; assign line1 = line==bCurBlockY?16'hffff:16'b0; assign line0 = line==bCurBlockY+1?16'hffff:16'b0; assign curblockline = line0&bCurBlock [15:0] |line1&bCurBlock [31:16] |line2&bCurBlock [47:32] |line3&bCurBlock [63:48] ; - assign leftline = bCurBlockX [5:4] ?selecteddata:leftline_0_15; - assign rightline = bCurBlockX [5:0] >=3?rightline_3_18:selecteddata; + assign leftline = bCurBlockX [5:4] ?selecteddata:leftline_0_15|selecteddata; + assign rightline = bCurBlockX [5:0] >=3?rightline_3_18|selecteddata:selecteddata; assign blockx_3 = bCurBlockX [5:0] -6'd3; - hdl4se_ram1p #( 32, 6 ) ram_0( wClk, wram_Write, bram_WriteAddr, bram_WriteData, bram_ReadAddr, bram_ReadData - ); - teris_ctrl ctrl( wClk, nwReset, wCtrlWrite, bCtrlWriteAddr, bCtrlWriteData, bCtrlReadAddr - , bCtrlReadData, bCtrlKeyData, wCtrlStateComplete, wCtrlStateChange, bCtrlState - , bCtrlScore, bCtrlSpeed, bCtrlLevel, bNextBlock, bCurBlock - , bCurBlockPos ); hdl4se_reg #( 6 ) ramreadaddr( wClk, wirein_readaddr, wireout_readaddr ); hdl4se_reg #( 6 ) ramreadaddr_delay_1( wClk, wireout_readaddr, wireout_readaddr_delay_1 ); hdl4se_bind2 #( 16, 16 ) curlinebind( curblockline, selecteddata [31:16] , curline ); - hdl4se_bind2 #( 4, 28 ) leftline0_gen( curblockline [15:12] , selecteddata [27:0] , leftline_1 ); - hdl4se_bind2 #( 8, 24 ) leftline0_gen( curblockline [15:8] , selecteddata [23:0] , leftline0 ); - hdl4se_bind2 #( 12, 20 ) leftline1_gen( curblockline [15:4] , selecteddata [19:0] , leftline1 ); - hdl4se_bind2 #( 16, 16 ) leftline2_gen( curblockline [15:0] , selecteddata [15:0] , leftline2 ); - hdl4se_bind3 #( 4, 16, 12 ) leftline3_gen( selecteddata [31:28] , curblockline [15:0] , selecteddata [11:0] , leftline3 ); - hdl4se_bind3 #( 8, 16, 8 ) leftline4_gen( selecteddata [31:24] , curblockline [15:0] , selecteddata [7:0] , leftline4 ); - hdl4se_bind3 #( 12, 16, 4 ) leftline5_gen( selecteddata [31:20] , curblockline [15:0] , selecteddata [3:0] , leftline5 ); - hdl4se_bind2 #( 16, 16 ) leftline6_gen( selecteddata [31:16] , curblockline [15:0] , leftline6 ); - hdl4se_bind2 #( 20, 12 ) leftline7_gen( selecteddata [31:12] , curblockline [11:0] , leftline7 ); - hdl4se_bind2 #( 24, 8 ) leftline8_gen( selecteddata [31:8] , curblockline [7:0] , leftline8 ); - hdl4se_bind2 #( 28, 4 ) leftline9_gen( selecteddata [31:4] , curblockline [3:0] , leftline9 ); + hdl4se_bind2 #( 4, 28 ) leftline0_gen( curblockline [15:12] , 32'h0, leftline_1 ); + hdl4se_bind2 #( 8, 24 ) leftline0_gen( curblockline [15:8] , 32'h0, leftline0 ); + hdl4se_bind2 #( 12, 20 ) leftline1_gen( curblockline [15:4] , 32'h0, leftline1 ); + hdl4se_bind2 #( 16, 16 ) leftline2_gen( curblockline [15:0] , 32'h0, leftline2 ); + hdl4se_bind3 #( 4, 16, 12 ) leftline3_gen( 32'h0, curblockline [15:0] , 32'h0, leftline3 ); + hdl4se_bind3 #( 8, 16, 8 ) leftline4_gen( 32'h0, curblockline [15:0] , 32'h0, leftline4 ); + hdl4se_bind3 #( 12, 16, 4 ) leftline5_gen( 32'h0, curblockline [15:0] , 32'h0, leftline5 ); + hdl4se_bind2 #( 16, 16 ) leftline6_gen( 32'h0, curblockline [15:0] , leftline6 ); + hdl4se_bind2 #( 20, 12 ) leftline7_gen( 32'h0, curblockline [11:0] , leftline7 ); + hdl4se_bind2 #( 24, 8 ) leftline8_gen( 32'h0, curblockline [7:0] , leftline8 ); + hdl4se_bind2 #( 28, 4 ) leftline9_gen( 32'h0, curblockline [3:0] , leftline9 ); hdl4se_mux16 #( 32 ) selectleftline( bCurBlockX [3:0] , leftline_1, leftline0, leftline1, leftline2, leftline3 , leftline4, leftline5, leftline6, leftline7, leftline8 , leftline9, selecteddata, selecteddata, selecteddata, selecteddata , selecteddata, leftline_0_15 ); - hdl4se_bind2 #( 4, 28 ) rightline0_gen( curblockline [15:12] , selecteddata [27:0] , rightline0 ); - hdl4se_bind2 #( 8, 24 ) rightline1_gen( curblockline [15:8] , selecteddata [23:0] , rightline1 ); - hdl4se_bind2 #( 12, 20 ) rightline2_gen( curblockline [15:4] , selecteddata [19:0] , rightline2 ); - hdl4se_bind2 #( 16, 16 ) rightline3_gen( curblockline [15:0] , selecteddata [15:0] , rightline3 ); - hdl4se_bind3 #( 4, 16, 12 ) rightline4_gen( selecteddata [31:28] , curblockline [15:0] , selecteddata [11:0] , rightline4 ); - hdl4se_bind3 #( 8, 16, 8 ) rightline5_gen( selecteddata [31:24] , curblockline [15:0] , selecteddata [7:0] , rightline5 ); - hdl4se_bind3 #( 12, 16, 4 ) rightline6_gen( selecteddata [31:20] , curblockline [15:0] , selecteddata [3:0] , rightline6 ); - hdl4se_bind2 #( 16, 16 ) rightline7_gen( selecteddata [31:16] , curblockline [15:0] , rightline7 ); - hdl4se_bind2 #( 20, 12 ) rightline8_gen( selecteddata [31:12] , curblockline [11:0] , rightline8 ); - hdl4se_bind2 #( 24, 8 ) rightline9_gen( selecteddata [31:8] , curblockline [7:0] , rightline9 ); - hdl4se_bind2 #( 28, 4 ) rightline10_gen( selecteddata [31:4] , curblockline [3:0] , rightline10 ); + hdl4se_bind2 #( 4, 28 ) rightline0_gen( curblockline [15:12] , 32'h0, rightline0 ); + hdl4se_bind2 #( 8, 24 ) rightline1_gen( curblockline [15:8] , 32'h0, rightline1 ); + hdl4se_bind2 #( 12, 20 ) rightline2_gen( curblockline [15:4] , 32'h0, rightline2 ); + hdl4se_bind2 #( 16, 16 ) rightline3_gen( curblockline [15:0] , 32'h0, rightline3 ); + hdl4se_bind3 #( 4, 16, 12 ) rightline4_gen( 32'h0, curblockline [15:0] , 32'h0, rightline4 ); + hdl4se_bind3 #( 8, 16, 8 ) rightline5_gen( 32'h0, curblockline [15:0] , 32'h0, rightline5 ); + hdl4se_bind3 #( 12, 16, 4 ) rightline6_gen( 32'h0, curblockline [15:0] , 32'h0, rightline6 ); + hdl4se_bind2 #( 16, 16 ) rightline7_gen( 32'h0, curblockline [15:0] , rightline7 ); + hdl4se_bind2 #( 20, 12 ) rightline8_gen( 32'h0, curblockline [11:0] , rightline8 ); + hdl4se_bind2 #( 24, 8 ) rightline9_gen( 32'h0, curblockline [7:0] , rightline9 ); + hdl4se_bind2 #( 28, 4 ) rightline10_gen( 32'h0, curblockline [3:0] , rightline10 ); hdl4se_mux16 #( 32 ) selectrightline( blockx_3 [3:0] , selecteddata, selecteddata, selecteddata, selecteddata, selecteddata , rightline0, rightline1, rightline2, rightline3, rightline4 , rightline5, rightline6, rightline7, rightline8, rightline9 , rightline10, rightline_3_18 ); hdl4se_mux8 #( 32 ) writedatasel( bWriteDataSel, bNextBlockLo, bNextBlockHi, 32'h0, 32'h0, bCtrlScore - , bCtrlLevel, bCtrlSpeed, bram_ReadData, selecteddata ); + , bCtrlLevel, bCtrlSpeed, right?bFlushReadData [63:32] :bFlushReadData [31:0] , selecteddata ); +endmodule + + +module main +( + input wClk, + input nwReset, + output wWrite, + output [31:0] bWriteAddr, + output [31:0] bWriteData, + output [3:0] bWriteMask, + output wRead, + output [31:0] bReadAddr, + input [31:0] bReadData +) +; + wire wram_Write; + wire [5:0] bram_WriteAddr; + wire [63:0] bram_WriteData; + wire [5:0] bram_ReadAddr; + wire [63:0] bram_ReadData; + wire wCtrlWrite; + wire [5:0] bCtrlWriteAddr; + wire [63:0] bCtrlWriteData; + wire [5:0] bCtrlReadAddr; + wire [63:0] bCtrlReadData; + wire [31:0] bCtrlKeyData; + wire wCtrlStateComplete; + wire wCtrlStateChange; + wire [3:0] bCtrlState; + wire [31:0] bCtrlSpeed; + wire [31:0] bCtrlLevel; + wire [31:0] bCtrlScore; + wire [63:0] bNextBlock; + wire [63:0] bCurBlock; + wire [15:0] bCurBlockPos; + wire [5:0] bFlushReadAddr; + wire [63:0] bFlushReadData; + assign wram_Write = bCtrlState==1?1'b0:wCtrlWrite; + assign bram_WriteAddr = bCtrlState==1?6'b0:bCtrlWriteAddr; + assign bram_WriteData = bCtrlState==1?64'b0:bCtrlWriteData; + assign bram_ReadAddr = bCtrlState==1?bFlushReadAddr:bCtrlReadAddr; + assign bCtrlReadData = bram_ReadData; + assign bFlushReadData = bram_ReadData; + assign wRead = 32'h1; + assign bReadAddr = 32'hf0000000; + assign bCtrlKeyData = bReadData; + hdl4se_ram1p #( 64, 6 ) ram_0( wClk, wram_Write, bram_WriteAddr, bram_WriteData, bram_ReadAddr, bram_ReadData + ); + teris_ctrl ctrl( wClk, nwReset, wCtrlWrite, bCtrlWriteAddr, bCtrlWriteData, bCtrlReadAddr + , bCtrlReadData, bCtrlKeyData, wCtrlStateComplete, wCtrlStateChange, bCtrlState + , bCtrlScore, bCtrlSpeed, bCtrlLevel, bNextBlock, bCurBlock + , bCurBlockPos ); + flushtodisp flusher( wClk, bCtrlState, wCtrlStateComplete, bFlushReadAddr, bFlushReadData, wWrite + , bWriteAddr, bWriteData, bCtrlSpeed, bCtrlLevel, bCtrlScore + , bNextBlock, bCurBlock, bCurBlockPos ); endmodule diff --git a/parser/verilog_expr.c b/parser/verilog_expr.c index 3a40748..8cc7c44 100644 --- a/parser/verilog_expr.c +++ b/parser/verilog_expr.c @@ -747,35 +747,43 @@ static int expr_verilognode_procheck(HOBJECT object, HOBJECT module, void * para pobj->data.isconst = 0; IBigNumber** left = NULL; IBigNumber** right = NULL; - verilogExpr* pexpr; + verilogExpr* pexpr0; + verilogExpr* pexpr1; if (1 != objectCall2(pobj->data.expr0, procheck, module, param)) return 0; if (1 != objectCall2(pobj->data.expr1, procheck, module, param)) return 0; - left = bigintegerCreate(32); - pexpr = verilogExprGetData(pobj->data.expr0); - if (pexpr == NULL) + + pexpr0 = verilogExprGetData(pobj->data.expr0); + if (pexpr0 == NULL) goto endofbinop; - pobj->data.width = pexpr->width; - if (pexpr->exprtype != EXPRTYPE_BIGNUMBER) + pobj->data.width = pexpr0->width; + + pexpr1 = verilogExprGetData(pobj->data.expr1); + if (pexpr1 == NULL) goto endofbinop; - if (0 != objectCall1(left, Clone, pexpr->bignumber)) + if (pobj->data.width < pexpr1->width) + pobj->data.width = pexpr1->width; + + if (pexpr0->exprtype != EXPRTYPE_BIGNUMBER) goto endofbinop; - right = bigintegerCreate(32); - pexpr = verilogExprGetData(pobj->data.expr1); - if (pexpr == NULL) + left = bigintegerCreate(32); + if (0 != objectCall1(left, Clone, pexpr0->bignumber)) goto endofbinop; - if (pobj->data.width < pexpr->width) - pobj->data.width = pexpr->width; - if (pexpr->exprtype != EXPRTYPE_BIGNUMBER) + + if (pexpr1->exprtype != EXPRTYPE_BIGNUMBER) goto endofbinop; - if (0 != objectCall1(right, Clone, pexpr->bignumber)) + right = bigintegerCreate(32); + if (0 != objectCall1(right, Clone, pexpr1->bignumber)) goto endofbinop; + if (0 != expr_calc_binop(pobj->data.op, left, left, right)) goto endofbinop; + if (0 != expr_setto_number(pobj, left)) { goto endofbinop; } + pobj->data.isconst = 1; endofbinop: objectRelease(left); @@ -813,7 +821,70 @@ static int expr_verilognode_procheck(HOBJECT object, HOBJECT module, void * para } break; case EXPRTYPE_IFOP: - break; + { + pobj->data.isconst = 0; + IBigNumber** cond = NULL; + IBigNumber** yes = NULL; + IBigNumber** no = NULL; + verilogExpr* expr_cond; + verilogExpr* expr_yes; + verilogExpr* expr_no; + if (1 != objectCall2(pobj->data.expr0, procheck, module, param)) + return 0; + if (1 != objectCall2(pobj->data.expr1, procheck, module, param)) + return 0; + + expr_cond = verilogExprGetData(pobj->data.expr0); + if (expr_cond == NULL) + goto endofifop; + + expr_yes = verilogExprGetData(pobj->data.expr1); + if (expr_yes == NULL) + goto endofifop; + pobj->data.width = expr_yes->width; + + expr_no = verilogExprGetData(pobj->data.expr2); + if (expr_no == NULL) + goto endofifop; + pobj->data.width = expr_yes->width; + + if (expr_cond->exprtype != EXPRTYPE_BIGNUMBER) + goto endofifop; + cond = bigintegerCreate(32); + if (0 != objectCall1(cond, Clone, expr_cond->bignumber)) + goto endofifop; + + if (expr_yes->exprtype != EXPRTYPE_BIGNUMBER) + goto endofifop; + yes = bigintegerCreate(32); + if (0 != objectCall1(yes, Clone, expr_yes->bignumber)) + goto endofifop; + + if (expr_no->exprtype != EXPRTYPE_BIGNUMBER) + goto endofifop; + no = bigintegerCreate(32); + if (0 != objectCall1(no, Clone, expr_no->bignumber)) + goto endofifop; + + if (objectCall0(cond, IsZero)) { + if (0 != expr_setto_number(pobj, no)) { + goto endofifop; + } + } + else { + if (0 != expr_setto_number(pobj, yes)) { + goto endofifop; + } + } + + pobj->data.isconst = 1; + endofifop: + objectRelease(cond); + objectRelease(yes); + objectRelease(no); + return pobj->data.isconst; + } + break; case EXPRTYPE_HIERARCHICAL_IDENT: break; default: @@ -844,6 +915,7 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module expr_result->index = varindex; expr_result->portindex = 0; expr_result->width = width; + pobj->data.width = expr_result->width; return 0; } if (verilogparseIsConstExpr(pobj, module)) { @@ -867,6 +939,7 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module expr_result->portindex = 0; expr_result->type = EXPR_RESULT_TYPE_TEMPVAR; expr_result->width = 64; /*fixed me*/ + pobj->data.width = expr_result->width; return 0; } switch (pobj->data.exprtype) { @@ -884,6 +957,7 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module expr_result->portindex = index; expr_result->type = EXPR_RESULT_TYPE_PORT; expr_result->width = 32;/*fixed me*/ + pobj->data.width = expr_result->width; return 0; } index = verilogModuleGetNetIndex(module, select->name->string); @@ -892,11 +966,43 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module expr_result->portindex = 0; expr_result->type = EXPR_RESULT_TYPE_NET; expr_result->width = 32;/*fixed me*/ + pobj->data.width = expr_result->width; return 0; } } else if (select->range_type == RANGE_TYPE_BITSELECT) { - + verilogExpr * msb; + int msbindex; + expr_verilognode_procheck(select->range_msb, module, param); + msb = verilogExprGetData(select->range_msb); + if (msb->exprtype == EXPRTYPE_BIGNUMBER) { + objectCall1(msb->bignumber, GetInt32, &msbindex); + int varindex = moduleinfo->tempvarindex++; + fprintf(pFile, "\tIHDL4SEUnit** tempvar_%d = hdl4seCreateUnit(module, CLSID_HDL4SE_SPLIT1, \"%d, %d, %d\", \"tempvar_%d\");\n", + varindex, + msbindex + 1, /*fixed me*/ + 1, + msbindex, + varindex); + expr_result->index = varindex; + expr_result->portindex = 1; + expr_result->type = EXPR_RESULT_TYPE_TEMPVAR; + expr_result->width = 1; + pobj->data.width = expr_result->width; + index = verilogModuleGetPortIndex(module, select->name->string); + if (index >= 0) { + fprintf(pFile, "\tobjectCall3(tempvar_%d, Connect, 0, unit, %d);\n", varindex, index); + return 0; + } + index = verilogModuleGetNetIndex(module, select->name->string); + if (index >= 0) { + fprintf(pFile, "\tobjectCall3(tempvar_%d, Connect, 0, nets[%d], 0);\n", varindex, index); + return 0; + } + } + else { + fprintf(pFile, "#error only support constant bit select\n"); + } } else if (select->range_type == RANGE_TYPE_PARTSELECT) { verilogExpr* lsb, * msb; @@ -920,6 +1026,7 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module expr_result->portindex = 1; expr_result->type = EXPR_RESULT_TYPE_TEMPVAR; expr_result->width = msbindex - lsbindex + 1; + pobj->data.width = expr_result->width; index = verilogModuleGetPortIndex(module, select->name->string); if (index >= 0) { fprintf(pFile, "\tobjectCall3(tempvar_%d, Connect, 0, unit, %d);\n", varindex, index); @@ -974,7 +1081,8 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module fprintf(pFile, "unit, %d);\n", expr_results[i].portindex); } } - + pobj->data.width = reswidth; + expr_result->width = reswidth; expr_result->index = varindex; expr_result->portindex = 2; expr_result->type = EXPR_RESULT_TYPE_TEMPVAR; @@ -1009,7 +1117,8 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module fprintf(pFile, "unit, %d);\n", expr_results[i].portindex); } } - + pobj->data.width = reswidth; + expr_result->width = reswidth; expr_result->index = varindex; expr_result->portindex = 1; expr_result->type = EXPR_RESULT_TYPE_TEMPVAR; @@ -1045,6 +1154,8 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module fprintf(pFile, "unit, %d);\n", expr_results[i].portindex); } } + pobj->data.width = reswidth; + expr_result->width = reswidth; expr_result->index = varindex; expr_result->portindex = 3; expr_result->type = EXPR_RESULT_TYPE_TEMPVAR; @@ -1055,46 +1166,6 @@ static int expr_verilognode_gencode(HOBJECT object, FILE * pFile, HOBJECT module return -1; } -#if 0 -HOBJECT verilogparseCreateExpr( - int exprtype, - IConstStringVar* value, - HOBJECT range0, - HOBJECT range1, - int op, - HOBJECT expr0, - HOBJECT expr1, - HOBJECT expr2, - IDListVarPtr attributes, - IDListVarPtr elementselect -) -{ - HOBJECT expr = NULL; - sExpr * pobj; - A_u_t_o_registor_expr(); - objectCreate(CLSID_VERILOG_EXPR, NULL, 0, &expr); - if (expr == NULL) - return NULL; - pobj = (sExpr *)objectThis(expr); - objectQueryInterface(value, IID_CONSTSTRING, (void**)&pobj->data.value); - pobj->data.exprtype = exprtype; - pobj->data.op = op; - pobj->data.attributes = attributes; - pobj->data.elementselect = elementselect; - objectQueryInterface(expr0, IID_VERILOG_NODE, (void**)&pobj->data.expr0); - objectRelease(expr0); - objectQueryInterface(expr1, IID_VERILOG_NODE, (void**)&pobj->data.expr1); - objectRelease(expr1); - objectQueryInterface(expr2, IID_VERILOG_NODE, (void**)&pobj->data.expr2); - objectRelease(expr2); - objectQueryInterface(range0, IID_VERILOG_NODE, (void**)&pobj->data.range0); - objectRelease(range0); - objectQueryInterface(range1, IID_VERILOG_NODE, (void**)&pobj->data.range1); - objectRelease(range1); - return expr; -} -#endif - static sExpr* verilogparseCreateGeneralExpr(int exprtype, IDListVarPtr attributes) { HOBJECT expr = NULL; -- GitLab