diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v3.qsf b/examples/hdl4se_riscv/de2/de2_riscv_v3.qsf index f84053f62a9bf4babe43ab8cc9ee9068ef110a23..0a6993d44b38932f51866eca6243937935e6179d 100644 --- a/examples/hdl4se_riscv/de2/de2_riscv_v3.qsf +++ b/examples/hdl4se_riscv/de2/de2_riscv_v3.qsf @@ -993,8 +993,8 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VERILOG_FILE ../verilog/uart/uart_ctrl.v set_global_assignment -name VERILOG_FILE ../verilog/altera/uart/uart_fifo.v -set_global_assignment -name VERILOG_FILE ../verilog/altera/uart/uart_ctrl.v set_global_assignment -name VERILOG_FILE ../verilog/altera/uart/altera_uart.v set_global_assignment -name VERILOG_FILE ../verilog/altera/regfile/regfile.v set_global_assignment -name VERILOG_FILE ../verilog/altera/ram/ram128kB.v diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v3.qws b/examples/hdl4se_riscv/de2/de2_riscv_v3.qws new file mode 100644 index 0000000000000000000000000000000000000000..63563b76eda4b19c3f4f321afd3f1b7df67b8d5e Binary files /dev/null and b/examples/hdl4se_riscv/de2/de2_riscv_v3.qws differ diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v3.v b/examples/hdl4se_riscv/de2/de2_riscv_v3.v index 156fd159f4efe55673f54d5458c7274ab7ccabb4..e9553daf71d102c5eb3e870261a1e6c791a3c57a 100644 --- a/examples/hdl4se_riscv/de2/de2_riscv_v3.v +++ b/examples/hdl4se_riscv/de2/de2_riscv_v3.v @@ -455,7 +455,7 @@ inout [35:0] GPIO; regfile regs(regno, regena, wClk, regwrdata, regwren, regrddata); regfile regs2(regno2, regena2, wClk, regwrdata2, regwren2, regrddata2); - ram128kB ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam); + ram16kB ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam); riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData, regno, regena, regwrdata, regwren, (lastregno == 0) ? 0 : regrddata, regno2, regena2, regwrdata2, regwren2, (lastregno2 == 0) ? 0 : regrddata2 diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v4.htm b/examples/hdl4se_riscv/de2/de2_riscv_v4.htm new file mode 100644 index 0000000000000000000000000000000000000000..8935db6ab8320e5462d3ffd3aec604f343c80114 --- /dev/null +++ b/examples/hdl4se_riscv/de2/de2_riscv_v4.htm @@ -0,0 +1,2979 @@ + + +

DE2-115 FPGA Board Configuration

+
+
+

Pin Assignments:

+ +
+
+
+

Pin Assignment Table:

+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + +
CLOCK
NameLocationDirectionStandard
CLOCK_50Y2input 3.3-V LVTTL
CLOCK2_50AG14input 3.3-V LVTTL
CLOCK3_50AG15input 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + +
Sma
NameLocationDirectionStandard
SMA_CLKINAH14input 3.3-V LVTTL
SMA_CLKOUTAE23output3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
LED
NameLocationDirectionStandard
LEDR[0]G19output2.5 V
LEDR[1]F19output2.5 V
LEDR[2]E19output2.5 V
LEDR[3]F21output2.5 V
LEDR[4]F18output2.5 V
LEDR[5]E18output2.5 V
LEDR[6]J19output2.5 V
LEDR[7]H19output2.5 V
LEDR[8]J17output2.5 V
LEDR[9]G17output2.5 V
LEDR[10]J15output2.5 V
LEDR[11]H16output2.5 V
LEDR[12]J16output2.5 V
LEDR[13]H17output2.5 V
LEDR[14]F15output2.5 V
LEDR[15]G15output2.5 V
LEDR[16]G16output2.5 V
LEDR[17]H15output2.5 V
LEDG[0]E21output2.5 V
LEDG[1]E22output2.5 V
LEDG[2]E25output2.5 V
LEDG[3]E24output2.5 V
LEDG[4]H21output2.5 V
LEDG[5]G20output2.5 V
LEDG[6]G22output2.5 V
LEDG[7]G21output2.5 V
LEDG[8]F17output2.5 V
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
KEY
NameLocationDirectionStandard
KEY[0]M23input 3.3-V LVTTL
KEY[1]M21input 3.3-V LVTTL
KEY[2]N21input 3.3-V LVTTL
KEY[3]R24input 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
EX_IO
NameLocationDirectionStandard
EX_IO[0]J10inout 3.3-V LVTTL
EX_IO[1]J14inout 3.3-V LVTTL
EX_IO[2]H13inout 3.3-V LVTTL
EX_IO[3]H14inout 3.3-V LVTTL
EX_IO[4]F14inout 3.3-V LVTTL
EX_IO[5]E10inout 3.3-V LVTTL
EX_IO[6]D9inout 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SW
NameLocationDirectionStandard
SW[0]AB28input 3.3-V LVTTL
SW[1]AC28input 3.3-V LVTTL
SW[2]AC27input 3.3-V LVTTL
SW[3]AD27input 3.3-V LVTTL
SW[4]AB27input 3.3-V LVTTL
SW[5]AC26input 3.3-V LVTTL
SW[6]AD26input 3.3-V LVTTL
SW[7]AB26input 3.3-V LVTTL
SW[8]AC25input 3.3-V LVTTL
SW[9]AB25input 3.3-V LVTTL
SW[10]AC24input 3.3-V LVTTL
SW[11]AB24input 3.3-V LVTTL
SW[12]AB23input 3.3-V LVTTL
SW[13]AA24input 3.3-V LVTTL
SW[14]AA23input 3.3-V LVTTL
SW[15]AA22input 3.3-V LVTTL
SW[16]Y24input 3.3-V LVTTL
SW[17]Y23input 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SEG7
NameLocationDirectionStandard
HEX0[0]G18output2.5 V
HEX0[1]F22output2.5 V
HEX0[2]E17output2.5 V
HEX0[3]L26output3.3-V LVTTL
HEX0[4]L25output3.3-V LVTTL
HEX0[5]J22output3.3-V LVTTL
HEX0[6]H22output3.3-V LVTTL
HEX1[0]M24output3.3-V LVTTL
HEX1[1]Y22output3.3-V LVTTL
HEX1[2]W21output3.3-V LVTTL
HEX1[3]W22output3.3-V LVTTL
HEX1[4]W25output3.3-V LVTTL
HEX1[5]U23output3.3-V LVTTL
HEX1[6]U24output3.3-V LVTTL
HEX2[0]AA25output3.3-V LVTTL
HEX2[1]AA26output3.3-V LVTTL
HEX2[2]Y25output3.3-V LVTTL
HEX2[3]W26output3.3-V LVTTL
HEX2[4]Y26output3.3-V LVTTL
HEX2[5]W27output3.3-V LVTTL
HEX2[6]W28output3.3-V LVTTL
HEX3[0]V21output3.3-V LVTTL
HEX3[1]U21output3.3-V LVTTL
HEX3[2]AB20output3.3-V LVTTL
HEX3[3]AA21output3.3-V LVTTL
HEX3[4]AD24output3.3-V LVTTL
HEX3[5]AF23output3.3-V LVTTL
HEX3[6]Y19output3.3-V LVTTL
HEX4[0]AB19output3.3-V LVTTL
HEX4[1]AA19output3.3-V LVTTL
HEX4[2]AG21output3.3-V LVTTL
HEX4[3]AH21output3.3-V LVTTL
HEX4[4]AE19output3.3-V LVTTL
HEX4[5]AF19output3.3-V LVTTL
HEX4[6]AE18output3.3-V LVTTL
HEX5[0]AD18output3.3-V LVTTL
HEX5[1]AC18output3.3-V LVTTL
HEX5[2]AB18output3.3-V LVTTL
HEX5[3]AH19output3.3-V LVTTL
HEX5[4]AG19output3.3-V LVTTL
HEX5[5]AF18output3.3-V LVTTL
HEX5[6]AH18output3.3-V LVTTL
HEX6[0]AA17output3.3-V LVTTL
HEX6[1]AB16output3.3-V LVTTL
HEX6[2]AA16output3.3-V LVTTL
HEX6[3]AB17output3.3-V LVTTL
HEX6[4]AB15output3.3-V LVTTL
HEX6[5]AA15output3.3-V LVTTL
HEX6[6]AC17output3.3-V LVTTL
HEX7[0]AD17output3.3-V LVTTL
HEX7[1]AE17output3.3-V LVTTL
HEX7[2]AG17output3.3-V LVTTL
HEX7[3]AH17output3.3-V LVTTL
HEX7[4]AF17output3.3-V LVTTL
HEX7[5]AG18output3.3-V LVTTL
HEX7[6]AA14output3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
LCD
NameLocationDirectionStandard
LCD_DATA[0]L3inout 3.3-V LVTTL
LCD_DATA[1]L1inout 3.3-V LVTTL
LCD_DATA[2]L2inout 3.3-V LVTTL
LCD_DATA[3]K7inout 3.3-V LVTTL
LCD_DATA[4]K1inout 3.3-V LVTTL
LCD_DATA[5]K2inout 3.3-V LVTTL
LCD_DATA[6]M3inout 3.3-V LVTTL
LCD_DATA[7]M5inout 3.3-V LVTTL
LCD_BLONL6output3.3-V LVTTL
LCD_RWM1output3.3-V LVTTL
LCD_ENL4output3.3-V LVTTL
LCD_RSM2output3.3-V LVTTL
LCD_ONL5output3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
RS232
NameLocationDirectionStandard
UART_TXDG9output3.3-V LVTTL
UART_RXDG12input 3.3-V LVTTL
UART_RTSG14output3.3-V LVTTL
UART_CTSJ13input 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
PS2 for Keyboard and Mouse
NameLocationDirectionStandard
PS2_CLKG6inout 3.3-V LVTTL
PS2_DATH5inout 3.3-V LVTTL
PS2_CLK2G5inout 3.3-V LVTTL
PS2_DAT2F5inout 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SDCARD
NameLocationDirectionStandard
SD_CMDAD14inout 3.3-V LVTTL
SD_CLKAE13output3.3-V LVTTL
SD_WP_NAF14input 3.3-V LVTTL
SD_DAT[0]AE14inout 3.3-V LVTTL
SD_DAT[1]AF13inout 3.3-V LVTTL
SD_DAT[2]AB14inout 3.3-V LVTTL
SD_DAT[3]AC14inout 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
VGA
NameLocationDirectionStandard
VGA_HSG13output3.3-V LVTTL
VGA_VSC13output3.3-V LVTTL
VGA_SYNC_NC10output3.3-V LVTTL
VGA_CLKA12output3.3-V LVTTL
VGA_BLANK_NF11output3.3-V LVTTL
VGA_R[0]E12output3.3-V LVTTL
VGA_R[1]E11output3.3-V LVTTL
VGA_R[2]D10output3.3-V LVTTL
VGA_R[3]F12output3.3-V LVTTL
VGA_R[4]G10output3.3-V LVTTL
VGA_R[5]J12output3.3-V LVTTL
VGA_R[6]H8output3.3-V LVTTL
VGA_R[7]H10output3.3-V LVTTL
VGA_G[0]G8output3.3-V LVTTL
VGA_G[1]G11output3.3-V LVTTL
VGA_G[2]F8output3.3-V LVTTL
VGA_G[3]H12output3.3-V LVTTL
VGA_G[4]C8output3.3-V LVTTL
VGA_G[5]B8output3.3-V LVTTL
VGA_G[6]F10output3.3-V LVTTL
VGA_G[7]C9output3.3-V LVTTL
VGA_B[0]B10output3.3-V LVTTL
VGA_B[1]A10output3.3-V LVTTL
VGA_B[2]C11output3.3-V LVTTL
VGA_B[3]B11output3.3-V LVTTL
VGA_B[4]A11output3.3-V LVTTL
VGA_B[5]C12output3.3-V LVTTL
VGA_B[6]D11output3.3-V LVTTL
VGA_B[7]D12output3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Audio
NameLocationDirectionStandard
AUD_ADCLRCKC2inout 3.3-V LVTTL
AUD_ADCDATD2input 3.3-V LVTTL
AUD_DACLRCKE3inout 3.3-V LVTTL
AUD_DACDATD1output3.3-V LVTTL
AUD_XCKE1output3.3-V LVTTL
AUD_BCLKF2inout 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + +
I2C for EEPROM
NameLocationDirectionStandard
EEP_I2C_SCLKD14output3.3-V LVTTL
EEP_I2C_SDATE14inout 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + +
I2C for Audio Tv-Decoder
NameLocationDirectionStandard
I2C_SCLKB7output3.3-V LVTTL
I2C_SDATA8inout 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Ethernet 0
NameLocationDirectionStandard
ENETCLK_25A14input 3.3-V LVTTL
ENET0_TX_DATA[0]C18output2.5 V
ENET0_RX_DATA[0]C16input 2.5 V
ENET0_TX_DATA[1]D19output2.5 V
ENET0_RX_DATA[1]D16input 2.5 V
ENET0_TX_DATA[2]A19output2.5 V
ENET0_RX_DATA[2]D17input 2.5 V
ENET0_TX_DATA[3]B19output2.5 V
ENET0_RX_DATA[3]C15input 2.5 V
ENET0_GTX_CLKA17output2.5 V
ENET0_TX_ENA18output2.5 V
ENET0_TX_ERB18output2.5 V
ENET0_INT_NA21input 2.5 V
ENET0_RST_NC19output2.5 V
ENET0_RX_DVC17input 2.5 V
ENET0_RX_ERD18input 2.5 V
ENET0_RX_CRSD15input 2.5 V
ENET0_RX_COLE15input 2.5 V
ENET0_RX_CLKA15input 2.5 V
ENET0_TX_CLKB17input 2.5 V
ENET0_MDCC20output2.5 V
ENET0_MDIOB21inout 2.5 V
ENET0_LINK100C14input 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Ethernet 1
NameLocationDirectionStandard
ENET1_TX_DATA[0]C25output2.5 V
ENET1_RX_DATA[0]B23input 2.5 V
ENET1_TX_DATA[1]A26output2.5 V
ENET1_RX_DATA[1]C21input 2.5 V
ENET1_TX_DATA[2]B26output2.5 V
ENET1_RX_DATA[2]A23input 2.5 V
ENET1_TX_DATA[3]C26output2.5 V
ENET1_RX_DATA[3]D21input 2.5 V
ENET1_GTX_CLKC23output2.5 V
ENET1_TX_ENB25output2.5 V
ENET1_TX_ERA25output2.5 V
ENET1_INT_ND24input 2.5 V
ENET1_RST_ND22output2.5 V
ENET1_RX_DVA22input 2.5 V
ENET1_RX_ERC24input 2.5 V
ENET1_RX_CRSD20input 2.5 V
ENET1_RX_COLB22input 2.5 V
ENET1_RX_CLKB15input 2.5 V
ENET1_TX_CLKC22input 2.5 V
ENET1_MDCD23output2.5 V
ENET1_MDIOD25inout 2.5 V
ENET1_LINK100D13input 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
TV Decoder
NameLocationDirectionStandard
TD_HSE5input 3.3-V LVTTL
TD_VSE4input 3.3-V LVTTL
TD_CLK27B14input 3.3-V LVTTL
TD_RESET_NG7output3.3-V LVTTL
TD_DATA[0]E8input 3.3-V LVTTL
TD_DATA[1]A7input 3.3-V LVTTL
TD_DATA[2]D8input 3.3-V LVTTL
TD_DATA[3]C7input 3.3-V LVTTL
TD_DATA[4]D7input 3.3-V LVTTL
TD_DATA[5]D6input 3.3-V LVTTL
TD_DATA[6]E7input 3.3-V LVTTL
TD_DATA[7]F7input 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
USB 2.0 OTG (Cypress CY7C67200)
NameLocationDirectionStandard
OTG_DATA[0]J6inout 3.3-V LVTTL
OTG_DATA[1]K4inout 3.3-V LVTTL
OTG_DATA[2]J5inout 3.3-V LVTTL
OTG_DATA[3]K3inout 3.3-V LVTTL
OTG_DATA[4]J4inout 3.3-V LVTTL
OTG_DATA[5]J3inout 3.3-V LVTTL
OTG_DATA[6]J7inout 3.3-V LVTTL
OTG_DATA[7]H6inout 3.3-V LVTTL
OTG_DATA[8]H3inout 3.3-V LVTTL
OTG_DATA[9]H4inout 3.3-V LVTTL
OTG_DATA[10]G1inout 3.3-V LVTTL
OTG_DATA[11]G2inout 3.3-V LVTTL
OTG_DATA[12]G3inout 3.3-V LVTTL
OTG_DATA[13]F1inout 3.3-V LVTTL
OTG_DATA[14]F3inout 3.3-V LVTTL
OTG_DATA[15]G4inout 3.3-V LVTTL
OTG_ADDR[0]H7output3.3-V LVTTL
OTG_ADDR[1]C3output3.3-V LVTTL
OTG_INTD5input 3.3-V LVTTL
OTG_RST_NC5output3.3-V LVTTL
OTG_CS_NA3output3.3-V LVTTL
OTG_RD_NB3output3.3-V LVTTL
OTG_WE_NA4output3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + +
IR Receiver
NameLocationDirectionStandard
IRDA_RXDY15input 3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SDRAM
NameLocationDirectionStandard
DRAM_BA[0]U7output3.3-V LVTTL
DRAM_BA[1]R4output3.3-V LVTTL
DRAM_DQM[0]U2output3.3-V LVTTL
DRAM_DQM[1]W4output3.3-V LVTTL
DRAM_DQM[2]K8output3.3-V LVTTL
DRAM_DQM[3]N8output3.3-V LVTTL
DRAM_RAS_NU6output3.3-V LVTTL
DRAM_CAS_NV7output3.3-V LVTTL
DRAM_CKEAA6output3.3-V LVTTL
DRAM_CLKAE5output3.3-V LVTTL
DRAM_WE_NV6output3.3-V LVTTL
DRAM_CS_NT4output3.3-V LVTTL
DRAM_DQ[0]W3inout 3.3-V LVTTL
DRAM_DQ[1]W2inout 3.3-V LVTTL
DRAM_DQ[2]V4inout 3.3-V LVTTL
DRAM_DQ[3]W1inout 3.3-V LVTTL
DRAM_DQ[4]V3inout 3.3-V LVTTL
DRAM_DQ[5]V2inout 3.3-V LVTTL
DRAM_DQ[6]V1inout 3.3-V LVTTL
DRAM_DQ[7]U3inout 3.3-V LVTTL
DRAM_DQ[8]Y3inout 3.3-V LVTTL
DRAM_DQ[9]Y4inout 3.3-V LVTTL
DRAM_DQ[10]AB1inout 3.3-V LVTTL
DRAM_DQ[11]AA3inout 3.3-V LVTTL
DRAM_DQ[12]AB2inout 3.3-V LVTTL
DRAM_DQ[13]AC1inout 3.3-V LVTTL
DRAM_DQ[14]AB3inout 3.3-V LVTTL
DRAM_DQ[15]AC2inout 3.3-V LVTTL
DRAM_DQ[16]M8inout 3.3-V LVTTL
DRAM_DQ[17]L8inout 3.3-V LVTTL
DRAM_DQ[18]P2inout 3.3-V LVTTL
DRAM_DQ[19]N3inout 3.3-V LVTTL
DRAM_DQ[20]N4inout 3.3-V LVTTL
DRAM_DQ[21]M4inout 3.3-V LVTTL
DRAM_DQ[22]M7inout 3.3-V LVTTL
DRAM_DQ[23]L7inout 3.3-V LVTTL
DRAM_DQ[24]U5inout 3.3-V LVTTL
DRAM_DQ[25]R7inout 3.3-V LVTTL
DRAM_DQ[26]R1inout 3.3-V LVTTL
DRAM_DQ[27]R2inout 3.3-V LVTTL
DRAM_DQ[28]R3inout 3.3-V LVTTL
DRAM_DQ[29]T3inout 3.3-V LVTTL
DRAM_DQ[30]U4inout 3.3-V LVTTL
DRAM_DQ[31]U1inout 3.3-V LVTTL
DRAM_ADDR[0]R6output3.3-V LVTTL
DRAM_ADDR[1]V8output3.3-V LVTTL
DRAM_ADDR[2]U8output3.3-V LVTTL
DRAM_ADDR[3]P1output3.3-V LVTTL
DRAM_ADDR[4]V5output3.3-V LVTTL
DRAM_ADDR[5]W8output3.3-V LVTTL
DRAM_ADDR[6]W7output3.3-V LVTTL
DRAM_ADDR[7]AA7output3.3-V LVTTL
DRAM_ADDR[8]Y5output3.3-V LVTTL
DRAM_ADDR[9]Y6output3.3-V LVTTL
DRAM_ADDR[10]R5output3.3-V LVTTL
DRAM_ADDR[11]AA5output3.3-V LVTTL
DRAM_ADDR[12]Y7output3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SRAM
NameLocationDirectionStandard
SRAM_ADDR[0]AB7output3.3-V LVTTL
SRAM_ADDR[1]AD7output3.3-V LVTTL
SRAM_ADDR[2]AE7output3.3-V LVTTL
SRAM_ADDR[3]AC7output3.3-V LVTTL
SRAM_ADDR[4]AB6output3.3-V LVTTL
SRAM_ADDR[5]AE6output3.3-V LVTTL
SRAM_ADDR[6]AB5output3.3-V LVTTL
SRAM_ADDR[7]AC5output3.3-V LVTTL
SRAM_ADDR[8]AF5output3.3-V LVTTL
SRAM_ADDR[9]T7output3.3-V LVTTL
SRAM_ADDR[10]AF2output3.3-V LVTTL
SRAM_ADDR[11]AD3output3.3-V LVTTL
SRAM_ADDR[12]AB4output3.3-V LVTTL
SRAM_ADDR[13]AC3output3.3-V LVTTL
SRAM_ADDR[14]AA4output3.3-V LVTTL
SRAM_ADDR[15]AB11output3.3-V LVTTL
SRAM_ADDR[16]AC11output3.3-V LVTTL
SRAM_ADDR[17]AB9output3.3-V LVTTL
SRAM_ADDR[18]AB8output3.3-V LVTTL
SRAM_ADDR[19]T8output3.3-V LVTTL
SRAM_DQ[0]AH3inout 3.3-V LVTTL
SRAM_DQ[1]AF4inout 3.3-V LVTTL
SRAM_DQ[2]AG4inout 3.3-V LVTTL
SRAM_DQ[3]AH4inout 3.3-V LVTTL
SRAM_DQ[4]AF6inout 3.3-V LVTTL
SRAM_DQ[5]AG6inout 3.3-V LVTTL
SRAM_DQ[6]AH6inout 3.3-V LVTTL
SRAM_DQ[7]AF7inout 3.3-V LVTTL
SRAM_DQ[8]AD1inout 3.3-V LVTTL
SRAM_DQ[9]AD2inout 3.3-V LVTTL
SRAM_DQ[10]AE2inout 3.3-V LVTTL
SRAM_DQ[11]AE1inout 3.3-V LVTTL
SRAM_DQ[12]AE3inout 3.3-V LVTTL
SRAM_DQ[13]AE4inout 3.3-V LVTTL
SRAM_DQ[14]AF3inout 3.3-V LVTTL
SRAM_DQ[15]AG3inout 3.3-V LVTTL
SRAM_UB_NAC4output3.3-V LVTTL
SRAM_LB_NAD4output3.3-V LVTTL
SRAM_CE_NAF8output3.3-V LVTTL
SRAM_OE_NAD5output3.3-V LVTTL
SRAM_WE_NAE8output3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Flash
NameLocationDirectionStandard
FL_ADDR[0]AG12output3.3-V LVTTL
FL_ADDR[1]AH7output3.3-V LVTTL
FL_ADDR[2]Y13output3.3-V LVTTL
FL_ADDR[3]Y14output3.3-V LVTTL
FL_ADDR[4]Y12output3.3-V LVTTL
FL_ADDR[5]AA13output3.3-V LVTTL
FL_ADDR[6]AA12output3.3-V LVTTL
FL_ADDR[7]AB13output3.3-V LVTTL
FL_ADDR[8]AB12output3.3-V LVTTL
FL_ADDR[9]AB10output3.3-V LVTTL
FL_ADDR[10]AE9output3.3-V LVTTL
FL_ADDR[11]AF9output3.3-V LVTTL
FL_ADDR[12]AA10output3.3-V LVTTL
FL_ADDR[13]AD8output3.3-V LVTTL
FL_ADDR[14]AC8output3.3-V LVTTL
FL_ADDR[15]Y10output3.3-V LVTTL
FL_ADDR[16]AA8output3.3-V LVTTL
FL_ADDR[17]AH12output3.3-V LVTTL
FL_ADDR[18]AC12output3.3-V LVTTL
FL_ADDR[19]AD12output3.3-V LVTTL
FL_ADDR[20]AE10output3.3-V LVTTL
FL_ADDR[21]AD10output3.3-V LVTTL
FL_ADDR[22]AD11output3.3-V LVTTL
FL_DQ[0]AH8inout 3.3-V LVTTL
FL_DQ[1]AF10inout 3.3-V LVTTL
FL_DQ[2]AG10inout 3.3-V LVTTL
FL_DQ[3]AH10inout 3.3-V LVTTL
FL_DQ[4]AF11inout 3.3-V LVTTL
FL_DQ[5]AG11inout 3.3-V LVTTL
FL_DQ[6]AH11inout 3.3-V LVTTL
FL_DQ[7]AF12inout 3.3-V LVTTL
FL_CE_NAG7output3.3-V LVTTL
FL_OE_NAG8output3.3-V LVTTL
FL_RST_NAE11output3.3-V LVTTL
FL_RYY1input 3.3-V LVTTL
FL_WE_NAC10output3.3-V LVTTL
FL_WP_NAE12output3.3-V LVTTL
+

+ +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
GPIO connect to GPIO Default
NameLocationDirectionStandardGPIO Pin Index
GPIO[0]AB22inout 3.3-V LVTTL1
GPIO[1]AC15inout 3.3-V LVTTL2
GPIO[2]AB21inout 3.3-V LVTTL3
GPIO[3]Y17inout 3.3-V LVTTL4
GPIO[4]AC21inout 3.3-V LVTTL5
GPIO[5]Y16inout 3.3-V LVTTL6
GPIO[6]AD21inout 3.3-V LVTTL7
GPIO[7]AE16inout 3.3-V LVTTL8
GPIO[8]AD15inout 3.3-V LVTTL9
GPIO[9]AE15inout 3.3-V LVTTL10
GPIO[10]AC19inout 3.3-V LVTTL13
GPIO[11]AF16inout 3.3-V LVTTL14
GPIO[12]AD19inout 3.3-V LVTTL15
GPIO[13]AF15inout 3.3-V LVTTL16
GPIO[14]AF24inout 3.3-V LVTTL17
GPIO[15]AE21inout 3.3-V LVTTL18
GPIO[16]AF25inout 3.3-V LVTTL19
GPIO[17]AC22inout 3.3-V LVTTL20
GPIO[18]AE22inout 3.3-V LVTTL21
GPIO[19]AF21inout 3.3-V LVTTL22
GPIO[20]AF22inout 3.3-V LVTTL23
GPIO[21]AD22inout 3.3-V LVTTL24
GPIO[22]AG25inout 3.3-V LVTTL25
GPIO[23]AD25inout 3.3-V LVTTL26
GPIO[24]AH25inout 3.3-V LVTTL27
GPIO[25]AE25inout 3.3-V LVTTL28
GPIO[26]AG22inout 3.3-V LVTTL31
GPIO[27]AE24inout 3.3-V LVTTL32
GPIO[28]AH22inout 3.3-V LVTTL33
GPIO[29]AF26inout 3.3-V LVTTL34
GPIO[30]AE20inout 3.3-V LVTTL35
GPIO[31]AG23inout 3.3-V LVTTL36
GPIO[32]AF20inout 3.3-V LVTTL37
GPIO[33]AH26inout 3.3-V LVTTL38
GPIO[34]AH23inout 3.3-V LVTTL39
GPIO[35]AG26inout 3.3-V LVTTL40
+ + diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v4.pin b/examples/hdl4se_riscv/de2/de2_riscv_v4.pin new file mode 100644 index 0000000000000000000000000000000000000000..a34c258cac9e349e29d15d549b8601e07e62c672 --- /dev/null +++ b/examples/hdl4se_riscv/de2/de2_riscv_v4.pin @@ -0,0 +1,850 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 2.5V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.1.0 Build 162 10/23/2013 SJ Full Version +CHIP "de2_riscv_v4" ASSIGNED TO AN: EP4CE115F29C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +VCCIO8 : A2 : power : : 3.3V : 8 : +OTG_CS_N : A3 : output : 3.3-V LVTTL : : 8 : Y +OTG_WE_N : A4 : output : 3.3-V LVTTL : : 8 : Y +VCCIO8 : A5 : power : : 3.3V : 8 : +RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8 : +TD_DATA[1] : A7 : input : 3.3-V LVTTL : : 8 : Y +I2C_SDAT : A8 : bidir : 3.3-V LVTTL : : 8 : Y +VCCIO8 : A9 : power : : 3.3V : 8 : +VGA_B[1] : A10 : output : 3.3-V LVTTL : : 8 : Y +VGA_B[4] : A11 : output : 3.3-V LVTTL : : 8 : Y +VGA_CLK : A12 : output : 3.3-V LVTTL : : 8 : Y +VCCIO8 : A13 : power : : 3.3V : 8 : +ENETCLK_25 : A14 : input : 3.3-V LVTTL : : 8 : Y +ENET0_RX_CLK : A15 : input : 2.5 V : : 7 : Y +VCCIO7 : A16 : power : : 2.5V : 7 : +ENET0_GTX_CLK : A17 : output : 2.5 V : : 7 : Y +ENET0_TX_EN : A18 : output : 2.5 V : : 7 : Y +ENET0_TX_DATA[2] : A19 : output : 2.5 V : : 7 : Y +VCCIO7 : A20 : power : : 2.5V : 7 : +ENET0_INT_N : A21 : input : 2.5 V : : 7 : Y +ENET1_RX_DV : A22 : input : 2.5 V : : 7 : Y +ENET1_RX_DATA[2] : A23 : input : 2.5 V : : 7 : Y +VCCIO7 : A24 : power : : 2.5V : 7 : +ENET1_TX_ER : A25 : output : 2.5 V : : 7 : Y +ENET1_TX_DATA[1] : A26 : output : 2.5 V : : 7 : Y +VCCIO7 : A27 : power : : 2.5V : 7 : +VCCIO2 : AA1 : power : : 3.3V : 2 : +GND : AA2 : gnd : : : : +DRAM_DQ[11] : AA3 : bidir : 3.3-V LVTTL : : 2 : Y +SRAM_ADDR[14] : AA4 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[11] : AA5 : output : 3.3-V LVTTL : : 2 : Y +DRAM_CKE : AA6 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[7] : AA7 : output : 3.3-V LVTTL : : 2 : Y +FL_ADDR[16] : AA8 : output : 3.3-V LVTTL : : 3 : Y +GNDA1 : AA9 : gnd : : : : +FL_ADDR[12] : AA10 : output : 3.3-V LVTTL : : 3 : Y +VCCIO3 : AA11 : power : : 3.3V : 3 : +FL_ADDR[6] : AA12 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[5] : AA13 : output : 3.3-V LVTTL : : 3 : Y +HEX7[6] : AA14 : output : 3.3-V LVTTL : : 3 : Y +HEX6[5] : AA15 : output : 3.3-V LVTTL : : 4 : Y +HEX6[2] : AA16 : output : 3.3-V LVTTL : : 4 : Y +HEX6[0] : AA17 : output : 3.3-V LVTTL : : 4 : Y +VCCIO4 : AA18 : power : : 3.3V : 4 : +HEX4[1] : AA19 : output : 3.3-V LVTTL : : 4 : Y +GNDA4 : AA20 : gnd : : : : +HEX3[3] : AA21 : output : 3.3-V LVTTL : : 4 : Y +SW[15] : AA22 : input : 3.3-V LVTTL : : 5 : Y +SW[14] : AA23 : input : 3.3-V LVTTL : : 5 : Y +SW[13] : AA24 : input : 3.3-V LVTTL : : 5 : Y +HEX2[0] : AA25 : output : 3.3-V LVTTL : : 5 : Y +HEX2[1] : AA26 : output : 3.3-V LVTTL : : 5 : Y +GND : AA27 : gnd : : : : +VCCIO5 : AA28 : power : : 3.3V : 5 : +DRAM_DQ[10] : AB1 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[12] : AB2 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[14] : AB3 : bidir : 3.3-V LVTTL : : 2 : Y +SRAM_ADDR[12] : AB4 : output : 3.3-V LVTTL : : 2 : Y +SRAM_ADDR[6] : AB5 : output : 3.3-V LVTTL : : 2 : Y +SRAM_ADDR[4] : AB6 : output : 3.3-V LVTTL : : 2 : Y +SRAM_ADDR[0] : AB7 : output : 3.3-V LVTTL : : 3 : Y +SRAM_ADDR[18] : AB8 : output : 3.3-V LVTTL : : 3 : Y +SRAM_ADDR[17] : AB9 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[9] : AB10 : output : 3.3-V LVTTL : : 3 : Y +SRAM_ADDR[15] : AB11 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[8] : AB12 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[7] : AB13 : output : 3.3-V LVTTL : : 3 : Y +SD_DAT[2] : AB14 : bidir : 3.3-V LVTTL : : 3 : Y +HEX6[4] : AB15 : output : 3.3-V LVTTL : : 4 : Y +HEX6[1] : AB16 : output : 3.3-V LVTTL : : 4 : Y +HEX6[3] : AB17 : output : 3.3-V LVTTL : : 4 : Y +HEX5[2] : AB18 : output : 3.3-V LVTTL : : 4 : Y +HEX4[0] : AB19 : output : 3.3-V LVTTL : : 4 : Y +HEX3[2] : AB20 : output : 3.3-V LVTTL : : 4 : Y +GPIO[2] : AB21 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[0] : AB22 : bidir : 3.3-V LVTTL : : 4 : Y +SW[12] : AB23 : input : 3.3-V LVTTL : : 5 : Y +SW[11] : AB24 : input : 3.3-V LVTTL : : 5 : Y +SW[9] : AB25 : input : 3.3-V LVTTL : : 5 : Y +SW[7] : AB26 : input : 3.3-V LVTTL : : 5 : Y +SW[4] : AB27 : input : 3.3-V LVTTL : : 5 : Y +SW[0] : AB28 : input : 3.3-V LVTTL : : 5 : Y +DRAM_DQ[13] : AC1 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[15] : AC2 : bidir : 3.3-V LVTTL : : 2 : Y +SRAM_ADDR[13] : AC3 : output : 3.3-V LVTTL : : 2 : Y +SRAM_UB_N : AC4 : output : 3.3-V LVTTL : : 2 : Y +SRAM_ADDR[7] : AC5 : output : 3.3-V LVTTL : : 2 : Y +GND : AC6 : gnd : : : : +SRAM_ADDR[3] : AC7 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[14] : AC8 : output : 3.3-V LVTTL : : 3 : Y +GND : AC9 : gnd : : : : +FL_WE_N : AC10 : output : 3.3-V LVTTL : : 3 : Y +SRAM_ADDR[16] : AC11 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[18] : AC12 : output : 3.3-V LVTTL : : 3 : Y +GND : AC13 : gnd : : : : +SD_DAT[3] : AC14 : bidir : 3.3-V LVTTL : : 3 : Y +GPIO[1] : AC15 : bidir : 3.3-V LVTTL : : 4 : Y +GND : AC16 : gnd : : : : +HEX6[6] : AC17 : output : 3.3-V LVTTL : : 4 : Y +HEX5[1] : AC18 : output : 3.3-V LVTTL : : 4 : Y +GPIO[10] : AC19 : bidir : 3.3-V LVTTL : : 4 : Y +GND : AC20 : gnd : : : : +GPIO[4] : AC21 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[17] : AC22 : bidir : 3.3-V LVTTL : : 4 : Y +GND : AC23 : gnd : : : : +SW[10] : AC24 : input : 3.3-V LVTTL : : 5 : Y +SW[8] : AC25 : input : 3.3-V LVTTL : : 5 : Y +SW[5] : AC26 : input : 3.3-V LVTTL : : 5 : Y +SW[2] : AC27 : input : 3.3-V LVTTL : : 5 : Y +SW[1] : AC28 : input : 3.3-V LVTTL : : 5 : Y +SRAM_DQ[8] : AD1 : bidir : 3.3-V LVTTL : : 2 : Y +SRAM_DQ[9] : AD2 : bidir : 3.3-V LVTTL : : 2 : Y +SRAM_ADDR[11] : AD3 : output : 3.3-V LVTTL : : 2 : Y +SRAM_LB_N : AD4 : output : 3.3-V LVTTL : : 3 : Y +SRAM_OE_N : AD5 : output : 3.3-V LVTTL : : 3 : Y +VCCIO3 : AD6 : power : : 3.3V : 3 : +SRAM_ADDR[1] : AD7 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[13] : AD8 : output : 3.3-V LVTTL : : 3 : Y +VCCIO3 : AD9 : power : : 3.3V : 3 : +FL_ADDR[21] : AD10 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[22] : AD11 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[19] : AD12 : output : 3.3-V LVTTL : : 3 : Y +VCCIO3 : AD13 : power : : 3.3V : 3 : +SD_CMD : AD14 : bidir : 3.3-V LVTTL : : 3 : Y +GPIO[8] : AD15 : bidir : 3.3-V LVTTL : : 4 : Y +VCCIO4 : AD16 : power : : 3.3V : 4 : +HEX7[0] : AD17 : output : 3.3-V LVTTL : : 4 : Y +HEX5[0] : AD18 : output : 3.3-V LVTTL : : 4 : Y +GPIO[12] : AD19 : bidir : 3.3-V LVTTL : : 4 : Y +VCCIO4 : AD20 : power : : 3.3V : 4 : +GPIO[6] : AD21 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[21] : AD22 : bidir : 3.3-V LVTTL : : 4 : Y +VCCIO4 : AD23 : power : : 3.3V : 4 : +HEX3[4] : AD24 : output : 3.3-V LVTTL : : 4 : Y +GPIO[23] : AD25 : bidir : 3.3-V LVTTL : : 4 : Y +SW[6] : AD26 : input : 3.3-V LVTTL : : 5 : Y +SW[3] : AD27 : input : 3.3-V LVTTL : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AD28 : : : : 5 : +SRAM_DQ[11] : AE1 : bidir : 3.3-V LVTTL : : 2 : Y +SRAM_DQ[10] : AE2 : bidir : 3.3-V LVTTL : : 2 : Y +SRAM_DQ[12] : AE3 : bidir : 3.3-V LVTTL : : 2 : Y +SRAM_DQ[13] : AE4 : bidir : 3.3-V LVTTL : : 3 : Y +DRAM_CLK : AE5 : output : 3.3-V LVTTL : : 3 : Y +SRAM_ADDR[5] : AE6 : output : 3.3-V LVTTL : : 3 : Y +SRAM_ADDR[2] : AE7 : output : 3.3-V LVTTL : : 3 : Y +SRAM_WE_N : AE8 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[10] : AE9 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[20] : AE10 : output : 3.3-V LVTTL : : 3 : Y +FL_RST_N : AE11 : output : 3.3-V LVTTL : : 3 : Y +FL_WP_N : AE12 : output : 3.3-V LVTTL : : 3 : Y +SD_CLK : AE13 : output : 3.3-V LVTTL : : 3 : Y +SD_DAT[0] : AE14 : bidir : 3.3-V LVTTL : : 3 : Y +GPIO[9] : AE15 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[7] : AE16 : bidir : 3.3-V LVTTL : : 4 : Y +HEX7[1] : AE17 : output : 3.3-V LVTTL : : 4 : Y +HEX4[6] : AE18 : output : 3.3-V LVTTL : : 4 : Y +HEX4[4] : AE19 : output : 3.3-V LVTTL : : 4 : Y +GPIO[30] : AE20 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[15] : AE21 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[18] : AE22 : bidir : 3.3-V LVTTL : : 4 : Y +SMA_CLKOUT : AE23 : output : 3.3-V LVTTL : : 4 : Y +GPIO[27] : AE24 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[25] : AE25 : bidir : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AE26 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE27 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5 : +GND : AF1 : gnd : : : : +SRAM_ADDR[10] : AF2 : output : 3.3-V LVTTL : : 2 : Y +SRAM_DQ[14] : AF3 : bidir : 3.3-V LVTTL : : 3 : Y +SRAM_DQ[1] : AF4 : bidir : 3.3-V LVTTL : : 3 : Y +SRAM_ADDR[8] : AF5 : output : 3.3-V LVTTL : : 3 : Y +SRAM_DQ[4] : AF6 : bidir : 3.3-V LVTTL : : 3 : Y +SRAM_DQ[7] : AF7 : bidir : 3.3-V LVTTL : : 3 : Y +SRAM_CE_N : AF8 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[11] : AF9 : output : 3.3-V LVTTL : : 3 : Y +FL_DQ[1] : AF10 : bidir : 3.3-V LVTTL : : 3 : Y +FL_DQ[4] : AF11 : bidir : 3.3-V LVTTL : : 3 : Y +FL_DQ[7] : AF12 : bidir : 3.3-V LVTTL : : 3 : Y +SD_DAT[1] : AF13 : bidir : 3.3-V LVTTL : : 3 : Y +SD_WP_N : AF14 : input : 3.3-V LVTTL : : 3 : Y +GPIO[13] : AF15 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[11] : AF16 : bidir : 3.3-V LVTTL : : 4 : Y +HEX7[4] : AF17 : output : 3.3-V LVTTL : : 4 : Y +HEX5[5] : AF18 : output : 3.3-V LVTTL : : 4 : Y +HEX4[5] : AF19 : output : 3.3-V LVTTL : : 4 : Y +GPIO[32] : AF20 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[19] : AF21 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[20] : AF22 : bidir : 3.3-V LVTTL : : 4 : Y +HEX3[5] : AF23 : output : 3.3-V LVTTL : : 4 : Y +GPIO[14] : AF24 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[16] : AF25 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[29] : AF26 : bidir : 3.3-V LVTTL : : 4 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : AF27 : : : : 5 : +GND : AF28 : gnd : : : : +VCCIO2 : AG1 : power : : 3.3V : 2 : +GND : AG2 : gnd : : : : +SRAM_DQ[15] : AG3 : bidir : 3.3-V LVTTL : : 3 : Y +SRAM_DQ[2] : AG4 : bidir : 3.3-V LVTTL : : 3 : Y +GND : AG5 : gnd : : : : +SRAM_DQ[5] : AG6 : bidir : 3.3-V LVTTL : : 3 : Y +FL_CE_N : AG7 : output : 3.3-V LVTTL : : 3 : Y +FL_OE_N : AG8 : output : 3.3-V LVTTL : : 3 : Y +GND : AG9 : gnd : : : : +FL_DQ[2] : AG10 : bidir : 3.3-V LVTTL : : 3 : Y +FL_DQ[5] : AG11 : bidir : 3.3-V LVTTL : : 3 : Y +FL_ADDR[0] : AG12 : output : 3.3-V LVTTL : : 3 : Y +GND : AG13 : gnd : : : : +CLOCK2_50 : AG14 : input : 3.3-V LVTTL : : 3 : Y +CLOCK3_50 : AG15 : input : 3.3-V LVTTL : : 4 : Y +GND : AG16 : gnd : : : : +HEX7[2] : AG17 : output : 3.3-V LVTTL : : 4 : Y +HEX7[5] : AG18 : output : 3.3-V LVTTL : : 4 : Y +HEX5[4] : AG19 : output : 3.3-V LVTTL : : 4 : Y +GND : AG20 : gnd : : : : +HEX4[2] : AG21 : output : 3.3-V LVTTL : : 4 : Y +GPIO[26] : AG22 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[31] : AG23 : bidir : 3.3-V LVTTL : : 4 : Y +GND : AG24 : gnd : : : : +GPIO[22] : AG25 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[35] : AG26 : bidir : 3.3-V LVTTL : : 4 : Y +GND : AG27 : gnd : : : : +VCCIO5 : AG28 : power : : 3.3V : 5 : +VCCIO3 : AH2 : power : : 3.3V : 3 : +SRAM_DQ[0] : AH3 : bidir : 3.3-V LVTTL : : 3 : Y +SRAM_DQ[3] : AH4 : bidir : 3.3-V LVTTL : : 3 : Y +VCCIO3 : AH5 : power : : 3.3V : 3 : +SRAM_DQ[6] : AH6 : bidir : 3.3-V LVTTL : : 3 : Y +FL_ADDR[1] : AH7 : output : 3.3-V LVTTL : : 3 : Y +FL_DQ[0] : AH8 : bidir : 3.3-V LVTTL : : 3 : Y +VCCIO3 : AH9 : power : : 3.3V : 3 : +FL_DQ[3] : AH10 : bidir : 3.3-V LVTTL : : 3 : Y +FL_DQ[6] : AH11 : bidir : 3.3-V LVTTL : : 3 : Y +FL_ADDR[17] : AH12 : output : 3.3-V LVTTL : : 3 : Y +VCCIO3 : AH13 : power : : 3.3V : 3 : +SMA_CLKIN : AH14 : input : 3.3-V LVTTL : : 3 : Y +GND+ : AH15 : : : : 4 : +VCCIO4 : AH16 : power : : 3.3V : 4 : +HEX7[3] : AH17 : output : 3.3-V LVTTL : : 4 : Y +HEX5[6] : AH18 : output : 3.3-V LVTTL : : 4 : Y +HEX5[3] : AH19 : output : 3.3-V LVTTL : : 4 : Y +VCCIO4 : AH20 : power : : 3.3V : 4 : +HEX4[3] : AH21 : output : 3.3-V LVTTL : : 4 : Y +GPIO[28] : AH22 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[34] : AH23 : bidir : 3.3-V LVTTL : : 4 : Y +VCCIO4 : AH24 : power : : 3.3V : 4 : +GPIO[24] : AH25 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[33] : AH26 : bidir : 3.3-V LVTTL : : 4 : Y +VCCIO4 : AH27 : power : : 3.3V : 4 : +VCCIO1 : B1 : power : : 3.3V : 1 : +GND : B2 : gnd : : : : +OTG_RD_N : B3 : output : 3.3-V LVTTL : : 8 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : B4 : : : : 8 : +GND : B5 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8 : +I2C_SCLK : B7 : output : 3.3-V LVTTL : : 8 : Y +VGA_G[5] : B8 : output : 3.3-V LVTTL : : 8 : Y +GND : B9 : gnd : : : : +VGA_B[0] : B10 : output : 3.3-V LVTTL : : 8 : Y +VGA_B[3] : B11 : output : 3.3-V LVTTL : : 8 : Y +GND : B12 : gnd : : : : +GND : B13 : gnd : : : : +TD_CLK27 : B14 : input : 3.3-V LVTTL : : 8 : Y +ENET1_RX_CLK : B15 : input : 2.5 V : : 7 : Y +GND : B16 : gnd : : : : +ENET0_TX_CLK : B17 : input : 2.5 V : : 7 : Y +ENET0_TX_ER : B18 : output : 2.5 V : : 7 : Y +ENET0_TX_DATA[3] : B19 : output : 2.5 V : : 7 : Y +GND : B20 : gnd : : : : +ENET0_MDIO : B21 : bidir : 2.5 V : : 7 : Y +ENET1_RX_COL : B22 : input : 2.5 V : : 7 : Y +ENET1_RX_DATA[0] : B23 : input : 2.5 V : : 7 : Y +GND : B24 : gnd : : : : +ENET1_TX_EN : B25 : output : 2.5 V : : 7 : Y +ENET1_TX_DATA[2] : B26 : output : 2.5 V : : 7 : Y +GND : B27 : gnd : : : : +VCCIO6 : B28 : power : : 3.3V : 6 : +GND : C1 : gnd : : : : +AUD_ADCLRCK : C2 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_ADDR[1] : C3 : output : 3.3-V LVTTL : : 8 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : : : : 8 : +OTG_RST_N : C5 : output : 3.3-V LVTTL : : 8 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C6 : : : : 8 : +TD_DATA[3] : C7 : input : 3.3-V LVTTL : : 8 : Y +VGA_G[4] : C8 : output : 3.3-V LVTTL : : 8 : Y +VGA_G[7] : C9 : output : 3.3-V LVTTL : : 8 : Y +VGA_SYNC_N : C10 : output : 3.3-V LVTTL : : 8 : Y +VGA_B[2] : C11 : output : 3.3-V LVTTL : : 8 : Y +VGA_B[5] : C12 : output : 3.3-V LVTTL : : 8 : Y +VGA_VS : C13 : output : 3.3-V LVTTL : : 8 : Y +ENET0_LINK100 : C14 : input : 3.3-V LVTTL : : 8 : Y +ENET0_RX_DATA[3] : C15 : input : 2.5 V : : 7 : Y +ENET0_RX_DATA[0] : C16 : input : 2.5 V : : 7 : Y +ENET0_RX_DV : C17 : input : 2.5 V : : 7 : Y +ENET0_TX_DATA[0] : C18 : output : 2.5 V : : 7 : Y +ENET0_RST_N : C19 : output : 2.5 V : : 7 : Y +ENET0_MDC : C20 : output : 2.5 V : : 7 : Y +ENET1_RX_DATA[1] : C21 : input : 2.5 V : : 7 : Y +ENET1_TX_CLK : C22 : input : 2.5 V : : 7 : Y +ENET1_GTX_CLK : C23 : output : 2.5 V : : 7 : Y +ENET1_RX_ER : C24 : input : 2.5 V : : 7 : Y +ENET1_TX_DATA[0] : C25 : output : 2.5 V : : 7 : Y +ENET1_TX_DATA[3] : C26 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : C27 : : : : 6 : +GND : C28 : gnd : : : : +AUD_DACDAT : D1 : output : 3.3-V LVTTL : : 1 : Y +AUD_ADCDAT : D2 : input : 3.3-V LVTTL : : 1 : Y +GND : D3 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : D4 : : : : 8 : +OTG_INT : D5 : input : 3.3-V LVTTL : : 8 : Y +TD_DATA[5] : D6 : input : 3.3-V LVTTL : : 8 : Y +TD_DATA[4] : D7 : input : 3.3-V LVTTL : : 8 : Y +TD_DATA[2] : D8 : input : 3.3-V LVTTL : : 8 : Y +EX_IO[6] : D9 : bidir : 3.3-V LVTTL : : 8 : Y +VGA_R[2] : D10 : output : 3.3-V LVTTL : : 8 : Y +VGA_B[6] : D11 : output : 3.3-V LVTTL : : 8 : Y +VGA_B[7] : D12 : output : 3.3-V LVTTL : : 8 : Y +ENET1_LINK100 : D13 : input : 3.3-V LVTTL : : 8 : Y +EEP_I2C_SCLK : D14 : output : 3.3-V LVTTL : : 8 : Y +ENET0_RX_CRS : D15 : input : 2.5 V : : 7 : Y +ENET0_RX_DATA[1] : D16 : input : 2.5 V : : 7 : Y +ENET0_RX_DATA[2] : D17 : input : 2.5 V : : 7 : Y +ENET0_RX_ER : D18 : input : 2.5 V : : 7 : Y +ENET0_TX_DATA[1] : D19 : output : 2.5 V : : 7 : Y +ENET1_RX_CRS : D20 : input : 2.5 V : : 7 : Y +ENET1_RX_DATA[3] : D21 : input : 2.5 V : : 7 : Y +ENET1_RST_N : D22 : output : 2.5 V : : 7 : Y +ENET1_MDC : D23 : output : 2.5 V : : 7 : Y +ENET1_INT_N : D24 : input : 2.5 V : : 7 : Y +ENET1_MDIO : D25 : bidir : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : D26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : D28 : : : : 6 : +AUD_XCK : E1 : output : 3.3-V LVTTL : : 1 : Y +~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : E2 : input : 3.3-V LVTTL : : 1 : N +AUD_DACLRCK : E3 : bidir : 3.3-V LVTTL : : 1 : Y +TD_VS : E4 : input : 3.3-V LVTTL : : 8 : Y +TD_HS : E5 : input : 3.3-V LVTTL : : 8 : Y +VCCIO8 : E6 : power : : 3.3V : 8 : +TD_DATA[6] : E7 : input : 3.3-V LVTTL : : 8 : Y +TD_DATA[0] : E8 : input : 3.3-V LVTTL : : 8 : Y +VCCIO8 : E9 : power : : 3.3V : 8 : +EX_IO[5] : E10 : bidir : 3.3-V LVTTL : : 8 : Y +VGA_R[1] : E11 : output : 3.3-V LVTTL : : 8 : Y +VGA_R[0] : E12 : output : 3.3-V LVTTL : : 8 : Y +VCCIO8 : E13 : power : : 3.3V : 8 : +EEP_I2C_SDAT : E14 : bidir : 3.3-V LVTTL : : 8 : Y +ENET0_RX_COL : E15 : input : 2.5 V : : 7 : Y +VCCIO7 : E16 : power : : 2.5V : 7 : +HEX0[2] : E17 : output : 2.5 V : : 7 : Y +LEDR[5] : E18 : output : 2.5 V : : 7 : Y +LEDR[2] : E19 : output : 2.5 V : : 7 : Y +VCCIO7 : E20 : power : : 2.5V : 7 : +LEDG[0] : E21 : output : 2.5 V : : 7 : Y +LEDG[1] : E22 : output : 2.5 V : : 7 : Y +VCCIO7 : E23 : power : : 2.5V : 7 : +LEDG[3] : E24 : output : 2.5 V : : 7 : Y +LEDG[2] : E25 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : E26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6 : +OTG_DATA[13] : F1 : bidir : 3.3-V LVTTL : : 1 : Y +AUD_BCLK : F2 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_DATA[14] : F3 : bidir : 3.3-V LVTTL : : 1 : Y +~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP : F4 : input : 3.3-V LVTTL : : 1 : N +PS2_DAT2 : F5 : bidir : 3.3-V LVTTL : : 1 : Y +GND : F6 : gnd : : : : +TD_DATA[7] : F7 : input : 3.3-V LVTTL : : 8 : Y +VGA_G[2] : F8 : output : 3.3-V LVTTL : : 8 : Y +GND : F9 : gnd : : : : +VGA_G[6] : F10 : output : 3.3-V LVTTL : : 8 : Y +VGA_BLANK_N : F11 : output : 3.3-V LVTTL : : 8 : Y +VGA_R[3] : F12 : output : 3.3-V LVTTL : : 8 : Y +GND : F13 : gnd : : : : +EX_IO[4] : F14 : bidir : 3.3-V LVTTL : : 8 : Y +LEDR[14] : F15 : output : 2.5 V : : 7 : Y +GND : F16 : gnd : : : : +LEDG[8] : F17 : output : 2.5 V : : 7 : Y +LEDR[4] : F18 : output : 2.5 V : : 7 : Y +LEDR[1] : F19 : output : 2.5 V : : 7 : Y +GND : F20 : gnd : : : : +LEDR[3] : F21 : output : 2.5 V : : 7 : Y +HEX0[1] : F22 : output : 2.5 V : : 7 : Y +GND : F23 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : F24 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6 : +OTG_DATA[10] : G1 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_DATA[11] : G2 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_DATA[12] : G3 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_DATA[15] : G4 : bidir : 3.3-V LVTTL : : 1 : Y +PS2_CLK2 : G5 : bidir : 3.3-V LVTTL : : 1 : Y +PS2_CLK : G6 : bidir : 3.3-V LVTTL : : 1 : Y +TD_RESET_N : G7 : output : 3.3-V LVTTL : : 8 : Y +VGA_G[0] : G8 : output : 3.3-V LVTTL : : 8 : Y +UART_TXD : G9 : output : 3.3-V LVTTL : : 8 : Y +VGA_R[4] : G10 : output : 3.3-V LVTTL : : 8 : Y +VGA_G[1] : G11 : output : 3.3-V LVTTL : : 8 : Y +UART_RXD : G12 : input : 3.3-V LVTTL : : 8 : Y +VGA_HS : G13 : output : 3.3-V LVTTL : : 8 : Y +UART_RTS : G14 : output : 3.3-V LVTTL : : 8 : Y +LEDR[15] : G15 : output : 2.5 V : : 7 : Y +LEDR[16] : G16 : output : 2.5 V : : 7 : Y +LEDR[9] : G17 : output : 2.5 V : : 7 : Y +HEX0[0] : G18 : output : 2.5 V : : 7 : Y +LEDR[0] : G19 : output : 2.5 V : : 7 : Y +LEDG[5] : G20 : output : 2.5 V : : 7 : Y +LEDG[7] : G21 : output : 2.5 V : : 7 : Y +LEDG[6] : G22 : output : 2.5 V : : 7 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : G23 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G24 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6 : +VCCIO1 : H1 : power : : 3.3V : 1 : +GND : H2 : gnd : : : : +OTG_DATA[8] : H3 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_DATA[9] : H4 : bidir : 3.3-V LVTTL : : 1 : Y +PS2_DAT : H5 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_DATA[7] : H6 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_ADDR[0] : H7 : output : 3.3-V LVTTL : : 1 : Y +VGA_R[6] : H8 : output : 3.3-V LVTTL : : 8 : Y +GNDA3 : H9 : gnd : : : : +VGA_R[7] : H10 : output : 3.3-V LVTTL : : 8 : Y +VCCIO8 : H11 : power : : 3.3V : 8 : +VGA_G[3] : H12 : output : 3.3-V LVTTL : : 8 : Y +EX_IO[2] : H13 : bidir : 3.3-V LVTTL : : 8 : Y +EX_IO[3] : H14 : bidir : 3.3-V LVTTL : : 8 : Y +LEDR[17] : H15 : output : 2.5 V : : 7 : Y +LEDR[11] : H16 : output : 2.5 V : : 7 : Y +LEDR[13] : H17 : output : 2.5 V : : 7 : Y +VCCIO7 : H18 : power : : 2.5V : 7 : +LEDR[7] : H19 : output : 2.5 V : : 7 : Y +GNDA2 : H20 : gnd : : : : +LEDG[4] : H21 : output : 2.5 V : : 7 : Y +HEX0[6] : H22 : output : 3.3-V LVTTL : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : H26 : : : : 6 : +GND : H27 : gnd : : : : +VCCIO6 : H28 : power : : 3.3V : 6 : +GND+ : J1 : : : : 1 : +GND : J2 : gnd : : : : +OTG_DATA[5] : J3 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_DATA[4] : J4 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_DATA[2] : J5 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_DATA[0] : J6 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_DATA[6] : J7 : bidir : 3.3-V LVTTL : : 1 : Y +VCCA3 : J8 : power : : 2.5V : : +VCCD_PLL3 : J9 : power : : 1.2V : : +EX_IO[0] : J10 : bidir : 3.3-V LVTTL : : 8 : Y +GND : J11 : gnd : : : : +VGA_R[5] : J12 : output : 3.3-V LVTTL : : 8 : Y +UART_CTS : J13 : input : 3.3-V LVTTL : : 8 : Y +EX_IO[1] : J14 : bidir : 3.3-V LVTTL : : 8 : Y +LEDR[10] : J15 : output : 2.5 V : : 7 : Y +LEDR[12] : J16 : output : 2.5 V : : 7 : Y +LEDR[8] : J17 : output : 2.5 V : : 7 : Y +GND : J18 : gnd : : : : +LEDR[6] : J19 : output : 2.5 V : : 7 : Y +VCCD_PLL2 : J20 : power : : 1.2V : : +VCCA2 : J21 : power : : 2.5V : : +HEX0[5] : J22 : output : 3.3-V LVTTL : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6 : +GND+ : J27 : : : : 6 : +GND+ : J28 : : : : 6 : +LCD_DATA[4] : K1 : bidir : 3.3-V LVTTL : : 1 : Y +LCD_DATA[5] : K2 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_DATA[3] : K3 : bidir : 3.3-V LVTTL : : 1 : Y +OTG_DATA[1] : K4 : bidir : 3.3-V LVTTL : : 1 : Y +VCCIO1 : K5 : power : : 3.3V : 1 : +GND : K6 : gnd : : : : +LCD_DATA[3] : K7 : bidir : 3.3-V LVTTL : : 1 : Y +DRAM_DQM[2] : K8 : output : 3.3-V LVTTL : : 1 : Y +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +VCCINT : K11 : power : : 1.2V : : +GND : K12 : gnd : : : : +VCCINT : K13 : power : : 1.2V : : +GND : K14 : gnd : : : : +VCCINT : K15 : power : : 1.2V : : +GND : K16 : gnd : : : : +VCCINT : K17 : power : : 1.2V : : +GND : K18 : gnd : : : : +VCCINT : K19 : power : : 1.2V : : +GND : K20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6 : +GND : K23 : gnd : : : : +VCCIO6 : K24 : power : : 3.3V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6 : +LCD_DATA[1] : L1 : bidir : 3.3-V LVTTL : : 1 : Y +LCD_DATA[2] : L2 : bidir : 3.3-V LVTTL : : 1 : Y +LCD_DATA[0] : L3 : bidir : 3.3-V LVTTL : : 1 : Y +LCD_EN : L4 : output : 3.3-V LVTTL : : 1 : Y +LCD_ON : L5 : output : 3.3-V LVTTL : : 1 : Y +LCD_BLON : L6 : output : 3.3-V LVTTL : : 1 : Y +DRAM_DQ[23] : L7 : bidir : 3.3-V LVTTL : : 1 : Y +DRAM_DQ[17] : L8 : bidir : 3.3-V LVTTL : : 1 : Y +GND : L9 : gnd : : : : +VCCINT : L10 : power : : 1.2V : : +GND : L11 : gnd : : : : +VCCINT : L12 : power : : 1.2V : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +GND : L15 : gnd : : : : +VCCINT : L16 : power : : 1.2V : : +GND : L17 : gnd : : : : +VCCINT : L18 : power : : 1.2V : : +GND : L19 : gnd : : : : +VCCINT : L20 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : L21 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L22 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6 : +HEX0[4] : L25 : output : 3.3-V LVTTL : : 6 : Y +HEX0[3] : L26 : output : 3.3-V LVTTL : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : L27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6 : +LCD_RW : M1 : output : 3.3-V LVTTL : : 1 : Y +LCD_RS : M2 : output : 3.3-V LVTTL : : 1 : Y +LCD_DATA[6] : M3 : bidir : 3.3-V LVTTL : : 1 : Y +DRAM_DQ[21] : M4 : bidir : 3.3-V LVTTL : : 1 : Y +LCD_DATA[7] : M5 : bidir : 3.3-V LVTTL : : 1 : Y +nSTATUS : M6 : : : : 1 : +DRAM_DQ[22] : M7 : bidir : 3.3-V LVTTL : : 1 : Y +DRAM_DQ[16] : M8 : bidir : 3.3-V LVTTL : : 1 : Y +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +VCCINT : M11 : power : : 1.2V : : +GND : M12 : gnd : : : : +VCCINT : M13 : power : : 1.2V : : +GND : M14 : gnd : : : : +VCCINT : M15 : power : : 1.2V : : +GND : M16 : gnd : : : : +VCCINT : M17 : power : : 1.2V : : +GND : M18 : gnd : : : : +VCCINT : M19 : power : : 1.2V : : +GND : M20 : gnd : : : : +KEY[1] : M21 : input : 3.3-V LVTTL : : 6 : Y +MSEL2 : M22 : : : : 6 : +KEY[0] : M23 : input : 3.3-V LVTTL : : 6 : Y +HEX1[0] : M24 : output : 3.3-V LVTTL : : 6 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6 : +VCCIO1 : N1 : power : : 3.3V : 1 : +GND : N2 : gnd : : : : +DRAM_DQ[19] : N3 : bidir : 3.3-V LVTTL : : 1 : Y +DRAM_DQ[20] : N4 : bidir : 3.3-V LVTTL : : 1 : Y +VCCIO1 : N5 : power : : 3.3V : 1 : +GND : N6 : gnd : : : : +~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP : N7 : input : 3.3-V LVTTL : : 1 : N +DRAM_DQM[3] : N8 : output : 3.3-V LVTTL : : 1 : Y +GND : N9 : gnd : : : : +VCCINT : N10 : power : : 1.2V : : +GND : N11 : gnd : : : : +VCCINT : N12 : power : : 1.2V : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +GND : N15 : gnd : : : : +VCCINT : N16 : power : : 1.2V : : +GND : N17 : gnd : : : : +VCCINT : N18 : power : : 1.2V : : +GND : N19 : gnd : : : : +VCCINT : N20 : power : : 1.2V : : +KEY[2] : N21 : input : 3.3-V LVTTL : : 6 : Y +MSEL0 : N22 : : : : 6 : +GND : N23 : gnd : : : : +VCCIO6 : N24 : power : : 3.3V : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : N26 : : : : 6 : +GND : N27 : gnd : : : : +VCCIO6 : N28 : power : : 3.3V : 6 : +DRAM_ADDR[3] : P1 : output : 3.3-V LVTTL : : 1 : Y +DRAM_DQ[18] : P2 : bidir : 3.3-V LVTTL : : 1 : Y +~ALTERA_DCLK~ : P3 : output : 3.3-V LVTTL : : 1 : N +nCONFIG : P4 : : : : 1 : +TCK : P5 : input : : : 1 : +TDO : P6 : output : : : 1 : +TDI : P7 : input : : : 1 : +TMS : P8 : input : : : 1 : +VCCINT : P9 : power : : 1.2V : : +GND : P10 : gnd : : : : +VCCINT : P11 : power : : 1.2V : : +GND : P12 : gnd : : : : +VCCINT : P13 : power : : 1.2V : : +GND : P14 : gnd : : : : +VCCINT : P15 : power : : 1.2V : : +GND : P16 : gnd : : : : +VCCINT : P17 : power : : 1.2V : : +GND : P18 : gnd : : : : +VCCINT : P19 : power : : 1.2V : : +GND : P20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : P21 : : : : 5 : +MSEL3 : P22 : : : : 6 : +MSEL1 : P23 : : : : 6 : +CONF_DONE : P24 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6 : +RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6 : +~ALTERA_nCEO~ / RESERVED_OUTPUT_OPEN_DRAIN : P28 : output : 3.3-V LVTTL : : 6 : N +DRAM_DQ[26] : R1 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[27] : R2 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[28] : R3 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_BA[1] : R4 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[10] : R5 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[0] : R6 : output : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[25] : R7 : bidir : 3.3-V LVTTL : : 2 : Y +nCE : R8 : : : : 1 : +GND : R9 : gnd : : : : +VCCINT : R10 : power : : 1.2V : : +GND : R11 : gnd : : : : +VCCINT : R12 : power : : 1.2V : : +GND : R13 : gnd : : : : +VCCINT : R14 : power : : 1.2V : : +GND : R15 : gnd : : : : +VCCINT : R16 : power : : 1.2V : : +GND : R17 : gnd : : : : +VCCINT : R18 : power : : 1.2V : : +GND : R19 : gnd : : : : +VCCINT : R20 : power : : 1.2V : : +RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R23 : : : : 5 : +KEY[3] : R24 : input : 3.3-V LVTTL : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : R25 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 5 : +VCCIO2 : T1 : power : : 3.3V : 2 : +GND : T2 : gnd : : : : +DRAM_DQ[29] : T3 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_CS_N : T4 : output : 3.3-V LVTTL : : 2 : Y +VCCIO2 : T5 : power : : 3.3V : 2 : +GND : T6 : gnd : : : : +SRAM_ADDR[9] : T7 : output : 3.3-V LVTTL : : 2 : Y +SRAM_ADDR[19] : T8 : output : 3.3-V LVTTL : : 2 : Y +VCCINT : T9 : power : : 1.2V : : +GND : T10 : gnd : : : : +VCCINT : T11 : power : : 1.2V : : +GND : T12 : gnd : : : : +VCCINT : T13 : power : : 1.2V : : +GND : T14 : gnd : : : : +VCCINT : T15 : power : : 1.2V : : +GND : T16 : gnd : : : : +VCCINT : T17 : power : : 1.2V : : +GND : T18 : gnd : : : : +VCCINT : T19 : power : : 1.2V : : +GND : T20 : gnd : : : : +RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T22 : : : : 5 : +GND : T23 : gnd : : : : +VCCIO5 : T24 : power : : 3.3V : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 5 : +GND : T27 : gnd : : : : +VCCIO5 : T28 : power : : 3.3V : 5 : +DRAM_DQ[31] : U1 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQM[0] : U2 : output : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[7] : U3 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[30] : U4 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[24] : U5 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_RAS_N : U6 : output : 3.3-V LVTTL : : 2 : Y +DRAM_BA[0] : U7 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[2] : U8 : output : 3.3-V LVTTL : : 2 : Y +GND : U9 : gnd : : : : +VCCINT : U10 : power : : 1.2V : : +GND : U11 : gnd : : : : +VCCINT : U12 : power : : 1.2V : : +GND : U13 : gnd : : : : +VCCINT : U14 : power : : 1.2V : : +GND : U15 : gnd : : : : +VCCINT : U16 : power : : 1.2V : : +GND : U17 : gnd : : : : +VCCINT : U18 : power : : 1.2V : : +GND : U19 : gnd : : : : +VCCINT : U20 : power : : 1.2V : : +HEX3[1] : U21 : output : 3.3-V LVTTL : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : U22 : : : : 5 : +HEX1[5] : U23 : output : 3.3-V LVTTL : : 5 : Y +HEX1[6] : U24 : output : 3.3-V LVTTL : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 5 : +DRAM_DQ[6] : V1 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[5] : V2 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[4] : V3 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[2] : V4 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[4] : V5 : output : 3.3-V LVTTL : : 2 : Y +DRAM_WE_N : V6 : output : 3.3-V LVTTL : : 2 : Y +DRAM_CAS_N : V7 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[1] : V8 : output : 3.3-V LVTTL : : 2 : Y +VCCINT : V9 : power : : 1.2V : : +GND : V10 : gnd : : : : +VCCINT : V11 : power : : 1.2V : : +GND : V12 : gnd : : : : +VCCINT : V13 : power : : 1.2V : : +GND : V14 : gnd : : : : +VCCINT : V15 : power : : 1.2V : : +GND : V16 : gnd : : : : +VCCINT : V17 : power : : 1.2V : : +GND : V18 : gnd : : : : +VCCINT : V19 : power : : 1.2V : : +GND : V20 : gnd : : : : +HEX3[0] : V21 : output : 3.3-V LVTTL : : 5 : Y +RESERVED_INPUT_WITH_WEAK_PULLUP : V22 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V24 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V26 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 5 : +RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 5 : +DRAM_DQ[3] : W1 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[1] : W2 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[0] : W3 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQM[1] : W4 : output : 3.3-V LVTTL : : 2 : Y +VCCIO2 : W5 : power : : 3.3V : 2 : +GND : W6 : gnd : : : : +DRAM_ADDR[6] : W7 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[5] : W8 : output : 3.3-V LVTTL : : 2 : Y +GND : W9 : gnd : : : : +VCCINT : W10 : power : : 1.2V : : +GND : W11 : gnd : : : : +VCCINT : W12 : power : : 1.2V : : +GND : W13 : gnd : : : : +VCCINT : W14 : power : : 1.2V : : +GND : W15 : gnd : : : : +VCCINT : W16 : power : : 1.2V : : +GND : W17 : gnd : : : : +VCCINT : W18 : power : : 1.2V : : +GND : W19 : gnd : : : : +VCCINT : W20 : power : : 1.2V : : +HEX1[2] : W21 : output : 3.3-V LVTTL : : 5 : Y +HEX1[3] : W22 : output : 3.3-V LVTTL : : 5 : Y +GND : W23 : gnd : : : : +VCCIO5 : W24 : power : : 3.3V : 5 : +HEX1[4] : W25 : output : 3.3-V LVTTL : : 5 : Y +HEX2[3] : W26 : output : 3.3-V LVTTL : : 5 : Y +HEX2[5] : W27 : output : 3.3-V LVTTL : : 5 : Y +HEX2[6] : W28 : output : 3.3-V LVTTL : : 5 : Y +FL_RY : Y1 : input : 3.3-V LVTTL : : 2 : Y +CLOCK_50 : Y2 : input : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[8] : Y3 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_DQ[9] : Y4 : bidir : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[8] : Y5 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[9] : Y6 : output : 3.3-V LVTTL : : 2 : Y +DRAM_ADDR[12] : Y7 : output : 3.3-V LVTTL : : 2 : Y +VCCA1 : Y8 : power : : 2.5V : : +VCCD_PLL1 : Y9 : power : : 1.2V : : +FL_ADDR[15] : Y10 : output : 3.3-V LVTTL : : 3 : Y +GND : Y11 : gnd : : : : +FL_ADDR[4] : Y12 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[2] : Y13 : output : 3.3-V LVTTL : : 3 : Y +FL_ADDR[3] : Y14 : output : 3.3-V LVTTL : : 3 : Y +IRDA_RXD : Y15 : input : 3.3-V LVTTL : : 3 : Y +GPIO[5] : Y16 : bidir : 3.3-V LVTTL : : 4 : Y +GPIO[3] : Y17 : bidir : 3.3-V LVTTL : : 4 : Y +GND : Y18 : gnd : : : : +HEX3[6] : Y19 : output : 3.3-V LVTTL : : 4 : Y +VCCD_PLL4 : Y20 : power : : 1.2V : : +VCCA4 : Y21 : power : : 2.5V : : +HEX1[1] : Y22 : output : 3.3-V LVTTL : : 5 : Y +SW[17] : Y23 : input : 3.3-V LVTTL : : 5 : Y +SW[16] : Y24 : input : 3.3-V LVTTL : : 5 : Y +HEX2[2] : Y25 : output : 3.3-V LVTTL : : 5 : Y +HEX2[4] : Y26 : output : 3.3-V LVTTL : : 5 : Y +GND+ : Y27 : : : : 5 : +GND+ : Y28 : : : : 5 : diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v4.qpf b/examples/hdl4se_riscv/de2/de2_riscv_v4.qpf new file mode 100644 index 0000000000000000000000000000000000000000..c5e8c77aa98aeca4f0aa903571c50db0b4765aa4 --- /dev/null +++ b/examples/hdl4se_riscv/de2/de2_riscv_v4.qpf @@ -0,0 +1,6 @@ +DATE = "19:51:38 September 01, 2021" +QUARTUS_VERSION = "12.0" + +# Revisions + +PROJECT_REVISION = "de2_riscv_v4" diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v4.qsf b/examples/hdl4se_riscv/de2/de2_riscv_v4.qsf new file mode 100644 index 0000000000000000000000000000000000000000..d50127a272f7f798a5c300e96cc851115c7a535a --- /dev/null +++ b/examples/hdl4se_riscv/de2/de2_riscv_v4.qsf @@ -0,0 +1,1013 @@ +#============================================================ +# Build by Terasic System Builder +#============================================================ + +set_global_assignment -name FAMILY "Cyclone IV E" +set_global_assignment -name DEVICE EP4CE115F29C7 +set_global_assignment -name TOP_LEVEL_ENTITY "de2_riscv_v4" +set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.0" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:51:38 SEPTEMBER 01,2021" +set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 780 +set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 7 +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" + +#============================================================ +# CLOCK +#============================================================ +set_location_assignment PIN_Y2 -to CLOCK_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 +set_location_assignment PIN_AG14 -to CLOCK2_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK2_50 +set_location_assignment PIN_AG15 -to CLOCK3_50 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK3_50 + +#============================================================ +# Sma +#============================================================ +set_location_assignment PIN_AH14 -to SMA_CLKIN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKIN +set_location_assignment PIN_AE23 -to SMA_CLKOUT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SMA_CLKOUT + +#============================================================ +# LED +#============================================================ +set_location_assignment PIN_G19 -to LEDR[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[0] +set_location_assignment PIN_F19 -to LEDR[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[1] +set_location_assignment PIN_E19 -to LEDR[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[2] +set_location_assignment PIN_F21 -to LEDR[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[3] +set_location_assignment PIN_F18 -to LEDR[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[4] +set_location_assignment PIN_E18 -to LEDR[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[5] +set_location_assignment PIN_J19 -to LEDR[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[6] +set_location_assignment PIN_H19 -to LEDR[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[7] +set_location_assignment PIN_J17 -to LEDR[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[8] +set_location_assignment PIN_G17 -to LEDR[9] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[9] +set_location_assignment PIN_J15 -to LEDR[10] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[10] +set_location_assignment PIN_H16 -to LEDR[11] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[11] +set_location_assignment PIN_J16 -to LEDR[12] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[12] +set_location_assignment PIN_H17 -to LEDR[13] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[13] +set_location_assignment PIN_F15 -to LEDR[14] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[14] +set_location_assignment PIN_G15 -to LEDR[15] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[15] +set_location_assignment PIN_G16 -to LEDR[16] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[16] +set_location_assignment PIN_H15 -to LEDR[17] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDR[17] +set_location_assignment PIN_E21 -to LEDG[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[0] +set_location_assignment PIN_E22 -to LEDG[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[1] +set_location_assignment PIN_E25 -to LEDG[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[2] +set_location_assignment PIN_E24 -to LEDG[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[3] +set_location_assignment PIN_H21 -to LEDG[4] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[4] +set_location_assignment PIN_G20 -to LEDG[5] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[5] +set_location_assignment PIN_G22 -to LEDG[6] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[6] +set_location_assignment PIN_G21 -to LEDG[7] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[7] +set_location_assignment PIN_F17 -to LEDG[8] +set_instance_assignment -name IO_STANDARD "2.5 V" -to LEDG[8] + +#============================================================ +# KEY +#============================================================ +set_location_assignment PIN_M23 -to KEY[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] +set_location_assignment PIN_M21 -to KEY[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] +set_location_assignment PIN_N21 -to KEY[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[2] +set_location_assignment PIN_R24 -to KEY[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[3] + +#============================================================ +# EX_IO +#============================================================ +set_location_assignment PIN_J10 -to EX_IO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[0] +set_location_assignment PIN_J14 -to EX_IO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[1] +set_location_assignment PIN_H13 -to EX_IO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[2] +set_location_assignment PIN_H14 -to EX_IO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[3] +set_location_assignment PIN_F14 -to EX_IO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[4] +set_location_assignment PIN_E10 -to EX_IO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[5] +set_location_assignment PIN_D9 -to EX_IO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EX_IO[6] + +#============================================================ +# SW +#============================================================ +set_location_assignment PIN_AB28 -to SW[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0] +set_location_assignment PIN_AC28 -to SW[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1] +set_location_assignment PIN_AC27 -to SW[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2] +set_location_assignment PIN_AD27 -to SW[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3] +set_location_assignment PIN_AB27 -to SW[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[4] +set_location_assignment PIN_AC26 -to SW[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[5] +set_location_assignment PIN_AD26 -to SW[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[6] +set_location_assignment PIN_AB26 -to SW[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[7] +set_location_assignment PIN_AC25 -to SW[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[8] +set_location_assignment PIN_AB25 -to SW[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[9] +set_location_assignment PIN_AC24 -to SW[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[10] +set_location_assignment PIN_AB24 -to SW[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[11] +set_location_assignment PIN_AB23 -to SW[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[12] +set_location_assignment PIN_AA24 -to SW[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[13] +set_location_assignment PIN_AA23 -to SW[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[14] +set_location_assignment PIN_AA22 -to SW[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[15] +set_location_assignment PIN_Y24 -to SW[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[16] +set_location_assignment PIN_Y23 -to SW[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[17] + +#============================================================ +# SEG7 +#============================================================ +set_location_assignment PIN_G18 -to HEX0[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[0] +set_location_assignment PIN_F22 -to HEX0[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[1] +set_location_assignment PIN_E17 -to HEX0[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to HEX0[2] +set_location_assignment PIN_L26 -to HEX0[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[3] +set_location_assignment PIN_L25 -to HEX0[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[4] +set_location_assignment PIN_J22 -to HEX0[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[5] +set_location_assignment PIN_H22 -to HEX0[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX0[6] +set_location_assignment PIN_M24 -to HEX1[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[0] +set_location_assignment PIN_Y22 -to HEX1[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[1] +set_location_assignment PIN_W21 -to HEX1[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[2] +set_location_assignment PIN_W22 -to HEX1[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[3] +set_location_assignment PIN_W25 -to HEX1[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[4] +set_location_assignment PIN_U23 -to HEX1[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[5] +set_location_assignment PIN_U24 -to HEX1[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX1[6] +set_location_assignment PIN_AA25 -to HEX2[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[0] +set_location_assignment PIN_AA26 -to HEX2[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[1] +set_location_assignment PIN_Y25 -to HEX2[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[2] +set_location_assignment PIN_W26 -to HEX2[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[3] +set_location_assignment PIN_Y26 -to HEX2[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[4] +set_location_assignment PIN_W27 -to HEX2[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[5] +set_location_assignment PIN_W28 -to HEX2[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX2[6] +set_location_assignment PIN_V21 -to HEX3[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[0] +set_location_assignment PIN_U21 -to HEX3[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[1] +set_location_assignment PIN_AB20 -to HEX3[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[2] +set_location_assignment PIN_AA21 -to HEX3[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[3] +set_location_assignment PIN_AD24 -to HEX3[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[4] +set_location_assignment PIN_AF23 -to HEX3[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[5] +set_location_assignment PIN_Y19 -to HEX3[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX3[6] +set_location_assignment PIN_AB19 -to HEX4[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[0] +set_location_assignment PIN_AA19 -to HEX4[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[1] +set_location_assignment PIN_AG21 -to HEX4[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[2] +set_location_assignment PIN_AH21 -to HEX4[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[3] +set_location_assignment PIN_AE19 -to HEX4[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[4] +set_location_assignment PIN_AF19 -to HEX4[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[5] +set_location_assignment PIN_AE18 -to HEX4[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX4[6] +set_location_assignment PIN_AD18 -to HEX5[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[0] +set_location_assignment PIN_AC18 -to HEX5[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[1] +set_location_assignment PIN_AB18 -to HEX5[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[2] +set_location_assignment PIN_AH19 -to HEX5[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[3] +set_location_assignment PIN_AG19 -to HEX5[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[4] +set_location_assignment PIN_AF18 -to HEX5[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[5] +set_location_assignment PIN_AH18 -to HEX5[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX5[6] +set_location_assignment PIN_AA17 -to HEX6[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[0] +set_location_assignment PIN_AB16 -to HEX6[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[1] +set_location_assignment PIN_AA16 -to HEX6[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[2] +set_location_assignment PIN_AB17 -to HEX6[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[3] +set_location_assignment PIN_AB15 -to HEX6[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[4] +set_location_assignment PIN_AA15 -to HEX6[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[5] +set_location_assignment PIN_AC17 -to HEX6[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX6[6] +set_location_assignment PIN_AD17 -to HEX7[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[0] +set_location_assignment PIN_AE17 -to HEX7[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[1] +set_location_assignment PIN_AG17 -to HEX7[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[2] +set_location_assignment PIN_AH17 -to HEX7[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[3] +set_location_assignment PIN_AF17 -to HEX7[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[4] +set_location_assignment PIN_AG18 -to HEX7[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[5] +set_location_assignment PIN_AA14 -to HEX7[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HEX7[6] + +#============================================================ +# LCD +#============================================================ +set_location_assignment PIN_L3 -to LCD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[0] +set_location_assignment PIN_L1 -to LCD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[1] +set_location_assignment PIN_L2 -to LCD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[2] +set_location_assignment PIN_K7 -to LCD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[3] +set_location_assignment PIN_K1 -to LCD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[4] +set_location_assignment PIN_K2 -to LCD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[5] +set_location_assignment PIN_M3 -to LCD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[6] +set_location_assignment PIN_M5 -to LCD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_DATA[7] +set_location_assignment PIN_L6 -to LCD_BLON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_BLON +set_location_assignment PIN_M1 -to LCD_RW +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RW +set_location_assignment PIN_L4 -to LCD_EN +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_EN +set_location_assignment PIN_M2 -to LCD_RS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_RS +set_location_assignment PIN_L5 -to LCD_ON +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LCD_ON + +#============================================================ +# RS232 +#============================================================ +set_location_assignment PIN_G9 -to UART_TXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_TXD +set_location_assignment PIN_G12 -to UART_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RXD +set_location_assignment PIN_G14 -to UART_RTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_RTS +set_location_assignment PIN_J13 -to UART_CTS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to UART_CTS + +#============================================================ +# PS2 for Keyboard and Mouse +#============================================================ +set_location_assignment PIN_G6 -to PS2_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK +set_location_assignment PIN_H5 -to PS2_DAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT +set_location_assignment PIN_G5 -to PS2_CLK2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_CLK2 +set_location_assignment PIN_F5 -to PS2_DAT2 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to PS2_DAT2 + +#============================================================ +# SDCARD +#============================================================ +set_location_assignment PIN_AD14 -to SD_CMD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CMD +set_location_assignment PIN_AE13 -to SD_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_CLK +set_location_assignment PIN_AF14 -to SD_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_WP_N +set_location_assignment PIN_AE14 -to SD_DAT[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[0] +set_location_assignment PIN_AF13 -to SD_DAT[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[1] +set_location_assignment PIN_AB14 -to SD_DAT[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[2] +set_location_assignment PIN_AC14 -to SD_DAT[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SD_DAT[3] + +#============================================================ +# VGA +#============================================================ +set_location_assignment PIN_G13 -to VGA_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_HS +set_location_assignment PIN_C13 -to VGA_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_VS +set_location_assignment PIN_C10 -to VGA_SYNC_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_SYNC_N +set_location_assignment PIN_A12 -to VGA_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_CLK +set_location_assignment PIN_F11 -to VGA_BLANK_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_BLANK_N +set_location_assignment PIN_E12 -to VGA_R[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[0] +set_location_assignment PIN_E11 -to VGA_R[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[1] +set_location_assignment PIN_D10 -to VGA_R[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[2] +set_location_assignment PIN_F12 -to VGA_R[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[3] +set_location_assignment PIN_G10 -to VGA_R[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[4] +set_location_assignment PIN_J12 -to VGA_R[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[5] +set_location_assignment PIN_H8 -to VGA_R[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[6] +set_location_assignment PIN_H10 -to VGA_R[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_R[7] +set_location_assignment PIN_G8 -to VGA_G[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[0] +set_location_assignment PIN_G11 -to VGA_G[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[1] +set_location_assignment PIN_F8 -to VGA_G[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[2] +set_location_assignment PIN_H12 -to VGA_G[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[3] +set_location_assignment PIN_C8 -to VGA_G[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[4] +set_location_assignment PIN_B8 -to VGA_G[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[5] +set_location_assignment PIN_F10 -to VGA_G[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[6] +set_location_assignment PIN_C9 -to VGA_G[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_G[7] +set_location_assignment PIN_B10 -to VGA_B[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[0] +set_location_assignment PIN_A10 -to VGA_B[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[1] +set_location_assignment PIN_C11 -to VGA_B[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[2] +set_location_assignment PIN_B11 -to VGA_B[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[3] +set_location_assignment PIN_A11 -to VGA_B[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[4] +set_location_assignment PIN_C12 -to VGA_B[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[5] +set_location_assignment PIN_D11 -to VGA_B[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[6] +set_location_assignment PIN_D12 -to VGA_B[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to VGA_B[7] + +#============================================================ +# Audio +#============================================================ +set_location_assignment PIN_C2 -to AUD_ADCLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCLRCK +set_location_assignment PIN_D2 -to AUD_ADCDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_ADCDAT +set_location_assignment PIN_E3 -to AUD_DACLRCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACLRCK +set_location_assignment PIN_D1 -to AUD_DACDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_DACDAT +set_location_assignment PIN_E1 -to AUD_XCK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_XCK +set_location_assignment PIN_F2 -to AUD_BCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to AUD_BCLK + +#============================================================ +# I2C for EEPROM +#============================================================ +set_location_assignment PIN_D14 -to EEP_I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SCLK +set_location_assignment PIN_E14 -to EEP_I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to EEP_I2C_SDAT + +#============================================================ +# I2C for Audio Tv-Decoder +#============================================================ +set_location_assignment PIN_B7 -to I2C_SCLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SCLK +set_location_assignment PIN_A8 -to I2C_SDAT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to I2C_SDAT + +#============================================================ +# Ethernet 0 +#============================================================ +set_location_assignment PIN_A14 -to ENETCLK_25 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENETCLK_25 +set_location_assignment PIN_C18 -to ENET0_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[0] +set_location_assignment PIN_C16 -to ENET0_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[0] +set_location_assignment PIN_D19 -to ENET0_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[1] +set_location_assignment PIN_D16 -to ENET0_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[1] +set_location_assignment PIN_A19 -to ENET0_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[2] +set_location_assignment PIN_D17 -to ENET0_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[2] +set_location_assignment PIN_B19 -to ENET0_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_DATA[3] +set_location_assignment PIN_C15 -to ENET0_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DATA[3] +set_location_assignment PIN_A17 -to ENET0_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_GTX_CLK +set_location_assignment PIN_A18 -to ENET0_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_EN +set_location_assignment PIN_B18 -to ENET0_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_ER +set_location_assignment PIN_A21 -to ENET0_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_INT_N +set_location_assignment PIN_C19 -to ENET0_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RST_N +set_location_assignment PIN_C17 -to ENET0_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_DV +set_location_assignment PIN_D18 -to ENET0_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_ER +set_location_assignment PIN_D15 -to ENET0_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CRS +set_location_assignment PIN_E15 -to ENET0_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_COL +set_location_assignment PIN_A15 -to ENET0_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_RX_CLK +set_location_assignment PIN_B17 -to ENET0_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_TX_CLK +set_location_assignment PIN_C20 -to ENET0_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDC +set_location_assignment PIN_B21 -to ENET0_MDIO +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET0_MDIO +set_location_assignment PIN_C14 -to ENET0_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET0_LINK100 + +#============================================================ +# Ethernet 1 +#============================================================ +set_location_assignment PIN_C25 -to ENET1_TX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[0] +set_location_assignment PIN_B23 -to ENET1_RX_DATA[0] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[0] +set_location_assignment PIN_A26 -to ENET1_TX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[1] +set_location_assignment PIN_C21 -to ENET1_RX_DATA[1] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[1] +set_location_assignment PIN_B26 -to ENET1_TX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[2] +set_location_assignment PIN_A23 -to ENET1_RX_DATA[2] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[2] +set_location_assignment PIN_C26 -to ENET1_TX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_DATA[3] +set_location_assignment PIN_D21 -to ENET1_RX_DATA[3] +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DATA[3] +set_location_assignment PIN_C23 -to ENET1_GTX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_GTX_CLK +set_location_assignment PIN_B25 -to ENET1_TX_EN +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_EN +set_location_assignment PIN_A25 -to ENET1_TX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_ER +set_location_assignment PIN_D24 -to ENET1_INT_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_INT_N +set_location_assignment PIN_D22 -to ENET1_RST_N +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RST_N +set_location_assignment PIN_A22 -to ENET1_RX_DV +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_DV +set_location_assignment PIN_C24 -to ENET1_RX_ER +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_ER +set_location_assignment PIN_D20 -to ENET1_RX_CRS +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CRS +set_location_assignment PIN_B22 -to ENET1_RX_COL +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_COL +set_location_assignment PIN_B15 -to ENET1_RX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_RX_CLK +set_location_assignment PIN_C22 -to ENET1_TX_CLK +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_TX_CLK +set_location_assignment PIN_D23 -to ENET1_MDC +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDC +set_location_assignment PIN_D25 -to ENET1_MDIO +set_instance_assignment -name IO_STANDARD "2.5 V" -to ENET1_MDIO +set_location_assignment PIN_D13 -to ENET1_LINK100 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to ENET1_LINK100 + +#============================================================ +# TV Decoder +#============================================================ +set_location_assignment PIN_E5 -to TD_HS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_HS +set_location_assignment PIN_E4 -to TD_VS +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_VS +set_location_assignment PIN_B14 -to TD_CLK27 +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_CLK27 +set_location_assignment PIN_G7 -to TD_RESET_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_RESET_N +set_location_assignment PIN_E8 -to TD_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[0] +set_location_assignment PIN_A7 -to TD_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[1] +set_location_assignment PIN_D8 -to TD_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[2] +set_location_assignment PIN_C7 -to TD_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[3] +set_location_assignment PIN_D7 -to TD_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[4] +set_location_assignment PIN_D6 -to TD_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[5] +set_location_assignment PIN_E7 -to TD_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[6] +set_location_assignment PIN_F7 -to TD_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to TD_DATA[7] + +#============================================================ +# USB 2.0 OTG (Cypress CY7C67200) +#============================================================ +set_location_assignment PIN_J6 -to OTG_DATA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[0] +set_location_assignment PIN_K4 -to OTG_DATA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[1] +set_location_assignment PIN_J5 -to OTG_DATA[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[2] +set_location_assignment PIN_K3 -to OTG_DATA[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[3] +set_location_assignment PIN_J4 -to OTG_DATA[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[4] +set_location_assignment PIN_J3 -to OTG_DATA[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[5] +set_location_assignment PIN_J7 -to OTG_DATA[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[6] +set_location_assignment PIN_H6 -to OTG_DATA[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[7] +set_location_assignment PIN_H3 -to OTG_DATA[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[8] +set_location_assignment PIN_H4 -to OTG_DATA[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[9] +set_location_assignment PIN_G1 -to OTG_DATA[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[10] +set_location_assignment PIN_G2 -to OTG_DATA[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[11] +set_location_assignment PIN_G3 -to OTG_DATA[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[12] +set_location_assignment PIN_F1 -to OTG_DATA[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[13] +set_location_assignment PIN_F3 -to OTG_DATA[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[14] +set_location_assignment PIN_G4 -to OTG_DATA[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_DATA[15] +set_location_assignment PIN_H7 -to OTG_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[0] +set_location_assignment PIN_C3 -to OTG_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_ADDR[1] +set_location_assignment PIN_D5 -to OTG_INT +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_INT +set_location_assignment PIN_C5 -to OTG_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RST_N +set_location_assignment PIN_A3 -to OTG_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_CS_N +set_location_assignment PIN_B3 -to OTG_RD_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_RD_N +set_location_assignment PIN_A4 -to OTG_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to OTG_WE_N + +#============================================================ +# IR Receiver +#============================================================ +set_location_assignment PIN_Y15 -to IRDA_RXD +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to IRDA_RXD + +#============================================================ +# SDRAM +#============================================================ +set_location_assignment PIN_U7 -to DRAM_BA[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] +set_location_assignment PIN_R4 -to DRAM_BA[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] +set_location_assignment PIN_U2 -to DRAM_DQM[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] +set_location_assignment PIN_W4 -to DRAM_DQM[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] +set_location_assignment PIN_K8 -to DRAM_DQM[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[2] +set_location_assignment PIN_N8 -to DRAM_DQM[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[3] +set_location_assignment PIN_U6 -to DRAM_RAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N +set_location_assignment PIN_V7 -to DRAM_CAS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N +set_location_assignment PIN_AA6 -to DRAM_CKE +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE +set_location_assignment PIN_AE5 -to DRAM_CLK +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK +set_location_assignment PIN_V6 -to DRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N +set_location_assignment PIN_T4 -to DRAM_CS_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N +set_location_assignment PIN_W3 -to DRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] +set_location_assignment PIN_W2 -to DRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] +set_location_assignment PIN_V4 -to DRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] +set_location_assignment PIN_W1 -to DRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] +set_location_assignment PIN_V3 -to DRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] +set_location_assignment PIN_V2 -to DRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] +set_location_assignment PIN_V1 -to DRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] +set_location_assignment PIN_U3 -to DRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] +set_location_assignment PIN_Y3 -to DRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] +set_location_assignment PIN_Y4 -to DRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] +set_location_assignment PIN_AB1 -to DRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] +set_location_assignment PIN_AA3 -to DRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] +set_location_assignment PIN_AB2 -to DRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] +set_location_assignment PIN_AC1 -to DRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] +set_location_assignment PIN_AB3 -to DRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] +set_location_assignment PIN_AC2 -to DRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] +set_location_assignment PIN_M8 -to DRAM_DQ[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[16] +set_location_assignment PIN_L8 -to DRAM_DQ[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[17] +set_location_assignment PIN_P2 -to DRAM_DQ[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[18] +set_location_assignment PIN_N3 -to DRAM_DQ[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[19] +set_location_assignment PIN_N4 -to DRAM_DQ[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[20] +set_location_assignment PIN_M4 -to DRAM_DQ[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[21] +set_location_assignment PIN_M7 -to DRAM_DQ[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[22] +set_location_assignment PIN_L7 -to DRAM_DQ[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[23] +set_location_assignment PIN_U5 -to DRAM_DQ[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[24] +set_location_assignment PIN_R7 -to DRAM_DQ[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[25] +set_location_assignment PIN_R1 -to DRAM_DQ[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[26] +set_location_assignment PIN_R2 -to DRAM_DQ[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[27] +set_location_assignment PIN_R3 -to DRAM_DQ[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[28] +set_location_assignment PIN_T3 -to DRAM_DQ[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[29] +set_location_assignment PIN_U4 -to DRAM_DQ[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[30] +set_location_assignment PIN_U1 -to DRAM_DQ[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[31] +set_location_assignment PIN_R6 -to DRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] +set_location_assignment PIN_V8 -to DRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] +set_location_assignment PIN_U8 -to DRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] +set_location_assignment PIN_P1 -to DRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] +set_location_assignment PIN_V5 -to DRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] +set_location_assignment PIN_W8 -to DRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] +set_location_assignment PIN_W7 -to DRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] +set_location_assignment PIN_AA7 -to DRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] +set_location_assignment PIN_Y5 -to DRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] +set_location_assignment PIN_Y6 -to DRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] +set_location_assignment PIN_R5 -to DRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] +set_location_assignment PIN_AA5 -to DRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] +set_location_assignment PIN_Y7 -to DRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] + +#============================================================ +# SRAM +#============================================================ +set_location_assignment PIN_AB7 -to SRAM_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[0] +set_location_assignment PIN_AD7 -to SRAM_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[1] +set_location_assignment PIN_AE7 -to SRAM_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[2] +set_location_assignment PIN_AC7 -to SRAM_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[3] +set_location_assignment PIN_AB6 -to SRAM_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[4] +set_location_assignment PIN_AE6 -to SRAM_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[5] +set_location_assignment PIN_AB5 -to SRAM_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[6] +set_location_assignment PIN_AC5 -to SRAM_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[7] +set_location_assignment PIN_AF5 -to SRAM_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[8] +set_location_assignment PIN_T7 -to SRAM_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[9] +set_location_assignment PIN_AF2 -to SRAM_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[10] +set_location_assignment PIN_AD3 -to SRAM_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[11] +set_location_assignment PIN_AB4 -to SRAM_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[12] +set_location_assignment PIN_AC3 -to SRAM_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[13] +set_location_assignment PIN_AA4 -to SRAM_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[14] +set_location_assignment PIN_AB11 -to SRAM_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[15] +set_location_assignment PIN_AC11 -to SRAM_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[16] +set_location_assignment PIN_AB9 -to SRAM_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[17] +set_location_assignment PIN_AB8 -to SRAM_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[18] +set_location_assignment PIN_T8 -to SRAM_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_ADDR[19] +set_location_assignment PIN_AH3 -to SRAM_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[0] +set_location_assignment PIN_AF4 -to SRAM_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[1] +set_location_assignment PIN_AG4 -to SRAM_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[2] +set_location_assignment PIN_AH4 -to SRAM_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[3] +set_location_assignment PIN_AF6 -to SRAM_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[4] +set_location_assignment PIN_AG6 -to SRAM_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[5] +set_location_assignment PIN_AH6 -to SRAM_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[6] +set_location_assignment PIN_AF7 -to SRAM_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[7] +set_location_assignment PIN_AD1 -to SRAM_DQ[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[8] +set_location_assignment PIN_AD2 -to SRAM_DQ[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[9] +set_location_assignment PIN_AE2 -to SRAM_DQ[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[10] +set_location_assignment PIN_AE1 -to SRAM_DQ[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[11] +set_location_assignment PIN_AE3 -to SRAM_DQ[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[12] +set_location_assignment PIN_AE4 -to SRAM_DQ[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[13] +set_location_assignment PIN_AF3 -to SRAM_DQ[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[14] +set_location_assignment PIN_AG3 -to SRAM_DQ[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_DQ[15] +set_location_assignment PIN_AC4 -to SRAM_UB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_UB_N +set_location_assignment PIN_AD4 -to SRAM_LB_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_LB_N +set_location_assignment PIN_AF8 -to SRAM_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_CE_N +set_location_assignment PIN_AD5 -to SRAM_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_OE_N +set_location_assignment PIN_AE8 -to SRAM_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SRAM_WE_N + +#============================================================ +# Flash +#============================================================ +set_location_assignment PIN_AG12 -to FL_ADDR[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[0] +set_location_assignment PIN_AH7 -to FL_ADDR[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[1] +set_location_assignment PIN_Y13 -to FL_ADDR[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[2] +set_location_assignment PIN_Y14 -to FL_ADDR[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[3] +set_location_assignment PIN_Y12 -to FL_ADDR[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[4] +set_location_assignment PIN_AA13 -to FL_ADDR[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[5] +set_location_assignment PIN_AA12 -to FL_ADDR[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[6] +set_location_assignment PIN_AB13 -to FL_ADDR[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[7] +set_location_assignment PIN_AB12 -to FL_ADDR[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[8] +set_location_assignment PIN_AB10 -to FL_ADDR[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[9] +set_location_assignment PIN_AE9 -to FL_ADDR[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[10] +set_location_assignment PIN_AF9 -to FL_ADDR[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[11] +set_location_assignment PIN_AA10 -to FL_ADDR[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[12] +set_location_assignment PIN_AD8 -to FL_ADDR[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[13] +set_location_assignment PIN_AC8 -to FL_ADDR[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[14] +set_location_assignment PIN_Y10 -to FL_ADDR[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[15] +set_location_assignment PIN_AA8 -to FL_ADDR[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[16] +set_location_assignment PIN_AH12 -to FL_ADDR[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[17] +set_location_assignment PIN_AC12 -to FL_ADDR[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[18] +set_location_assignment PIN_AD12 -to FL_ADDR[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[19] +set_location_assignment PIN_AE10 -to FL_ADDR[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[20] +set_location_assignment PIN_AD10 -to FL_ADDR[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[21] +set_location_assignment PIN_AD11 -to FL_ADDR[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_ADDR[22] +set_location_assignment PIN_AH8 -to FL_DQ[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[0] +set_location_assignment PIN_AF10 -to FL_DQ[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[1] +set_location_assignment PIN_AG10 -to FL_DQ[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[2] +set_location_assignment PIN_AH10 -to FL_DQ[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[3] +set_location_assignment PIN_AF11 -to FL_DQ[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[4] +set_location_assignment PIN_AG11 -to FL_DQ[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[5] +set_location_assignment PIN_AH11 -to FL_DQ[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[6] +set_location_assignment PIN_AF12 -to FL_DQ[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_DQ[7] +set_location_assignment PIN_AG7 -to FL_CE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_CE_N +set_location_assignment PIN_AG8 -to FL_OE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_OE_N +set_location_assignment PIN_AE11 -to FL_RST_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RST_N +set_location_assignment PIN_Y1 -to FL_RY +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_RY +set_location_assignment PIN_AC10 -to FL_WE_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WE_N +set_location_assignment PIN_AE12 -to FL_WP_N +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FL_WP_N + +#============================================================ +# GPIO, GPIO connect to GPIO Default +#============================================================ +set_location_assignment PIN_AB22 -to GPIO[0] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] +set_location_assignment PIN_AC15 -to GPIO[1] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] +set_location_assignment PIN_AB21 -to GPIO[2] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] +set_location_assignment PIN_Y17 -to GPIO[3] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] +set_location_assignment PIN_AC21 -to GPIO[4] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] +set_location_assignment PIN_Y16 -to GPIO[5] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] +set_location_assignment PIN_AD21 -to GPIO[6] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] +set_location_assignment PIN_AE16 -to GPIO[7] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] +set_location_assignment PIN_AD15 -to GPIO[8] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] +set_location_assignment PIN_AE15 -to GPIO[9] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] +set_location_assignment PIN_AC19 -to GPIO[10] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] +set_location_assignment PIN_AF16 -to GPIO[11] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] +set_location_assignment PIN_AD19 -to GPIO[12] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] +set_location_assignment PIN_AF15 -to GPIO[13] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] +set_location_assignment PIN_AF24 -to GPIO[14] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] +set_location_assignment PIN_AE21 -to GPIO[15] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] +set_location_assignment PIN_AF25 -to GPIO[16] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] +set_location_assignment PIN_AC22 -to GPIO[17] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] +set_location_assignment PIN_AE22 -to GPIO[18] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] +set_location_assignment PIN_AF21 -to GPIO[19] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] +set_location_assignment PIN_AF22 -to GPIO[20] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] +set_location_assignment PIN_AD22 -to GPIO[21] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] +set_location_assignment PIN_AG25 -to GPIO[22] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] +set_location_assignment PIN_AD25 -to GPIO[23] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] +set_location_assignment PIN_AH25 -to GPIO[24] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] +set_location_assignment PIN_AE25 -to GPIO[25] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] +set_location_assignment PIN_AG22 -to GPIO[26] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] +set_location_assignment PIN_AE24 -to GPIO[27] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] +set_location_assignment PIN_AH22 -to GPIO[28] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] +set_location_assignment PIN_AF26 -to GPIO[29] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] +set_location_assignment PIN_AE20 -to GPIO[30] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] +set_location_assignment PIN_AG23 -to GPIO[31] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] +set_location_assignment PIN_AF20 -to GPIO[32] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] +set_location_assignment PIN_AH26 -to GPIO[33] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] +set_location_assignment PIN_AH23 -to GPIO[34] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[34] +set_location_assignment PIN_AG26 -to GPIO[35] +set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[35] + +#============================================================ +# End of pin assignments by Terasic System Builder +#============================================================ + + +set_global_assignment -name VERILOG_FILE ../verilog/riscv_core_v4.v +set_global_assignment -name VERILOG_FILE ../verilog/altera/uart/uart_fifo.v +set_global_assignment -name VERILOG_FILE ../verilog/altera/uart/altera_uart.v +set_global_assignment -name VERILOG_FILE ../verilog/altera/ram/ram128kB.v +set_global_assignment -name VERILOG_FILE ../verilog/altera/ram/ram16kB.v +set_global_assignment -name VERILOG_FILE ../verilog/altera/ram/ram8kb.v +set_global_assignment -name VERILOG_FILE ../verilog/altera/alu/suber.v +set_global_assignment -name VERILOG_FILE ../verilog/altera/alu/mult_s.v +set_global_assignment -name VERILOG_FILE ../verilog/altera/alu/mult.v +set_global_assignment -name VERILOG_FILE ../verilog/altera/alu/mulsu.v +set_global_assignment -name VERILOG_FILE ../verilog/altera/alu/div_s.v +set_global_assignment -name VERILOG_FILE ../verilog/altera/alu/div.v +set_global_assignment -name VERILOG_FILE ../verilog/altera/alu/adder.v +set_global_assignment -name VERILOG_FILE ../verilog/uart/uart_ctrl.v +set_global_assignment -name VERILOG_FILE ../verilog/uart/hdl4se_uart.v +set_global_assignment -name VERILOG_FILE de2_riscv_v4.v +set_global_assignment -name SDC_FILE de2_riscv_v4.SDC +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v4.qws b/examples/hdl4se_riscv/de2/de2_riscv_v4.qws new file mode 100644 index 0000000000000000000000000000000000000000..63ba63c2d7679b7231492fa2836df27883046370 Binary files /dev/null and b/examples/hdl4se_riscv/de2/de2_riscv_v4.qws differ diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v4.sdc b/examples/hdl4se_riscv/de2/de2_riscv_v4.sdc new file mode 100644 index 0000000000000000000000000000000000000000..52e78c1da270664c61d8a0b09efd0132fe628f56 --- /dev/null +++ b/examples/hdl4se_riscv/de2/de2_riscv_v4.sdc @@ -0,0 +1,86 @@ +#************************************************************** +# This .sdc file is created by Terasic Tool. +# Users are recommended to modify this file to match users logic. +#************************************************************** + +#************************************************************** +# Create Clock +#************************************************************** +create_clock -period 20 [get_ports CLOCK_50] +create_clock -period 20 [get_ports CLOCK2_50] +create_clock -period 20 [get_ports CLOCK3_50] + +#************************************************************** +# Create Generated Clock +#************************************************************** +derive_pll_clocks + + + +#************************************************************** +# Set Clock Latency +#************************************************************** + + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** +derive_clock_uncertainty + + + +#************************************************************** +# Set Input Delay +#************************************************************** + + + +#************************************************************** +# Set Output Delay +#************************************************************** + + + +#************************************************************** +# Set Clock Groups +#************************************************************** + + + +#************************************************************** +# Set False Path +#************************************************************** + + + +#************************************************************** +# Set Multicycle Path +#************************************************************** + + + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** + + + +#************************************************************** +# Set Load +#************************************************************** + + + diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v3.sof b/examples/hdl4se_riscv/de2/de2_riscv_v4.sof similarity index 76% rename from examples/hdl4se_riscv/de2/de2_riscv_v3.sof rename to examples/hdl4se_riscv/de2/de2_riscv_v4.sof index 7ef92622e366978e5f64c26b867fb635096b61a5..129716af774b3b5cdf1a43947ccb82c504f5b5a4 100644 Binary files a/examples/hdl4se_riscv/de2/de2_riscv_v3.sof and b/examples/hdl4se_riscv/de2/de2_riscv_v4.sof differ diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v4.v b/examples/hdl4se_riscv/de2/de2_riscv_v4.v new file mode 100644 index 0000000000000000000000000000000000000000..63779234beca88acd28ebc89249806f16f362cc3 --- /dev/null +++ b/examples/hdl4se_riscv/de2/de2_riscv_v4.v @@ -0,0 +1,517 @@ + +//======================================================= +// This code is generated by Terasic System Builder +//======================================================= +`define USECLOCK50 + +module de2_riscv_v4( + + //////////// CLOCK ////////// + CLOCK_50, + CLOCK2_50, + CLOCK3_50, + + //////////// Sma ////////// + SMA_CLKIN, + SMA_CLKOUT, + + //////////// LED ////////// + LEDG, + LEDR, + + //////////// KEY ////////// + KEY, + + //////////// EX_IO ////////// + EX_IO, + + //////////// SW ////////// + SW, + + //////////// SEG7 ////////// + HEX0, + HEX1, + HEX2, + HEX3, + HEX4, + HEX5, + HEX6, + HEX7, + + //////////// LCD ////////// + LCD_BLON, + LCD_DATA, + LCD_EN, + LCD_ON, + LCD_RS, + LCD_RW, + + //////////// RS232 ////////// + UART_CTS, + UART_RTS, + UART_RXD, + UART_TXD, + + //////////// PS2 for Keyboard and Mouse ////////// + PS2_CLK, + PS2_CLK2, + PS2_DAT, + PS2_DAT2, + + //////////// SDCARD ////////// + SD_CLK, + SD_CMD, + SD_DAT, + SD_WP_N, + + //////////// VGA ////////// + VGA_B, + VGA_BLANK_N, + VGA_CLK, + VGA_G, + VGA_HS, + VGA_R, + VGA_SYNC_N, + VGA_VS, + + //////////// Audio ////////// + AUD_ADCDAT, + AUD_ADCLRCK, + AUD_BCLK, + AUD_DACDAT, + AUD_DACLRCK, + AUD_XCK, + + //////////// I2C for EEPROM ////////// + EEP_I2C_SCLK, + EEP_I2C_SDAT, + + //////////// I2C for Audio Tv-Decoder ////////// + I2C_SCLK, + I2C_SDAT, + + //////////// Ethernet 0 ////////// + ENET0_GTX_CLK, + ENET0_INT_N, + ENET0_LINK100, + ENET0_MDC, + ENET0_MDIO, + ENET0_RST_N, + ENET0_RX_CLK, + ENET0_RX_COL, + ENET0_RX_CRS, + ENET0_RX_DATA, + ENET0_RX_DV, + ENET0_RX_ER, + ENET0_TX_CLK, + ENET0_TX_DATA, + ENET0_TX_EN, + ENET0_TX_ER, + ENETCLK_25, + + //////////// Ethernet 1 ////////// + ENET1_GTX_CLK, + ENET1_INT_N, + ENET1_LINK100, + ENET1_MDC, + ENET1_MDIO, + ENET1_RST_N, + ENET1_RX_CLK, + ENET1_RX_COL, + ENET1_RX_CRS, + ENET1_RX_DATA, + ENET1_RX_DV, + ENET1_RX_ER, + ENET1_TX_CLK, + ENET1_TX_DATA, + ENET1_TX_EN, + ENET1_TX_ER, + + //////////// TV Decoder ////////// + TD_CLK27, + TD_DATA, + TD_HS, + TD_RESET_N, + TD_VS, + + //////////// USB 2.0 OTG (Cypress CY7C67200) ////////// + OTG_ADDR, + OTG_CS_N, + OTG_DATA, + OTG_INT, + OTG_RD_N, + OTG_RST_N, + OTG_WE_N, + + //////////// IR Receiver ////////// + IRDA_RXD, + + //////////// SDRAM ////////// + DRAM_ADDR, + DRAM_BA, + DRAM_CAS_N, + DRAM_CKE, + DRAM_CLK, + DRAM_CS_N, + DRAM_DQ, + DRAM_DQM, + DRAM_RAS_N, + DRAM_WE_N, + + //////////// SRAM ////////// + SRAM_ADDR, + SRAM_CE_N, + SRAM_DQ, + SRAM_LB_N, + SRAM_OE_N, + SRAM_UB_N, + SRAM_WE_N, + + //////////// Flash ////////// + FL_ADDR, + FL_CE_N, + FL_DQ, + FL_OE_N, + FL_RST_N, + FL_RY, + FL_WE_N, + FL_WP_N, + + //////////// GPIO, GPIO connect to GPIO Default ////////// + GPIO +); + +//======================================================= +// PARAMETER declarations +//======================================================= + + +//======================================================= +// PORT declarations +//======================================================= + +//////////// CLOCK ////////// +input CLOCK_50; +input CLOCK2_50; +input CLOCK3_50; + +//////////// Sma ////////// +input SMA_CLKIN; +output SMA_CLKOUT; + +//////////// LED ////////// +output [8:0] LEDG; +output [17:0] LEDR; + +//////////// KEY ////////// +input [3:0] KEY; + +//////////// EX_IO ////////// +inout [6:0] EX_IO; + +//////////// SW ////////// +input [17:0] SW; + +//////////// SEG7 ////////// +output [6:0] HEX0; +output [6:0] HEX1; +output [6:0] HEX2; +output [6:0] HEX3; +output [6:0] HEX4; +output [6:0] HEX5; +output [6:0] HEX6; +output [6:0] HEX7; + +//////////// LCD ////////// +output LCD_BLON; +inout [7:0] LCD_DATA; +output LCD_EN; +output LCD_ON; +output LCD_RS; +output LCD_RW; + +//////////// RS232 ////////// +input UART_CTS; +output UART_RTS; +input UART_RXD; +output UART_TXD; + +//////////// PS2 for Keyboard and Mouse ////////// +inout PS2_CLK; +inout PS2_CLK2; +inout PS2_DAT; +inout PS2_DAT2; + +//////////// SDCARD ////////// +output SD_CLK; +inout SD_CMD; +inout [3:0] SD_DAT; +input SD_WP_N; + +//////////// VGA ////////// +output [7:0] VGA_B; +output VGA_BLANK_N; +output VGA_CLK; +output [7:0] VGA_G; +output VGA_HS; +output [7:0] VGA_R; +output VGA_SYNC_N; +output VGA_VS; + +//////////// Audio ////////// +input AUD_ADCDAT; +inout AUD_ADCLRCK; +inout AUD_BCLK; +output AUD_DACDAT; +inout AUD_DACLRCK; +output AUD_XCK; + +//////////// I2C for EEPROM ////////// +output EEP_I2C_SCLK; +inout EEP_I2C_SDAT; + +//////////// I2C for Audio Tv-Decoder ////////// +output I2C_SCLK; +inout I2C_SDAT; + +//////////// Ethernet 0 ////////// +output ENET0_GTX_CLK; +input ENET0_INT_N; +input ENET0_LINK100; +output ENET0_MDC; +inout ENET0_MDIO; +output ENET0_RST_N; +input ENET0_RX_CLK; +input ENET0_RX_COL; +input ENET0_RX_CRS; +input [3:0] ENET0_RX_DATA; +input ENET0_RX_DV; +input ENET0_RX_ER; +input ENET0_TX_CLK; +output [3:0] ENET0_TX_DATA; +output ENET0_TX_EN; +output ENET0_TX_ER; +input ENETCLK_25; + +//////////// Ethernet 1 ////////// +output ENET1_GTX_CLK; +input ENET1_INT_N; +input ENET1_LINK100; +output ENET1_MDC; +inout ENET1_MDIO; +output ENET1_RST_N; +input ENET1_RX_CLK; +input ENET1_RX_COL; +input ENET1_RX_CRS; +input [3:0] ENET1_RX_DATA; +input ENET1_RX_DV; +input ENET1_RX_ER; +input ENET1_TX_CLK; +output [3:0] ENET1_TX_DATA; +output ENET1_TX_EN; +output ENET1_TX_ER; + +//////////// TV Decoder ////////// +input TD_CLK27; +input [7:0] TD_DATA; +input TD_HS; +output TD_RESET_N; +input TD_VS; + +//////////// USB 2.0 OTG (Cypress CY7C67200) ////////// +output [1:0] OTG_ADDR; +output OTG_CS_N; +inout [15:0] OTG_DATA; +input OTG_INT; +output OTG_RD_N; +output OTG_RST_N; +output OTG_WE_N; + +//////////// IR Receiver ////////// +input IRDA_RXD; + +//////////// SDRAM ////////// +output [12:0] DRAM_ADDR; +output [1:0] DRAM_BA; +output DRAM_CAS_N; +output DRAM_CKE; +output DRAM_CLK; +output DRAM_CS_N; +inout [31:0] DRAM_DQ; +output [3:0] DRAM_DQM; +output DRAM_RAS_N; +output DRAM_WE_N; + +//////////// SRAM ////////// +output [19:0] SRAM_ADDR; +output SRAM_CE_N; +inout [15:0] SRAM_DQ; +output SRAM_LB_N; +output SRAM_OE_N; +output SRAM_UB_N; +output SRAM_WE_N; + +//////////// Flash ////////// +output [22:0] FL_ADDR; +output FL_CE_N; +inout [7:0] FL_DQ; +output FL_OE_N; +output FL_RST_N; +input FL_RY; +output FL_WE_N; +output FL_WP_N; + +//////////// GPIO, GPIO connect to GPIO Default ////////// +inout [35:0] GPIO; + + + + wire uart_tx; + wire uart_rx; + assign GPIO[5] = uart_tx; + assign GPIO[7] = 1'bz; + assign uart_rx = GPIO[7]; + + assign LEDR[0] = uart_tx; + assign LEDR[1] = uart_rx; + +`ifdef USECLOCK50 + wire wClk = CLOCK_50; +`else + wire clk100MHz, clk75MHz, clklocked; + clk100M clk100(.refclk(CLOCK_50), + .rst(~KEY[3]), + .outclk_0(clk100MHz), + .outclk_1(clk75MHz), + .locked(clklocked)); + + wire wClk = clk100MHz; +`endif + wire nwReset = KEY[3]; + + wire wWrite, wRead; + wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey, bReadDataUart; + wire [3:0] bWriteMask; + + assign bReadDataKey = {18'b0, KEY, SW}; + + reg readcmd; + reg [31:0] readaddr; + + always @(posedge wClk) begin + if (!nwReset) begin + readcmd <= 1'b0; + readaddr <= 32'b0; + end else begin + readcmd <= wRead; + readaddr <= bReadAddr; + end + end + + assign bReadData = + ((readaddr & 32'hffffff00) == 32'hF0000000) ? bReadDataKey : ( + ((readaddr & 32'hff000000) == 32'h00000000) ? bReadDataRam : ( + ((readaddr & 32'hffffff00) == 32'hF0000100) ? bReadDataUart : (32'hffffffff) + ) + ); + + wire [29:0] ramaddr; + assign ramaddr = wWrite?bWriteAddr[31:2]:bReadAddr[31:2]; + + wire [4:0] regno; + wire [3:0] regena; + wire [31:0] regwrdata; + wire regwren; + wire [31:0] regrddata; + wire [4:0] regno2; + wire [3:0] regena2; + wire [31:0] regwrdata2; + wire regwren2; + wire [31:0] regrddata2; + + uart_ctrl uart_ctrl( + .wClk(wClk), + .nwReset(nwReset), + .wRead(((bReadAddr & 32'hffffff00) == 32'hf0000100)?wRead:1'b0), + .bReadAddr(bReadAddr), + .wWrite(((bWriteAddr & 32'hffffff00) == 32'hf0000100)?wWrite:1'b0), + .bWriteAddr(bWriteAddr), + .bWriteData(bWriteData), + .bReadData(bReadDataUart), + .uart_tx(uart_tx), + .uart_rx(uart_rx), + .dataready(LEDR[2]), + .sendready(LEDR[3]), + .sendfull(LEDR[4]), + .recvempty(LEDR[5]) + ); + ram16kB ram(ramaddr, ~bWriteMask, wClk, bWriteData, ((bWriteAddr & 32'hff000000) == 0)?wWrite:1'b0, bReadDataRam); + riscv_core core(wClk, nwReset, wWrite, bWriteAddr, bWriteData, bWriteMask, wRead, bReadAddr, bReadData + ); + + + +//======================================================= +// Structural coding +//======================================================= + + + reg [6:0] led0; + reg [6:0] led1; + reg [6:0] led2; + reg [6:0] led3; + reg [6:0] led4; + reg [6:0] led5; + reg [6:0] led6; + reg [6:0] led7; + assign HEX0 = ~led0; + assign HEX1 = ~led1; + assign HEX2 = ~led2; + assign HEX3 = ~led3; + assign HEX4 = ~led4; + assign HEX5 = ~led5; + assign HEX6 = ~led6; + assign HEX7 = ~led7; + + + + always @(posedge wClk) begin + if (!nwReset) begin + led0 <= 8'h3f; + led1 <= 8'h3f; + led2 <= 8'h3f; + led3 <= 8'h3f; + led4 <= 8'h3f; + led5 <= 8'h3f; + end else begin + if (SW[17]) begin + led0 <= 8'h06; + led1 <= 8'h06; + led2 <= 8'h06; + led3 <= 8'h07; + led4 <= 8'h07; + led5 <= 8'h07; + end + else if (SW[16]) begin + led0 <= 8'h3f; + led1 <= 8'h06; + led2 <= 8'h5b; + led3 <= 8'h4f; + led4 <= 8'h66; + led5 <= 8'h6d; + end + else if (wWrite && ((bWriteAddr & 32'hffffff00) == 32'hf0000000)) begin + if (bWriteAddr[7:0] == 8'h10) begin + led0 <= bWriteData[6:0]; + led1 <= bWriteData[14:8]; + led2 <= bWriteData[22:16]; + led3 <= bWriteData[30:24]; + end else if (bWriteAddr[7:0] == 8'h14) begin + led4 <= bWriteData[6:0]; + led5 <= bWriteData[14:8]; + end + end + end + end + +endmodule diff --git a/examples/hdl4se_riscv/de2/de2_riscv_v4_assignment_defaults.qdf b/examples/hdl4se_riscv/de2/de2_riscv_v4_assignment_defaults.qdf new file mode 100644 index 0000000000000000000000000000000000000000..68a5d815001adef6231ed3a5597205346d4e101d --- /dev/null +++ b/examples/hdl4se_riscv/de2/de2_riscv_v4_assignment_defaults.qdf @@ -0,0 +1,692 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.1.0 Build 162 10/23/2013 SJ Full Version +# Date created = 19:58:27 September 01, 2021 +# +# -------------------------------------------------------------------------- # +# +# Note: +# +# 1) Do not modify this file. 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"Stratix IV" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III" +set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V" +set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation" +set_global_assignment -name HDL_MESSAGE_LEVEL Level2 +set_global_assignment -name USE_HIGH_SPEED_ADDER Auto +set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000 +set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000 +set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100 +set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On +set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off +set_global_assignment -name BLOCK_DESIGN_NAMING Auto +set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off +set_global_assignment -name SYNTHESIS_EFFORT Auto +set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On +set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off +set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium +set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V" +set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX" +set_global_assignment -name MAX_LABS "-1 (Unlimited)" +set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On +set_global_assignment -name SYNTHESIS_SEED 1 +set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)" +set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On +set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off +set_global_assignment -name AUTO_MERGE_PLLS On +set_global_assignment -name IGNORE_MODE_FOR_MERGE Off +set_global_assignment -name TXPMA_SLEW_RATE Low +set_global_assignment -name ADCE_ENABLED Auto +set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal +set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0 +set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0 +set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off +set_global_assignment -name DEVICE AUTO +set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off +set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off +set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On +set_global_assignment -name ENABLE_NCEO_OUTPUT Off +set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name STRATIXIII_UPDATE_MODE Standard +set_global_assignment -name STRATIX_UPDATE_MODE Standard +set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE Standard +set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off +set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 00000000 +set_global_assignment -name CVP_MODE Off +set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial" +set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial" +set_global_assignment -name USER_START_UP_CLOCK Off +set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC +set_global_assignment -name ENABLE_VREFA_PIN Off +set_global_assignment -name ENABLE_VREFB_PIN Off +set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off +set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off +set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off +set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground" +set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off +set_global_assignment -name INIT_DONE_OPEN_DRAIN On +set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated" +set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin" +set_global_assignment -name ENABLE_CONFIGURATION_PINS On +set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off +set_global_assignment -name ENABLE_NCE_PIN On +set_global_assignment -name ENABLE_BOOT_SEL_PIN On +set_global_assignment -name CRC_ERROR_CHECKING Off +set_global_assignment -name INTERNAL_SCRUBBING Off +set_global_assignment -name PR_ERROR_OPEN_DRAIN On +set_global_assignment -name PR_READY_OPEN_DRAIN On +set_global_assignment -name ENABLE_CVP_CONFDONE Off +set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V" +set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto +set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care +set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic +set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0 +set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On +set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation" +set_global_assignment -name OPTIMIZE_SSN Off +set_global_assignment -name OPTIMIZE_TIMING "Normal compilation" +set_global_assignment -name ECO_OPTIMIZE_TIMING Off +set_global_assignment -name ECO_REGENERATE_REPORT Off +set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal +set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off +set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically +set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically +set_global_assignment -name SEED 1 +set_global_assignment -name SLOW_SLEW_RATE Off +set_global_assignment -name PCI_IO Off +set_global_assignment -name VREF_MODE EXTERNAL +set_global_assignment -name TURBO_BIT On +set_global_assignment -name WEAK_PULL_UP_RESISTOR Off +set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off +set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off +set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO +set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto +set_global_assignment -name AUTO_PACKED_REGISTERS Off +set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO +set_global_assignment -name NORMAL_LCELL_INSERT On +set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On +set_global_assignment -name AUTO_DELAY_CHAINS On +set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF +set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off +set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off +set_global_assignment -name AUTO_TURBO_BIT ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off +set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off +set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On +set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off +set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off +set_global_assignment -name FITTER_EFFORT "Auto Fit" +set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal +set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO +set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO +set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off +set_global_assignment -name AUTO_GLOBAL_CLOCK On +set_global_assignment -name AUTO_GLOBAL_OE On +set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On +set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic +set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off +set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off +set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off +set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off +set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off +set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up" +set_global_assignment -name ENABLE_HOLD_BACK_OFF On +set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto +set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off +set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off +set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On +set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III" +set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V" +set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_LARGE_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX" +set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V" +set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off +set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On +set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off +set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off +set_global_assignment -name PR_DONE_OPEN_DRAIN On +set_global_assignment -name NCEO_OPEN_DRAIN On +set_global_assignment -name ENABLE_CRC_ERROR_PIN Off +set_global_assignment -name ENABLE_PR_PINS Off +set_global_assignment -name PR_PINS_OPEN_DRAIN Off +set_global_assignment -name CLAMPING_DIODE Off +set_global_assignment -name TRI_STATE_SPI_PINS Off +set_global_assignment -name UNUSED_TSD_PINS_GND Off +set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off +set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off +set_global_assignment -name ALM_REGISTER_PACKING_EFFORT MEDIUM +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "" +set_global_assignment -name EDA_BOARD_DESIGN_TOOL "" +set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "" +set_global_assignment -name EDA_RESYNTHESIS_TOOL "" +set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On +set_global_assignment -name COMPRESSION_MODE Off +set_global_assignment -name CLOCK_SOURCE Internal +set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz" +set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1 +set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off +set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On +set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF +set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F +set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name USE_CHECKSUM_AS_USERCODE On +set_global_assignment -name SECURITY_BIT Off +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V" +set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS" +set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III" +set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto +set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto +set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto +set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto +set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF +set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off +set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On +set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off +set_global_assignment -name GENERATE_TTF_FILE Off +set_global_assignment -name GENERATE_RBF_FILE Off +set_global_assignment -name GENERATE_HEX_FILE Off +set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0 +set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up +set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal" +set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off +set_global_assignment -name AUTO_RESTART_CONFIGURATION On +set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off +set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On +set_global_assignment -name ENABLE_OCT_DONE Off +set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF +set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off +set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off +set_global_assignment -name START_TIME 0ns +set_global_assignment -name SIMULATION_MODE TIMING +set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off +set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On +set_global_assignment -name SETUP_HOLD_DETECTION Off +set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off +set_global_assignment -name CHECK_OUTPUTS Off +set_global_assignment -name SIMULATION_COVERAGE On +set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On +set_global_assignment -name GLITCH_DETECTION Off +set_global_assignment -name GLITCH_INTERVAL 1ns +set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off +set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On +set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off +set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On +set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE +set_global_assignment -name SIMULATION_NETLIST_VIEWER Off +set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT +set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off +set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO +set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO +set_global_assignment -name DRC_TOP_FANOUT 50 +set_global_assignment -name DRC_FANOUT_EXCEEDING 30 +set_global_assignment -name DRC_GATED_CLOCK_FEED 30 +set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY +set_global_assignment -name ENABLE_DRC_SETTINGS Off +set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25 +set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10 +set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30 +set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2 +set_global_assignment -name MERGE_HEX_FILE Off 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+set_global_assignment -name POWER_USE_INPUT_FILE "No File" +set_global_assignment -name POWER_USE_INPUT_FILES Off +set_global_assignment -name POWER_VCD_FILTER_GLITCHES On +set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off +set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off +set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL +set_global_assignment -name POWER_AUTO_COMPUTE_TJ On +set_global_assignment -name POWER_TJ_VALUE 25 +set_global_assignment -name POWER_USE_TA_VALUE 25 +set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off +set_global_assignment -name POWER_BOARD_TEMPERATURE 25 +set_global_assignment -name POWER_HPS_ENABLE Off +set_global_assignment -name POWER_HPS_PROC_FREQ 0.0 +set_global_assignment -name IGNORE_PARTITIONS Off +set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off +set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On +set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End" 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EQC_POWER_UP_COMPARE Off +set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On +set_global_assignment -name EQC_AUTO_INVERSION On +set_global_assignment -name EQC_AUTO_TERMINATE On +set_global_assignment -name EQC_SUB_CONE_REPORT Off +set_global_assignment -name EQC_RENAMING_RULES On +set_global_assignment -name EQC_PARAMETER_CHECK On +set_global_assignment -name EQC_AUTO_PORTSWAP On +set_global_assignment -name EQC_DETECT_DONT_CARES On +set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off +set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ? +set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ? +set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ? +set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ? +set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ? +set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ? +set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ? +set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ? +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ? +set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ? +set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "" -section_id ? +set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ? +set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ? +set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ? +set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ? +set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ? +set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ? +set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ? +set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ? +set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ? +set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ? +set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ? +set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ? +set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ? +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ? +set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ? +set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ? +set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ? +set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ? +set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ? +set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ? +set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ? +set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ? +set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ? +set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ? +set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ? +set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ? +set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ? +set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ? +set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ? +set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ? +set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ? +set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ? +set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ? +set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ? +set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ? +set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ? +set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ? +set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ? +set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ? +set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ? diff --git a/examples/hdl4se_riscv/test_code/console.c b/examples/hdl4se_riscv/test_code/console.c index c8de7511dfd2964396e888b609fbc2067eb3f9c6..ce489069fb88ec87a5e784a07e263fa98fc2b7e8 100644 --- a/examples/hdl4se_riscv/test_code/console.c +++ b/examples/hdl4se_riscv/test_code/console.c @@ -292,7 +292,7 @@ void dispmem() temp[0] = disp[i]; } else { - temp[0] = ' '; + temp[0] = '.'; } temp[1] = 0; _strcat(buf, temp); @@ -315,6 +315,8 @@ int main(int argc, char* argv[]) char buf[256]; _puts(">>"); _gets(buf, 255); + _puts(":"); + _puts(buf); if (_strncmp(buf, "help ", 4) == 0) { _puts(" d -- display memory \n"); _puts(" b -- set baudrate \n"); diff --git a/examples/hdl4se_riscv/test_code/test.cod b/examples/hdl4se_riscv/test_code/test.cod index 06455621eef7c85262a21d71d37cd2e42ef15c30..2ec448fcb0736d83fb81a0c89a67305cd4ebc1c3 100644 --- a/examples/hdl4se_riscv/test_code/test.cod +++ b/examples/hdl4se_riscv/test_code/test.cod @@ -1,16 +1,16 @@ @00000074 -93 07 00 00 63 88 07 00 37 15 00 00 13 05 85 17 -6F 10 00 15 67 80 00 00 97 31 00 00 93 81 41 AC +93 07 00 00 63 88 07 00 37 15 00 00 13 05 05 19 +6F 10 80 16 67 80 00 00 97 31 00 00 93 81 C1 AD 13 85 81 C3 13 86 C1 C5 33 06 A6 40 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+:102588000000000000000000000000000000000043 +:102598000000000000000000000000000000000033 +:1025A8000000000000000000000000000000000023 +:1025B8000000000000000000000000000000000013 +:1025C8000000000000000000000000000000000003 +:1025D80000000000000000000000000000000000F3 +:1025E80000000000000000000000000000000000E3 +:1025F80000000000000000000000000000000000D3 +:1026080000000000000000000000000000000000C2 +:1026180000000000000000000000000000000000B2 +:1026280000000000000000000000000000000000A2 +:102638000000000000000000000000000000000092 +:102648000000000000000000000000000000000082 +:102658000000000000000000000000000000000072 +:102668000000000000000000000000000000000062 +:102678000000000000000000000000000000000052 +:102688000000000000000000000000000000000042 +:102698000000000000000000000000000000000032 +:1026A8000000000000000000000000000000000022 +:1026B8000000000000000000000000000000000012 +:1026C8000000000000000000000000000000000002 +:1026D80000000000000000000000000000000000F2 +:1026E80000000000000000000000000000000000E2 +:1026F80000000000000000000000000000000000D2 +:1027080000000000000000000000000000000000C1 +:1027180000000000000000000000000000000000B1 +:1027280000000000000000000000000000000000A1 +:102738000000000000000000000000000000000091 +:102748000000000000000000000000000000000081 +:102758000000000000000000000000000000000071 +:102768000000000000000000000000000000000061 +:102778000000000000000000000000000000000051 +:08278800000000000000000049 +:102790006823000000000000000100F06823000032 :040000030000008C6D :00000001FF diff --git a/examples/hdl4se_riscv/test_code/test.info b/examples/hdl4se_riscv/test_code/test.info index b936f447488412fbc8887565ce9ed46b8223adb5..caa8258d36c2d919c3ecea9cae9b0e84d1081a03 100644 --- a/examples/hdl4se_riscv/test_code/test.info +++ b/examples/hdl4se_riscv/test_code/test.info @@ -10,7 +10,7 @@ ELF Header: Version: 0x1 Entry point address: 0x8c Start of program headers: 52 (bytes into file) - Start of section headers: 8272 (bytes into file) + Start of section headers: 8292 (bytes into file) Flags: 0x0 Size of this header: 52 (bytes) Size of program headers: 32 (bytes) @@ -22,20 +22,20 @@ ELF Header: Section Headers: [Nr] Name Type Addr Off Size ES Flg Lk Inf Al [ 0] NULL 00000000 000000 000000 00 0 0 0 - [ 1] .text PROGBITS 00000074 000074 001244 00 AX 0 0 4 - [ 2] .rodata PROGBITS 000012b8 0012b8 000082 00 A 0 0 4 - [ 3] .eh_frame PROGBITS 0000233c 00133c 000004 00 WA 0 0 4 - [ 4] .init_array INIT_ARRAY 00002340 001340 000008 04 WA 0 0 4 - [ 5] .fini_array FINI_ARRAY 00002348 001348 000004 04 WA 0 0 4 - [ 6] .data PROGBITS 00002350 001350 000428 00 WA 0 0 8 - [ 7] .sdata PROGBITS 00002778 001778 000010 00 WA 0 0 4 - [ 8] .sbss NOBITS 00002788 001788 000008 00 WA 0 0 4 - [ 9] .bss NOBITS 00002790 001788 00001c 00 WA 0 0 4 - [10] .comment PROGBITS 00000000 001788 000012 01 MS 0 0 1 - [11] .riscv.attributes RISCV_ATTRIBUTE 00000000 00179a 000026 00 0 0 1 - [12] .symtab SYMTAB 00000000 0017c0 000520 10 13 41 4 - [13] .strtab STRTAB 00000000 001ce0 0002f2 00 0 0 1 - [14] .shstrtab STRTAB 00000000 001fd2 00007e 00 0 0 1 + [ 1] .text PROGBITS 00000074 000074 00125c 00 AX 0 0 4 + [ 2] .rodata PROGBITS 000012d0 0012d0 000086 00 A 0 0 4 + [ 3] .eh_frame PROGBITS 00002358 001358 000004 00 WA 0 0 4 + [ 4] .init_array INIT_ARRAY 0000235c 00135c 000008 04 WA 0 0 4 + [ 5] .fini_array FINI_ARRAY 00002364 001364 000004 04 WA 0 0 4 + [ 6] .data PROGBITS 00002368 001368 000428 00 WA 0 0 8 + [ 7] .sdata PROGBITS 00002790 001790 000010 00 WA 0 0 4 + [ 8] .sbss NOBITS 000027a0 0017a0 000008 00 WA 0 0 4 + [ 9] .bss NOBITS 000027a8 0017a0 00001c 00 WA 0 0 4 + [10] .comment PROGBITS 00000000 0017a0 000012 01 MS 0 0 1 + [11] .riscv.attributes RISCV_ATTRIBUTE 00000000 0017b2 000021 00 0 0 1 + [12] .symtab SYMTAB 00000000 0017d4 000520 10 13 41 4 + [13] .strtab STRTAB 00000000 001cf4 0002f2 00 0 0 1 + [14] .shstrtab STRTAB 00000000 001fe6 00007e 00 0 0 1 Key to Flags: W (write), A (alloc), X (execute), M (merge), S (strings), I (info), L (link order), O (extra OS processing required), G (group), T (TLS), @@ -46,8 +46,8 @@ There are no section groups in this file. Program Headers: Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align - LOAD 0x000000 0x00000000 0x00000000 0x0133a 0x0133a R E 0x1000 - LOAD 0x00133c 0x0000233c 0x0000233c 0x0044c 0x00470 RW 0x1000 + LOAD 0x000000 0x00000000 0x00000000 0x01356 0x01356 R E 0x1000 + LOAD 0x001358 0x00002358 0x00002358 0x00448 0x0046c RW 0x1000 Section to Segment mapping: Segment Sections... @@ -64,30 +64,30 @@ Symbol table '.symtab' contains 82 entries: Num: Value Size Type Bind Vis Ndx Name 0: 00000000 0 NOTYPE LOCAL DEFAULT UND 1: 00000074 0 SECTION LOCAL DEFAULT 1 .text - 2: 000012b8 0 SECTION LOCAL DEFAULT 2 .rodata - 3: 0000233c 0 SECTION LOCAL DEFAULT 3 .eh_frame - 4: 00002340 0 SECTION LOCAL DEFAULT 4 .init_array - 5: 00002348 0 SECTION LOCAL DEFAULT 5 .fini_array - 6: 00002350 0 SECTION LOCAL DEFAULT 6 .data - 7: 00002778 0 SECTION LOCAL DEFAULT 7 .sdata - 8: 00002788 0 SECTION LOCAL DEFAULT 8 .sbss - 9: 00002790 0 SECTION LOCAL DEFAULT 9 .bss + 2: 000012d0 0 SECTION LOCAL DEFAULT 2 .rodata + 3: 00002358 0 SECTION LOCAL DEFAULT 3 .eh_frame + 4: 0000235c 0 SECTION LOCAL DEFAULT 4 .init_array + 5: 00002364 0 SECTION LOCAL DEFAULT 5 .fini_array + 6: 00002368 0 SECTION LOCAL DEFAULT 6 .data + 7: 00002790 0 SECTION LOCAL DEFAULT 7 .sdata + 8: 000027a0 0 SECTION LOCAL DEFAULT 8 .sbss + 9: 000027a8 0 SECTION LOCAL DEFAULT 9 .bss 10: 00000000 0 SECTION LOCAL DEFAULT 10 .comment 11: 00000000 0 SECTION LOCAL DEFAULT 11 .riscv.attributes 12: 00000000 0 FILE LOCAL DEFAULT ABS __call_atexit.c 13: 00000074 24 FUNC LOCAL DEFAULT 1 register_fini 14: 00000000 0 FILE LOCAL DEFAULT ABS crtstuff.c - 15: 0000233c 0 OBJECT LOCAL DEFAULT 3 + 15: 00002358 0 OBJECT LOCAL DEFAULT 3 16: 000000d8 0 FUNC LOCAL DEFAULT 1 __do_global_dtors_aux - 17: 00002790 1 OBJECT LOCAL DEFAULT 9 completed.1 - 18: 00002348 0 OBJECT LOCAL DEFAULT 5 __do_global_dtor[...] + 17: 000027a8 1 OBJECT LOCAL DEFAULT 9 completed.1 + 18: 00002364 0 OBJECT LOCAL DEFAULT 5 __do_global_dtor[...] 19: 0000011c 0 FUNC LOCAL DEFAULT 1 frame_dummy - 20: 00002794 24 OBJECT LOCAL DEFAULT 9 object.0 - 21: 00002344 0 OBJECT LOCAL DEFAULT 4 __frame_dummy_in[...] + 20: 000027ac 24 OBJECT LOCAL DEFAULT 9 object.0 + 21: 00002360 0 OBJECT LOCAL DEFAULT 4 __frame_dummy_in[...] 22: 00000000 0 FILE LOCAL DEFAULT ABS console.c 23: 00000000 0 FILE LOCAL DEFAULT ABS exit.c 24: 00000000 0 FILE LOCAL DEFAULT ABS impure.c - 25: 00002350 1064 OBJECT LOCAL DEFAULT 6 impure_data + 25: 00002368 1064 OBJECT LOCAL DEFAULT 6 impure_data 26: 00000000 0 FILE LOCAL DEFAULT ABS init.c 27: 00000000 0 FILE LOCAL DEFAULT ABS fini.c 28: 00000000 0 FILE LOCAL DEFAULT ABS atexit.c @@ -95,58 +95,58 @@ Symbol table '.symtab' contains 82 entries: 30: 00000000 0 FILE LOCAL DEFAULT ABS sys_exit.c 31: 00000000 0 FILE LOCAL DEFAULT ABS errno.c 32: 00000000 0 FILE LOCAL DEFAULT ABS crtstuff.c - 33: 0000233c 0 OBJECT LOCAL DEFAULT 3 __FRAME_END__ + 33: 00002358 0 OBJECT LOCAL DEFAULT 3 __FRAME_END__ 34: 00000000 0 FILE LOCAL DEFAULT ABS - 35: 0000234c 0 NOTYPE LOCAL DEFAULT 5 __fini_array_end - 36: 00002348 0 NOTYPE LOCAL DEFAULT 5 __fini_array_start - 37: 00002348 0 NOTYPE LOCAL DEFAULT 4 __init_array_end - 38: 00002340 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_end - 39: 00002340 0 NOTYPE LOCAL DEFAULT 4 __init_array_start - 40: 00002340 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_start + 35: 00002368 0 NOTYPE LOCAL DEFAULT 5 __fini_array_end + 36: 00002364 0 NOTYPE LOCAL DEFAULT 5 __fini_array_start + 37: 00002364 0 NOTYPE LOCAL DEFAULT 4 __init_array_end + 38: 0000235c 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_end + 39: 0000235c 0 NOTYPE LOCAL DEFAULT 4 __init_array_start + 40: 0000235c 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_start 41: 000001b8 88 FUNC GLOBAL DEFAULT 1 _putchar 42: 00000970 140 FUNC GLOBAL DEFAULT 1 _strcat - 43: 00002b50 0 NOTYPE GLOBAL DEFAULT ABS __global_pointer$ + 43: 00002b68 0 NOTYPE GLOBAL DEFAULT ABS __global_pointer$ 44: 000009fc 112 FUNC GLOBAL DEFAULT 1 _strcmp - 45: 000012b0 8 FUNC GLOBAL DEFAULT 1 __errno - 46: 00002778 0 NOTYPE GLOBAL DEFAULT 7 __SDATA_BEGIN__ + 45: 000012c8 8 FUNC GLOBAL DEFAULT 1 __errno + 46: 00002790 0 NOTYPE GLOBAL DEFAULT 7 __SDATA_BEGIN__ 47: 0000013c 60 FUNC GLOBAL DEFAULT 1 _canputchar 48: 00000778 312 FUNC GLOBAL DEFAULT 1 _s2h 49: 0000025c 104 FUNC GLOBAL DEFAULT 1 _puts 50: 00000b04 64 FUNC GLOBAL DEFAULT 1 _buadrateset 51: 000004f8 388 FUNC GLOBAL DEFAULT 1 _h2s - 52: 0000277c 0 OBJECT GLOBAL HIDDEN 7 __dso_handle + 52: 00002794 0 OBJECT GLOBAL HIDDEN 7 __dso_handle 53: 00000b44 584 FUNC GLOBAL DEFAULT 1 dispmem 54: 00000178 64 FUNC GLOBAL DEFAULT 1 _haschar - 55: 00002778 4 OBJECT GLOBAL DEFAULT 7 _global_impure_ptr - 56: 00000ee0 156 FUNC GLOBAL DEFAULT 1 __libc_init_array + 55: 00002790 4 OBJECT GLOBAL DEFAULT 7 _global_impure_ptr + 56: 00000ef8 156 FUNC GLOBAL DEFAULT 1 __libc_init_array 57: 000002c4 216 FUNC GLOBAL DEFAULT 1 _gets - 58: 00001178 92 FUNC GLOBAL DEFAULT 1 __libc_fini_array + 58: 00001190 92 FUNC GLOBAL DEFAULT 1 __libc_fini_array 59: 0000067c 252 FUNC GLOBAL DEFAULT 1 _s2d - 60: 00001058 288 FUNC GLOBAL DEFAULT 1 __call_exitprocs + 60: 00001070 288 FUNC GLOBAL DEFAULT 1 __call_exitprocs 61: 0000008c 76 FUNC GLOBAL DEFAULT 1 _start - 62: 000011e8 152 FUNC GLOBAL DEFAULT 1 __register_exitproc + 62: 00001200 152 FUNC GLOBAL DEFAULT 1 __register_exitproc 63: 00000210 76 FUNC GLOBAL DEFAULT 1 _getchar - 64: 000027ac 0 NOTYPE GLOBAL DEFAULT 9 __BSS_END__ - 65: 00002780 4 OBJECT GLOBAL DEFAULT 7 _uartaddr + 64: 000027c4 0 NOTYPE GLOBAL DEFAULT 9 __BSS_END__ + 65: 00002798 4 OBJECT GLOBAL DEFAULT 7 _uartaddr 66: 0000039c 348 FUNC GLOBAL DEFAULT 1 _d2s - 67: 00002788 0 NOTYPE GLOBAL DEFAULT 8 __bss_start - 68: 00000f7c 220 FUNC GLOBAL DEFAULT 1 memset - 69: 00000d8c 292 FUNC GLOBAL DEFAULT 1 main - 70: 0000278c 4 OBJECT GLOBAL DEFAULT 8 displayaddr + 67: 000027a0 0 NOTYPE GLOBAL DEFAULT 8 __bss_start + 68: 00000f94 220 FUNC GLOBAL DEFAULT 1 memset + 69: 00000d8c 316 FUNC GLOBAL DEFAULT 1 main + 70: 000027a4 4 OBJECT GLOBAL DEFAULT 8 displayaddr 71: 00000900 112 FUNC GLOBAL DEFAULT 1 _strcpy - 72: 000011d4 20 FUNC GLOBAL DEFAULT 1 atexit - 73: 00002784 4 OBJECT GLOBAL DEFAULT 7 _impure_ptr - 74: 00002350 0 NOTYPE GLOBAL DEFAULT 6 __DATA_BEGIN__ + 72: 000011ec 20 FUNC GLOBAL DEFAULT 1 atexit + 73: 0000279c 4 OBJECT GLOBAL DEFAULT 7 _impure_ptr + 74: 00002368 0 NOTYPE GLOBAL DEFAULT 6 __DATA_BEGIN__ 75: 00000a6c 152 FUNC GLOBAL DEFAULT 1 _strncmp - 76: 00002788 4 OBJECT GLOBAL DEFAULT 8 _uartstate - 77: 00002788 0 NOTYPE GLOBAL DEFAULT 7 _edata - 78: 000027ac 0 NOTYPE GLOBAL DEFAULT 9 _end - 79: 00000eb0 48 FUNC GLOBAL DEFAULT 1 exit + 76: 000027a0 4 OBJECT GLOBAL DEFAULT 8 _uartstate + 77: 000027a0 0 NOTYPE GLOBAL DEFAULT 7 _edata + 78: 000027c4 0 NOTYPE GLOBAL DEFAULT 9 _end + 79: 00000ec8 48 FUNC GLOBAL DEFAULT 1 exit 80: 000008b0 80 FUNC GLOBAL DEFAULT 1 _strlen - 81: 00001280 48 FUNC GLOBAL DEFAULT 1 _exit + 81: 00001298 48 FUNC GLOBAL DEFAULT 1 _exit No version information found in this file. Attribute Section: riscv File Attributes Tag_RISCV_stack_align: 16-bytes - Tag_RISCV_arch: "rv32i2p0_m2p0_a2p0" + Tag_RISCV_arch: "rv32i2p0_m2p0" diff --git a/examples/hdl4se_riscv/test_code/test.mif b/examples/hdl4se_riscv/test_code/test.mif index d4b24e474334b1074b6585a80e0042ebf12ffd36..353bf0c9b608bce2cf3a6e4b4efc988d4829bcf0 100644 --- a/examples/hdl4se_riscv/test_code/test.mif +++ b/examples/hdl4se_riscv/test_code/test.mif @@ -36,28 +36,28 @@ BEGIN 001D : 00000793; 001E : 00078863; 001F : 00001537; -0020 : 17850513; -0021 : 1500106F; +0020 : 19050513; +0021 : 1680106F; 0022 : 00008067; 0023 : 00003197; -0024 : AC418193; +0024 : ADC18193; 0025 : C3818513; 0026 : C5C18613; 0027 : 40A60633; 0028 : 00000593; -0029 : 6D9000EF; +0029 : 6F1000EF; 002A : 00001517; -002B : 12C50513; +002B : 14450513; 002C : 00050863; 002D : 00001517; -002E : 0C450513; -002F : 118010EF; -0030 : 621000EF; +002E : 0DC50513; +002F : 130010EF; +0030 : 639000EF; 0031 : 00012503; 0032 : 00410593; 0033 : 00000613; 0034 : 4BD000EF; -0035 : 5DD0006F; +0035 : 5F50006F; 0036 : FF010113; 0037 : 00812423; 0038 : C401C783; @@ -66,7 +66,7 @@ BEGIN 003B : 00000793; 003C : 00078A63; 003D : 00002537; -003E : 33C50513; +003E : 35850513; 003F : 00000097; 0040 : 000000E7; 0041 : 00100793; @@ -79,7 +79,7 @@ BEGIN 0048 : 00078C63; 0049 : 00002537; 004A : C4418593; -004B : 33C50513; +004B : 35850513; 004C : 00000317; 004D : 00000067; 004E : 00008067; @@ -742,7 +742,7 @@ BEGIN 02DF : 97DFF0EF; 02E0 : ED840713; 02E1 : 000017B7; -02E2 : 2B878593; +02E2 : 2D078593; 02E3 : 00070513; 02E4 : DE1FF0EF; 02E5 : FEA42023; @@ -757,7 +757,7 @@ BEGIN 02EE : 02F77063; 02EF : ED840713; 02F0 : 000017B7; -02F1 : 2BC78593; +02F1 : 2D478593; 02F2 : 00070513; 02F3 : DA5FF0EF; 02F4 : FEA42023; @@ -775,7 +775,7 @@ BEGIN 0300 : 8F9FF0EF; 0301 : ED040713; 0302 : 000017B7; -0303 : 2C078593; +0303 : 2D878593; 0304 : 00070513; 0305 : D5DFF0EF; 0306 : ED040713; @@ -789,7 +789,7 @@ BEGIN 030E : 00F71C63; 030F : ED840713; 0310 : 000017B7; -0311 : 2C478593; +0311 : 2DC78593; 0312 : 00070513; 0313 : D25FF0EF; 0314 : FEC42783; @@ -800,7 +800,7 @@ BEGIN 0319 : F2E7DEE3; 031A : ED840713; 031B : 000017B7; -031C : 2C878593; +031C : 2E078593; 031D : 00070513; 031E : CF9FF0EF; 031F : FE042623; @@ -825,7 +825,7 @@ BEGIN 0332 : 0007C783; 0333 : ECF40623; 0334 : 00C0006F; -0335 : 02000793; +0335 : 02E00793; 0336 : ECF40623; 0337 : EC0406A3; 0338 : ECC40713; @@ -841,7 +841,7 @@ BEGIN 0342 : F6E7DEE3; 0343 : ED840713; 0344 : 000017B7; -0345 : 2CC78593; +0345 : 2E478593; 0346 : 00070513; 0347 : C55FF0EF; 0348 : ED840793; @@ -862,7 +862,7 @@ BEGIN 0357 : 0080006F; 0358 : 00000013; 0359 : 000017B7; -035A : 2D078513; +035A : 2E878513; 035B : CF0FF0EF; 035C : FE442703; 035D : C2E1AE23; @@ -881,367 +881,367 @@ BEGIN 036A : 20078513; 036B : D59FF0EF; 036C : 000017B7; -036D : 2D478513; +036D : 2EC78513; 036E : CA4FF0EF; 036F : 000017B7; -0370 : 2E478513; +0370 : 2FC78513; 0371 : C98FF0EF; 0372 : EE840793; 0373 : 0FF00593; 0374 : 00078513; 0375 : CF0FF0EF; -0376 : EE840713; -0377 : 00400613; -0378 : 000017B7; -0379 : 2E878593; -037A : 00070513; -037B : C81FF0EF; -037C : 00050793; -037D : 02079063; +0376 : 000017B7; +0377 : 30078513; +0378 : C7CFF0EF; +0379 : EE840793; +037A : 00078513; +037B : C70FF0EF; +037C : EE840713; +037D : 00400613; 037E : 000017B7; -037F : 2F078513; -0380 : C5CFF0EF; -0381 : 000017B7; -0382 : 31078513; -0383 : C50FF0EF; -0384 : FADFF06F; -0385 : EE840713; -0386 : 00100613; +037F : 30478593; +0380 : 00070513; +0381 : C69FF0EF; +0382 : 00050793; +0383 : 02079063; +0384 : 000017B7; +0385 : 30C78513; +0386 : C44FF0EF; 0387 : 000017B7; -0388 : 33478593; -0389 : 00070513; -038A : C45FF0EF; -038B : 00050793; -038C : 02079863; -038D : EE840793; -038E : 00278793; -038F : 00000593; -0390 : 00078513; -0391 : 839FF0EF; -0392 : FEA42423; -0393 : FE842783; -0394 : F6F056E3; -0395 : FE842503; -0396 : CADFF0EF; -0397 : F61FF06F; -0398 : EE840713; -0399 : 00100613; -039A : 000017B7; -039B : 33878593; -039C : 00070513; -039D : BF9FF0EF; -039E : 00050793; -039F : F40790E3; -03A0 : EE840793; -03A1 : 00278793; -03A2 : 00000593; -03A3 : 00078513; -03A4 : 8E9FF0EF; -03A5 : FEA42623; -03A6 : FEC42783; -03A7 : 00F05663; -03A8 : FEC42703; -03A9 : C2E1AE23; -03AA : C9DFF0EF; -03AB : F11FF06F; -03AC : FF010113; -03AD : 00000593; -03AE : 00812423; -03AF : 00112623; -03B0 : 00050413; -03B1 : 194000EF; -03B2 : C281A503; -03B3 : 03C52783; -03B4 : 00078463; -03B5 : 000780E7; -03B6 : 00040513; -03B7 : 3A4000EF; -03B8 : FF010113; -03B9 : 00812423; -03BA : 01212023; -03BB : 00002437; -03BC : 00002937; -03BD : 34040793; -03BE : 34090913; -03BF : 40F90933; -03C0 : 00112623; -03C1 : 00912223; -03C2 : 40295913; -03C3 : 02090063; -03C4 : 34040413; -03C5 : 00000493; -03C6 : 00042783; -03C7 : 00148493; -03C8 : 00440413; -03C9 : 000780E7; -03CA : FE9918E3; -03CB : 00002437; -03CC : 00002937; -03CD : 34040793; -03CE : 34890913; -03CF : 40F90933; -03D0 : 40295913; -03D1 : 02090063; -03D2 : 34040413; -03D3 : 00000493; -03D4 : 00042783; -03D5 : 00148493; -03D6 : 00440413; -03D7 : 000780E7; -03D8 : FE9918E3; -03D9 : 00C12083; -03DA : 00812403; -03DB : 00412483; -03DC : 00012903; -03DD : 01010113; -03DE : 00008067; -03DF : 00F00313; -03E0 : 00050713; -03E1 : 02C37E63; -03E2 : 00F77793; -03E3 : 0A079063; -03E4 : 08059263; -03E5 : FF067693; -03E6 : 00F67613; -03E7 : 00E686B3; -03E8 : 00B72023; -03E9 : 00B72223; -03EA : 00B72423; -03EB : 00B72623; -03EC : 01070713; -03ED : FED766E3; -03EE : 00061463; -03EF : 00008067; -03F0 : 40C306B3; -03F1 : 00269693; -03F2 : 00000297; -03F3 : 005686B3; -03F4 : 00C68067; -03F5 : 00B70723; -03F6 : 00B706A3; -03F7 : 00B70623; -03F8 : 00B705A3; -03F9 : 00B70523; -03FA : 00B704A3; -03FB : 00B70423; -03FC : 00B703A3; -03FD : 00B70323; -03FE : 00B702A3; -03FF : 00B70223; -0400 : 00B701A3; -0401 : 00B70123; -0402 : 00B700A3; -0403 : 00B70023; -0404 : 00008067; -0405 : 0FF5F593; -0406 : 00859693; -0407 : 00D5E5B3; -0408 : 01059693; -0409 : 00D5E5B3; -040A : F6DFF06F; -040B : 00279693; -040C : 00000297; -040D : 005686B3; -040E : 00008293; -040F : FA0680E7; -0410 : 00028093; -0411 : FF078793; -0412 : 40F70733; -0413 : 00F60633; -0414 : F6C378E3; -0415 : F3DFF06F; -0416 : FD010113; -0417 : 01412C23; -0418 : C281AA03; -0419 : 03212023; -041A : 02112623; -041B : 148A2903; -041C : 02812423; -041D : 02912223; -041E : 01312E23; -041F : 01512A23; -0420 : 01612823; -0421 : 01712623; -0422 : 01812423; -0423 : 04090063; -0424 : 00050B13; -0425 : 00058B93; -0426 : 00100A93; -0427 : FFF00993; -0428 : 00492483; -0429 : FFF48413; -042A : 02044263; -042B : 00249493; -042C : 009904B3; -042D : 040B8463; -042E : 1044A783; -042F : 05778063; -0430 : FFF40413; -0431 : FFC48493; -0432 : FF3416E3; -0433 : 02C12083; -0434 : 02812403; -0435 : 02412483; -0436 : 02012903; -0437 : 01C12983; -0438 : 01812A03; -0439 : 01412A83; -043A : 01012B03; -043B : 00C12B83; -043C : 00812C03; -043D : 03010113; -043E : 00008067; -043F : 00492783; -0440 : 0044A683; -0441 : FFF78793; -0442 : 04878E63; -0443 : 0004A223; -0444 : FA0688E3; -0445 : 18892783; -0446 : 008A9733; -0447 : 00492C03; -0448 : 00F777B3; -0449 : 02079263; -044A : 000680E7; -044B : 00492703; -044C : 148A2783; -044D : 01871463; -044E : F92784E3; -044F : F80788E3; -0450 : 00078913; -0451 : F5DFF06F; -0452 : 18C92783; -0453 : 0844A583; -0454 : 00F77733; -0455 : 00071C63; -0456 : 000B0513; -0457 : 000680E7; -0458 : FCDFF06F; -0459 : 00892223; -045A : FA9FF06F; -045B : 00058513; -045C : 000680E7; -045D : FB9FF06F; -045E : FF010113; -045F : 00812423; -0460 : 000027B7; -0461 : 00002437; -0462 : 34878793; -0463 : 34C40413; -0464 : 40F40433; -0465 : 00912223; -0466 : 00112623; -0467 : 40245493; -0468 : 02048063; -0469 : FFC40413; -046A : 00F40433; -046B : 00042783; -046C : FFF48493; -046D : FFC40413; -046E : 000780E7; -046F : FE0498E3; -0470 : 00C12083; -0471 : 00812403; -0472 : 00412483; -0473 : 01010113; -0474 : 00008067; -0475 : 00050593; -0476 : 00000693; -0477 : 00000613; -0478 : 00000513; -0479 : 0040006F; -047A : C281A703; -047B : 14872783; -047C : 04078C63; -047D : 0047A703; -047E : 01F00813; -047F : 06E84E63; -0480 : 00271813; -0481 : 02050663; -0482 : 01078333; -0483 : 08C32423; -0484 : 1887A883; -0485 : 00100613; -0486 : 00E61633; -0487 : 00C8E8B3; -0488 : 1917A423; -0489 : 10D32423; -048A : 00200693; -048B : 02D50463; -048C : 00170713; -048D : 00E7A223; -048E : 010787B3; -048F : 00B7A423; -0490 : 00000513; -0491 : 00008067; -0492 : 14C70793; -0493 : 14F72423; -0494 : FA5FF06F; -0495 : 18C7A683; -0496 : 00170713; -0497 : 00E7A223; -0498 : 00C6E6B3; -0499 : 18D7A623; -049A : 010787B3; -049B : 00B7A423; -049C : 00000513; -049D : 00008067; -049E : FFF00513; -049F : 00008067; -04A0 : 05D00893; -04A1 : 00000073; -04A2 : 00054463; -04A3 : 0000006F; -04A4 : FF010113; -04A5 : 00812423; -04A6 : 00050413; -04A7 : 00112623; -04A8 : 40800433; -04A9 : 00C000EF; -04AA : 00852023; -04AB : 0000006F; -04AC : C341A503; -04AD : 00008067; -04AE : 00002020; -04AF : 00202020; -04B0 : 00000020; -04B1 : 0000202D; -04B2 : 007C2020; -04B3 : 00000A7C; -04B4 : 0000000A; -04B5 : 6C6C6548; -04B6 : 57202C6F; -04B7 : 646C726F; -04B8 : 0000000A; -04B9 : 00003E3E; -04BA : 706C6568; -04BB : 00000020; -04BC : 20642020; -04BD : 6464613C; -04BE : 2D203E72; -04BF : 6964202D; -04C0 : 616C7073; -04C1 : 656D2079; -04C2 : 79726F6D; -04C3 : 00000A20; -04C4 : 20622020; -04C5 : 7561623C; -04C6 : 74617264; -04C7 : 2D203E65; -04C8 : 6573202D; -04C9 : 61622074; -04CA : 61726475; -04CB : 0A206574; -04CC : 00000000; -04CD : 00000062; -04CE : CDCD0064; -04CF : CDCDCDCD; -04D0 : CDCDCDCD; -04D1 : CDCDCDCD; -04D2 : CDCDCDCD; -04D3 : CDCDCDCD; -04D4 : CDCDCDCD; -04D5 : CDCDCDCD; +0388 : 32C78513; +0389 : C38FF0EF; +038A : F95FF06F; +038B : EE840713; +038C : 00100613; +038D : 000017B7; +038E : 35078593; +038F : 00070513; +0390 : C2DFF0EF; +0391 : 00050793; +0392 : 02079863; +0393 : EE840793; +0394 : 00278793; +0395 : 00000593; +0396 : 00078513; +0397 : 821FF0EF; +0398 : FEA42423; +0399 : FE842783; +039A : F4F05AE3; +039B : FE842503; +039C : C95FF0EF; +039D : F49FF06F; +039E : EE840713; +039F : 00100613; +03A0 : 000017B7; +03A1 : 35478593; +03A2 : 00070513; +03A3 : BE1FF0EF; +03A4 : 00050793; +03A5 : F20794E3; +03A6 : EE840793; +03A7 : 00278793; +03A8 : 00000593; +03A9 : 00078513; +03AA : 8D1FF0EF; +03AB : FEA42623; +03AC : FEC42783; +03AD : 00F05663; +03AE : FEC42703; +03AF : C2E1AE23; +03B0 : C85FF0EF; +03B1 : EF9FF06F; +03B2 : FF010113; +03B3 : 00000593; +03B4 : 00812423; +03B5 : 00112623; +03B6 : 00050413; +03B7 : 194000EF; +03B8 : C281A503; +03B9 : 03C52783; +03BA : 00078463; +03BB : 000780E7; +03BC : 00040513; +03BD : 3A4000EF; +03BE : FF010113; +03BF : 00812423; +03C0 : 01212023; +03C1 : 00002437; +03C2 : 00002937; +03C3 : 35C40793; +03C4 : 35C90913; +03C5 : 40F90933; +03C6 : 00112623; +03C7 : 00912223; +03C8 : 40295913; +03C9 : 02090063; +03CA : 35C40413; +03CB : 00000493; +03CC : 00042783; +03CD : 00148493; +03CE : 00440413; +03CF : 000780E7; +03D0 : FE9918E3; +03D1 : 00002437; +03D2 : 00002937; +03D3 : 35C40793; +03D4 : 36490913; +03D5 : 40F90933; +03D6 : 40295913; +03D7 : 02090063; +03D8 : 35C40413; +03D9 : 00000493; +03DA : 00042783; +03DB : 00148493; +03DC : 00440413; +03DD : 000780E7; +03DE : FE9918E3; +03DF : 00C12083; +03E0 : 00812403; +03E1 : 00412483; +03E2 : 00012903; +03E3 : 01010113; +03E4 : 00008067; +03E5 : 00F00313; +03E6 : 00050713; +03E7 : 02C37E63; +03E8 : 00F77793; +03E9 : 0A079063; +03EA : 08059263; +03EB : FF067693; +03EC : 00F67613; +03ED : 00E686B3; +03EE : 00B72023; +03EF : 00B72223; +03F0 : 00B72423; +03F1 : 00B72623; +03F2 : 01070713; +03F3 : FED766E3; +03F4 : 00061463; +03F5 : 00008067; +03F6 : 40C306B3; +03F7 : 00269693; +03F8 : 00000297; +03F9 : 005686B3; +03FA : 00C68067; +03FB : 00B70723; +03FC : 00B706A3; +03FD : 00B70623; +03FE : 00B705A3; +03FF : 00B70523; +0400 : 00B704A3; +0401 : 00B70423; +0402 : 00B703A3; +0403 : 00B70323; +0404 : 00B702A3; +0405 : 00B70223; +0406 : 00B701A3; +0407 : 00B70123; +0408 : 00B700A3; +0409 : 00B70023; +040A : 00008067; +040B : 0FF5F593; +040C : 00859693; +040D : 00D5E5B3; +040E : 01059693; +040F : 00D5E5B3; +0410 : F6DFF06F; +0411 : 00279693; +0412 : 00000297; +0413 : 005686B3; +0414 : 00008293; +0415 : FA0680E7; +0416 : 00028093; +0417 : FF078793; +0418 : 40F70733; +0419 : 00F60633; +041A : F6C378E3; +041B : F3DFF06F; +041C : FD010113; +041D : 01412C23; +041E : C281AA03; +041F : 03212023; +0420 : 02112623; +0421 : 148A2903; +0422 : 02812423; +0423 : 02912223; +0424 : 01312E23; +0425 : 01512A23; +0426 : 01612823; +0427 : 01712623; +0428 : 01812423; +0429 : 04090063; +042A : 00050B13; +042B : 00058B93; +042C : 00100A93; +042D : FFF00993; +042E : 00492483; +042F : FFF48413; +0430 : 02044263; +0431 : 00249493; +0432 : 009904B3; +0433 : 040B8463; +0434 : 1044A783; +0435 : 05778063; +0436 : FFF40413; +0437 : FFC48493; +0438 : FF3416E3; +0439 : 02C12083; +043A : 02812403; +043B : 02412483; +043C : 02012903; +043D : 01C12983; +043E : 01812A03; +043F : 01412A83; +0440 : 01012B03; +0441 : 00C12B83; +0442 : 00812C03; +0443 : 03010113; +0444 : 00008067; +0445 : 00492783; +0446 : 0044A683; +0447 : FFF78793; +0448 : 04878E63; +0449 : 0004A223; +044A : FA0688E3; +044B : 18892783; +044C : 008A9733; +044D : 00492C03; +044E : 00F777B3; +044F : 02079263; +0450 : 000680E7; +0451 : 00492703; +0452 : 148A2783; +0453 : 01871463; +0454 : F92784E3; +0455 : F80788E3; +0456 : 00078913; +0457 : F5DFF06F; +0458 : 18C92783; +0459 : 0844A583; +045A : 00F77733; +045B : 00071C63; +045C : 000B0513; +045D : 000680E7; +045E : FCDFF06F; +045F : 00892223; +0460 : FA9FF06F; +0461 : 00058513; +0462 : 000680E7; +0463 : FB9FF06F; +0464 : FF010113; +0465 : 00812423; +0466 : 000027B7; +0467 : 00002437; +0468 : 36478793; +0469 : 36840413; +046A : 40F40433; +046B : 00912223; +046C : 00112623; +046D : 40245493; +046E : 02048063; +046F : FFC40413; +0470 : 00F40433; +0471 : 00042783; +0472 : FFF48493; +0473 : FFC40413; +0474 : 000780E7; +0475 : FE0498E3; +0476 : 00C12083; +0477 : 00812403; +0478 : 00412483; +0479 : 01010113; +047A : 00008067; +047B : 00050593; +047C : 00000693; +047D : 00000613; +047E : 00000513; +047F : 0040006F; +0480 : C281A703; +0481 : 14872783; +0482 : 04078C63; +0483 : 0047A703; +0484 : 01F00813; +0485 : 06E84E63; +0486 : 00271813; +0487 : 02050663; +0488 : 01078333; +0489 : 08C32423; +048A : 1887A883; +048B : 00100613; +048C : 00E61633; +048D : 00C8E8B3; +048E : 1917A423; +048F : 10D32423; +0490 : 00200693; +0491 : 02D50463; +0492 : 00170713; +0493 : 00E7A223; +0494 : 010787B3; +0495 : 00B7A423; +0496 : 00000513; +0497 : 00008067; +0498 : 14C70793; +0499 : 14F72423; +049A : FA5FF06F; +049B : 18C7A683; +049C : 00170713; +049D : 00E7A223; +049E : 00C6E6B3; +049F : 18D7A623; +04A0 : 010787B3; +04A1 : 00B7A423; +04A2 : 00000513; +04A3 : 00008067; +04A4 : FFF00513; +04A5 : 00008067; +04A6 : 05D00893; +04A7 : 00000073; +04A8 : 00054463; +04A9 : 0000006F; +04AA : FF010113; +04AB : 00812423; +04AC : 00050413; +04AD : 00112623; +04AE : 40800433; +04AF : 00C000EF; +04B0 : 00852023; +04B1 : 0000006F; +04B2 : C341A503; +04B3 : 00008067; +04B4 : 00002020; +04B5 : 00202020; +04B6 : 00000020; +04B7 : 0000202D; +04B8 : 007C2020; +04B9 : 00000A7C; +04BA : 0000000A; +04BB : 6C6C6548; +04BC : 57202C6F; +04BD : 646C726F; +04BE : 0000000A; +04BF : 00003E3E; +04C0 : 0000003A; +04C1 : 706C6568; +04C2 : 00000020; +04C3 : 20642020; +04C4 : 6464613C; +04C5 : 2D203E72; +04C6 : 6964202D; +04C7 : 616C7073; +04C8 : 656D2079; +04C9 : 79726F6D; +04CA : 00000A20; +04CB : 20622020; +04CC : 7561623C; +04CD : 74617264; +04CE : 2D203E65; +04CF : 6573202D; +04D0 : 61622074; +04D1 : 61726475; +04D2 : 0A206574; +04D3 : 00000000; +04D4 : 00000062; +04D5 : CDCD0064; 04D6 : CDCDCDCD; 04D7 : CDCDCDCD; 04D8 : CDCDCDCD; @@ -2259,21 +2259,21 @@ BEGIN 08CC : CDCDCDCD; 08CD : CDCDCDCD; 08CE : CDCDCDCD; -08CF : 00000000; -08D0 : 00000074; -08D1 : 0000011C; -08D2 : 000000D8; +08CF : CDCDCDCD; +08D0 : CDCDCDCD; +08D1 : CDCDCDCD; +08D2 : CDCDCDCD; 08D3 : CDCDCDCD; -08D4 : 00000000; -08D5 : 0000263C; -08D6 : 000026A4; -08D7 : 0000270C; -08D8 : 00000000; -08D9 : 00000000; +08D4 : CDCDCDCD; +08D5 : CDCDCDCD; +08D6 : 00000000; +08D7 : 00000074; +08D8 : 0000011C; +08D9 : 000000D8; 08DA : 00000000; -08DB : 00000000; -08DC : 00000000; -08DD : 00000000; +08DB : 00002654; +08DC : 000026BC; +08DD : 00002724; 08DE : 00000000; 08DF : 00000000; 08E0 : 00000000; @@ -2306,18 +2306,18 @@ BEGIN 08FB : 00000000; 08FC : 00000000; 08FD : 00000000; -08FE : 00000001; +08FE : 00000000; 08FF : 00000000; -0900 : ABCD330E; -0901 : E66D1234; -0902 : 0005DEEC; -0903 : 0000000B; -0904 : 00000000; +0900 : 00000000; +0901 : 00000000; +0902 : 00000000; +0903 : 00000000; +0904 : 00000001; 0905 : 00000000; -0906 : 00000000; -0907 : 00000000; -0908 : 00000000; -0909 : 00000000; +0906 : ABCD330E; +0907 : E66D1234; +0908 : 0005DEEC; +0909 : 0000000B; 090A : 00000000; 090B : 00000000; 090C : 00000000; @@ -2530,20 +2530,20 @@ BEGIN 09DB : 00000000; 09DC : 00000000; 09DD : 00000000; -09DE : 00002350; +09DE : 00000000; 09DF : 00000000; -09E0 : F0000100; -09E1 : 00002350; -09E2 : 00002350; +09E0 : 00000000; +09E1 : 00000000; +09E2 : 00000000; 09E3 : 00000000; -09E4 : F0000100; -09E5 : 00002350; -09E6 : CDCDCDCD; -09E7 : CDCDCDCD; -09E8 : CDCDCDCD; -09E9 : CDCDCDCD; -09EA : CDCDCDCD; -09EB : CDCDCDCD; +09E4 : 00002368; +09E5 : 00000000; +09E6 : F0000100; +09E7 : 00002368; +09E8 : 00002368; +09E9 : 00000000; +09EA : F0000100; +09EB : 00002368; 09EC : CDCDCDCD; 09ED : CDCDCDCD; 09EE : CDCDCDCD; diff --git a/examples/hdl4se_riscv/test_code/test.txt b/examples/hdl4se_riscv/test_code/test.txt index 65c0bcfba968d9157cb6a6b3f02951a99c34700c..806b388ee85c455936b875001d55c4ac55ff5c88 100644 --- a/examples/hdl4se_riscv/test_code/test.txt +++ b/examples/hdl4se_riscv/test_code/test.txt @@ -8,45 +8,45 @@ Disassembly of section .text: 74: 00000793 addi x15,x0,0 78: 00078863 beq x15,x0,88 7c: 00001537 lui x10,0x1 - 80: 17850513 addi x10,x10,376 # 1178 <__libc_fini_array> - 84: 1500106f jal x0,11d4 + 80: 19050513 addi x10,x10,400 # 1190 <__libc_fini_array> + 84: 1680106f jal x0,11ec 88: 00008067 jalr x0,0(x1) 0000008c <_start>: 8c: 00003197 auipc x3,0x3 - 90: ac418193 addi x3,x3,-1340 # 2b50 <__global_pointer$> - 94: c3818513 addi x10,x3,-968 # 2788 <_uartstate> - 98: c5c18613 addi x12,x3,-932 # 27ac <__BSS_END__> + 90: adc18193 addi x3,x3,-1316 # 2b68 <__global_pointer$> + 94: c3818513 addi x10,x3,-968 # 27a0 <_uartstate> + 98: c5c18613 addi x12,x3,-932 # 27c4 <__BSS_END__> 9c: 40a60633 sub x12,x12,x10 a0: 00000593 addi x11,x0,0 - a4: 6d9000ef jal x1,f7c + a4: 6f1000ef jal x1,f94 a8: 00001517 auipc x10,0x1 - ac: 12c50513 addi x10,x10,300 # 11d4 + ac: 14450513 addi x10,x10,324 # 11ec b0: 00050863 beq x10,x0,c0 <_start+0x34> b4: 00001517 auipc x10,0x1 - b8: 0c450513 addi x10,x10,196 # 1178 <__libc_fini_array> - bc: 118010ef jal x1,11d4 - c0: 621000ef jal x1,ee0 <__libc_init_array> + b8: 0dc50513 addi x10,x10,220 # 1190 <__libc_fini_array> + bc: 130010ef jal x1,11ec + c0: 639000ef jal x1,ef8 <__libc_init_array> c4: 00012503 lw x10,0(x2) c8: 00410593 addi x11,x2,4 cc: 00000613 addi x12,x0,0 d0: 4bd000ef jal x1,d8c
- d4: 5dd0006f jal x0,eb0 + d4: 5f50006f jal x0,ec8 000000d8 <__do_global_dtors_aux>: d8: ff010113 addi x2,x2,-16 dc: 00812423 sw x8,8(x2) - e0: c401c783 lbu x15,-960(x3) # 2790 + e0: c401c783 lbu x15,-960(x3) # 27a8 e4: 00112623 sw x1,12(x2) e8: 02079263 bne x15,x0,10c <__do_global_dtors_aux+0x34> ec: 00000793 addi x15,x0,0 f0: 00078a63 beq x15,x0,104 <__do_global_dtors_aux+0x2c> f4: 00002537 lui x10,0x2 - f8: 33c50513 addi x10,x10,828 # 233c <__FRAME_END__> + f8: 35850513 addi x10,x10,856 # 2358 <__FRAME_END__> fc: 00000097 auipc x1,0x0 100: 000000e7 jalr x1,0(x0) # 0 104: 00100793 addi x15,x0,1 - 108: c4f18023 sb x15,-960(x3) # 2790 + 108: c4f18023 sb x15,-960(x3) # 27a8 10c: 00c12083 lw x1,12(x2) 110: 00812403 lw x8,8(x2) 114: 01010113 addi x2,x2,16 @@ -56,8 +56,8 @@ Disassembly of section .text: 11c: 00000793 addi x15,x0,0 120: 00078c63 beq x15,x0,138 124: 00002537 lui x10,0x2 - 128: c4418593 addi x11,x3,-956 # 2794 - 12c: 33c50513 addi x10,x10,828 # 233c <__FRAME_END__> + 128: c4418593 addi x11,x3,-956 # 27ac + 12c: 35850513 addi x10,x10,856 # 2358 <__FRAME_END__> 130: 00000317 auipc x6,0x0 134: 00000067 jalr x0,0(x0) # 0 138: 00008067 jalr x0,0(x1) @@ -66,11 +66,11 @@ Disassembly of section .text: 13c: ff010113 addi x2,x2,-16 140: 00812623 sw x8,12(x2) 144: 01010413 addi x8,x2,16 - 148: c301a783 lw x15,-976(x3) # 2780 <_uartaddr> + 148: c301a783 lw x15,-976(x3) # 2798 <_uartaddr> 14c: 00878793 addi x15,x15,8 150: 0007a703 lw x14,0(x15) - 154: c2e1ac23 sw x14,-968(x3) # 2788 <_uartstate> - 158: c381a783 lw x15,-968(x3) # 2788 <_uartstate> + 154: c2e1ac23 sw x14,-968(x3) # 27a0 <_uartstate> + 158: c381a783 lw x15,-968(x3) # 27a0 <_uartstate> 15c: 0017f793 andi x15,x15,1 160: 0017b793 sltiu x15,x15,1 164: 0ff7f793 andi x15,x15,255 @@ -83,16 +83,16 @@ Disassembly of section .text: 178: ff010113 addi x2,x2,-16 17c: 00812623 sw x8,12(x2) 180: 01010413 addi x8,x2,16 - 184: c301a783 lw x15,-976(x3) # 2780 <_uartaddr> + 184: c301a783 lw x15,-976(x3) # 2798 <_uartaddr> 188: 00878793 addi x15,x15,8 18c: 0007a703 lw x14,0(x15) - 190: c2e1ac23 sw x14,-968(x3) # 2788 <_uartstate> - 194: c381a703 lw x14,-968(x3) # 2788 <_uartstate> + 190: c2e1ac23 sw x14,-968(x3) # 27a0 <_uartstate> + 194: c381a703 lw x14,-968(x3) # 27a0 <_uartstate> 198: 000107b7 lui x15,0x10 19c: 00f777b3 and x15,x14,x15 1a0: 0017b793 sltiu x15,x15,1 1a4: 0ff7f793 andi x15,x15,255 - 1a8: 00078513 addi x10,x15,0 # 10000 <__global_pointer$+0xd4b0> + 1a8: 00078513 addi x10,x15,0 # 10000 <__global_pointer$+0xd498> 1ac: 00c12403 lw x8,12(x2) 1b0: 01010113 addi x2,x2,16 1b4: 00008067 jalr x0,0(x1) @@ -102,14 +102,14 @@ Disassembly of section .text: 1bc: 00812e23 sw x8,28(x2) 1c0: 02010413 addi x8,x2,32 1c4: fea42623 sw x10,-20(x8) - 1c8: c301a783 lw x15,-976(x3) # 2780 <_uartaddr> + 1c8: c301a783 lw x15,-976(x3) # 2798 <_uartaddr> 1cc: 00878793 addi x15,x15,8 1d0: 0007a703 lw x14,0(x15) - 1d4: c2e1ac23 sw x14,-968(x3) # 2788 <_uartstate> - 1d8: c381a783 lw x15,-968(x3) # 2788 <_uartstate> + 1d4: c2e1ac23 sw x14,-968(x3) # 27a0 <_uartstate> + 1d8: c381a783 lw x15,-968(x3) # 27a0 <_uartstate> 1dc: 0017f793 andi x15,x15,1 1e0: 00079e63 bne x15,x0,1fc <_putchar+0x44> - 1e4: c301a783 lw x15,-976(x3) # 2780 <_uartaddr> + 1e4: c301a783 lw x15,-976(x3) # 2798 <_uartaddr> 1e8: 00478793 addi x15,x15,4 1ec: fec42703 lw x14,-20(x8) 1f0: 00e7a023 sw x14,0(x15) @@ -125,16 +125,16 @@ Disassembly of section .text: 210: ff010113 addi x2,x2,-16 214: 00812623 sw x8,12(x2) 218: 01010413 addi x8,x2,16 - 21c: c301a783 lw x15,-976(x3) # 2780 <_uartaddr> + 21c: c301a783 lw x15,-976(x3) # 2798 <_uartaddr> 220: 00878793 addi x15,x15,8 224: 0007a703 lw x14,0(x15) - 228: c2e1ac23 sw x14,-968(x3) # 2788 <_uartstate> - 22c: c381a703 lw x14,-968(x3) # 2788 <_uartstate> + 228: c2e1ac23 sw x14,-968(x3) # 27a0 <_uartstate> + 22c: c381a703 lw x14,-968(x3) # 27a0 <_uartstate> 230: 000107b7 lui x15,0x10 234: 00f777b3 and x15,x14,x15 238: 00079863 bne x15,x0,248 <_getchar+0x38> - 23c: c301a783 lw x15,-976(x3) # 2780 <_uartaddr> - 240: 0007a783 lw x15,0(x15) # 10000 <__global_pointer$+0xd4b0> + 23c: c301a783 lw x15,-976(x3) # 2798 <_uartaddr> + 240: 0007a783 lw x15,0(x15) # 10000 <__global_pointer$+0xd498> 244: 0080006f jal x0,24c <_getchar+0x3c> 248: fff00793 addi x15,x0,-1 24c: 00078513 addi x10,x15,0 @@ -724,10 +724,10 @@ Disassembly of section .text: b0c: 02010413 addi x8,x2,32 b10: fea42623 sw x10,-20(x8) b14: 02faf7b7 lui x15,0x2faf - b18: 08078713 addi x14,x15,128 # 2faf080 <__global_pointer$+0x2fac530> + b18: 08078713 addi x14,x15,128 # 2faf080 <__global_pointer$+0x2fac518> b1c: fec42783 lw x15,-20(x8) b20: 02f74733 div x14,x14,x15 - b24: c301a783 lw x15,-976(x3) # 2780 <_uartaddr> + b24: c301a783 lw x15,-976(x3) # 2798 <_uartaddr> b28: 01078793 addi x15,x15,16 b2c: 00e7a023 sw x14,0(x15) b30: 00000793 addi x15,x0,0 @@ -741,7 +741,7 @@ Disassembly of section .text: b48: 12112e23 sw x1,316(x2) b4c: 12812c23 sw x8,312(x2) b50: 14010413 addi x8,x2,320 - b54: c3c1a783 lw x15,-964(x3) # 278c + b54: c3c1a783 lw x15,-964(x3) # 27a4 b58: ff07f793 andi x15,x15,-16 b5c: fef42223 sw x15,-28(x8) b60: fe042423 sw x0,-24(x8) @@ -754,7 +754,7 @@ Disassembly of section .text: b7c: 97dff0ef jal x1,4f8 <_h2s> b80: ed840713 addi x14,x8,-296 b84: 000017b7 lui x15,0x1 - b88: 2b878593 addi x11,x15,696 # 12b8 <__errno+0x8> + b88: 2d078593 addi x11,x15,720 # 12d0 <__errno+0x8> b8c: 00070513 addi x10,x14,0 b90: de1ff0ef jal x1,970 <_strcat> b94: fea42023 sw x10,-32(x8) @@ -765,11 +765,11 @@ Disassembly of section .text: ba8: fec42703 lw x14,-20(x8) bac: fe442783 lw x15,-28(x8) bb0: 00f70733 add x14,x14,x15 - bb4: c3c1a783 lw x15,-964(x3) # 278c + bb4: c3c1a783 lw x15,-964(x3) # 27a4 bb8: 02f77063 bgeu x14,x15,bd8 bbc: ed840713 addi x14,x8,-296 bc0: 000017b7 lui x15,0x1 - bc4: 2bc78593 addi x11,x15,700 # 12bc <__errno+0xc> + bc4: 2d478593 addi x11,x15,724 # 12d4 <__errno+0xc> bc8: 00070513 addi x10,x14,0 bcc: da5ff0ef jal x1,970 <_strcat> bd0: fea42023 sw x10,-32(x8) @@ -787,7 +787,7 @@ Disassembly of section .text: c00: 8f9ff0ef jal x1,4f8 <_h2s> c04: ed040713 addi x14,x8,-304 c08: 000017b7 lui x15,0x1 - c0c: 2c078593 addi x11,x15,704 # 12c0 <__errno+0x10> + c0c: 2d878593 addi x11,x15,728 # 12d8 <__errno+0x10> c10: 00070513 addi x10,x14,0 c14: d5dff0ef jal x1,970 <_strcat> c18: ed040713 addi x14,x8,-304 @@ -801,7 +801,7 @@ Disassembly of section .text: c38: 00f71c63 bne x14,x15,c50 c3c: ed840713 addi x14,x8,-296 c40: 000017b7 lui x15,0x1 - c44: 2c478593 addi x11,x15,708 # 12c4 <__errno+0x14> + c44: 2dc78593 addi x11,x15,732 # 12dc <__errno+0x14> c48: 00070513 addi x10,x14,0 c4c: d25ff0ef jal x1,970 <_strcat> c50: fec42783 lw x15,-20(x8) @@ -812,7 +812,7 @@ Disassembly of section .text: c64: f2e7dee3 bge x15,x14,ba0 c68: ed840713 addi x14,x8,-296 c6c: 000017b7 lui x15,0x1 - c70: 2c878593 addi x11,x15,712 # 12c8 <__errno+0x18> + c70: 2e078593 addi x11,x15,736 # 12e0 <__errno+0x18> c74: 00070513 addi x10,x14,0 c78: cf9ff0ef jal x1,970 <_strcat> c7c: fe042623 sw x0,-20(x8) @@ -837,7 +837,7 @@ Disassembly of section .text: cc8: 0007c783 lbu x15,0(x15) ccc: ecf40623 sb x15,-308(x8) cd0: 00c0006f jal x0,cdc - cd4: 02000793 addi x15,x0,32 + cd4: 02e00793 addi x15,x0,46 cd8: ecf40623 sb x15,-308(x8) cdc: ec0406a3 sb x0,-307(x8) ce0: ecc40713 addi x14,x8,-308 @@ -853,7 +853,7 @@ Disassembly of section .text: d08: f6e7dee3 bge x15,x14,c84 d0c: ed840713 addi x14,x8,-296 d10: 000017b7 lui x15,0x1 - d14: 2cc78593 addi x11,x15,716 # 12cc <__errno+0x1c> + d14: 2e478593 addi x11,x15,740 # 12e4 <__errno+0x1c> d18: 00070513 addi x10,x14,0 d1c: c55ff0ef jal x1,970 <_strcat> d20: ed840793 addi x15,x8,-296 @@ -874,10 +874,10 @@ Disassembly of section .text: d5c: 0080006f jal x0,d64 d60: 00000013 addi x0,x0,0 d64: 000017b7 lui x15,0x1 - d68: 2d078513 addi x10,x15,720 # 12d0 <__errno+0x20> + d68: 2e878513 addi x10,x15,744 # 12e8 <__errno+0x20> d6c: cf0ff0ef jal x1,25c <_puts> d70: fe442703 lw x14,-28(x8) - d74: c2e1ae23 sw x14,-964(x3) # 278c + d74: c2e1ae23 sw x14,-964(x3) # 27a4 d78: 00000013 addi x0,x0,0 d7c: 13c12083 lw x1,316(x2) d80: 13812403 lw x8,312(x2) @@ -892,496 +892,504 @@ Disassembly of section .text: d9c: eca42e23 sw x10,-292(x8) da0: ecb42c23 sw x11,-296(x8) da4: 0001c7b7 lui x15,0x1c - da8: 20078513 addi x10,x15,512 # 1c200 <__global_pointer$+0x196b0> + da8: 20078513 addi x10,x15,512 # 1c200 <__global_pointer$+0x19698> dac: d59ff0ef jal x1,b04 <_buadrateset> db0: 000017b7 lui x15,0x1 - db4: 2d478513 addi x10,x15,724 # 12d4 <__errno+0x24> + db4: 2ec78513 addi x10,x15,748 # 12ec <__errno+0x24> db8: ca4ff0ef jal x1,25c <_puts> dbc: 000017b7 lui x15,0x1 - dc0: 2e478513 addi x10,x15,740 # 12e4 <__errno+0x34> + dc0: 2fc78513 addi x10,x15,764 # 12fc <__errno+0x34> dc4: c98ff0ef jal x1,25c <_puts> dc8: ee840793 addi x15,x8,-280 dcc: 0ff00593 addi x11,x0,255 dd0: 00078513 addi x10,x15,0 dd4: cf0ff0ef jal x1,2c4 <_gets> - dd8: ee840713 addi x14,x8,-280 - ddc: 00400613 addi x12,x0,4 - de0: 000017b7 lui x15,0x1 - de4: 2e878593 addi x11,x15,744 # 12e8 <__errno+0x38> - de8: 00070513 addi x10,x14,0 - dec: c81ff0ef jal x1,a6c <_strncmp> - df0: 00050793 addi x15,x10,0 - df4: 02079063 bne x15,x0,e14 + dd8: 000017b7 lui x15,0x1 + ddc: 30078513 addi x10,x15,768 # 1300 <__errno+0x38> + de0: c7cff0ef jal x1,25c <_puts> + de4: ee840793 addi x15,x8,-280 + de8: 00078513 addi x10,x15,0 + dec: c70ff0ef jal x1,25c <_puts> + df0: ee840713 addi x14,x8,-280 + df4: 00400613 addi x12,x0,4 df8: 000017b7 lui x15,0x1 - dfc: 2f078513 addi x10,x15,752 # 12f0 <__errno+0x40> - e00: c5cff0ef jal x1,25c <_puts> - e04: 000017b7 lui x15,0x1 - e08: 31078513 addi x10,x15,784 # 1310 <__errno+0x60> - e0c: c50ff0ef jal x1,25c <_puts> - e10: fadff06f jal x0,dbc - e14: ee840713 addi x14,x8,-280 - e18: 00100613 addi x12,x0,1 + dfc: 30478593 addi x11,x15,772 # 1304 <__errno+0x3c> + e00: 00070513 addi x10,x14,0 + e04: c69ff0ef jal x1,a6c <_strncmp> + e08: 00050793 addi x15,x10,0 + e0c: 02079063 bne x15,x0,e2c + e10: 000017b7 lui x15,0x1 + e14: 30c78513 addi x10,x15,780 # 130c <__errno+0x44> + e18: c44ff0ef jal x1,25c <_puts> e1c: 000017b7 lui x15,0x1 - e20: 33478593 addi x11,x15,820 # 1334 <__errno+0x84> - e24: 00070513 addi x10,x14,0 - e28: c45ff0ef jal x1,a6c <_strncmp> - e2c: 00050793 addi x15,x10,0 - e30: 02079863 bne x15,x0,e60 - e34: ee840793 addi x15,x8,-280 - e38: 00278793 addi x15,x15,2 - e3c: 00000593 addi x11,x0,0 - e40: 00078513 addi x10,x15,0 - e44: 839ff0ef jal x1,67c <_s2d> - e48: fea42423 sw x10,-24(x8) - e4c: fe842783 lw x15,-24(x8) - e50: f6f056e3 bge x0,x15,dbc - e54: fe842503 lw x10,-24(x8) - e58: cadff0ef jal x1,b04 <_buadrateset> - e5c: f61ff06f jal x0,dbc - e60: ee840713 addi x14,x8,-280 - e64: 00100613 addi x12,x0,1 - e68: 000017b7 lui x15,0x1 - e6c: 33878593 addi x11,x15,824 # 1338 <__errno+0x88> - e70: 00070513 addi x10,x14,0 - e74: bf9ff0ef jal x1,a6c <_strncmp> - e78: 00050793 addi x15,x10,0 - e7c: f40790e3 bne x15,x0,dbc - e80: ee840793 addi x15,x8,-280 - e84: 00278793 addi x15,x15,2 - e88: 00000593 addi x11,x0,0 - e8c: 00078513 addi x10,x15,0 - e90: 8e9ff0ef jal x1,778 <_s2h> - e94: fea42623 sw x10,-20(x8) - e98: fec42783 lw x15,-20(x8) - e9c: 00f05663 bge x0,x15,ea8 - ea0: fec42703 lw x14,-20(x8) - ea4: c2e1ae23 sw x14,-964(x3) # 278c - ea8: c9dff0ef jal x1,b44 - eac: f11ff06f jal x0,dbc + e20: 32c78513 addi x10,x15,812 # 132c <__errno+0x64> + e24: c38ff0ef jal x1,25c <_puts> + e28: f95ff06f jal x0,dbc + e2c: ee840713 addi x14,x8,-280 + e30: 00100613 addi x12,x0,1 + e34: 000017b7 lui x15,0x1 + e38: 35078593 addi x11,x15,848 # 1350 <__errno+0x88> + e3c: 00070513 addi x10,x14,0 + e40: c2dff0ef jal x1,a6c <_strncmp> + e44: 00050793 addi x15,x10,0 + e48: 02079863 bne x15,x0,e78 + e4c: ee840793 addi x15,x8,-280 + e50: 00278793 addi x15,x15,2 + e54: 00000593 addi x11,x0,0 + e58: 00078513 addi x10,x15,0 + e5c: 821ff0ef jal x1,67c <_s2d> + e60: fea42423 sw x10,-24(x8) + e64: fe842783 lw x15,-24(x8) + e68: f4f05ae3 bge x0,x15,dbc + e6c: fe842503 lw x10,-24(x8) + e70: c95ff0ef jal x1,b04 <_buadrateset> + e74: f49ff06f jal x0,dbc + e78: ee840713 addi x14,x8,-280 + e7c: 00100613 addi x12,x0,1 + e80: 000017b7 lui x15,0x1 + e84: 35478593 addi x11,x15,852 # 1354 <__errno+0x8c> + e88: 00070513 addi x10,x14,0 + e8c: be1ff0ef jal x1,a6c <_strncmp> + e90: 00050793 addi x15,x10,0 + e94: f20794e3 bne x15,x0,dbc + e98: ee840793 addi x15,x8,-280 + e9c: 00278793 addi x15,x15,2 + ea0: 00000593 addi x11,x0,0 + ea4: 00078513 addi x10,x15,0 + ea8: 8d1ff0ef jal x1,778 <_s2h> + eac: fea42623 sw x10,-20(x8) + eb0: fec42783 lw x15,-20(x8) + eb4: 00f05663 bge x0,x15,ec0 + eb8: fec42703 lw x14,-20(x8) + ebc: c2e1ae23 sw x14,-964(x3) # 27a4 + ec0: c85ff0ef jal x1,b44 + ec4: ef9ff06f jal x0,dbc -00000eb0 : - eb0: ff010113 addi x2,x2,-16 - eb4: 00000593 addi x11,x0,0 - eb8: 00812423 sw x8,8(x2) - ebc: 00112623 sw x1,12(x2) - ec0: 00050413 addi x8,x10,0 - ec4: 194000ef jal x1,1058 <__call_exitprocs> - ec8: c281a503 lw x10,-984(x3) # 2778 <_global_impure_ptr> - ecc: 03c52783 lw x15,60(x10) - ed0: 00078463 beq x15,x0,ed8 - ed4: 000780e7 jalr x1,0(x15) - ed8: 00040513 addi x10,x8,0 - edc: 3a4000ef jal x1,1280 <_exit> +00000ec8 : + ec8: ff010113 addi x2,x2,-16 + ecc: 00000593 addi x11,x0,0 + ed0: 00812423 sw x8,8(x2) + ed4: 00112623 sw x1,12(x2) + ed8: 00050413 addi x8,x10,0 + edc: 194000ef jal x1,1070 <__call_exitprocs> + ee0: c281a503 lw x10,-984(x3) # 2790 <_global_impure_ptr> + ee4: 03c52783 lw x15,60(x10) + ee8: 00078463 beq x15,x0,ef0 + eec: 000780e7 jalr x1,0(x15) + ef0: 00040513 addi x10,x8,0 + ef4: 3a4000ef jal x1,1298 <_exit> -00000ee0 <__libc_init_array>: - ee0: ff010113 addi x2,x2,-16 - ee4: 00812423 sw x8,8(x2) - ee8: 01212023 sw x18,0(x2) - eec: 00002437 lui x8,0x2 - ef0: 00002937 lui x18,0x2 - ef4: 34040793 addi x15,x8,832 # 2340 <__init_array_start> - ef8: 34090913 addi x18,x18,832 # 2340 <__init_array_start> - efc: 40f90933 sub x18,x18,x15 - f00: 00112623 sw x1,12(x2) - f04: 00912223 sw x9,4(x2) - f08: 40295913 srai x18,x18,0x2 - f0c: 02090063 beq x18,x0,f2c <__libc_init_array+0x4c> - f10: 34040413 addi x8,x8,832 - f14: 00000493 addi x9,x0,0 - f18: 00042783 lw x15,0(x8) - f1c: 00148493 addi x9,x9,1 - f20: 00440413 addi x8,x8,4 - f24: 000780e7 jalr x1,0(x15) - f28: fe9918e3 bne x18,x9,f18 <__libc_init_array+0x38> - f2c: 00002437 lui x8,0x2 - f30: 00002937 lui x18,0x2 - f34: 34040793 addi x15,x8,832 # 2340 <__init_array_start> - f38: 34890913 addi x18,x18,840 # 2348 <__do_global_dtors_aux_fini_array_entry> - f3c: 40f90933 sub x18,x18,x15 - f40: 40295913 srai x18,x18,0x2 - f44: 02090063 beq x18,x0,f64 <__libc_init_array+0x84> - f48: 34040413 addi x8,x8,832 - f4c: 00000493 addi x9,x0,0 - f50: 00042783 lw x15,0(x8) - f54: 00148493 addi x9,x9,1 - f58: 00440413 addi x8,x8,4 - f5c: 000780e7 jalr x1,0(x15) - f60: fe9918e3 bne x18,x9,f50 <__libc_init_array+0x70> - f64: 00c12083 lw x1,12(x2) - f68: 00812403 lw x8,8(x2) - f6c: 00412483 lw x9,4(x2) - f70: 00012903 lw x18,0(x2) - f74: 01010113 addi x2,x2,16 - f78: 00008067 jalr x0,0(x1) +00000ef8 <__libc_init_array>: + ef8: ff010113 addi x2,x2,-16 + efc: 00812423 sw x8,8(x2) + f00: 01212023 sw x18,0(x2) + f04: 00002437 lui x8,0x2 + f08: 00002937 lui x18,0x2 + f0c: 35c40793 addi x15,x8,860 # 235c <__init_array_start> + f10: 35c90913 addi x18,x18,860 # 235c <__init_array_start> + f14: 40f90933 sub x18,x18,x15 + f18: 00112623 sw x1,12(x2) + f1c: 00912223 sw x9,4(x2) + f20: 40295913 srai x18,x18,0x2 + f24: 02090063 beq x18,x0,f44 <__libc_init_array+0x4c> + f28: 35c40413 addi x8,x8,860 + f2c: 00000493 addi x9,x0,0 + f30: 00042783 lw x15,0(x8) + f34: 00148493 addi x9,x9,1 + f38: 00440413 addi x8,x8,4 + f3c: 000780e7 jalr x1,0(x15) + f40: fe9918e3 bne x18,x9,f30 <__libc_init_array+0x38> + f44: 00002437 lui x8,0x2 + f48: 00002937 lui x18,0x2 + f4c: 35c40793 addi x15,x8,860 # 235c <__init_array_start> + f50: 36490913 addi x18,x18,868 # 2364 <__do_global_dtors_aux_fini_array_entry> + f54: 40f90933 sub x18,x18,x15 + f58: 40295913 srai x18,x18,0x2 + f5c: 02090063 beq x18,x0,f7c <__libc_init_array+0x84> + f60: 35c40413 addi x8,x8,860 + f64: 00000493 addi x9,x0,0 + f68: 00042783 lw x15,0(x8) + f6c: 00148493 addi x9,x9,1 + f70: 00440413 addi x8,x8,4 + f74: 000780e7 jalr x1,0(x15) + f78: fe9918e3 bne x18,x9,f68 <__libc_init_array+0x70> + f7c: 00c12083 lw x1,12(x2) + f80: 00812403 lw x8,8(x2) + f84: 00412483 lw x9,4(x2) + f88: 00012903 lw x18,0(x2) + f8c: 01010113 addi x2,x2,16 + f90: 00008067 jalr x0,0(x1) -00000f7c : - f7c: 00f00313 addi x6,x0,15 - f80: 00050713 addi x14,x10,0 - f84: 02c37e63 bgeu x6,x12,fc0 - f88: 00f77793 andi x15,x14,15 - f8c: 0a079063 bne x15,x0,102c - f90: 08059263 bne x11,x0,1014 - f94: ff067693 andi x13,x12,-16 - f98: 00f67613 andi x12,x12,15 - f9c: 00e686b3 add x13,x13,x14 - fa0: 00b72023 sw x11,0(x14) - fa4: 00b72223 sw x11,4(x14) - fa8: 00b72423 sw x11,8(x14) - fac: 00b72623 sw x11,12(x14) - fb0: 01070713 addi x14,x14,16 - fb4: fed766e3 bltu x14,x13,fa0 - fb8: 00061463 bne x12,x0,fc0 - fbc: 00008067 jalr x0,0(x1) - fc0: 40c306b3 sub x13,x6,x12 - fc4: 00269693 slli x13,x13,0x2 - fc8: 00000297 auipc x5,0x0 - fcc: 005686b3 add x13,x13,x5 - fd0: 00c68067 jalr x0,12(x13) - fd4: 00b70723 sb x11,14(x14) - fd8: 00b706a3 sb x11,13(x14) - fdc: 00b70623 sb x11,12(x14) - fe0: 00b705a3 sb x11,11(x14) - fe4: 00b70523 sb x11,10(x14) - fe8: 00b704a3 sb x11,9(x14) - fec: 00b70423 sb x11,8(x14) - ff0: 00b703a3 sb x11,7(x14) - ff4: 00b70323 sb x11,6(x14) - ff8: 00b702a3 sb x11,5(x14) - ffc: 00b70223 sb x11,4(x14) - 1000: 00b701a3 sb x11,3(x14) - 1004: 00b70123 sb x11,2(x14) - 1008: 00b700a3 sb x11,1(x14) - 100c: 00b70023 sb x11,0(x14) - 1010: 00008067 jalr x0,0(x1) - 1014: 0ff5f593 andi x11,x11,255 - 1018: 00859693 slli x13,x11,0x8 - 101c: 00d5e5b3 or x11,x11,x13 - 1020: 01059693 slli x13,x11,0x10 - 1024: 00d5e5b3 or x11,x11,x13 - 1028: f6dff06f jal x0,f94 - 102c: 00279693 slli x13,x15,0x2 - 1030: 00000297 auipc x5,0x0 - 1034: 005686b3 add x13,x13,x5 - 1038: 00008293 addi x5,x1,0 - 103c: fa0680e7 jalr x1,-96(x13) - 1040: 00028093 addi x1,x5,0 # 1030 - 1044: ff078793 addi x15,x15,-16 - 1048: 40f70733 sub x14,x14,x15 - 104c: 00f60633 add x12,x12,x15 - 1050: f6c378e3 bgeu x6,x12,fc0 - 1054: f3dff06f jal x0,f90 +00000f94 : + f94: 00f00313 addi x6,x0,15 + f98: 00050713 addi x14,x10,0 + f9c: 02c37e63 bgeu x6,x12,fd8 + fa0: 00f77793 andi x15,x14,15 + fa4: 0a079063 bne x15,x0,1044 + fa8: 08059263 bne x11,x0,102c + fac: ff067693 andi x13,x12,-16 + fb0: 00f67613 andi x12,x12,15 + fb4: 00e686b3 add x13,x13,x14 + fb8: 00b72023 sw x11,0(x14) + fbc: 00b72223 sw x11,4(x14) + fc0: 00b72423 sw x11,8(x14) + fc4: 00b72623 sw x11,12(x14) + fc8: 01070713 addi x14,x14,16 + fcc: fed766e3 bltu x14,x13,fb8 + fd0: 00061463 bne x12,x0,fd8 + fd4: 00008067 jalr x0,0(x1) + fd8: 40c306b3 sub x13,x6,x12 + fdc: 00269693 slli x13,x13,0x2 + fe0: 00000297 auipc x5,0x0 + fe4: 005686b3 add x13,x13,x5 + fe8: 00c68067 jalr x0,12(x13) + fec: 00b70723 sb x11,14(x14) + ff0: 00b706a3 sb x11,13(x14) + ff4: 00b70623 sb x11,12(x14) + ff8: 00b705a3 sb x11,11(x14) + ffc: 00b70523 sb x11,10(x14) + 1000: 00b704a3 sb x11,9(x14) + 1004: 00b70423 sb x11,8(x14) + 1008: 00b703a3 sb x11,7(x14) + 100c: 00b70323 sb x11,6(x14) + 1010: 00b702a3 sb x11,5(x14) + 1014: 00b70223 sb x11,4(x14) + 1018: 00b701a3 sb x11,3(x14) + 101c: 00b70123 sb x11,2(x14) + 1020: 00b700a3 sb x11,1(x14) + 1024: 00b70023 sb x11,0(x14) + 1028: 00008067 jalr x0,0(x1) + 102c: 0ff5f593 andi x11,x11,255 + 1030: 00859693 slli x13,x11,0x8 + 1034: 00d5e5b3 or x11,x11,x13 + 1038: 01059693 slli x13,x11,0x10 + 103c: 00d5e5b3 or x11,x11,x13 + 1040: f6dff06f jal x0,fac + 1044: 00279693 slli x13,x15,0x2 + 1048: 00000297 auipc x5,0x0 + 104c: 005686b3 add x13,x13,x5 + 1050: 00008293 addi x5,x1,0 + 1054: fa0680e7 jalr x1,-96(x13) + 1058: 00028093 addi x1,x5,0 # 1048 + 105c: ff078793 addi x15,x15,-16 + 1060: 40f70733 sub x14,x14,x15 + 1064: 00f60633 add x12,x12,x15 + 1068: f6c378e3 bgeu x6,x12,fd8 + 106c: f3dff06f jal x0,fa8 -00001058 <__call_exitprocs>: - 1058: fd010113 addi x2,x2,-48 - 105c: 01412c23 sw x20,24(x2) - 1060: c281aa03 lw x20,-984(x3) # 2778 <_global_impure_ptr> - 1064: 03212023 sw x18,32(x2) - 1068: 02112623 sw x1,44(x2) - 106c: 148a2903 lw x18,328(x20) - 1070: 02812423 sw x8,40(x2) - 1074: 02912223 sw x9,36(x2) - 1078: 01312e23 sw x19,28(x2) - 107c: 01512a23 sw x21,20(x2) - 1080: 01612823 sw x22,16(x2) - 1084: 01712623 sw x23,12(x2) - 1088: 01812423 sw x24,8(x2) - 108c: 04090063 beq x18,x0,10cc <__call_exitprocs+0x74> - 1090: 00050b13 addi x22,x10,0 - 1094: 00058b93 addi x23,x11,0 - 1098: 00100a93 addi x21,x0,1 - 109c: fff00993 addi x19,x0,-1 - 10a0: 00492483 lw x9,4(x18) - 10a4: fff48413 addi x8,x9,-1 - 10a8: 02044263 blt x8,x0,10cc <__call_exitprocs+0x74> - 10ac: 00249493 slli x9,x9,0x2 - 10b0: 009904b3 add x9,x18,x9 - 10b4: 040b8463 beq x23,x0,10fc <__call_exitprocs+0xa4> - 10b8: 1044a783 lw x15,260(x9) - 10bc: 05778063 beq x15,x23,10fc <__call_exitprocs+0xa4> - 10c0: fff40413 addi x8,x8,-1 - 10c4: ffc48493 addi x9,x9,-4 - 10c8: ff3416e3 bne x8,x19,10b4 <__call_exitprocs+0x5c> - 10cc: 02c12083 lw x1,44(x2) - 10d0: 02812403 lw x8,40(x2) - 10d4: 02412483 lw x9,36(x2) - 10d8: 02012903 lw x18,32(x2) - 10dc: 01c12983 lw x19,28(x2) - 10e0: 01812a03 lw x20,24(x2) - 10e4: 01412a83 lw x21,20(x2) - 10e8: 01012b03 lw x22,16(x2) - 10ec: 00c12b83 lw x23,12(x2) - 10f0: 00812c03 lw x24,8(x2) - 10f4: 03010113 addi x2,x2,48 - 10f8: 00008067 jalr x0,0(x1) - 10fc: 00492783 lw x15,4(x18) - 1100: 0044a683 lw x13,4(x9) - 1104: fff78793 addi x15,x15,-1 - 1108: 04878e63 beq x15,x8,1164 <__call_exitprocs+0x10c> - 110c: 0004a223 sw x0,4(x9) - 1110: fa0688e3 beq x13,x0,10c0 <__call_exitprocs+0x68> - 1114: 18892783 lw x15,392(x18) - 1118: 008a9733 sll x14,x21,x8 - 111c: 00492c03 lw x24,4(x18) - 1120: 00f777b3 and x15,x14,x15 - 1124: 02079263 bne x15,x0,1148 <__call_exitprocs+0xf0> - 1128: 000680e7 jalr x1,0(x13) - 112c: 00492703 lw x14,4(x18) - 1130: 148a2783 lw x15,328(x20) - 1134: 01871463 bne x14,x24,113c <__call_exitprocs+0xe4> - 1138: f92784e3 beq x15,x18,10c0 <__call_exitprocs+0x68> - 113c: f80788e3 beq x15,x0,10cc <__call_exitprocs+0x74> - 1140: 00078913 addi x18,x15,0 - 1144: f5dff06f jal x0,10a0 <__call_exitprocs+0x48> - 1148: 18c92783 lw x15,396(x18) - 114c: 0844a583 lw x11,132(x9) - 1150: 00f77733 and x14,x14,x15 - 1154: 00071c63 bne x14,x0,116c <__call_exitprocs+0x114> - 1158: 000b0513 addi x10,x22,0 - 115c: 000680e7 jalr x1,0(x13) - 1160: fcdff06f jal x0,112c <__call_exitprocs+0xd4> - 1164: 00892223 sw x8,4(x18) - 1168: fa9ff06f jal x0,1110 <__call_exitprocs+0xb8> - 116c: 00058513 addi x10,x11,0 - 1170: 000680e7 jalr x1,0(x13) - 1174: fb9ff06f jal x0,112c <__call_exitprocs+0xd4> +00001070 <__call_exitprocs>: + 1070: fd010113 addi x2,x2,-48 + 1074: 01412c23 sw x20,24(x2) + 1078: c281aa03 lw x20,-984(x3) # 2790 <_global_impure_ptr> + 107c: 03212023 sw x18,32(x2) + 1080: 02112623 sw x1,44(x2) + 1084: 148a2903 lw x18,328(x20) + 1088: 02812423 sw x8,40(x2) + 108c: 02912223 sw x9,36(x2) + 1090: 01312e23 sw x19,28(x2) + 1094: 01512a23 sw x21,20(x2) + 1098: 01612823 sw x22,16(x2) + 109c: 01712623 sw x23,12(x2) + 10a0: 01812423 sw x24,8(x2) + 10a4: 04090063 beq x18,x0,10e4 <__call_exitprocs+0x74> + 10a8: 00050b13 addi x22,x10,0 + 10ac: 00058b93 addi x23,x11,0 + 10b0: 00100a93 addi x21,x0,1 + 10b4: fff00993 addi x19,x0,-1 + 10b8: 00492483 lw x9,4(x18) + 10bc: fff48413 addi x8,x9,-1 + 10c0: 02044263 blt x8,x0,10e4 <__call_exitprocs+0x74> + 10c4: 00249493 slli x9,x9,0x2 + 10c8: 009904b3 add x9,x18,x9 + 10cc: 040b8463 beq x23,x0,1114 <__call_exitprocs+0xa4> + 10d0: 1044a783 lw x15,260(x9) + 10d4: 05778063 beq x15,x23,1114 <__call_exitprocs+0xa4> + 10d8: fff40413 addi x8,x8,-1 + 10dc: ffc48493 addi x9,x9,-4 + 10e0: ff3416e3 bne x8,x19,10cc <__call_exitprocs+0x5c> + 10e4: 02c12083 lw x1,44(x2) + 10e8: 02812403 lw x8,40(x2) + 10ec: 02412483 lw x9,36(x2) + 10f0: 02012903 lw x18,32(x2) + 10f4: 01c12983 lw x19,28(x2) + 10f8: 01812a03 lw x20,24(x2) + 10fc: 01412a83 lw x21,20(x2) + 1100: 01012b03 lw x22,16(x2) + 1104: 00c12b83 lw x23,12(x2) + 1108: 00812c03 lw x24,8(x2) + 110c: 03010113 addi x2,x2,48 + 1110: 00008067 jalr x0,0(x1) + 1114: 00492783 lw x15,4(x18) + 1118: 0044a683 lw x13,4(x9) + 111c: fff78793 addi x15,x15,-1 + 1120: 04878e63 beq x15,x8,117c <__call_exitprocs+0x10c> + 1124: 0004a223 sw x0,4(x9) + 1128: fa0688e3 beq x13,x0,10d8 <__call_exitprocs+0x68> + 112c: 18892783 lw x15,392(x18) + 1130: 008a9733 sll x14,x21,x8 + 1134: 00492c03 lw x24,4(x18) + 1138: 00f777b3 and x15,x14,x15 + 113c: 02079263 bne x15,x0,1160 <__call_exitprocs+0xf0> + 1140: 000680e7 jalr x1,0(x13) + 1144: 00492703 lw x14,4(x18) + 1148: 148a2783 lw x15,328(x20) + 114c: 01871463 bne x14,x24,1154 <__call_exitprocs+0xe4> + 1150: f92784e3 beq x15,x18,10d8 <__call_exitprocs+0x68> + 1154: f80788e3 beq x15,x0,10e4 <__call_exitprocs+0x74> + 1158: 00078913 addi x18,x15,0 + 115c: f5dff06f jal x0,10b8 <__call_exitprocs+0x48> + 1160: 18c92783 lw x15,396(x18) + 1164: 0844a583 lw x11,132(x9) + 1168: 00f77733 and x14,x14,x15 + 116c: 00071c63 bne x14,x0,1184 <__call_exitprocs+0x114> + 1170: 000b0513 addi x10,x22,0 + 1174: 000680e7 jalr x1,0(x13) + 1178: fcdff06f jal x0,1144 <__call_exitprocs+0xd4> + 117c: 00892223 sw x8,4(x18) + 1180: fa9ff06f jal x0,1128 <__call_exitprocs+0xb8> + 1184: 00058513 addi x10,x11,0 + 1188: 000680e7 jalr x1,0(x13) + 118c: fb9ff06f jal x0,1144 <__call_exitprocs+0xd4> -00001178 <__libc_fini_array>: - 1178: ff010113 addi x2,x2,-16 - 117c: 00812423 sw x8,8(x2) - 1180: 000027b7 lui x15,0x2 - 1184: 00002437 lui x8,0x2 - 1188: 34878793 addi x15,x15,840 # 2348 <__do_global_dtors_aux_fini_array_entry> - 118c: 34c40413 addi x8,x8,844 # 234c <__fini_array_end> - 1190: 40f40433 sub x8,x8,x15 - 1194: 00912223 sw x9,4(x2) - 1198: 00112623 sw x1,12(x2) - 119c: 40245493 srai x9,x8,0x2 - 11a0: 02048063 beq x9,x0,11c0 <__libc_fini_array+0x48> - 11a4: ffc40413 addi x8,x8,-4 - 11a8: 00f40433 add x8,x8,x15 - 11ac: 00042783 lw x15,0(x8) - 11b0: fff48493 addi x9,x9,-1 - 11b4: ffc40413 addi x8,x8,-4 - 11b8: 000780e7 jalr x1,0(x15) - 11bc: fe0498e3 bne x9,x0,11ac <__libc_fini_array+0x34> - 11c0: 00c12083 lw x1,12(x2) - 11c4: 00812403 lw x8,8(x2) - 11c8: 00412483 lw x9,4(x2) - 11cc: 01010113 addi x2,x2,16 - 11d0: 00008067 jalr x0,0(x1) +00001190 <__libc_fini_array>: + 1190: ff010113 addi x2,x2,-16 + 1194: 00812423 sw x8,8(x2) + 1198: 000027b7 lui x15,0x2 + 119c: 00002437 lui x8,0x2 + 11a0: 36478793 addi x15,x15,868 # 2364 <__do_global_dtors_aux_fini_array_entry> + 11a4: 36840413 addi x8,x8,872 # 2368 + 11a8: 40f40433 sub x8,x8,x15 + 11ac: 00912223 sw x9,4(x2) + 11b0: 00112623 sw x1,12(x2) + 11b4: 40245493 srai x9,x8,0x2 + 11b8: 02048063 beq x9,x0,11d8 <__libc_fini_array+0x48> + 11bc: ffc40413 addi x8,x8,-4 + 11c0: 00f40433 add x8,x8,x15 + 11c4: 00042783 lw x15,0(x8) + 11c8: fff48493 addi x9,x9,-1 + 11cc: ffc40413 addi x8,x8,-4 + 11d0: 000780e7 jalr x1,0(x15) + 11d4: fe0498e3 bne x9,x0,11c4 <__libc_fini_array+0x34> + 11d8: 00c12083 lw x1,12(x2) + 11dc: 00812403 lw x8,8(x2) + 11e0: 00412483 lw x9,4(x2) + 11e4: 01010113 addi x2,x2,16 + 11e8: 00008067 jalr x0,0(x1) -000011d4 : - 11d4: 00050593 addi x11,x10,0 - 11d8: 00000693 addi x13,x0,0 - 11dc: 00000613 addi x12,x0,0 - 11e0: 00000513 addi x10,x0,0 - 11e4: 0040006f jal x0,11e8 <__register_exitproc> +000011ec : + 11ec: 00050593 addi x11,x10,0 + 11f0: 00000693 addi x13,x0,0 + 11f4: 00000613 addi x12,x0,0 + 11f8: 00000513 addi x10,x0,0 + 11fc: 0040006f jal x0,1200 <__register_exitproc> -000011e8 <__register_exitproc>: - 11e8: c281a703 lw x14,-984(x3) # 2778 <_global_impure_ptr> - 11ec: 14872783 lw x15,328(x14) - 11f0: 04078c63 beq x15,x0,1248 <__register_exitproc+0x60> - 11f4: 0047a703 lw x14,4(x15) - 11f8: 01f00813 addi x16,x0,31 - 11fc: 06e84e63 blt x16,x14,1278 <__register_exitproc+0x90> - 1200: 00271813 slli x16,x14,0x2 - 1204: 02050663 beq x10,x0,1230 <__register_exitproc+0x48> - 1208: 01078333 add x6,x15,x16 - 120c: 08c32423 sw x12,136(x6) # 1b8 <_putchar> - 1210: 1887a883 lw x17,392(x15) - 1214: 00100613 addi x12,x0,1 - 1218: 00e61633 sll x12,x12,x14 - 121c: 00c8e8b3 or x17,x17,x12 - 1220: 1917a423 sw x17,392(x15) - 1224: 10d32423 sw x13,264(x6) - 1228: 00200693 addi x13,x0,2 - 122c: 02d50463 beq x10,x13,1254 <__register_exitproc+0x6c> - 1230: 00170713 addi x14,x14,1 - 1234: 00e7a223 sw x14,4(x15) - 1238: 010787b3 add x15,x15,x16 - 123c: 00b7a423 sw x11,8(x15) - 1240: 00000513 addi x10,x0,0 - 1244: 00008067 jalr x0,0(x1) - 1248: 14c70793 addi x15,x14,332 - 124c: 14f72423 sw x15,328(x14) - 1250: fa5ff06f jal x0,11f4 <__register_exitproc+0xc> - 1254: 18c7a683 lw x13,396(x15) - 1258: 00170713 addi x14,x14,1 - 125c: 00e7a223 sw x14,4(x15) - 1260: 00c6e6b3 or x13,x13,x12 - 1264: 18d7a623 sw x13,396(x15) - 1268: 010787b3 add x15,x15,x16 - 126c: 00b7a423 sw x11,8(x15) - 1270: 00000513 addi x10,x0,0 - 1274: 00008067 jalr x0,0(x1) - 1278: fff00513 addi x10,x0,-1 - 127c: 00008067 jalr x0,0(x1) +00001200 <__register_exitproc>: + 1200: c281a703 lw x14,-984(x3) # 2790 <_global_impure_ptr> + 1204: 14872783 lw x15,328(x14) + 1208: 04078c63 beq x15,x0,1260 <__register_exitproc+0x60> + 120c: 0047a703 lw x14,4(x15) + 1210: 01f00813 addi x16,x0,31 + 1214: 06e84e63 blt x16,x14,1290 <__register_exitproc+0x90> + 1218: 00271813 slli x16,x14,0x2 + 121c: 02050663 beq x10,x0,1248 <__register_exitproc+0x48> + 1220: 01078333 add x6,x15,x16 + 1224: 08c32423 sw x12,136(x6) # 1b8 <_putchar> + 1228: 1887a883 lw x17,392(x15) + 122c: 00100613 addi x12,x0,1 + 1230: 00e61633 sll x12,x12,x14 + 1234: 00c8e8b3 or x17,x17,x12 + 1238: 1917a423 sw x17,392(x15) + 123c: 10d32423 sw x13,264(x6) + 1240: 00200693 addi x13,x0,2 + 1244: 02d50463 beq x10,x13,126c <__register_exitproc+0x6c> + 1248: 00170713 addi x14,x14,1 + 124c: 00e7a223 sw x14,4(x15) + 1250: 010787b3 add x15,x15,x16 + 1254: 00b7a423 sw x11,8(x15) + 1258: 00000513 addi x10,x0,0 + 125c: 00008067 jalr x0,0(x1) + 1260: 14c70793 addi x15,x14,332 + 1264: 14f72423 sw x15,328(x14) + 1268: fa5ff06f jal x0,120c <__register_exitproc+0xc> + 126c: 18c7a683 lw x13,396(x15) + 1270: 00170713 addi x14,x14,1 + 1274: 00e7a223 sw x14,4(x15) + 1278: 00c6e6b3 or x13,x13,x12 + 127c: 18d7a623 sw x13,396(x15) + 1280: 010787b3 add x15,x15,x16 + 1284: 00b7a423 sw x11,8(x15) + 1288: 00000513 addi x10,x0,0 + 128c: 00008067 jalr x0,0(x1) + 1290: fff00513 addi x10,x0,-1 + 1294: 00008067 jalr x0,0(x1) -00001280 <_exit>: - 1280: 05d00893 addi x17,x0,93 - 1284: 00000073 ecall - 1288: 00054463 blt x10,x0,1290 <_exit+0x10> - 128c: 0000006f jal x0,128c <_exit+0xc> - 1290: ff010113 addi x2,x2,-16 - 1294: 00812423 sw x8,8(x2) - 1298: 00050413 addi x8,x10,0 - 129c: 00112623 sw x1,12(x2) - 12a0: 40800433 sub x8,x0,x8 - 12a4: 00c000ef jal x1,12b0 <__errno> - 12a8: 00852023 sw x8,0(x10) - 12ac: 0000006f jal x0,12ac <_exit+0x2c> +00001298 <_exit>: + 1298: 05d00893 addi x17,x0,93 + 129c: 00000073 ecall + 12a0: 00054463 blt x10,x0,12a8 <_exit+0x10> + 12a4: 0000006f jal x0,12a4 <_exit+0xc> + 12a8: ff010113 addi x2,x2,-16 + 12ac: 00812423 sw x8,8(x2) + 12b0: 00050413 addi x8,x10,0 + 12b4: 00112623 sw x1,12(x2) + 12b8: 40800433 sub x8,x0,x8 + 12bc: 00c000ef jal x1,12c8 <__errno> + 12c0: 00852023 sw x8,0(x10) + 12c4: 0000006f jal x0,12c4 <_exit+0x2c> -000012b0 <__errno>: - 12b0: c341a503 lw x10,-972(x3) # 2784 <_impure_ptr> - 12b4: 00008067 jalr x0,0(x1) +000012c8 <__errno>: + 12c8: c341a503 lw x10,-972(x3) # 279c <_impure_ptr> + 12cc: 00008067 jalr x0,0(x1) Disassembly of section .rodata: -000012b8 <.rodata>: - 12b8: 2020 c.fld f8,64(x8) - 12ba: 0000 c.unimp - 12bc: 2020 c.fld f8,64(x8) - 12be: 0020 c.addi4spn x8,x2,8 - 12c0: 0020 c.addi4spn x8,x2,8 - 12c2: 0000 c.unimp - 12c4: 202d c.jal 12ee <__errno+0x3e> - 12c6: 0000 c.unimp - 12c8: 2020 c.fld f8,64(x8) - 12ca: 007c c.addi4spn x15,x2,12 - 12cc: 0a7c c.addi4spn x15,x2,284 - 12ce: 0000 c.unimp - 12d0: 000a c.slli x0,0x2 +000012d0 <.rodata>: + 12d0: 2020 c.fld f8,64(x8) 12d2: 0000 c.unimp - 12d4: 6548 c.flw f10,12(x10) - 12d6: 6c6c c.flw f11,92(x8) - 12d8: 57202c6f jal x24,384a <__global_pointer$+0xcfa> - 12dc: 646c726f jal x4,c8922 <__global_pointer$+0xc5dd2> - 12e0: 000a c.slli x0,0x2 - 12e2: 0000 c.unimp - 12e4: 3e3e c.fldsp f28,488(x2) + 12d4: 2020 c.fld f8,64(x8) + 12d6: 0020 c.addi4spn x8,x2,8 + 12d8: 0020 c.addi4spn x8,x2,8 + 12da: 0000 c.unimp + 12dc: 202d c.jal 1306 <__errno+0x3e> + 12de: 0000 c.unimp + 12e0: 2020 c.fld f8,64(x8) + 12e2: 007c c.addi4spn x15,x2,12 + 12e4: 0a7c c.addi4spn x15,x2,284 12e6: 0000 c.unimp - 12e8: 6568 c.flw f10,76(x10) - 12ea: 706c c.flw f11,100(x8) - 12ec: 0020 c.addi4spn x8,x2,8 - 12ee: 0000 c.unimp - 12f0: 2020 c.fld f8,64(x8) - 12f2: 2064 c.fld f9,192(x8) - 12f4: 613c c.flw f15,64(x10) - 12f6: 6464 c.flw f9,76(x8) - 12f8: 3e72 c.fldsp f28,312(x2) - 12fa: 2d20 c.fld f8,88(x10) - 12fc: 202d c.jal 1326 <__errno+0x76> - 12fe: 6964 c.flw f9,84(x10) - 1300: 616c7073 csrrci x0,0x616,24 - 1304: 2079 c.jal 1392 <__errno+0xe2> - 1306: 656d c.lui x10,0x1b - 1308: 6f6d c.lui x30,0x1b - 130a: 7972 c.flwsp f18,60(x2) - 130c: 0a20 c.addi4spn x8,x2,280 - 130e: 0000 c.unimp - 1310: 2020 c.fld f8,64(x8) - 1312: 2062 c.fldsp f0,24(x2) - 1314: 623c c.flw f15,64(x12) - 1316: 7561 c.lui x10,0xffff8 - 1318: 7264 c.flw f9,100(x12) - 131a: 7461 c.lui x8,0xffff8 - 131c: 3e65 c.jal ed4 - 131e: 2d20 c.fld f8,88(x10) - 1320: 202d c.jal 134a <__errno+0x9a> - 1322: 20746573 csrrsi x10,0x207,8 - 1326: 6162 c.flwsp f2,24(x2) - 1328: 6475 c.lui x8,0x1d - 132a: 6172 c.flwsp f2,28(x2) - 132c: 6574 c.flw f13,76(x10) - 132e: 0a20 c.addi4spn x8,x2,280 - 1330: 0000 c.unimp - 1332: 0000 c.unimp - 1334: 0062 c.slli x0,0x18 - 1336: 0000 c.unimp - 1338: 0064 c.addi4spn x9,x2,12 + 12e8: 000a c.slli x0,0x2 + 12ea: 0000 c.unimp + 12ec: 6548 c.flw f10,12(x10) + 12ee: 6c6c c.flw f11,92(x8) + 12f0: 57202c6f jal x24,3862 <__global_pointer$+0xcfa> + 12f4: 646c726f jal x4,c893a <__global_pointer$+0xc5dd2> + 12f8: 000a c.slli x0,0x2 + 12fa: 0000 c.unimp + 12fc: 3e3e c.fldsp f28,488(x2) + 12fe: 0000 c.unimp + 1300: 003a c.slli x0,0xe + 1302: 0000 c.unimp + 1304: 6568 c.flw f10,76(x10) + 1306: 706c c.flw f11,100(x8) + 1308: 0020 c.addi4spn x8,x2,8 + 130a: 0000 c.unimp + 130c: 2020 c.fld f8,64(x8) + 130e: 2064 c.fld f9,192(x8) + 1310: 613c c.flw f15,64(x10) + 1312: 6464 c.flw f9,76(x8) + 1314: 3e72 c.fldsp f28,312(x2) + 1316: 2d20 c.fld f8,88(x10) + 1318: 202d c.jal 1342 <__errno+0x7a> + 131a: 6964 c.flw f9,84(x10) + 131c: 616c7073 csrrci x0,0x616,24 + 1320: 2079 c.jal 13ae <__errno+0xe6> + 1322: 656d c.lui x10,0x1b + 1324: 6f6d c.lui x30,0x1b + 1326: 7972 c.flwsp f18,60(x2) + 1328: 0a20 c.addi4spn x8,x2,280 + 132a: 0000 c.unimp + 132c: 2020 c.fld f8,64(x8) + 132e: 2062 c.fldsp f0,24(x2) + 1330: 623c c.flw f15,64(x12) + 1332: 7561 c.lui x10,0xffff8 + 1334: 7264 c.flw f9,100(x12) + 1336: 7461 c.lui x8,0xffff8 + 1338: 3e65 c.jal ef0 + 133a: 2d20 c.fld f8,88(x10) + 133c: 202d c.jal 1366 <__errno+0x9e> + 133e: 20746573 csrrsi x10,0x207,8 + 1342: 6162 c.flwsp f2,24(x2) + 1344: 6475 c.lui x8,0x1d + 1346: 6172 c.flwsp f2,28(x2) + 1348: 6574 c.flw f13,76(x10) + 134a: 0a20 c.addi4spn x8,x2,280 + 134c: 0000 c.unimp + 134e: 0000 c.unimp + 1350: 0062 c.slli x0,0x18 + 1352: 0000 c.unimp + 1354: 0064 c.addi4spn x9,x2,12 Disassembly of section .eh_frame: -0000233c <__FRAME_END__>: - 233c: 0000 c.unimp +00002358 <__FRAME_END__>: + 2358: 0000 c.unimp ... Disassembly of section .init_array: -00002340 <__init_array_start>: - 2340: 0074 c.addi4spn x13,x2,12 +0000235c <__init_array_start>: + 235c: 0074 c.addi4spn x13,x2,12 ... -00002344 <__frame_dummy_init_array_entry>: - 2344: 011c c.addi4spn x15,x2,128 +00002360 <__frame_dummy_init_array_entry>: + 2360: 011c c.addi4spn x15,x2,128 ... Disassembly of section .fini_array: -00002348 <__do_global_dtors_aux_fini_array_entry>: - 2348: 00d8 c.addi4spn x14,x2,68 +00002364 <__do_global_dtors_aux_fini_array_entry>: + 2364: 00d8 c.addi4spn x14,x2,68 ... Disassembly of section .data: -00002350 : - 2350: 0000 c.unimp - 2352: 0000 c.unimp - 2354: 263c c.fld f15,72(x12) - 2356: 0000 c.unimp - 2358: 26a4 c.fld f9,72(x13) - 235a: 0000 c.unimp - 235c: 270c c.fld f11,8(x14) +00002368 : + 2368: 0000 c.unimp + 236a: 0000 c.unimp + 236c: 2654 c.fld f13,136(x12) + 236e: 0000 c.unimp + 2370: 26bc c.fld f15,72(x13) + 2372: 0000 c.unimp + 2374: 2724 c.fld f9,72(x14) ... - 23f6: 0000 c.unimp - 23f8: 0001 c.addi x0,0 - 23fa: 0000 c.unimp - 23fc: 0000 c.unimp - 23fe: 0000 c.unimp - 2400: 330e c.fldsp f6,224(x2) - 2402: abcd c.j 29f4 <__BSS_END__+0x248> - 2404: 1234 c.addi4spn x13,x2,296 - 2406: e66d c.bnez x12,24f0 - 2408: deec c.sw x11,124(x13) - 240a: 0005 c.addi x0,1 - 240c: 0000000b 0xb + 240e: 0000 c.unimp + 2410: 0001 c.addi x0,0 + 2412: 0000 c.unimp + 2414: 0000 c.unimp + 2416: 0000 c.unimp + 2418: 330e c.fldsp f6,224(x2) + 241a: abcd c.j 2a0c <__BSS_END__+0x248> + 241c: 1234 c.addi4spn x13,x2,296 + 241e: e66d c.bnez x12,2508 + 2420: deec c.sw x11,124(x13) + 2422: 0005 c.addi x0,1 + 2424: 0000000b 0xb ... Disassembly of section .sdata: -00002778 <_global_impure_ptr>: - 2778: 2350 c.fld f12,128(x14) +00002790 <_global_impure_ptr>: + 2790: 2368 c.fld f10,192(x14) ... -0000277c <__dso_handle>: - 277c: 0000 c.unimp +00002794 <__dso_handle>: + 2794: 0000 c.unimp ... -00002780 <_uartaddr>: - 2780: 0100 c.addi4spn x8,x2,128 - 2782: f000 c.fsw f8,32(x8) +00002798 <_uartaddr>: + 2798: 0100 c.addi4spn x8,x2,128 + 279a: f000 c.fsw f8,32(x8) -00002784 <_impure_ptr>: - 2784: 2350 c.fld f12,128(x14) +0000279c <_impure_ptr>: + 279c: 2368 c.fld f10,192(x14) ... Disassembly of section .sbss: -00002788 <_uartstate>: - 2788: 0000 c.unimp +000027a0 <_uartstate>: + 27a0: 0000 c.unimp ... -0000278c : - 278c: 0000 c.unimp +000027a4 : + 27a4: 0000 c.unimp ... Disassembly of section .bss: -00002790 : - 2790: 0000 c.unimp +000027a8 : + 27a8: 0000 c.unimp ... -00002794 : +000027ac : ... Disassembly of section .comment: @@ -1398,18 +1406,19 @@ Disassembly of section .comment: Disassembly of section .riscv.attributes: 00000000 <.riscv.attributes>: - 0: 2541 c.jal 680 <_s2d+0x4> + 0: 2041 c.jal 80 2: 0000 c.unimp 4: 7200 c.flw f8,32(x12) 6: 7369 c.lui x6,0xffffa 8: 01007663 bgeu x0,x16,14 - c: 0000001b 0x1b + c: 0016 c.slli x0,0x5 + e: 0000 c.unimp 10: 1004 c.addi4spn x9,x2,32 12: 7205 c.lui x4,0xfffe1 14: 3376 c.fldsp f6,376(x2) 16: 6932 c.flwsp f18,12(x2) 18: 7032 c.flwsp f0,44(x2) 1a: 5f30 c.lw x12,120(x14) - 1c: 326d c.jal fffff9c6 <__global_pointer$+0xffffce76> + 1c: 326d c.jal fffff9c6 <__global_pointer$+0xffffce5e> 1e: 3070 c.fld f12,224(x8) - 20: 615f 7032 0030 0x307032615f + ... diff --git a/examples/hdl4se_riscv/verilog/riscv_core_v4.v b/examples/hdl4se_riscv/verilog/riscv_core_v4.v index 1a149ec28e7bcd83ea9eb672a893922f3951375e..05e5ee43ac96e9bf73c9e0f6ef1df0d6b7299752 100644 --- a/examples/hdl4se_riscv/verilog/riscv_core_v4.v +++ b/examples/hdl4se_riscv/verilog/riscv_core_v4.v @@ -31,13 +31,11 @@ */ /* riscv_core_v4.v */ -`define RISCVSTATE_INIT_REGX1 0 -`define RISCVSTATE_INIT_REGX2 1 -`define RISCVSTATE_READ_INST 2 -`define RISCVSTATE_EXEC_INST 3 -`define RISCVSTATE_WAIT_LD 4 -`define RISCVSTATE_WAIT_ST 5 -`define RISCVSTATE_WAIT_DIV 6 +`define RISCVSTATE_STARTUP 0 +`define RISCVSTATE_EXEC_INST 1 +`define RISCVSTATE_WAIT_LD 2 +`define RISCVSTATE_WAIT_ST 3 +`define RISCVSTATE_WAIT_DIV 4 `define RAMSIZE 4096 @@ -54,31 +52,10 @@ module riscv_core( output [3:0] bWriteMask, output reg wRead, output reg [31:0] bReadAddr, - input [31:0] bReadData, - output reg [4:0] regno, - output reg [3:0] regena, - output reg [31:0] regwrdata, - output reg regwren, - input [31:0] regrddata, - output reg [4:0] regno2, - output reg [3:0] regena2, - output reg [31:0] regwrdata2, - output reg regwren2, - input [31:0] regrddata2 + input [31:0] bReadData ); reg [31:0] pc; //GREG(pc, 32, riscv_core_reg_gen_pc); - reg write; //GREG(write, 1, riscv_core_gen_write); - reg [31:0] writeaddr; //GREG(writeaddr, 32, riscv_core_gen_write); - reg [31:0] writedata; //GREG(writedata, 32, riscv_core_gen_write); - reg [3:0] writemask; //GREG(writemask, 4, riscv_core_gen_write); - reg [4:0] readreg; //GREG(readreg, 5, riscv_core_reg_gen_readreg); - reg [3:0] state; //GREG(state, 4, riscv_core_gen_state); - reg [31:0] imm; //GREG(imm, 32, riscv_core_gen_imm); - reg [4:0] dstreg; //GREG(dstreg, 5, riscv_core_gen_dstreg); - reg [31:0] dstvalue; //GREG(dstvalue, 32, riscv_core_gen_dstreg); - reg [1:0] ldaddr; //GREG(ldaddr, 2, riscv_core_gen_ldaddr); - reg [4:0] divclk; reg [31:0] x1; reg [31:0] x2; @@ -112,11 +89,25 @@ module riscv_core( reg [31:0] x30; reg [31:0] x31; + reg [3:0] state; + + reg [31:0] imm; + reg [4:0] dstreg; + reg [31:0] dstvalue; + reg [4:0] divclk; + + reg write; + reg [31:0] writeaddr; + reg [31:0] writedata; + reg [3:0] writemask; + + assign wWrite = write; assign bWriteAddr = writeaddr; assign bWriteData = writedata; assign bWriteMask = writemask; + wire [31:0] instr = bReadData; wire [4:0] rs1_no = bReadData[19:15]; wire [4:0] rs2_no = bReadData[24:20]; @@ -231,7 +222,11 @@ module riscv_core( endcase always@(posedge wClk) - if (state == `RISCVSTATE_EXEC_INST) + if (~nwReset) begin + x1 <= 32'h0000008c; + x2 <= `RAMSIZE * 4 - 16; + end + else case (dstreg) 5'd0: ;//0 <= dstvalue; 5'd1: x1 <= dstvalue; @@ -278,137 +273,154 @@ module riscv_core( 7:/*bgeu*/cond = rs1 >= rs2; default: cond = 1'b0; endcase - - //DEFINE_FUNC(riscv_core_reg_gen_pc, "nwReset, state, instr, pc, rs1, imm, regrddata") { + always @(bReadData) + case (bReadData[6:2]) + 5'h0d: imm = {bReadData[31:12], 12'b0}; + 5'h05: imm = {bReadData[31:12], 12'b0}; + 5'h1b: imm = {{12{bReadData[31]}}, bReadData[19:12], bReadData[20], bReadData[30:21], 1'b0}; + 5'h19: imm = {{20{bReadData[31]}}, bReadData[31:20]}; + 5'h18: imm = {{20{bReadData[31]}}, bReadData[7], bReadData[30:25], bReadData[11:8], 1'b0}; + 5'h00: imm = {{20{bReadData[31]}}, bReadData[31:20]}; + 5'h08: imm = {{20{bReadData[31]}}, bReadData[31:25], bReadData[11:7]}; + 5'h04: imm = {{20{bReadData[31]}}, bReadData[31:20]}; + endcase + + + /* state */ + always @(posedge wClk) + if (!nwReset) begin + state <= `RISCVSTATE_STARTUP; + end else begin + case (state) + `RISCVSTATE_STARTUP: state <= `RISCVSTATE_EXEC_INST; + `RISCVSTATE_EXEC_INST: begin + if (opcode == 5'h00) + state <= `RISCVSTATE_WAIT_LD; + else if (opcode == 5'h08) + state <= `RISCVSTATE_WAIT_ST; + else if (opcode == 5'h0c && instr[25] && func3[2] && (rs2 != 0)) begin + state <= `RISCVSTATE_WAIT_DIV; + divclk <= 11; + end + end + `RISCVSTATE_WAIT_LD: state <= `RISCVSTATE_EXEC_INST; + `RISCVSTATE_WAIT_ST: state <= `RISCVSTATE_EXEC_INST; + `RISCVSTATE_WAIT_DIV: begin + if (divclk == 0) + state <= `RISCVSTATE_EXEC_INST; + else + divclk <= divclk - 1; + end + endcase + end + + reg [31:0] newpc; + always @(state or pc or rs1 or imm or cond or opcode) + if (state == `RISCVSTATE_EXEC_INST) begin + case (opcode) + 5'h1b: newpc = pc + imm; + 5'h19: newpc = rs1 + imm; + 5'h18: newpc = cond ? pc + imm : pc + 4; + default: newpc = pc + 4; + endcase + end else begin + newpc = pc; + end + + /* pc */ always @(posedge wClk) if (!nwReset) begin pc <= 32'h00000074; end else begin + pc <= newpc; + end + + /* read and readaddr */ + always @(state or pc or opcode or imm or rs1 or nwReset) + if (~nwReset) begin + wRead = 0; + bReadAddr = 0; + end else begin + wRead = 1; + bReadAddr = newpc; if (state == `RISCVSTATE_EXEC_INST) begin - case (opcode) - 5'h1b: pc <= pc + imm; - 5'h19: pc <= rs1 + imm; - 5'h18: pc <= cond ? pc + imm : pc + 4; - default: pc <= pc + 4; - endcase + if (opcode == 5'h00) begin /*LOAD*/ + wRead = 1; + bReadAddr = rs1 + imm; + end else if (opcode == 5'h08) begin /*STORE*/ + wRead = 0; + bReadAddr = 0; + end end end wire [31:0] newwriteaddr = rs1 + imm; - //DEFINE_FUNC(riscv_core_gen_write, "nwReset, state, pc, instr, rs1, regrddata, imm") { - always @(posedge wClk) - if (!nwReset) begin - write <= 0; - end else if (state == `RISCVSTATE_EXEC_INST) begin - write <= 0; - if (opcode == 5'h08) begin + + /* write */ + always @(nwReset or state or opcode or newwriteaddr or rs1 or imm or rs2) + begin + write = 0; + writeaddr = 0; + writemask = 0; + writedata = 0; + if (nwReset && (state == `RISCVSTATE_EXEC_INST) && (opcode == 5'h08)) begin /* riscv支持地址不对齐访问，但是假定写在一个32位字中 */ - writeaddr <= newwriteaddr; - writemask <= 4'h0; - writedata <= rs2; - write <= 1'b1; + writeaddr = newwriteaddr; + writemask = 4'h0; + writedata = rs2; + write = 1'b1; case (func3) 0:/*sb*/ begin case (newwriteaddr[1:0]) 0: begin - writemask <= 4'he; - writedata <= rs2; + writemask = 4'he; + writedata = rs2; end 1: begin - writemask <= 4'hd; - writedata <= {rs2[23:0], 8'h33}; + writemask = 4'hd; + writedata = {rs2[23:0], 8'h0}; end 2: begin - writemask <= 4'hb; - writedata <= {rs2[15:0], 16'h4455}; + writemask = 4'hb; + writedata = {rs2[15:0], 16'h0}; end 3: begin - writemask <= 4'h7; - writedata <= {rs2[7:0], 24'h667788}; + writemask = 4'h7; + writedata = {rs2[7:0], 24'h0}; end endcase end 1:/*sh*/ begin case (newwriteaddr[1:0]) 0: begin - writemask <= 4'hc; - writedata <= rs2; + writemask = 4'hc; + writedata = rs2; end 1: begin - writemask <= 4'h9; - writedata <= {rs2[23:0], 8'h40}; + writemask = 4'h9; + writedata = {rs2[23:0], 8'h0}; end 2: begin - writemask <= 4'h3; - writedata <= {rs2[15:0], 16'h0307}; + writemask = 4'h3; + writedata = {rs2[15:0], 16'h0}; end endcase end endcase end - end else begin - write <= 0; - end - - //DEFINE_FUNC(riscv_core_gen_state, "state, instr, nwReset") { - always @(posedge wClk) - if (!nwReset) begin - state <= `RISCVSTATE_INIT_REGX1; - end else begin - case (state) - `RISCVSTATE_INIT_REGX1: state <= `RISCVSTATE_INIT_REGX2; - `RISCVSTATE_INIT_REGX2: state <= `RISCVSTATE_READ_INST; - `RISCVSTATE_READ_INST: state <= `RISCVSTATE_EXEC_INST; - `RISCVSTATE_EXEC_INST: begin - if (opcode == 5'h00) - state <= `RISCVSTATE_WAIT_LD; - else if (opcode == 5'h08) - state <= `RISCVSTATE_WAIT_ST; - else if (opcode == 5'h0c && instr[25] && func3[2] && (rs2 != 0)) begin - state <= `RISCVSTATE_WAIT_DIV; - divclk <= 11; - end - end - `RISCVSTATE_WAIT_LD: state <= `RISCVSTATE_READ_INST; - `RISCVSTATE_WAIT_ST: state <= `RISCVSTATE_READ_INST; - `RISCVSTATE_WAIT_DIV: begin - if (divclk == 0) - state <= `RISCVSTATE_READ_INST; - else - divclk <= divclk - 1; - end - endcase end - //DEFINE_FUNC(riscv_core_gen_imm, "bReadData, state") { - /* 在RISCVSTATE_READ_REGS周期生成imm */ - always @(bReadData) - case (bReadData[6:2]) - 5'h0d: imm = {bReadData[31:12], 12'b0}; - 5'h05: imm = {bReadData[31:12], 12'b0}; - 5'h1b: imm = {{12{bReadData[31]}}, bReadData[19:12], bReadData[20], bReadData[30:21], 1'b0}; - 5'h19: imm = {{20{bReadData[31]}}, bReadData[31:20]}; - 5'h18: imm = {{20{bReadData[31]}}, bReadData[7], bReadData[30:25], bReadData[11:8], 1'b0}; - 5'h00: imm = {{20{bReadData[31]}}, bReadData[31:20]}; - 5'h08: imm = {{20{bReadData[31]}}, bReadData[31:25], bReadData[11:7]}; - 5'h04: imm = {{20{bReadData[31]}}, bReadData[31:20]}; - endcase - + reg [4:0] readreg; + reg [1:0] ldaddr; - //DEFINE_FUNC(riscv_core_gen_ldaddr, "state, pc, instr, rs1") { always @(posedge wClk) - if (state == `RISCVSTATE_READ_INST) begin - ldaddr <= pc; - end else if (state == `RISCVSTATE_EXEC_INST) begin - if (opcode == 5'h00) begin - /* ld inst */ - ldaddr <= rs1 + imm; - end + if (state == `RISCVSTATE_EXEC_INST) begin + ldaddr <= rs1 + imm; + readreg <= rd; end - //DEFINE_FUNC(riscv_core_gen_dstreg, "state, instr, ldaddr, readreg, bReadData, pc, rs1, regrddata, imm") { - always @(state or readreg or ldaddr or func3 or bReadData or divclk or imm or pc or rs1 or rs2 or instr) + always @(state or ldaddr or func3 or bReadData or divclk or imm or pc or rs1 or rs2 or instr) case (state) `RISCVSTATE_WAIT_LD: begin dstreg = readreg; @@ -452,19 +464,19 @@ module riscv_core( dstreg = 0; case (func3[1:0]) 0: begin //div - dstreg = rd; + dstreg = readreg; dstvalue = divs_result; end 1: begin //divu - dstreg = rd; + dstreg = readreg; dstvalue = div_result; end 2: begin//rem - dstreg = rd; + dstreg = readreg; dstvalue = mods_result; end 3: begin //remu - dstreg = rd; + dstreg = readreg; dstvalue = mod_result; end endcase @@ -590,20 +602,4 @@ module riscv_core( end endcase - //DEFINE_FUNC(riscv_core_read_sig, "state, pc, instr, bReadData, rs1") { - always @(state or pc or opcode or imm or rs1) begin - wRead = 0; - bReadAddr = 0; - if (state == `RISCVSTATE_READ_INST) begin - wRead = 1; - bReadAddr = pc; - end else if (state == `RISCVSTATE_EXEC_INST) begin - if (opcode == 5'h00) begin - /* ld inst */ - bReadAddr = rs1 + imm; - wRead = 1; - end - end - end - endmodule \ No newline at end of file