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提交 08c63023 编写于 作者: 饶先宏's avatar 饶先宏
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202108271344

上级 36cd978d 03db2b6f
展开全部 隐藏空白更改
内联 并排
Showing with 13444 addition and 2157 deletion
examples/hdl4se_riscv/de1/.gitignore
浏览文件 @ 08c63023
......@@ -33,7 +33,6 @@ bld/
[Ll]og/
[Ll]ogs/
# Visual Studio 2015/2017 cache/options directory
.vs/
# Uncomment if you have tasks that create the project's static files in wwwroot
......@@ -111,6 +110,7 @@ incremental_db/
*.cdf
*.jdi
*.smsg
work/
# Chutzpah Test files
_Chutzpah*
......
examples/hdl4se_riscv/de1/PLLJ_PLLSPE_INFO.txt
浏览文件 @ 08c63023
PLL_Name vga_pll_0002:vgaclock|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
PLLJITTER 27
PLL_Name clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL
PLLJITTER 21
PLLSPEmax 50
PLLSPEmin -50
PLL_Name vga_pll_0002:vgaclock|altera_pll:altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER
PLL_Name clk100M:clk100|clk100M_0002:clk100m_inst|altera_pll:altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER
PLLJITTER NA
PLLSPEmax NA
PLLSPEmin NA
......
examples/hdl4se_riscv/de1/compare.qip → examples/hdl4se_riscv/de1/alu/mulsu.qip
浏览文件 @ 08c63023
set_global_assignment -name IP_TOOL_NAME "LPM_COMPARE"
set_global_assignment -name IP_TOOL_NAME "LPM_MULT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "compare.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "compare_bb.v"]
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mulsu.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mulsu_bb.v"]
examples/hdl4se_riscv/de1/compare.v → examples/hdl4se_riscv/de1/alu/mulsu.v
浏览文件 @ 08c63023
// megafunction wizard: %LPM_COMPARE%
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COMPARE
// MODULE: lpm_mult
// ============================================================
// File Name: compare.v
// File Name: mulsu.v
// Megafunction Name(s):
// LPM_COMPARE
// lpm_mult
//
// Simulation Library Files(s):
// lpm
......@@ -36,54 +36,33 @@
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module compare (
module mulsu (
dataa,
datab,
aeb,
agb,
ageb,
alb,
aleb,
aneb);
result);
input [31:0] dataa;
input [31:0] datab;
output aeb;
output agb;
output ageb;
output alb;
output aleb;
output aneb;
input [39:0] datab;
output [71:0] result;
wire sub_wire0;
wire sub_wire1;
wire sub_wire2;
wire sub_wire3;
wire sub_wire4;
wire sub_wire5;
wire aeb = sub_wire0;
wire agb = sub_wire1;
wire aleb = sub_wire2;
wire aneb = sub_wire3;
wire ageb = sub_wire4;
wire alb = sub_wire5;
wire [71:0] sub_wire0;
wire [71:0] result = sub_wire0[71:0];
lpm_compare LPM_COMPARE_component (
.datab (datab),
lpm_mult lpm_mult_component (
.dataa (dataa),
.aeb (sub_wire0),
.agb (sub_wire1),
.aleb (sub_wire2),
.aneb (sub_wire3),
.ageb (sub_wire4),
.alb (sub_wire5),
.datab (datab),
.result (sub_wire0),
.aclr (1'b0),
.clken (1'b1),
.clock (1'b0));
.clock (1'b0),
.sum (1'b0));
defparam
LPM_COMPARE_component.lpm_representation = "UNSIGNED",
LPM_COMPARE_component.lpm_type = "LPM_COMPARE",
LPM_COMPARE_component.lpm_width = 32;
lpm_mult_component.lpm_hint = "MAXIMIZE_SPEED=5",
lpm_mult_component.lpm_representation = "SIGNED",
lpm_mult_component.lpm_type = "LPM_MULT",
lpm_mult_component.lpm_widtha = 32,
lpm_mult_component.lpm_widthb = 40,
lpm_mult_component.lpm_widthp = 72;
endmodule
......@@ -91,48 +70,40 @@ endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AeqB NUMERIC "1"
// Retrieval info: PRIVATE: AgeB NUMERIC "1"
// Retrieval info: PRIVATE: AgtB NUMERIC "1"
// Retrieval info: PRIVATE: AleB NUMERIC "1"
// Retrieval info: PRIVATE: AltB NUMERIC "1"
// Retrieval info: PRIVATE: AneB NUMERIC "1"
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: PortBValue NUMERIC "0"
// Retrieval info: PRIVATE: Radix NUMERIC "10"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "32"
// Retrieval info: PRIVATE: WidthB NUMERIC "40"
// Retrieval info: PRIVATE: WidthP NUMERIC "72"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "32"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: USED_PORT: aeb 0 0 0 0 OUTPUT NODEFVAL "aeb"
// Retrieval info: USED_PORT: agb 0 0 0 0 OUTPUT NODEFVAL "agb"
// Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
// Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
// Retrieval info: USED_PORT: aleb 0 0 0 0 OUTPUT NODEFVAL "aleb"
// Retrieval info: USED_PORT: aneb 0 0 0 0 OUTPUT NODEFVAL "aneb"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "40"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "72"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: USED_PORT: datab 0 0 40 0 INPUT NODEFVAL "datab[39..0]"
// Retrieval info: USED_PORT: result 0 0 72 0 OUTPUT NODEFVAL "result[71..0]"
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: aeb 0 0 0 0 @aeb 0 0 0 0
// Retrieval info: CONNECT: agb 0 0 0 0 @agb 0 0 0 0
// Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
// Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
// Retrieval info: CONNECT: aleb 0 0 0 0 @aleb 0 0 0 0
// Retrieval info: CONNECT: aneb 0 0 0 0 @aneb 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL compare.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL compare.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL compare.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL compare.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL compare_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL compare_bb.v TRUE
// Retrieval info: CONNECT: @datab 0 0 40 0 datab 0 0 40 0
// Retrieval info: CONNECT: result 0 0 72 0 @result 0 0 72 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mulsu.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mulsu.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mulsu.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mulsu.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mulsu_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mulsu_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
examples/hdl4se_riscv/de1/compare_bb.v → examples/hdl4se_riscv/de1/alu/mulsu_bb.v
浏览文件 @ 08c63023
// megafunction wizard: %LPM_COMPARE%VBB%
// megafunction wizard: %LPM_MULT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: LPM_COMPARE
// MODULE: lpm_mult
// ============================================================
// File Name: compare.v
// File Name: mulsu.v
// Megafunction Name(s):
// LPM_COMPARE
// lpm_mult
//
// Simulation Library Files(s):
// lpm
......@@ -31,72 +31,54 @@
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module compare (
module mulsu (
dataa,
datab,
aeb,
agb,
ageb,
alb,
aleb,
aneb);
result);
input [31:0] dataa;
input [31:0] datab;
output aeb;
output agb;
output ageb;
output alb;
output aleb;
output aneb;
input [39:0] datab;
output [71:0] result;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AeqB NUMERIC "1"
// Retrieval info: PRIVATE: AgeB NUMERIC "1"
// Retrieval info: PRIVATE: AgtB NUMERIC "1"
// Retrieval info: PRIVATE: AleB NUMERIC "1"
// Retrieval info: PRIVATE: AltB NUMERIC "1"
// Retrieval info: PRIVATE: AneB NUMERIC "1"
// Retrieval info: PRIVATE: AutoSizeResult NUMERIC "1"
// Retrieval info: PRIVATE: B_isConstant NUMERIC "0"
// Retrieval info: PRIVATE: ConstantB NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0"
// Retrieval info: PRIVATE: Latency NUMERIC "0"
// Retrieval info: PRIVATE: PortBValue NUMERIC "0"
// Retrieval info: PRIVATE: Radix NUMERIC "10"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SignedCompare NUMERIC "0"
// Retrieval info: PRIVATE: SignedMult NUMERIC "1"
// Retrieval info: PRIVATE: USE_MULT NUMERIC "1"
// Retrieval info: PRIVATE: ValidConstant NUMERIC "0"
// Retrieval info: PRIVATE: WidthA NUMERIC "32"
// Retrieval info: PRIVATE: WidthB NUMERIC "40"
// Retrieval info: PRIVATE: WidthP NUMERIC "72"
// Retrieval info: PRIVATE: aclr NUMERIC "0"
// Retrieval info: PRIVATE: clken NUMERIC "0"
// Retrieval info: PRIVATE: isPortBConstant NUMERIC "0"
// Retrieval info: PRIVATE: nBit NUMERIC "32"
// Retrieval info: PRIVATE: new_diagram STRING "1"
// Retrieval info: PRIVATE: optimize NUMERIC "0"
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COMPARE"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
// Retrieval info: USED_PORT: aeb 0 0 0 0 OUTPUT NODEFVAL "aeb"
// Retrieval info: USED_PORT: agb 0 0 0 0 OUTPUT NODEFVAL "agb"
// Retrieval info: USED_PORT: ageb 0 0 0 0 OUTPUT NODEFVAL "ageb"
// Retrieval info: USED_PORT: alb 0 0 0 0 OUTPUT NODEFVAL "alb"
// Retrieval info: USED_PORT: aleb 0 0 0 0 OUTPUT NODEFVAL "aleb"
// Retrieval info: USED_PORT: aneb 0 0 0 0 OUTPUT NODEFVAL "aneb"
// Retrieval info: CONSTANT: LPM_HINT STRING "MAXIMIZE_SPEED=5"
// Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "SIGNED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MULT"
// Retrieval info: CONSTANT: LPM_WIDTHA NUMERIC "32"
// Retrieval info: CONSTANT: LPM_WIDTHB NUMERIC "40"
// Retrieval info: CONSTANT: LPM_WIDTHP NUMERIC "72"
// Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]"
// Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]"
// Retrieval info: USED_PORT: datab 0 0 40 0 INPUT NODEFVAL "datab[39..0]"
// Retrieval info: USED_PORT: result 0 0 72 0 OUTPUT NODEFVAL "result[71..0]"
// Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0
// Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0
// Retrieval info: CONNECT: aeb 0 0 0 0 @aeb 0 0 0 0
// Retrieval info: CONNECT: agb 0 0 0 0 @agb 0 0 0 0
// Retrieval info: CONNECT: ageb 0 0 0 0 @ageb 0 0 0 0
// Retrieval info: CONNECT: alb 0 0 0 0 @alb 0 0 0 0
// Retrieval info: CONNECT: aleb 0 0 0 0 @aleb 0 0 0 0
// Retrieval info: CONNECT: aneb 0 0 0 0 @aneb 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL compare.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL compare.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL compare.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL compare.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL compare_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL compare_bb.v TRUE
// Retrieval info: CONNECT: @datab 0 0 40 0 datab 0 0 40 0
// Retrieval info: CONNECT: result 0 0 72 0 @result 0 0 72 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mulsu.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mulsu.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mulsu.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mulsu.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mulsu_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mulsu_bb.v TRUE
// Retrieval info: LIB_FILE: lpm
examples/hdl4se_riscv/de1/clk/clk100M.bsf 0 → 100644
浏览文件 @ 08c63023
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 160 184)
(text "clk100M" (rect 57 -1 88 11)(font "Arial" (font_size 10)))
(text "inst" (rect 8 168 20 180)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1))
)
(port
(pt 0 112)
(input)
(text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8)))
(text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 48 112)(line_width 1))
)
(port
(pt 160 72)
(output)
(text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8)))
(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
(line (pt 160 72)(pt 112 72)(line_width 1))
)
(port
(pt 160 112)
(output)
(text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8)))
(text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8)))
(line (pt 160 112)(pt 112 112)(line_width 1))
)
(port
(pt 160 152)
(output)
(text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8)))
(text "locked" (rect 127 141 163 152)(font "Arial" (font_size 8)))
(line (pt 160 152)(pt 112 152)(line_width 1))
)
(drawing
(text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0)))
(text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0)))
(text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
(text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9)))
(text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0)))
(text "locked" (rect 113 123 262 259)(font "Arial" (color 128 0 0)(font_size 9)))
(text "export" (rect 82 147 200 304)(font "Arial" (color 0 0 0)))
(text " altera_pll " (rect 118 168 308 346)(font "Arial" ))
(line (pt 49 52)(pt 49 76)(line_width 1))
(line (pt 50 52)(pt 50 76)(line_width 1))
(line (pt 49 92)(pt 49 116)(line_width 1))
(line (pt 50 92)(pt 50 116)(line_width 1))
(line (pt 111 52)(pt 111 76)(line_width 1))
(line (pt 110 52)(pt 110 76)(line_width 1))
(line (pt 111 92)(pt 111 116)(line_width 1))
(line (pt 110 92)(pt 110 116)(line_width 1))
(line (pt 111 132)(pt 111 156)(line_width 1))
(line (pt 110 132)(pt 110 156)(line_width 1))
(line (pt 48 32)(pt 112 32)(line_width 1))
(line (pt 112 32)(pt 112 168)(line_width 1))
(line (pt 48 168)(pt 112 168)(line_width 1))
(line (pt 48 32)(pt 48 168)(line_width 1))
(line (pt 0 0)(pt 160 0)(line_width 1))
(line (pt 160 0)(pt 160 184)(line_width 1))
(line (pt 0 184)(pt 160 184)(line_width 1))
(line (pt 0 0)(pt 0 184)(line_width 1))
)
)
examples/hdl4se_riscv/de1/clk/clk100M.cmp 0 → 100644
浏览文件 @ 08c63023
component clk100M is
port (
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
outclk_1 : out std_logic; -- clk
locked : out std_logic -- export
);
end component clk100M;
examples/hdl4se_riscv/de1/clk/clk100M.ppf 0 → 100644
浏览文件 @ 08c63023
<?xml version="1.0" encoding="UTF-8"?>
<pinplan
variation_name="clk100M"
megafunction_name="ALTERA_PLL"
intended_family="Cyclone V"
specifies="all_ports">
<global>
<pin name="refclk" direction="input" scope="external" />
<pin name="rst" direction="input" scope="external" />
<pin name="outclk_0" direction="output" scope="external" />
<pin name="outclk_1" direction="output" scope="external" />
<pin name="locked" direction="output" scope="external" />
</global>
</pinplan>
examples/hdl4se_riscv/de1/clk/clk100M.qip 0 → 100644
浏览文件 @ 08c63023
set_global_assignment -entity "clk100M" -library "clk100M" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "clk100M" -library "clk100M" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "clk100M" -library "clk100M" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "clk100M" -name MISC_FILE [file join $::quartus(qip_path) "clk100M.cmp"]
set_global_assignment -name SYNTHESIS_ONLY_QIP ON
set_global_assignment -library "clk100M" -name VERILOG_FILE [file join $::quartus(qip_path) "clk100M.v"]
set_global_assignment -library "clk100M" -name VERILOG_FILE [file join $::quartus(qip_path) "clk100M/clk100M_0002.v"]
set_global_assignment -library "clk100M" -name QIP_FILE [file join $::quartus(qip_path) "clk100M/clk100M_0002.qip"]
set_global_assignment -entity "clk100M_0002" -library "clk100M" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "clk100M_0002" -library "clk100M" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "clk100M_0002" -library "clk100M" -name IP_TOOL_ENV "mwpim"
examples/hdl4se_riscv/de1/clk/clk100M.sip 0 → 100644
浏览文件 @ 08c63023
set_global_assignment -entity "clk100M" -library "lib_clk100M" -name IP_TOOL_NAME "altera_pll"
set_global_assignment -entity "clk100M" -library "lib_clk100M" -name IP_TOOL_VERSION "13.1"
set_global_assignment -entity "clk100M" -library "lib_clk100M" -name IP_TOOL_ENV "mwpim"
set_global_assignment -library "lib_clk100M" -name SPD_FILE [file join $::quartus(sip_path) "clk100M.spd"]
set_global_assignment -library "lib_clk100M" -name MISC_FILE [file join $::quartus(sip_path) "clk100M_sim/clk100M.vo"]
examples/hdl4se_riscv/de1/clk/clk100M.spd 0 → 100644
浏览文件 @ 08c63023
<?xml version="1.0" encoding="UTF-8"?>
<simPackage>
<file path="clk100M_sim/clk100M.vo" type="VERILOG" />
<topLevel name="clk100M" />
<deviceFamily name="cyclonev" />
</simPackage>
examples/hdl4se_riscv/de1/clk/clk100M.v 0 → 100644
浏览文件 @ 08c63023
// megafunction wizard: %Altera PLL v13.1%
// GENERATION: XML
// clk100M.v
// Generated using ACDS version 13.1 162 at 2021.08.27.08:01:33
`timescale 1 ps / 1 ps
module clk100M (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0, // outclk0.clk
output wire outclk_1, // outclk1.clk
output wire locked // locked.export
);
clk100M_0002 clk100m_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.outclk_1 (outclk_1), // outclk1.clk
.locked (locked) // locked.export
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2021 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="13.1" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="Unknown" />
// Retrieval info: <generic name="gui_device_speed_grade" value="2" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="direct" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="true" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="2" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="400.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="75.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: <generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
// Retrieval info: </instance>
// IPFS_FILES : clk100M.vo
// RELATED_FILES: clk100M.v, clk100M_0002.v
examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.qip 0 → 100644
浏览文件 @ 08c63023
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to "*clk100M_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_AUTO_RESET OFF -to "*clk100M_0002*|altera_pll:altera_pll_i*|*"
set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*clk100M_0002*|altera_pll:altera_pll_i*|*"
examples/hdl4se_riscv/de1/clk/clk100M/clk100M_0002.v 0 → 100644
浏览文件 @ 08c63023
`timescale 1ns/10ps
module clk100M_0002(
// interface 'refclk'
input wire refclk,
// interface 'reset'
input wire rst,
// interface 'outclk0'
output wire outclk_0,
// interface 'outclk1'
output wire outclk_1,
// interface 'locked'
output wire locked
);
altera_pll #(
.fractional_vco_multiplier("false"),
.reference_clock_frequency("50.0 MHz"),
.operation_mode("direct"),
.number_of_clocks(2),
.output_clock_frequency0("400.000000 MHz"),
.phase_shift0("0 ps"),
.duty_cycle0(50),
.output_clock_frequency1("75.000000 MHz"),
.phase_shift1("0 ps"),
.duty_cycle1(50),
.output_clock_frequency2("0 MHz"),
.phase_shift2("0 ps"),
.duty_cycle2(50),
.output_clock_frequency3("0 MHz"),
.phase_shift3("0 ps"),
.duty_cycle3(50),
.output_clock_frequency4("0 MHz"),
.phase_shift4("0 ps"),
.duty_cycle4(50),
.output_clock_frequency5("0 MHz"),
.phase_shift5("0 ps"),
.duty_cycle5(50),
.output_clock_frequency6("0 MHz"),
.phase_shift6("0 ps"),
.duty_cycle6(50),
.output_clock_frequency7("0 MHz"),
.phase_shift7("0 ps"),
.duty_cycle7(50),
.output_clock_frequency8("0 MHz"),
.phase_shift8("0 ps"),
.duty_cycle8(50),
.output_clock_frequency9("0 MHz"),
.phase_shift9("0 ps"),
.duty_cycle9(50),
.output_clock_frequency10("0 MHz"),
.phase_shift10("0 ps"),
.duty_cycle10(50),
.output_clock_frequency11("0 MHz"),
.phase_shift11("0 ps"),
.duty_cycle11(50),
.output_clock_frequency12("0 MHz"),
.phase_shift12("0 ps"),
.duty_cycle12(50),
.output_clock_frequency13("0 MHz"),
.phase_shift13("0 ps"),
.duty_cycle13(50),
.output_clock_frequency14("0 MHz"),
.phase_shift14("0 ps"),
.duty_cycle14(50),
.output_clock_frequency15("0 MHz"),
.phase_shift15("0 ps"),
.duty_cycle15(50),
.output_clock_frequency16("0 MHz"),
.phase_shift16("0 ps"),
.duty_cycle16(50),
.output_clock_frequency17("0 MHz"),
.phase_shift17("0 ps"),
.duty_cycle17(50),
.pll_type("General"),
.pll_subtype("General")
) altera_pll_i (
.rst (rst),
.outclk ({outclk_1, outclk_0}),
.locked (locked),
.fboutclk ( ),
.fbclk (1'b0),
.refclk (refclk)
);
endmodule
examples/hdl4se_riscv/de1/clk/clk100M_sim/aldec/rivierapro_setup.tcl 0 → 100644
浏览文件 @ 08c63023
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40
# ----------------------------------------
# Auto-generated simulation script
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "clk100M"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "C:/altera/13.1/quartus/"
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
} else {
}
set Aldec "Riviera"
if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
set Aldec "Active"
}
if { [ string match "Active" $Aldec ] } {
scripterconf -tcl
createdesign "$TOP_LEVEL_NAME" "."
opendesign "$TOP_LEVEL_NAME"
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo "\[exec\] file_copy"
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries
ensure_lib ./libraries/work
vmap work ./libraries/work
ensure_lib ./libraries/altera_ver
vmap altera_ver ./libraries/altera_ver
ensure_lib ./libraries/lpm_ver
vmap lpm_ver ./libraries/lpm_ver
ensure_lib ./libraries/sgate_ver
vmap sgate_ver ./libraries/sgate_ver
ensure_lib ./libraries/altera_mf_ver
vmap altera_mf_ver ./libraries/altera_mf_ver
ensure_lib ./libraries/altera_lnsim_ver
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver
ensure_lib ./libraries/cyclonev_ver
vmap cyclonev_ver ./libraries/cyclonev_ver
ensure_lib ./libraries/cyclonev_hssi_ver
vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver
ensure_lib ./libraries/cyclonev_pcie_hip_ver
vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver
# ----------------------------------------
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
vlog +define+SKIP_KEYWORDS_PRAGMA "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo "\[exec\] com"
vlog "$QSYS_SIMDIR/clk100M.vo"
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo "\[exec\] elab"
eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with -dbg -O2 option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -dbg -O2
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with -dbg -O2 option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -dbg -O2"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Qsys base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
}
file_copy
h
examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/cds.lib 0 → 100644
浏览文件 @ 08c63023
DEFINE std $CDS_ROOT/tools/inca/files/STD/
DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
DEFINE work ./libraries/work/
DEFINE altera_ver ./libraries/altera_ver/
DEFINE lpm_ver ./libraries/lpm_ver/
DEFINE sgate_ver ./libraries/sgate_ver/
DEFINE altera_mf_ver ./libraries/altera_mf_ver/
DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/
DEFINE cyclonev_ver ./libraries/cyclonev_ver/
DEFINE cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
examples/hdl4se_riscv/de1/clk/clk100M_sim/cadence/ncsim_setup.sh 0 → 100644
浏览文件 @ 08c63023
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40
# ----------------------------------------
# ncsim - auto-generated simulation script
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="clk100M"
QSYS_SIMDIR="./../"
QUARTUS_INSTALL_DIR="C:/altera/13.1/quartus/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_ELAB=1 SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
:
else
:
fi
# ----------------------------------------
# create compilation libraries
mkdir -p ./libraries/work/
mkdir -p ./libraries/altera_ver/
mkdir -p ./libraries/lpm_ver/
mkdir -p ./libraries/sgate_ver/
mkdir -p ./libraries/altera_mf_ver/
mkdir -p ./libraries/altera_lnsim_ver/
mkdir -p ./libraries/cyclonev_ver/
mkdir -p ./libraries/cyclonev_hssi_ver/
mkdir -p ./libraries/cyclonev_pcie_hip_ver/
# ----------------------------------------
# copy RAM/ROM files to simulation directory
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
ncvlog -sv "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
ncvlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
fi
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
ncvlog "$QSYS_SIMDIR/clk100M.vo"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
fi
examples/hdl4se_riscv/de1/clk/clk100M_sim/clk100M.vo 0 → 100644
浏览文件 @ 08c63023
//IP Functional Simulation Model
//VERSION_BEGIN 13.1 cbx_mgl 2013:10:24:09:16:30:SJ cbx_simgen 2013:10:24:09:15:20:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions
// and other software and tools, and its AMPP partner logic
// functions, and any output files from any of the foregoing
// (including device programming or simulation files), and any
// associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License
// Subscription Agreement, Altera MegaCore Function License
// Agreement, or other applicable license agreement, including,
// without limitation, that your use is for the sole purpose of
// programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the
// applicable agreement for further details.
// You may only use these simulation model output files for simulation
// purposes and expressly not for synthesis or any other purposes (in which
// event Altera disclaims all warranties of any kind).
//synopsys translate_off
//synthesis_resources = altera_pll 1
`timescale 1 ps / 1 ps
module clk100M
(
locked,
outclk_0,
outclk_1,
refclk,
rst) /* synthesis synthesis_clearbox=1 */;
output locked;
output outclk_0;
output outclk_1;
input refclk;
input rst;
wire wire_clk100m_altera_pll_altera_pll_i_1096_locked;
wire [1:0] wire_clk100m_altera_pll_altera_pll_i_1096_outclk;
altera_pll clk100m_altera_pll_altera_pll_i_1096
(
.fbclk(1'b0),
.locked(wire_clk100m_altera_pll_altera_pll_i_1096_locked),
.outclk(wire_clk100m_altera_pll_altera_pll_i_1096_outclk),
.refclk(refclk),
.rst(rst));
defparam
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en0 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en1 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en10 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en11 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en12 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en13 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en14 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en15 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en16 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en17 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en2 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en3 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en4 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en5 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en6 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en7 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en8 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_bypass_en9 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div0 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div1 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div10 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div11 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div12 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div13 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div14 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div15 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div16 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div17 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div2 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div3 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div4 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div5 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div6 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div7 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div8 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_hi_div9 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src0 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src1 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src10 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src11 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src12 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src13 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src14 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src15 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src16 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src17 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src2 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src3 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src4 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src5 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src6 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src7 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src8 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_in_src9 = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div0 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div1 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div10 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div11 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div12 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div13 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div14 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div15 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div16 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div17 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div2 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div3 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div4 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div5 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div6 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div7 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div8 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_lo_div9 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en0 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en1 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en10 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en11 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en12 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en13 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en14 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en15 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en16 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en17 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en2 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en3 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en4 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en5 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en6 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en7 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en8 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_odd_div_duty_en9 = "false",
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst0 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst1 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst10 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst11 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst12 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst13 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst14 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst15 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst16 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst17 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst2 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst3 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst4 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst5 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst6 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst7 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst8 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_ph_mux_prst9 = 0,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst0 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst1 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst10 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst11 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst12 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst13 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst14 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst15 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst16 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst17 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst2 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst3 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst4 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst5 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst6 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst7 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst8 = 1,
clk100m_altera_pll_altera_pll_i_1096.c_cnt_prst9 = 1,
clk100m_altera_pll_altera_pll_i_1096.data_rate = 0,
clk100m_altera_pll_altera_pll_i_1096.deserialization_factor = 4,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle0 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle1 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle10 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle11 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle12 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle13 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle14 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle15 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle16 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle17 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle2 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle3 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle4 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle5 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle6 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle7 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle8 = 50,
clk100m_altera_pll_altera_pll_i_1096.duty_cycle9 = 50,
clk100m_altera_pll_altera_pll_i_1096.fractional_vco_multiplier = "false",
clk100m_altera_pll_altera_pll_i_1096.m_cnt_bypass_en = "false",
clk100m_altera_pll_altera_pll_i_1096.m_cnt_hi_div = 1,
clk100m_altera_pll_altera_pll_i_1096.m_cnt_lo_div = 1,
clk100m_altera_pll_altera_pll_i_1096.m_cnt_odd_div_duty_en = "false",
clk100m_altera_pll_altera_pll_i_1096.mimic_fbclk_type = "gclk",
clk100m_altera_pll_altera_pll_i_1096.n_cnt_bypass_en = "false",
clk100m_altera_pll_altera_pll_i_1096.n_cnt_hi_div = 1,
clk100m_altera_pll_altera_pll_i_1096.n_cnt_lo_div = 1,
clk100m_altera_pll_altera_pll_i_1096.n_cnt_odd_div_duty_en = "false",
clk100m_altera_pll_altera_pll_i_1096.number_of_clocks = 2,
clk100m_altera_pll_altera_pll_i_1096.operation_mode = "direct",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency0 = "400.000000 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency1 = "75.000000 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency10 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency11 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency12 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency13 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency14 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency15 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency16 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency17 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency2 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency3 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency4 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency5 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency6 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency7 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency8 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.output_clock_frequency9 = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.phase_shift0 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift1 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift10 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift11 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift12 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift13 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift14 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift15 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift16 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift17 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift2 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift3 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift4 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift5 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift6 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift7 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift8 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.phase_shift9 = "0 ps",
clk100m_altera_pll_altera_pll_i_1096.pll_auto_clk_sw_en = "false",
clk100m_altera_pll_altera_pll_i_1096.pll_bwctrl = 0,
clk100m_altera_pll_altera_pll_i_1096.pll_clk_loss_sw_en = "false",
clk100m_altera_pll_altera_pll_i_1096.pll_clk_sw_dly = 0,
clk100m_altera_pll_altera_pll_i_1096.pll_clkin_0_src = "clk_0",
clk100m_altera_pll_altera_pll_i_1096.pll_clkin_1_src = "clk_0",
clk100m_altera_pll_altera_pll_i_1096.pll_cp_current = 0,
clk100m_altera_pll_altera_pll_i_1096.pll_dsm_out_sel = "1st_order",
clk100m_altera_pll_altera_pll_i_1096.pll_fbclk_mux_1 = "glb",
clk100m_altera_pll_altera_pll_i_1096.pll_fbclk_mux_2 = "fb_1",
clk100m_altera_pll_altera_pll_i_1096.pll_fractional_cout = 24,
clk100m_altera_pll_altera_pll_i_1096.pll_fractional_division = 1,
clk100m_altera_pll_altera_pll_i_1096.pll_m_cnt_in_src = "ph_mux_clk",
clk100m_altera_pll_altera_pll_i_1096.pll_manu_clk_sw_en = "false",
clk100m_altera_pll_altera_pll_i_1096.pll_output_clk_frequency = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.pll_subtype = "General",
clk100m_altera_pll_altera_pll_i_1096.pll_type = "General",
clk100m_altera_pll_altera_pll_i_1096.pll_vco_div = 1,
clk100m_altera_pll_altera_pll_i_1096.pll_vcoph_div = 1,
clk100m_altera_pll_altera_pll_i_1096.refclk1_frequency = "0 MHz",
clk100m_altera_pll_altera_pll_i_1096.reference_clock_frequency = "50.0 MHz",
clk100m_altera_pll_altera_pll_i_1096.sim_additional_refclk_cycles_to_lock = 0;
assign
locked = wire_clk100m_altera_pll_altera_pll_i_1096_locked,
outclk_0 = wire_clk100m_altera_pll_altera_pll_i_1096_outclk[0],
outclk_1 = wire_clk100m_altera_pll_altera_pll_i_1096_outclk[1];
endmodule //clk100M
//synopsys translate_on
//VALID FILE
examples/hdl4se_riscv/de1/clk/clk100M_sim/mentor/msim_setup.tcl 0 → 100644
浏览文件 @ 08c63023
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40
# ----------------------------------------
# Auto-generated simulation script
# ----------------------------------------
# Initialize variables
if ![info exists SYSTEM_INSTANCE_NAME] {
set SYSTEM_INSTANCE_NAME ""
} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } {
set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
}
if ![info exists TOP_LEVEL_NAME] {
set TOP_LEVEL_NAME "clk100M"
}
if ![info exists QSYS_SIMDIR] {
set QSYS_SIMDIR "./../"
}
if ![info exists QUARTUS_INSTALL_DIR] {
set QUARTUS_INSTALL_DIR "C:/altera/13.1/quartus/"
}
# ----------------------------------------
# Initialize simulation properties - DO NOT MODIFY!
set ELAB_OPTIONS ""
set SIM_OPTIONS ""
if ![ string match "*-64 vsim*" [ vsim -version ] ] {
} else {
}
# ----------------------------------------
# Copy ROM/RAM files to simulation directory
alias file_copy {
echo "\[exec\] file_copy"
}
# ----------------------------------------
# Create compilation libraries
proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
ensure_lib ./libraries/
ensure_lib ./libraries/work/
vmap work ./libraries/work/
vmap work_lib ./libraries/work/
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
ensure_lib ./libraries/altera_ver/
vmap altera_ver ./libraries/altera_ver/
ensure_lib ./libraries/lpm_ver/
vmap lpm_ver ./libraries/lpm_ver/
ensure_lib ./libraries/sgate_ver/
vmap sgate_ver ./libraries/sgate_ver/
ensure_lib ./libraries/altera_mf_ver/
vmap altera_mf_ver ./libraries/altera_mf_ver/
ensure_lib ./libraries/altera_lnsim_ver/
vmap altera_lnsim_ver ./libraries/altera_lnsim_ver/
ensure_lib ./libraries/cyclonev_ver/
vmap cyclonev_ver ./libraries/cyclonev_ver/
ensure_lib ./libraries/cyclonev_hssi_ver/
vmap cyclonev_hssi_ver ./libraries/cyclonev_hssi_ver/
ensure_lib ./libraries/cyclonev_pcie_hip_ver/
vmap cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
}
# ----------------------------------------
# Compile device library files
alias dev_com {
echo "\[exec\] dev_com"
if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlog -sv "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
vlog "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
}
}
# ----------------------------------------
# Compile the design files in correct order
alias com {
echo "\[exec\] com"
vlog "$QSYS_SIMDIR/clk100M.vo"
}
# ----------------------------------------
# Elaborate top level design
alias elab {
echo "\[exec\] elab"
eval vsim -t ps $ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Elaborate the top level design with novopt option
alias elab_debug {
echo "\[exec\] elab_debug"
eval vsim -novopt -t ps $ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
}
# ----------------------------------------
# Compile all the design files and elaborate the top level design
alias ld "
dev_com
com
elab
"
# ----------------------------------------
# Compile all the design files and elaborate the top level design with -novopt
alias ld_debug "
dev_com
com
elab_debug
"
# ----------------------------------------
# Print out user commmand line aliases
alias h {
echo "List Of Command Line Aliases"
echo
echo "file_copy -- Copy ROM/RAM files to simulation directory"
echo
echo "dev_com -- Compile device library files"
echo
echo "com -- Compile the design files in correct order"
echo
echo "elab -- Elaborate top level design"
echo
echo "elab_debug -- Elaborate the top level design with novopt option"
echo
echo "ld -- Compile all the design files and elaborate the top level design"
echo
echo "ld_debug -- Compile all the design files and elaborate the top level design with -novopt"
echo
echo
echo
echo "List Of Variables"
echo
echo "TOP_LEVEL_NAME -- Top level module name."
echo
echo "SYSTEM_INSTANCE_NAME -- Instantiated system module name inside top level module."
echo
echo "QSYS_SIMDIR -- Qsys base simulation directory."
echo
echo "QUARTUS_INSTALL_DIR -- Quartus installation directory."
}
file_copy
h
examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcs/vcs_setup.sh 0 → 100644
浏览文件 @ 08c63023
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40
# ----------------------------------------
# vcs - auto-generated simulation script
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="clk100M"
QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="C:/altera/13.1/quartus/"
SKIP_FILE_COPY=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_ELAB=1 SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `vcs -platform` != *"amd64"* ]]; then
:
else
:
fi
# ----------------------------------------
# copy RAM/ROM files to simulation directory
vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v \
-v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v \
$QSYS_SIMDIR/clk100M.vo \
-top $TOP_LEVEL_NAME
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
fi
examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/synopsys_sim.setup 0 → 100644
浏览文件 @ 08c63023
WORK > DEFAULT
DEFAULT: ./libraries/work/
work: ./libraries/work/
altera_ver: ./libraries/altera_ver/
lpm_ver: ./libraries/lpm_ver/
sgate_ver: ./libraries/sgate_ver/
altera_mf_ver: ./libraries/altera_mf_ver/
altera_lnsim_ver: ./libraries/altera_lnsim_ver/
cyclonev_ver: ./libraries/cyclonev_ver/
cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/
cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/
LIBRARY_SCAN = TRUE
examples/hdl4se_riscv/de1/clk/clk100M_sim/synopsys/vcsmx/vcsmx_setup.sh 0 → 100644
浏览文件 @ 08c63023
# (C) 2001-2021 Altera Corporation. All rights reserved.
# Your use of Altera Corporation's design tools, logic functions and
# other software and tools, and its AMPP partner logic functions, and
# any output files any of the foregoing (including device programming
# or simulation files), and any associated documentation or information
# are expressly subject to the terms and conditions of the Altera
# Program License Subscription Agreement, Altera MegaCore Function
# License Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by Altera
# or its authorized distributors. Please refer to the applicable
# agreement for further details.
# ACDS 13.1 162 win32 2021.08.27.08:01:40
# ----------------------------------------
# vcsmx - auto-generated simulation script
# ----------------------------------------
# initialize variables
TOP_LEVEL_NAME="clk100M"
QSYS_SIMDIR="./../../"
QUARTUS_INSTALL_DIR="C:/altera/13.1/quartus/"
SKIP_FILE_COPY=0
SKIP_DEV_COM=0
SKIP_COM=0
SKIP_ELAB=0
SKIP_SIM=0
USER_DEFINED_ELAB_OPTIONS=""
USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
# ----------------------------------------
# overwrite variables - DO NOT MODIFY!
# This block evaluates each command line argument, typically used for
# overwriting variables. An example usage:
# sh <simulator>_setup.sh SKIP_ELAB=1 SKIP_SIM=1
for expression in "$@"; do
eval $expression
if [ $? -ne 0 ]; then
echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
exit $?
fi
done
# ----------------------------------------
# initialize simulation properties - DO NOT MODIFY!
ELAB_OPTIONS=""
SIM_OPTIONS=""
if [[ `vcs -platform` != *"amd64"* ]]; then
:
else
:
fi
# ----------------------------------------
# create compilation libraries
mkdir -p ./libraries/work/
mkdir -p ./libraries/altera_ver/
mkdir -p ./libraries/lpm_ver/
mkdir -p ./libraries/sgate_ver/
mkdir -p ./libraries/altera_mf_ver/
mkdir -p ./libraries/altera_lnsim_ver/
mkdir -p ./libraries/cyclonev_ver/
mkdir -p ./libraries/cyclonev_hssi_ver/
mkdir -p ./libraries/cyclonev_pcie_hip_ver/
# ----------------------------------------
# copy RAM/ROM files to simulation directory
# ----------------------------------------
# compile device library files
if [ $SKIP_DEV_COM -eq 0 ]; then
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v" -work altera_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v" -work lpm_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v" -work sgate_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v" -work altera_mf_ver
vlogan +v2k -sverilog "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv" -work altera_lnsim_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v" -work cyclonev_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v" -work cyclonev_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v" -work cyclonev_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v" -work cyclonev_hssi_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v" -work cyclonev_hssi_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
vlogan +v2k "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v" -work cyclonev_pcie_hip_ver
fi
# ----------------------------------------
# compile design files in correct order
if [ $SKIP_COM -eq 0 ]; then
vlogan +v2k "$QSYS_SIMDIR/clk100M.vo"
fi
# ----------------------------------------
# elaborate top level design
if [ $SKIP_ELAB -eq 0 ]; then
vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
fi
# ----------------------------------------
# simulate
if [ $SKIP_SIM -eq 0 ]; then
./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
fi
examples/hdl4se_riscv/de1/clk100M.xml 0 → 100644
浏览文件 @ 08c63023
<?xml version="1.0"?>
<instance entity-name="altera_pll" version="13.1" >
<generic name="debug_print_output" value="false" />
<generic name="debug_use_rbc_taf_method" value="false" />
<generic name="device_family" value="Cyclone V" />
<generic name="device" value="Unknown" />
<generic name="gui_device_speed_grade" value="2" />
<generic name="gui_pll_mode" value="Integer-N PLL" />
<generic name="gui_reference_clock_frequency" value="50.0" />
<generic name="gui_channel_spacing" value="0.0" />
<generic name="gui_operation_mode" value="direct" />
<generic name="gui_feedback_clock" value="Global Clock" />
<generic name="gui_fractional_cout" value="32" />
<generic name="gui_dsm_out_sel" value="1st_order" />
<generic name="gui_use_locked" value="true" />
<generic name="gui_en_adv_params" value="false" />
<generic name="gui_number_of_clocks" value="2" />
<generic name="gui_multiply_factor" value="1" />
<generic name="gui_frac_multiply_factor" value="1" />
<generic name="gui_divide_factor_n" value="1" />
<generic name="gui_cascade_counter0" value="false" />
<generic name="gui_output_clock_frequency0" value="100.0" />
<generic name="gui_divide_factor_c0" value="1" />
<generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
<generic name="gui_ps_units0" value="ps" />
<generic name="gui_phase_shift0" value="0" />
<generic name="gui_phase_shift_deg0" value="0.0" />
<generic name="gui_actual_phase_shift0" value="0" />
<generic name="gui_duty_cycle0" value="50" />
<generic name="gui_cascade_counter1" value="false" />
<generic name="gui_output_clock_frequency1" value="75.0" />
<generic name="gui_divide_factor_c1" value="1" />
<generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
<generic name="gui_ps_units1" value="ps" />
<generic name="gui_phase_shift1" value="0" />
<generic name="gui_phase_shift_deg1" value="0.0" />
<generic name="gui_actual_phase_shift1" value="0" />
<generic name="gui_duty_cycle1" value="50" />
<generic name="gui_cascade_counter2" value="false" />
<generic name="gui_output_clock_frequency2" value="100.0" />
<generic name="gui_divide_factor_c2" value="1" />
<generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
<generic name="gui_ps_units2" value="ps" />
<generic name="gui_phase_shift2" value="0" />
<generic name="gui_phase_shift_deg2" value="0.0" />
<generic name="gui_actual_phase_shift2" value="0" />
<generic name="gui_duty_cycle2" value="50" />
<generic name="gui_cascade_counter3" value="false" />
<generic name="gui_output_clock_frequency3" value="100.0" />
<generic name="gui_divide_factor_c3" value="1" />
<generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
<generic name="gui_ps_units3" value="ps" />
<generic name="gui_phase_shift3" value="0" />
<generic name="gui_phase_shift_deg3" value="0.0" />
<generic name="gui_actual_phase_shift3" value="0" />
<generic name="gui_duty_cycle3" value="50" />
<generic name="gui_cascade_counter4" value="false" />
<generic name="gui_output_clock_frequency4" value="100.0" />
<generic name="gui_divide_factor_c4" value="1" />
<generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
<generic name="gui_ps_units4" value="ps" />
<generic name="gui_phase_shift4" value="0" />
<generic name="gui_phase_shift_deg4" value="0.0" />
<generic name="gui_actual_phase_shift4" value="0" />
<generic name="gui_duty_cycle4" value="50" />
<generic name="gui_cascade_counter5" value="false" />
<generic name="gui_output_clock_frequency5" value="100.0" />
<generic name="gui_divide_factor_c5" value="1" />
<generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
<generic name="gui_ps_units5" value="ps" />
<generic name="gui_phase_shift5" value="0" />
<generic name="gui_phase_shift_deg5" value="0.0" />
<generic name="gui_actual_phase_shift5" value="0" />
<generic name="gui_duty_cycle5" value="50" />
<generic name="gui_cascade_counter6" value="false" />
<generic name="gui_output_clock_frequency6" value="100.0" />
<generic name="gui_divide_factor_c6" value="1" />
<generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
<generic name="gui_ps_units6" value="ps" />
<generic name="gui_phase_shift6" value="0" />
<generic name="gui_phase_shift_deg6" value="0.0" />
<generic name="gui_actual_phase_shift6" value="0" />
<generic name="gui_duty_cycle6" value="50" />
<generic name="gui_cascade_counter7" value="false" />
<generic name="gui_output_clock_frequency7" value="100.0" />
<generic name="gui_divide_factor_c7" value="1" />
<generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
<generic name="gui_ps_units7" value="ps" />
<generic name="gui_phase_shift7" value="0" />
<generic name="gui_phase_shift_deg7" value="0.0" />
<generic name="gui_actual_phase_shift7" value="0" />
<generic name="gui_duty_cycle7" value="50" />
<generic name="gui_cascade_counter8" value="false" />
<generic name="gui_output_clock_frequency8" value="100.0" />
<generic name="gui_divide_factor_c8" value="1" />
<generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
<generic name="gui_ps_units8" value="ps" />
<generic name="gui_phase_shift8" value="0" />
<generic name="gui_phase_shift_deg8" value="0.0" />
<generic name="gui_actual_phase_shift8" value="0" />
<generic name="gui_duty_cycle8" value="50" />
<generic name="gui_cascade_counter9" value="false" />
<generic name="gui_output_clock_frequency9" value="100.0" />
<generic name="gui_divide_factor_c9" value="1" />
<generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
<generic name="gui_ps_units9" value="ps" />
<generic name="gui_phase_shift9" value="0" />
<generic name="gui_phase_shift_deg9" value="0.0" />
<generic name="gui_actual_phase_shift9" value="0" />
<generic name="gui_duty_cycle9" value="50" />
<generic name="gui_cascade_counter10" value="false" />
<generic name="gui_output_clock_frequency10" value="100.0" />
<generic name="gui_divide_factor_c10" value="1" />
<generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
<generic name="gui_ps_units10" value="ps" />
<generic name="gui_phase_shift10" value="0" />
<generic name="gui_phase_shift_deg10" value="0.0" />
<generic name="gui_actual_phase_shift10" value="0" />
<generic name="gui_duty_cycle10" value="50" />
<generic name="gui_cascade_counter11" value="false" />
<generic name="gui_output_clock_frequency11" value="100.0" />
<generic name="gui_divide_factor_c11" value="1" />
<generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
<generic name="gui_ps_units11" value="ps" />
<generic name="gui_phase_shift11" value="0" />
<generic name="gui_phase_shift_deg11" value="0.0" />
<generic name="gui_actual_phase_shift11" value="0" />
<generic name="gui_duty_cycle11" value="50" />
<generic name="gui_cascade_counter12" value="false" />
<generic name="gui_output_clock_frequency12" value="100.0" />
<generic name="gui_divide_factor_c12" value="1" />
<generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
<generic name="gui_ps_units12" value="ps" />
<generic name="gui_phase_shift12" value="0" />
<generic name="gui_phase_shift_deg12" value="0.0" />
<generic name="gui_actual_phase_shift12" value="0" />
<generic name="gui_duty_cycle12" value="50" />
<generic name="gui_cascade_counter13" value="false" />
<generic name="gui_output_clock_frequency13" value="100.0" />
<generic name="gui_divide_factor_c13" value="1" />
<generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
<generic name="gui_ps_units13" value="ps" />
<generic name="gui_phase_shift13" value="0" />
<generic name="gui_phase_shift_deg13" value="0.0" />
<generic name="gui_actual_phase_shift13" value="0" />
<generic name="gui_duty_cycle13" value="50" />
<generic name="gui_cascade_counter14" value="false" />
<generic name="gui_output_clock_frequency14" value="100.0" />
<generic name="gui_divide_factor_c14" value="1" />
<generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
<generic name="gui_ps_units14" value="ps" />
<generic name="gui_phase_shift14" value="0" />
<generic name="gui_phase_shift_deg14" value="0.0" />
<generic name="gui_actual_phase_shift14" value="0" />
<generic name="gui_duty_cycle14" value="50" />
<generic name="gui_cascade_counter15" value="false" />
<generic name="gui_output_clock_frequency15" value="100.0" />
<generic name="gui_divide_factor_c15" value="1" />
<generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
<generic name="gui_ps_units15" value="ps" />
<generic name="gui_phase_shift15" value="0" />
<generic name="gui_phase_shift_deg15" value="0.0" />
<generic name="gui_actual_phase_shift15" value="0" />
<generic name="gui_duty_cycle15" value="50" />
<generic name="gui_cascade_counter16" value="false" />
<generic name="gui_output_clock_frequency16" value="100.0" />
<generic name="gui_divide_factor_c16" value="1" />
<generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
<generic name="gui_ps_units16" value="ps" />
<generic name="gui_phase_shift16" value="0" />
<generic name="gui_phase_shift_deg16" value="0.0" />
<generic name="gui_actual_phase_shift16" value="0" />
<generic name="gui_duty_cycle16" value="50" />
<generic name="gui_cascade_counter17" value="false" />
<generic name="gui_output_clock_frequency17" value="100.0" />
<generic name="gui_divide_factor_c17" value="1" />
<generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
<generic name="gui_ps_units17" value="ps" />
<generic name="gui_phase_shift17" value="0" />
<generic name="gui_phase_shift_deg17" value="0.0" />
<generic name="gui_actual_phase_shift17" value="0" />
<generic name="gui_duty_cycle17" value="50" />
<generic name="gui_pll_auto_reset" value="Off" />
<generic name="gui_pll_bandwidth_preset" value="Auto" />
<generic name="gui_en_reconf" value="false" />
<generic name="gui_en_dps_ports" value="false" />
<generic name="gui_en_phout_ports" value="false" />
<generic name="gui_phout_division" value="1" />
<generic name="gui_en_lvds_ports" value="false" />
<generic name="gui_mif_generate" value="false" />
<generic name="gui_enable_mif_dps" value="false" />
<generic name="gui_dps_cntr" value="C0" />
<generic name="gui_dps_num" value="1" />
<generic name="gui_dps_dir" value="Positive" />
<generic name="gui_refclk_switch" value="false" />
<generic name="gui_refclk1_frequency" value="100.0" />
<generic name="gui_switchover_mode" value="Automatic Switchover" />
<generic name="gui_switchover_delay" value="0" />
<generic name="gui_active_clk" value="false" />
<generic name="gui_clk_bad" value="false" />
<generic name="gui_enable_cascade_out" value="false" />
<generic name="gui_cascade_outclk_index" value="0" />
<generic name="gui_enable_cascade_in" value="false" />
<generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
<generic name="AUTO_REFCLK_CLOCK_RATE" value="-1" />
</instance>
examples/hdl4se_riscv/de1/de1_risc.cr.mti 0 → 100644
浏览文件 @ 08c63023
D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv_test.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv_test.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module de1_riscv_test
-- Compiling module de1_tester
Top level modules:
de1_tester
} {} {}} C:/altera/13.1/quartus/eda/sim_lib/220model.v {1 {vlog -work work C:/altera/13.1/quartus/eda/sim_lib/220model.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module LPM_MEMORY_INITIALIZATION
-- Compiling module LPM_HINT_EVALUATION
-- Compiling module LPM_DEVICE_FAMILIES
-- Compiling module lpm_constant
-- Compiling module lpm_inv
-- Compiling module lpm_and
-- Compiling module lpm_or
-- Compiling module lpm_xor
-- Compiling module lpm_bustri
-- Compiling module lpm_mux
-- Compiling module lpm_decode
-- Compiling module lpm_clshift
-- Compiling module lpm_add_sub
-- Compiling module lpm_compare
-- Compiling module lpm_mult
-- Compiling module lpm_divide
-- Compiling module lpm_abs
-- Compiling module lpm_counter
-- Compiling module lpm_latch
-- Compiling module lpm_ff
-- Compiling module lpm_shiftreg
-- Compiling module lpm_ram_dq
-- Compiling module lpm_ram_dp
-- Compiling module lpm_ram_io
-- Compiling module lpm_rom
-- Compiling module lpm_fifo
-- Compiling module lpm_fifo_dc_dffpipe
-- Compiling module lpm_fifo_dc_fefifo
-- Compiling module lpm_fifo_dc_async
-- Compiling module lpm_fifo_dc
-- Compiling module lpm_inpad
-- Compiling module lpm_outpad
-- Compiling module lpm_bipad
Top level modules:
lpm_constant
lpm_inv
lpm_and
lpm_or
lpm_xor
lpm_bustri
lpm_mux
lpm_decode
lpm_clshift
lpm_add_sub
lpm_compare
lpm_mult
lpm_divide
lpm_abs
lpm_counter
lpm_latch
lpm_ff
lpm_shiftreg
lpm_ram_dq
lpm_ram_dp
lpm_ram_io
lpm_rom
lpm_fifo
lpm_fifo_dc
lpm_inpad
lpm_outpad
lpm_bipad
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/suber.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module suber
Top level modules:
suber
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module mult
Top level modules:
mult
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/ram/ram8kb.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/ram/ram8kb.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module ram8kb
Top level modules:
ram8kb
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/verilog/riscv_core.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module riscv_core
Top level modules:
riscv_core
} {} {}} C:/altera/13.1/quartus/eda/sim_lib/altera_mf.v {1 {vlog -work work C:/altera/13.1/quartus/eda/sim_lib/altera_mf.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module lcell
-- Compiling module ALTERA_MF_MEMORY_INITIALIZATION
-- Compiling module ALTERA_MF_HINT_EVALUATION
-- Compiling module ALTERA_DEVICE_FAMILIES
-- Compiling module dffp
-- Compiling module pll_iobuf
-- Compiling module stx_m_cntr
-- Compiling module stx_n_cntr
-- Compiling module stx_scale_cntr
-- Compiling module MF_pll_reg
-- Compiling module MF_stratix_pll
-- Compiling module arm_m_cntr
-- Compiling module arm_n_cntr
-- Compiling module arm_scale_cntr
-- Compiling module MF_stratixii_pll
-- Compiling module ttn_m_cntr
-- Compiling module ttn_n_cntr
-- Compiling module ttn_scale_cntr
-- Compiling module MF_stratixiii_pll
-- Compiling module cda_m_cntr
-- Compiling module cda_n_cntr
-- Compiling module cda_scale_cntr
-- Compiling module MF_cycloneiii_pll
-- Compiling module MF_cycloneiiigl_m_cntr
-- Compiling module MF_cycloneiiigl_n_cntr
-- Compiling module MF_cycloneiiigl_scale_cntr
-- Compiling module cycloneiiigl_post_divider
-- Compiling module MF_cycloneiiigl_pll
-- Compiling module altpll
-- Compiling module altlvds_rx
-- Compiling module stratix_lvds_rx
-- Compiling module stratixgx_dpa_lvds_rx
-- Compiling module stratixii_lvds_rx
-- Compiling module flexible_lvds_rx
-- Compiling module stratixiii_lvds_rx
-- Compiling module stratixiii_lvds_rx_channel
-- Compiling module stratixiii_lvds_rx_dpa
-- Compiling module altlvds_tx
-- Compiling module stratixv_local_clk_divider
-- Compiling module stratix_tx_outclk
-- Compiling module stratixii_tx_outclk
-- Compiling module flexible_lvds_tx
-- Compiling module dcfifo_dffpipe
-- Compiling module dcfifo_fefifo
-- Compiling module dcfifo_async
-- Compiling module dcfifo_sync
-- Compiling module dcfifo_low_latency
-- Compiling module dcfifo_mixed_widths
-- Compiling module dcfifo
-- Compiling module altaccumulate
-- Compiling module altmult_accum
-- Compiling module altmult_add
-- Compiling module altfp_mult
-- Compiling module altsqrt
-- Compiling module altclklock
-- Compiling module altddio_in
-- Compiling module altddio_out
-- Compiling module altddio_bidir
-- Compiling module altdpram
-- Compiling module altsyncram
-- Compiling module alt3pram
-- Compiling module parallel_add
-- Compiling module scfifo
-- Compiling module altshift_taps
-- Compiling module a_graycounter
-- Compiling module altsquare
-- Compiling module altera_std_synchronizer
-- Compiling module altera_std_synchronizer_bundle
-- Compiling module alt_cal
-- Compiling module alt_cal_mm
-- Compiling module alt_cal_c3gxb
-- Compiling module alt_cal_sv
-- Compiling module alt_cal_av
-- Compiling module alt_aeq_s4
-- Compiling module alt_eyemon
-- Compiling module alt_dfe
-- Compiling module signal_gen
-- Compiling module jtag_tap_controller
-- Compiling module dummy_hub
-- Compiling module sld_virtual_jtag
-- Compiling module sld_signaltap
-- Compiling module altstratixii_oct
-- Compiling module altparallel_flash_loader
-- Compiling module altserial_flash_loader
-- Compiling module sld_virtual_jtag_basic
-- Compiling module altsource_probe
Top level modules:
lcell
altpll
altlvds_rx
altlvds_tx
dcfifo
altaccumulate
altmult_accum
altmult_add
altfp_mult
altsqrt
altclklock
altddio_bidir
altdpram
alt3pram
parallel_add
scfifo
altshift_taps
a_graycounter
altsquare
altera_std_synchronizer_bundle
alt_cal
alt_cal_mm
alt_cal_c3gxb
alt_cal_sv
alt_cal_av
alt_aeq_s4
alt_eyemon
alt_dfe
sld_virtual_jtag
sld_signaltap
altstratixii_oct
altparallel_flash_loader
altserial_flash_loader
sld_virtual_jtag_basic
altsource_probe
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div_s.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module div_s
Top level modules:
div_s
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mulsu.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module mulsu
Top level modules:
mulsu
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/de1_riscv.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module de1_riscv
Top level modules:
de1_riscv
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/adder.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module adder
Top level modules:
adder
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/regfile/regfile.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module regfile
Top level modules:
regfile
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/div.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module div
Top level modules:
div
} {} {}} D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult_s.v {1 {vlog -work work D:/gitwork/hdl4se/examples/hdl4se_riscv/de1/alu/mult_s.v
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module mult_s
Top level modules:
mult_s
} {} {}}
examples/hdl4se_riscv/de1/de1_risc.mpf 0 → 100644
浏览文件 @ 08c63023
此差异已折叠。
examples/hdl4se_riscv/de1/de1_riscv.qsf
浏览文件 @ 08c63023
......@@ -503,4 +503,7 @@ set_global_assignment -name QIP_FILE alu/div.qip
set_global_assignment -name QIP_FILE alu/div_s.qip
set_global_assignment -name QIP_FILE alu/adder.qip
set_global_assignment -name QIP_FILE alu/suber.qip
set_global_assignment -name QIP_FILE alu/mulsu.qip
set_global_assignment -name QIP_FILE clk/clk100M.qip
set_global_assignment -name SIP_FILE clk/clk100M.sip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
examples/hdl4se_riscv/de1/de1_riscv.sdc
浏览文件 @ 08c63023
......@@ -11,6 +11,8 @@ create_clock -period 20.000ns [get_ports CLOCK3_50]
create_clock -period 20.000ns [get_ports CLOCK4_50]
create_clock -period 20.000ns [get_ports CLOCK_50]
create_clock -period 2.500ns -name clk_core
create_clock -period "27 MHz" -name tv_27m [get_ports TD_CLK27]
create_clock -period "100 MHz" -name clk_dram [get_ports DRAM_CLK]
# AUDIO : 48kHz 384fs 32-bit data
......
examples/hdl4se_riscv/de1/de1_riscv.v
浏览文件 @ 08c63023
......@@ -90,20 +90,29 @@ module de1_riscv(
inout [35:0] GPIO
);
wire wClk = CLOCK_50;
wire clk100MHz, clk75MHz, clklocked;
clk100M clk100(.refclk(CLOCK_50),
.rst(~KEY[3]),
.outclk_0(clk100MHz),
.outclk_1(clk75MHz),
.locked(clklocked));
wire wClk = clk100MHz;
wire nwReset = KEY[3];
wire wWrite, wRead;
wire [31:0] bWriteAddr, bWriteData, bReadAddr, bReadData, bReadDataRam, bReadDataKey;
wire [3:0] bWriteMask;
wire wRead_out = readcmd;
wire [31:0] bReadAddr_out = readaddr;
assign bReadDataKey = {18'b0, KEY, SW};
reg readcmd;
reg [31:0] readaddr;
wire wRead_out = readcmd;
wire [31:0] bReadAddr_out = readaddr;
always @(posedge wClk) begin
if (!nwReset) begin
readcmd <= 1'b0;
......
examples/hdl4se_riscv/de1/de1_riscv_test.v 0 → 100644
浏览文件 @ 08c63023
//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
module de1_riscv_test(
output CLOCK_50,
output [3:0] KEY
);
reg wClk;
reg nwReset;
assign CLOCK_50 = wClk;
assign KEY[3] = nwReset;
always #1 wClk = ~wClk;
initial begin
wClk = 0;
nwReset = 1;
#10
nwReset = 0;
#100
nwReset = 1;
end
endmodule
module de1_tester;
wire wClk;
wire [3:0] key;
de1_riscv_test test(wClk, key);
de1_riscv riscv(.CLOCK_50(wClk), .KEY(key));
endmodule
examples/hdl4se_riscv/de1/ram/ram8kb.v
浏览文件 @ 08c63023
......@@ -90,19 +90,14 @@ module ram8kb (
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "test.rif"
`else
altsyncram_component.init_file = "test.hex"
`endif
,
altsyncram_component.init_file = "test.mif",
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 11,
......@@ -134,13 +129,13 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "test.hex"
// Retrieval info: PRIVATE: MIFfilename STRING "test.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
......@@ -152,14 +147,14 @@ endmodule
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "test.hex"
// Retrieval info: CONSTANT: INIT_FILE STRING "test.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
......
examples/hdl4se_riscv/de1/ram/ram8kb_bb.v
浏览文件 @ 08c63023
......@@ -78,13 +78,13 @@ endmodule
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "test.hex"
// Retrieval info: PRIVATE: MIFfilename STRING "test.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
......@@ -96,14 +96,14 @@ endmodule
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "test.hex"
// Retrieval info: CONSTANT: INIT_FILE STRING "test.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
......
examples/hdl4se_riscv/de1/ram_256KB.qip 已删除 100644 → 0
浏览文件 @ 36cd978d
set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram_256KB.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_256KB_bb.v"]
examples/hdl4se_riscv/de1/ram_256KB.v 已删除 100644 → 0
浏览文件 @ 36cd978d
// megafunction wizard: %RAM: 1-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_256KB.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module ram_256KB (
address,
byteena,
clock,
data,
wren,
q);
input [15:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
altsyncram altsyncram_component (
.address_a (address),
.byteena_a (byteena),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_a (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.address_b (1'b1),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b (1'b1),
.eccstatus (),
.q_b (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.byte_size = 8,
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_output_a = "BYPASS",
`ifdef NO_PLI
altsyncram_component.init_file = "test.rif"
`else
altsyncram_component.init_file = "test.hex"
`endif
,
altsyncram_component.intended_device_family = "Cyclone V",
altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 65536,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 16,
altsyncram_component.width_a = 32,
altsyncram_component.width_byteena_a = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "test.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "test.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256KB.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256KB.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256KB.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256KB.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256KB_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256KB_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
examples/hdl4se_riscv/de1/ram_256KB_bb.v 已删除 100644 → 0
浏览文件 @ 36cd978d
// megafunction wizard: %RAM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram_256KB.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.0 Build 162 10/23/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module ram_256KB (
address,
byteena,
clock,
data,
wren,
q);
input [15:0] address;
input [3:0] byteena;
input clock;
input [31:0] data;
input wren;
output [31:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 [3:0] byteena;
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrData NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "1"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "test.hex"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "65536"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
// Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "16"
// Retrieval info: PRIVATE: WidthData NUMERIC "32"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "test.hex"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "65536"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4"
// Retrieval info: USED_PORT: address 0 0 16 0 INPUT NODEFVAL "address[15..0]"
// Retrieval info: USED_PORT: byteena 0 0 4 0 INPUT VCC "byteena[3..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
// Retrieval info: CONNECT: @address_a 0 0 16 0 address 0 0 16 0
// Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena 0 0 4 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 32 0 data 0 0 32 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256KB.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256KB.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256KB.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256KB.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256KB_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL ram_256KB_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
examples/hdl4se_riscv/de1/regfile/regfile.v
浏览文件 @ 08c63023
......@@ -96,7 +96,7 @@ module regfile (
altsyncram_component.numwords_a = 32,
altsyncram_component.operation_mode = "SINGLE_PORT",
altsyncram_component.outdata_aclr_a = "NONE",
altsyncram_component.outdata_reg_a = "CLOCK0",
altsyncram_component.outdata_reg_a = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ",
altsyncram_component.widthad_a = 5,
......@@ -134,7 +134,7 @@ endmodule
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
......@@ -152,7 +152,7 @@ endmodule
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
......
examples/hdl4se_riscv/de1/regfile/regfile_bb.v
浏览文件 @ 08c63023
......@@ -84,7 +84,7 @@ endmodule
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegData NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
......@@ -102,7 +102,7 @@ endmodule
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "5"
......
examples/hdl4se_riscv/de1/test.hex 0 → 100644
浏览文件 @ 08c63023
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examples/hdl4se_riscv/de1/test.mif 0 → 100644
浏览文件 @ 08c63023
此差异已折叠。
examples/hdl4se_riscv/de1/test.ver 0 → 100644
浏览文件 @ 08c63023
此差异已折叠。
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_core_v2.c
浏览文件 @ 08c63023
......@@ -308,16 +308,28 @@ void riscv_core_exec_alu_inst(MODULE_DATA_TYPE* pobj, unsigned int pc, unsigned
rst = s1 >> 32;
}break;
case 4: { //div
*(int *)&rst = *(int*)&rs1 / *(int*)&rs2;
if (rs2 == 0)
rst = 0xffffffff;
else
*(int *)&rst = *(int*)&rs1 / *(int*)&rs2;
}break;
case 5: { //divu
rst = rs1 / rs2;
if (rs2 == 0)
rst = 0xffffffff;
else
rst = rs1 / rs2;
}break;
case 6: { //rem
*(int*)&rst = *(int*)&rs1 % *(int*)&rs2;
if (rs2 == 0)
rst = rs1;
else
*(int*)&rst = *(int*)&rs1 % *(int*)&rs2;
}break;
case 7: { //remu
rst = rs1 % rs2;
if (rs2 == 0)
rst = rs1;
else
rst = rs1 % rs2;
}break;
}
......@@ -790,7 +802,7 @@ MODULE_INIT(riscv_core)
PORT_IN(bReadData, 32);
GPORT_OUT(regno, 5, riscv_core_reg_wr_sig);
GPORT_OUT(regena, 4, riscv_core_reg_wr_sig);
GPORT_OUT(regwrdata, 31, riscv_core_reg_wr_sig);
GPORT_OUT(regwrdata, 32, riscv_core_reg_wr_sig);
GPORT_OUT(regwren, 1, riscv_core_reg_wr_sig);
PORT_IN(regrddata, 32);
GREG(pc, 32, riscv_core_reg_gen_pc);
......
examples/hdl4se_riscv/hdl4se_riscv_sim/hdl4se_riscv_ram8k.c
浏览文件 @ 08c63023
......@@ -184,6 +184,19 @@ static int loadExecImage(unsigned char* data, int maxlen)
}
}
fclose(pFile);
pFile = fopen(DATADIR"test_code/test.mif", "wt");
fprintf(pFile, "DEPTH = %d;\n", RAMSIZE);
fprintf(pFile, "WIDTH = 32;\n");
fprintf(pFile, "ADDRESS_RADIX = HEX;\n");
fprintf(pFile, "DATA_RADIX = HEX;\n");
fprintf(pFile, "CONTENT\n");
fprintf(pFile, "BEGIN\n");
for (addr = 0; addr < RAMSIZE; addr++) {
fprintf(pFile, "%04X : %08X;\n", addr, *(unsigned int *)(data + addr * 4));
}
fprintf(pFile, "END;\n");
fclose(pFile);
}
MODULE_INIT(riscv_ram)
......
examples/hdl4se_riscv/hdl4se_riscv_sim/riscv_sim_main_v2.c
浏览文件 @ 08c63023
......@@ -31,7 +31,7 @@
/*
* Created by HDL4SE @ Wed Aug 25 16:02:24 2021
* Created by HDL4SE @ Thu Aug 26 19:19:15 2021
* Don't edit it.
*/
......
examples/hdl4se_riscv/test_code/main.c
浏览文件 @ 08c63023
......@@ -22,13 +22,14 @@ unsigned int num2seg(unsigned int num)
int main(int argc, char* argv[])
{
unsigned long long count, ctemp;
int countit = 0;
int countit = 1;
unsigned int* ledkey = (unsigned int*)0xF0000000;
unsigned int* leddata = (unsigned int*)0xf0000010;
count = 0;
leddata[0] = 0x3f3f3f3f;
leddata[0] = 0x6f7f077d;
leddata[1] = 0x6d664f5b;
do {
unsigned int key;
/*unsigned int key;
key = *ledkey;
if (key & 1) {
count = 0;
......@@ -39,8 +40,9 @@ int main(int argc, char* argv[])
else if (key & 4) {
countit = 1;
}
if (countit)
if (countit)*/
count++;
ctemp = count;
leddata[0] = num2seg(ctemp) |
((num2seg(ctemp / 10ll)) << 8) |
......
examples/hdl4se_riscv/test_code/test.cod
浏览文件 @ 08c63023
@00000074
93 07 00 00 63 88 07 00 37 15 00 00 13 05 C5 BB
6F 00 50 39 67 80 00 00 97 11 00 00 93 81 C1 7A
93 07 00 00 63 88 07 00 37 15 00 00 13 05 85 B7
6F 00 10 35 67 80 00 00 97 11 00 00 93 81 C1 7A
13 85 41 C4 13 86 01 C6 33 06 A6 40 93 05 00 00
EF 00 D0 11 17 15 00 00 13 05 05 B7 63 08 05 00
17 15 00 00 13 05 85 B0 EF 00 D0 35 EF 00 50 06
EF 00 90 0D 17 15 00 00 13 05 C5 B2 63 08 05 00
17 15 00 00 13 05 45 AC EF 00 90 31 EF 00 10 02
03 25 01 00 93 05 41 00 13 06 00 00 EF 00 C0 0A
6F 00 10 02 13 01 01 FF 23 24 81 00 83 C7 41 C4
6F 00 C0 7D 13 01 01 FF 23 24 81 00 83 C7 41 C4
23 26 11 00 63 92 07 02 93 07 00 00 63 8A 07 00
37 15 00 00 13 05 05 00 97 00 00 00 E7 00 00 00
93 07 10 00 23 82 F1 C4 83 20 C1 00 03 24 81 00
......@@ -17,190 +17,186 @@ B3 77 F7 02 17 17 00 00 03 27 47 31 93 97 27 00
B3 07 F7 00 83 A7 07 00 13 85 07 00 03 24 C1 01
13 01 01 02 67 80 00 00 13 01 01 FC 23 2E 11 02
23 2C 81 02 23 2A 91 02 13 04 01 04 23 26 A4 FC
23 24 B4 FC 23 22 04 FE B7 07 00 F0 23 20 F4 FE
B7 07 00 F0 93 87 07 01 23 2E F4 FC 93 07 00 00
13 08 00 00 23 24 F4 FE 23 26 04 FF 83 27 C4 FD
37 47 3F 3F 13 07 F7 F3 23 A0 E7 00 83 27 04 FE
83 A7 07 00 23 2C F4 FC 83 27 84 FD 93 F7 17 00
63 8C 07 00 93 07 00 00 13 08 00 00 23 24 F4 FE
23 26 04 FF 6F 00 C0 02 83 27 84 FD 93 F7 27 00
63 86 07 00 23 22 04 FE 6F 00 80 01 83 27 84 FD
93 F7 47 00 63 86 07 00 93 07 10 00 23 22 F4 FE
83 27 44 FE 63 8A 07 02 03 26 84 FE 83 26 C4 FE
13 05 10 00 93 05 00 00 33 07 A6 00 13 08 07 00
33 38 C8 00 B3 87 B6 00 B3 06 F8 00 93 87 06 00
23 24 E4 FE 23 26 F4 FE 03 27 84 FE 83 27 C4 FE
23 28 E4 FC 23 2A F4 FC 83 27 04 FD 13 85 07 00
EF F0 9F EC 93 04 05 00 03 27 04 FD 83 27 44 FD
13 06 A0 00 93 06 00 00 13 05 07 00 93 85 07 00
EF 00 00 23 13 07 05 00 93 87 05 00 93 07 07 00
13 85 07 00 EF F0 5F E9 93 07 05 00 93 97 87 00
B3 E4 F4 00 03 27 04 FD 83 27 44 FD 13 06 40 06
93 06 00 00 13 05 07 00 93 85 07 00 EF 00 40 1F
13 07 05 00 93 87 05 00 93 07 07 00 13 85 07 00
EF F0 9F E5 93 07 05 00 93 97 07 01 B3 E4 F4 00
03 27 04 FD 83 27 44 FD 13 06 80 3E 93 06 00 00
13 05 07 00 93 85 07 00 EF 00 80 1B 13 07 05 00
93 87 05 00 93 07 07 00 13 85 07 00 EF F0 DF E1
93 07 05 00 93 97 87 01 33 E7 F4 00 83 27 C4 FD
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@00000CFC
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13 04 C4 FF 33 04 F4 00 83 27 04 00 93 84 F4 FF
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93 05 05 00 93 06 00 00 13 06 00 00 13 05 00 00
6F 00 40 00 03 A7 81 C3 83 27 87 14 63 8C 07 04
03 A7 47 00 13 08 F0 01 63 4E E8 06 13 18 27 00
63 06 05 02 33 83 07 01 23 24 C3 08 83 A8 87 18
13 06 10 00 33 16 E6 00 B3 E8 C8 00 23 A4 17 19
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23 A2 E7 00 B3 87 07 01 23 A4 B7 00 13 05 00 00
67 80 00 00 93 07 C7 14 23 24 F7 14 6F F0 5F FA
83 A6 C7 18 13 07 17 00 23 A2 E7 00 B3 E6 C6 00
23 A6 D7 18 B3 87 07 01 23 A4 B7 00 13 05 00 00
67 80 00 00 13 05 F0 FF 67 80 00 00 93 08 D0 05
73 00 00 00 63 44 05 00 6F 00 00 00 13 01 01 FF
23 24 81 00 13 04 05 00 23 26 11 00 33 04 80 40
EF 00 C0 00 23 20 85 00 6F 00 00 00 03 A5 01 C4
67 80 00 00
@00000CB8
3F 00 00 00 06 00 00 00 5B 00 00 00 4F 00 00 00
66 00 00 00 6D 00 00 00 7D 00 00 00 07 00 00 00
7F 00 00 00 6F 00 00 00 00 01 02 02 03 03 03 03
......@@ -222,7 +218,7 @@ B3 E6 C6 00 23 A6 D7 18 B3 87 07 01 23 A4 B7 00
08 08 08 08 08 08 08 08
@00001000
10 00 00 00 00 00 00 00 03 7A 52 00 01 7C 01 01
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1B 0D 02 00 10 00 00 00 18 00 00 00 64 F4 FF FF
30 04 00 00 00 00 00 00 00 00 00 00
@0000102C
74 00 00 00 1C 01 00 00
......@@ -297,6 +293,6 @@ D8 00 00 00
00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
00 00 00 00 00 00 00 00
@00001460
FF FF FF FF 00 00 00 00 00 00 00 00 FC 0C 00 00
FF FF FF FF 00 00 00 00 00 00 00 00 B8 0C 00 00
@00001470
38 10 00 00 00 00 00 00 38 10 00 00
examples/hdl4se_riscv/test_code/test.hex
浏览文件 @ 08c63023
:100074009307000063880700371500001305C5BB0C
:100084006F00503967800000971100009381C17A96
:10007400930700006388070037150000130585B750
:100084006F00103567800000971100009381C17ADA
:10009400138541C4138601C63306A64093050000A8
:1000A400EF00D01117150000130505B7630805000C
:1000B40017150000130585B0EF00D035EF0050068A
:1000A400EF00900D171500001305C5B26308050095
:1000B40017150000130545ACEF009031EF00100256
:1000C400032501009305410013060000EF00C00A58
:1000D4006F001002130101FF2324810083C741C470
:1000D4006F00C07D130101FF2324810083C741C445
:1000E400232611006392070293070000638A070026
:1000F400371500001305050097000000E700000015
:10010400930710002382F1C48320C10003248100DB
......@@ -16,210 +16,206 @@
:10016400B307F70083A70700138507000324C10121
:100174001301010267800000130101FC232E110208
:10018400232C8102232A9102130401042326A4FCB4
:100194002324B4FC232204FEB70700F02320F4FE3A
:1001A400B70700F093870701232EF4FC93070000A0
:1001B400130800002324F4FE232604FF8327C4FD30
:1001C40037473F3F1307F7F323A0E700832704FED5
:1001D40083A70700232CF4FC832784FD93F71700DF
:1001E400638C070093070000130800002324F4FE27
:1001F400232604FF6F00C002832784FD93F72700A2
:1002040063860700232204FE6F008001832784FD98
:1002140093F7470063860700930710002322F4FE38
:10022400832744FE638A0702032684FE8326C4FED2
:1002340013051000930500003307A60013080700F8
:100244003338C800B387B600B306F80093870600B6
:100254002324E4FE2326F4FE032784FE8327C4FE1E
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:100C7400678000001305F0FF678000009308D0052B
:100C840073000000634405006F000000130101FFBE
:100C9400232481001304050023261100330480401B
:100CA400EF00C000232085006F00000003A501C4ED
:040CB4006780000055
:100CB8003F000000060000005B0000004F0000003D
:100CC800660000006D0000007D00000007000000C5
:100CD8007F0000006F00000000010202030303030D
:100CE80004040404040404040505050505050505B4
:100CF8000505050505050505060606060606060694
:100D0800060606060606060606060606060606067B
:100D18000606060606060606070707070707070763
:100D2800070707070707070707070707070707074B
:100D3800070707070707070707070707070707073B
:100D4800070707070707070707070707070707072B
:100D58000707070707070707080808080808080813
:100D680008080808080808080808080808080808FB
:100D780008080808080808080808080808080808EB
:100D880008080808080808080808080808080808DB
:100D980008080808080808080808080808080808CB
:100DA80008080808080808080808080808080808BB
:100DB80008080808080808080808080808080808AB
:100DC800080808080808080808080808080808089B
:080DD8000808080808080808D3
:101000001000000000000000037A5200017C010182
:101010001B0D02001000000018000000A8F4FFFFE4
:101010001B0D0200100000001800000064F4FFFF28
:0C10200030040000000000000000000090
:08102C00740000001C0100002B
:04103400D8000000E0
......@@ -290,7 +286,7 @@
:1014380000000000000000000000000000000000A4
:101448000000000000000000000000000000000094
:0814580000000000000000008C
:10146000FFFFFFFF0000000000000000FC0C000078
:10146000FFFFFFFF0000000000000000B80C0000BC
:0C147000381000000000000038100000E0
:040000030000008C6D
:00000001FF
examples/hdl4se_riscv/test_code/test.info
浏览文件 @ 08c63023
......@@ -22,8 +22,8 @@ ELF Header:
Section Headers:
[Nr] Name Type Addr Off Size ES Flg Lk Inf Al
[ 0] NULL 00000000 000000 000000 00 0 0 0
[ 1] .text PROGBITS 00000074 000074 000c88 00 AX 0 0 4
[ 2] .rodata PROGBITS 00000cfc 000cfc 000128 00 A 0 0 4
[ 1] .text PROGBITS 00000074 000074 000c44 00 AX 0 0 4
[ 2] .rodata PROGBITS 00000cb8 000cb8 000128 00 A 0 0 4
[ 3] .eh_frame PROGBITS 00001000 001000 00002c 00 WA 0 0 4
[ 4] .init_array INIT_ARRAY 0000102c 00102c 000008 04 WA 0 0 4
[ 5] .fini_array FINI_ARRAY 00001034 001034 000004 04 WA 0 0 4
......@@ -54,7 +54,7 @@ There are no section groups in this file.
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000000 0x00000000 0x00000000 0x00e24 0x00e24 R E 0x1000
LOAD 0x000000 0x00000000 0x00000000 0x00de0 0x00de0 R E 0x1000
LOAD 0x001000 0x00001000 0x00001000 0x0047c 0x00498 RW 0x1000
Section to Segment mapping:
......@@ -72,7 +72,7 @@ Symbol table '.symtab' contains 77 entries:
Num: Value Size Type Bind Vis Ndx Name
0: 00000000 0 NOTYPE LOCAL DEFAULT UND
1: 00000074 0 SECTION LOCAL DEFAULT 1 .text
2: 00000cfc 0 SECTION LOCAL DEFAULT 2 .rodata
2: 00000cb8 0 SECTION LOCAL DEFAULT 2 .rodata
3: 00001000 0 SECTION LOCAL DEFAULT 3 .eh_frame
4: 0000102c 0 SECTION LOCAL DEFAULT 4 .init_array
5: 00001034 0 SECTION LOCAL DEFAULT 5 .fini_array
......@@ -123,30 +123,30 @@ Symbol table '.symtab' contains 77 entries:
50: 0000102c 0 NOTYPE LOCAL DEFAULT 4 __init_array_start
51: 0000102c 0 NOTYPE LOCAL DEFAULT 4 __preinit_array_start
52: 00001838 0 NOTYPE GLOBAL DEFAULT ABS __global_pointer$
53: 00000cfc 40 OBJECT GLOBAL DEFAULT 2 segcode
54: 00000cf4 8 FUNC GLOBAL DEFAULT 1 __errno
53: 00000cb8 40 OBJECT GLOBAL DEFAULT 2 segcode
54: 00000cb0 8 FUNC GLOBAL DEFAULT 1 __errno
55: 00001470 0 NOTYPE GLOBAL DEFAULT 8 __SDATA_BEGIN__
56: 00001474 0 OBJECT GLOBAL HIDDEN 8 __dso_handle
57: 00001470 4 OBJECT GLOBAL DEFAULT 8 _global_impure_ptr
58: 00000924 156 FUNC GLOBAL DEFAULT 1 __libc_init_array
59: 000004c4 1072 FUNC GLOBAL HIDDEN 1 __udivdi3
60: 00000bbc 92 FUNC GLOBAL DEFAULT 1 __libc_fini_array
61: 00000a9c 288 FUNC GLOBAL DEFAULT 1 __call_exitprocs
58: 000008e0 156 FUNC GLOBAL DEFAULT 1 __libc_init_array
59: 00000480 1072 FUNC GLOBAL HIDDEN 1 __udivdi3
60: 00000b78 92 FUNC GLOBAL DEFAULT 1 __libc_fini_array
61: 00000a58 288 FUNC GLOBAL DEFAULT 1 __call_exitprocs
62: 0000008c 76 FUNC GLOBAL DEFAULT 1 _start
63: 00000c2c 152 FUNC GLOBAL DEFAULT 1 __register_exitproc
63: 00000be8 152 FUNC GLOBAL DEFAULT 1 __register_exitproc
64: 00001498 0 NOTYPE GLOBAL DEFAULT 9 __BSS_END__
65: 0000147c 0 NOTYPE GLOBAL DEFAULT 9 __bss_start
66: 000009c0 220 FUNC GLOBAL DEFAULT 1 memset
67: 0000017c 840 FUNC GLOBAL DEFAULT 1 main
68: 00000d24 256 OBJECT GLOBAL HIDDEN 2 __clz_tab
69: 00000c18 20 FUNC GLOBAL DEFAULT 1 atexit
66: 0000097c 220 FUNC GLOBAL DEFAULT 1 memset
67: 0000017c 772 FUNC GLOBAL DEFAULT 1 main
68: 00000ce0 256 OBJECT GLOBAL HIDDEN 2 __clz_tab
69: 00000bd4 20 FUNC GLOBAL DEFAULT 1 atexit
70: 00001478 4 OBJECT GLOBAL DEFAULT 8 _impure_ptr
71: 00001038 0 NOTYPE GLOBAL DEFAULT 6 __DATA_BEGIN__
72: 0000013c 64 FUNC GLOBAL DEFAULT 1 num2seg
73: 0000147c 0 NOTYPE GLOBAL DEFAULT 8 _edata
74: 00001498 0 NOTYPE GLOBAL DEFAULT 9 _end
75: 000008f4 48 FUNC GLOBAL DEFAULT 1 exit
76: 00000cc4 48 FUNC GLOBAL DEFAULT 1 _exit
75: 000008b0 48 FUNC GLOBAL DEFAULT 1 exit
76: 00000c80 48 FUNC GLOBAL DEFAULT 1 _exit
No version information found in this file.
Attribute Section: riscv
......
examples/hdl4se_riscv/test_code/test.mif 0 → 100644
浏览文件 @ 08c63023
此差异已折叠。
examples/hdl4se_riscv/verilog/riscv_core.v
浏览文件 @ 08c63023
......@@ -61,7 +61,7 @@ module riscv_core(
output reg [3:0] regena,
output reg [31:0] regwrdata,
output reg regwren,
input regrddata
input [31:0] regrddata
);
reg [31:0] pc; //GREG(pc, 32, riscv_core_reg_gen_pc);
......@@ -96,13 +96,21 @@ module riscv_core(
wire [31:0] sub_result;
wire [63:0] mul_result;
wire [63:0] muls_result;
wire [71:0] mulsu_result;
wire [31:0] div_result_r, mod_result_r, divs_result_r, mods_result_r;
wire [31:0] div_result, mod_result, divs_result, mods_result;
adder add(rs1, rs2, add_result);
suber sub(rs1, rs2, sub_result);
mult mul(rs1, rs2, mul_result);
mult_s mul_s(rs1, rs2, muls_result);
div div(rs1, rs2, div_result, mod_result);
div_s divs(rs1, rs2, divs_result, mods_result);
mulsu mul_su(rs1, {8'b0, rs2}, mulsu_result);
div div(rs2, rs1, div_result_r, mod_result_r);
div_s divs(rs2, rs1, divs_result_r, mods_result_r);
assign div_result = (rs2 == 0) ? 32'hffffffff : div_result_r;
assign divs_result = (rs2 == 0) ? 32'hffffffff : divs_result_r;
assign mod_result = (rs2 == 0) ? rs1 : mod_result_r;
assign mods_result = (rs2 == 0) ? rs1 : mods_result_r;
/* cond */
always @(rs1 or rs2 or rs1_s or rs2_s or func3)
......@@ -119,7 +127,7 @@ module riscv_core(
//DEFINE_FUNC(riscv_core_reg_gen_pc, "nwReset, state, instr, pc, rs1, imm, regrddata") {
always @(posedge wClk)
if (!nwReset == 0) begin
if (!nwReset) begin
pc <= 32'h00000074;
end else begin
if (state == `RISCVSTATE_EXEC_INST) begin
......@@ -199,6 +207,8 @@ module riscv_core(
end
endcase
end
end else begin
write <= 0;
end
//DEFINE_FUNC(riscv_core_gen_state, "state, instr, nwReset") {
......@@ -374,22 +384,34 @@ module riscv_core(
dstvalue <= muls_result[63:32];
end
2: begin //mulhsu
dstvalue <= muls_result[63:32]; //?
dstvalue <= mulsu_result[63:32];
end
3: begin //mulhu
dstvalue <= mul_result[63:32];
end
4: begin //div
dstvalue <= divs_result;
if (rs2 == 0)
dstvalue <= 32'hffffffff;
else
dstvalue <= divs_result;
end
5: begin //divu
dstvalue <= div_result;
if (rs2 == 0)
dstvalue <= 32'hffffffff;
else
dstvalue <= div_result;
end
6: begin//rem
dstvalue <= mods_result;
if (rs2 == 0)
dstvalue <= rs1;
else
dstvalue <= mods_result;
end
7: begin //remu
dstvalue <= mod_result;
if (rs2 == 0)
dstvalue <= rs1;
else
dstvalue <= mod_result;
end
endcase
end else begin
......
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