risc_axi_v5_top_wrapper_control_sets_placed.rpt

Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
| Date         : Mon Sep 13 22:01:06 2021
| Host         : DESKTOP-I91JIJO running 64-bit major release  (build 9200)
| Command      : report_control_sets -verbose -file risc_axi_v5_top_wrapper_control_sets_placed.rpt
| Design       : risc_axi_v5_top_wrapper
| Device       : xc7z020
----------------------------------------------------------------------------------------------------

Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |    45 |
|    Minimum number of control sets                        |    45 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   111 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |    45 |
| >= 0 to < 4        |     1 |
| >= 4 to < 6        |     4 |
| >= 6 to < 8        |     8 |
| >= 8 to < 10       |     5 |
| >= 10 to < 12      |     5 |
| >= 12 to < 14      |     1 |
| >= 14 to < 16      |     1 |
| >= 16              |    20 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              86 |           44 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |             121 |           41 |
| Yes          | No                    | No                     |             342 |          159 |
| Yes          | No                    | Yes                    |               0 |            0 |
| Yes          | Yes                   | No                     |             348 |          142 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+-----------------+--------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
|   Clock Signal  |                                                    Enable Signal                                                   |                                                       Set/Reset Signal                                                      | Slice Load Count | Bel Load Count | Bels / Slice |
+-----------------+--------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/reg_slice_r/aa_rready        | risc_axi_v5_top_i/riscv_core_with_axi_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/reg_slice_r/skid_buffer[17]_i_1_n_0   |                1 |              1 |         1.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/axi_uartlite_0/U0/UARTLITE_CORE_I/BAUD_RATE_I/en_16x_Baud                                        |                                                                                                                             |                1 |              4 |         4.00 |
|  wClk_IBUF_BUFG |                                                                                                                    | risc_axi_v5_top_i/rst_wClk_50M/U0/EXT_LPF/lpf_int                                                                           |                1 |              4 |         4.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/mul/FSM_sequential_state_reg[2][0]               | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/SR[0]                                                     |                3 |              4 |         1.33 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/axi_uartlite_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/start2                                      | risc_axi_v5_top_i/axi_uartlite_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/cs_ce_clr                                  |                1 |              4 |         4.00 |
|  wClk_IBUF_BUFG |                                                                                                                    | risc_axi_v5_top_i/axi_uartlite_0/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] |                3 |              6 |         2.00 |
|  wClk_IBUF_BUFG |                                                                                                                    | risc_axi_v5_top_i/axi_uartlite_0/U0/UARTLITE_CORE_I/UARTLITE_TX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] |                2 |              6 |         3.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/rst_wClk_50M/U0/SEQ/seq_cnt_en                                                                   | risc_axi_v5_top_i/rst_wClk_50M/U0/SEQ/SEQ_COUNTER/clear                                                                     |                1 |              6 |         6.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/div/count[5]_i_1_n_0                             | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/mul/E[0]                                                  |                2 |              6 |         3.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/reg_slice_r/aa_rready        |                                                                                                                             |                1 |              6 |         6.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/imm                                              | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/imm[10]_i_1_n_0                                           |                2 |              6 |         3.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/imm                                              |                                                                                                                             |                4 |              7 |         1.75 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/axi_uartlite_0/U0/UARTLITE_CORE_I/BAUD_RATE_I/en_16x_Baud                                        | risc_axi_v5_top_i/axi_uartlite_0/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SERIAL_TO_PARALLEL[8].fifo_din[8]_i_1_n_0                 |                1 |              7 |         7.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/lastv                                            | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/lastv[31]_i_1_n_0                                         |                4 |              8 |         2.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/imm                                              | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/imm[19]_i_1_n_0                                           |                2 |              8 |         4.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/axi_uartlite_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/I_DECODER/fifo_wr                           |                                                                                                                             |                1 |              8 |         8.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/axi_uartlite_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/s_axi_rresp_i                               | risc_axi_v5_top_i/axi_uartlite_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst                                                  |                2 |              8 |         4.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/axi_uartlite_0/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SRL_FIFO_I/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/fifo_wr |                                                                                                                             |                1 |              8 |         8.00 |
|  wClk_IBUF_BUFG |                                                                                                                    | risc_axi_v5_top_i/axi_uartlite_0/U0/AXI_LITE_IPIF_I/I_SLAVE_ATTACHMENT/rst                                                  |                5 |             10 |         2.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/E[0]       |                                                                                                                             |                2 |             10 |         5.00 |
|  wClk_IBUF_BUFG |                                                                                                                    | risc_axi_v5_top_i/riscv_core_with_axi_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/SR[0]               |                5 |             11 |         2.20 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/writeaxi                                         |                                                                                                                             |                4 |             11 |         2.75 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/imm                                              | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/imm[30]_i_1_n_0                                           |                5 |             11 |         2.20 |
|  wClk_IBUF_BUFG |                                                                                                                    | risc_axi_v5_top_i/led_key_0/inst/p_0_in                                                                                     |                4 |             12 |         3.00 |
|  wClk_IBUF_BUFG |                                                                                                                    | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/SR[0]                                                     |                4 |             15 |         3.75 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/lastv                                            |                                                                                                                             |               18 |             24 |         1.33 |
|  wClk_IBUF_BUFG |                                                                                                                    | risc_axi_v5_top_i/axi_uartlite_0/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SR[0]                                                     |                9 |             25 |         2.78 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/p_0_in1_in | risc_axi_v5_top_i/riscv_core_with_axi_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/SR[0]               |               12 |             27 |         2.25 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N[0]           |                                                                                                                             |               18 |             27 |         1.50 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/div/ACTIVE_LOW_PR_OUT_DFF[0].FDRE_PER_N[0]       |                                                                                                                             |               11 |             27 |         2.45 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/csr_r                                            |                                                                                                                             |               11 |             28 |         2.55 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/axi_uartlite_0/U0/UARTLITE_CORE_I/BAUD_RATE_I/en_16x_Baud                                        | risc_axi_v5_top_i/axi_uartlite_0/U0/UARTLITE_CORE_I/UARTLITE_RX_I/SR[0]                                                     |                8 |             28 |         3.50 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/misa                                             | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/SR[0]                                                     |               26 |             32 |         1.23 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/mul/bbuf                                         | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/mul/abuf[63]_i_1_n_0                                      |                8 |             32 |         4.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/div/abuf[31]_i_1__0_n_0                          | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/mul/E[0]                                                  |                9 |             32 |         3.56 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/lastaddr                                         |                                                                                                                             |                9 |             32 |         3.56 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/mul/E[0]                                         | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/SR[0]                                                     |               19 |             32 |         1.68 |
|  wClk_IBUF_BUFG |                                                                                                                    | risc_axi_v5_top_i/led_key_0/inst/count[0]_i_1_n_0                                                                           |                8 |             32 |         4.00 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/csr_r                                            | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/csr_r[31]_i_1_n_0                                         |               20 |             32 |         1.60 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/div/abuf[31]_i_1__0_n_0                          |                                                                                                                             |               19 |             32 |         1.68 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/mul/E[0]                                         |                                                                                                                             |               24 |             35 |         1.46 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/readreg                                          |                                                                                                                             |               10 |             37 |         3.70 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/mul/bbuf                                         |                                                                                                                             |               27 |             64 |         2.37 |
|  wClk_IBUF_BUFG | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/mul/result                                       | risc_axi_v5_top_i/riscv_core_with_axi_0/inst/riscv_core_inst/core/mul/E[0]                                                  |               16 |             64 |         4.00 |
|  wClk_IBUF_BUFG |                                                                                                                    |                                                                                                                             |               45 |             87 |         1.93 |
+-----------------+--------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------+------------------+----------------+--------------+