risc_axi_v5_top_wrapper.v

//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2021.1 (win64) Build 3247384 Thu Jun 10 19:36:33 MDT 2021
//Date        : Mon Sep 13 21:54:53 2021
//Host        : DESKTOP-I91JIJO running 64-bit major release  (build 9200)
//Command     : generate_target risc_axi_v5_top_wrapper.bd
//Design      : risc_axi_v5_top_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module risc_axi_v5_top_wrapper
   (key,
    led,
    nwReset,
    uart_rx,
    uart_tx,
    wClk);
  input [2:0]key;
  output [3:0]led;
  input nwReset;
  input uart_rx;
  output uart_tx;
  input wClk;

  wire [2:0]key;
  wire [3:0]led;
  wire nwReset;
  wire uart_rx;
  wire uart_tx;
  wire wClk;

  risc_axi_v5_top risc_axi_v5_top_i
       (.key(key),
        .led(led),
        .nwReset(nwReset),
        .uart_rx(uart_rx),
        .uart_tx(uart_tx),
        .wClk(wClk));
endmodule