risc_axi_v5_top_bd.tcl

################################################################
# This is a generated script based on design: risc_axi_v5_top
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

namespace eval _tcl {
proc get_script_folder {} {
   set script_path [file normalize [info script]]
   set script_folder [file dirname $script_path]
   return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2021.1
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
   puts ""
   catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}

   return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source risc_axi_v5_top_script.tcl


# The design that will be created by this Tcl script contains the following 
# module references:
# led_key, riscv_core_with_axi_master

# Please add the sources of those modules before sourcing this Tcl script.

# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
   create_project project_1 myproj -part xc7z020clg400-2
}


# CHANGE DESIGN NAME HERE
variable design_name
set design_name risc_axi_v5_top

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
#    create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
   # USE CASES:
   #    1) Design_name not set

   set errMsg "Please set the variable <design_name> to a non-empty value."
   set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
   # USE CASES:
   #    2): Current design opened AND is empty AND names same.
   #    3): Current design opened AND is empty AND names diff; design_name NOT in project.
   #    4): Current design opened AND is empty AND names diff; design_name exists in project.

   if { $cur_design ne $design_name } {
      common::send_gid_msg -ssname BD::TCL -id 2001 -severity "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
      set design_name [get_property NAME $cur_design]
   }
   common::send_gid_msg -ssname BD::TCL -id 2002 -severity "INFO" "Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
   # USE CASES:
   #    5) Current design opened AND has components AND same names.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
   # USE CASES: 
   #    6) Current opened design, has components, but diff names, design_name exists in project.
   #    7) No opened design, design_name exists in project.

   set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
   set nRet 2

} else {
   # USE CASES:
   #    8) No opened design, design_name not in project.
   #    9) Current opened design, has components, but diff names, design_name not in project.

   common::send_gid_msg -ssname BD::TCL -id 2003 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."

   create_bd_design $design_name

   common::send_gid_msg -ssname BD::TCL -id 2004 -severity "INFO" "Making design <$design_name> as current_bd_design."
   current_bd_design $design_name

}

common::send_gid_msg -ssname BD::TCL -id 2005 -severity "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
   catch {common::send_gid_msg -ssname BD::TCL -id 2006 -severity "ERROR" $errMsg}
   return $nRet
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

  variable script_folder
  variable design_name

  if { $parentCell eq "" } {
     set parentCell [get_bd_cells /]
  }

  # Get object for parentCell
  set parentObj [get_bd_cells $parentCell]
  if { $parentObj == "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
     return
  }

  # Make sure parentObj is hier blk
  set parentType [get_property TYPE $parentObj]
  if { $parentType ne "hier" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
     return
  }

  # Save current instance; Restore later
  set oldCurInst [current_bd_instance .]

  # Set parent object as current
  current_bd_instance $parentObj


  # Create interface ports

  # Create ports
  set key [ create_bd_port -dir I -from 2 -to 0 -type data key ]
  set led [ create_bd_port -dir O -from 3 -to 0 -type data led ]
  set nwReset [ create_bd_port -dir I -type rst nwReset ]
  set uart_rx [ create_bd_port -dir I -type data uart_rx ]
  set uart_tx [ create_bd_port -dir O -type data uart_tx ]
  set wClk [ create_bd_port -dir I -type clk -freq_hz 50000000 wClk ]

  # Create instance: axi_uartlite_0, and set properties
  set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
  set_property -dict [ list \
   CONFIG.C_BAUDRATE {115200} \
 ] $axi_uartlite_0

  # Create instance: led_key_0, and set properties
  set block_name led_key
  set block_cell_name led_key_0
  if { [catch {set led_key_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $led_key_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: riscv_core_with_axi_0, and set properties
  set block_name riscv_core_with_axi_master
  set block_cell_name riscv_core_with_axi_0
  if { [catch {set riscv_core_with_axi_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   } elseif { $riscv_core_with_axi_0 eq "" } {
     catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
     return 1
   }
  
  # Create instance: riscv_core_with_axi_0_axi_periph, and set properties
  set riscv_core_with_axi_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 riscv_core_with_axi_0_axi_periph ]
  set_property -dict [ list \
   CONFIG.NUM_MI {2} \
 ] $riscv_core_with_axi_0_axi_periph

  # Create instance: rst_wClk_50M, and set properties
  set rst_wClk_50M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_wClk_50M ]

  # Create interface connections
  connect_bd_intf_net -intf_net riscv_core_with_axi_0_axi_periph_M00_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/M00_AXI]
  connect_bd_intf_net -intf_net riscv_core_with_axi_0_axi_periph_M01_AXI [get_bd_intf_pins led_key_0/s00_axi] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/M01_AXI]
  connect_bd_intf_net -intf_net riscv_core_with_axi_0_m00_axi [get_bd_intf_pins riscv_core_with_axi_0/m00_axi] [get_bd_intf_pins riscv_core_with_axi_0_axi_periph/S00_AXI]

  # Create port connections
  connect_bd_net -net axi_uartlite_0_tx [get_bd_ports uart_tx] [get_bd_pins axi_uartlite_0/tx]
  connect_bd_net -net key_1 [get_bd_ports key] [get_bd_pins led_key_0/key]
  connect_bd_net -net led_key_0_led [get_bd_ports led] [get_bd_pins led_key_0/led]
  connect_bd_net -net nwReset_1 [get_bd_ports nwReset] [get_bd_pins rst_wClk_50M/ext_reset_in]
  connect_bd_net -net rst_wClk_50M_peripheral_aresetn [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins led_key_0/s00_axi_aresetn] [get_bd_pins riscv_core_with_axi_0/m00_axi_aresetn] [get_bd_pins riscv_core_with_axi_0_axi_periph/ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/M00_ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/M01_ARESETN] [get_bd_pins riscv_core_with_axi_0_axi_periph/S00_ARESETN] [get_bd_pins rst_wClk_50M/peripheral_aresetn]
  connect_bd_net -net uart_rx_1 [get_bd_ports uart_rx] [get_bd_pins axi_uartlite_0/rx]
  connect_bd_net -net wClk_1 [get_bd_ports wClk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins led_key_0/s00_axi_aclk] [get_bd_pins riscv_core_with_axi_0/m00_axi_aclk] [get_bd_pins riscv_core_with_axi_0_axi_periph/ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/M00_ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/M01_ACLK] [get_bd_pins riscv_core_with_axi_0_axi_periph/S00_ACLK] [get_bd_pins rst_wClk_50M/slowest_sync_clk]

  # Create address segments
  assign_bd_address -offset 0xF0000100 -range 0x00000080 -target_address_space [get_bd_addr_spaces riscv_core_with_axi_0/m00_axi] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] -force
  assign_bd_address -offset 0xF0000000 -range 0x00000080 -target_address_space [get_bd_addr_spaces riscv_core_with_axi_0/m00_axi] [get_bd_addr_segs led_key_0/s00_axi/reg0] -force


  # Restore current instance
  current_bd_instance $oldCurInst

  validate_bd_design
  save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""