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提交 5e643ff6 编写于 作者: B bernard 提交者： Gitee
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!331 增加VangoV85xx初版BSP，提供Keil编译支持，增加数据手册链接，芯片PACK包 

Merge pull request !331 from 傅尔先森/gitee_master
上级 554d5bd8 ad197870
展开全部 隐藏空白更改
内联 并排
Showing with 30943 addition and 0 deletion
.gitignore
浏览文件 @ 5e643ff6
......@@ -10,6 +10,7 @@
*.idb
*.ilk
*.old
*.crf
build
Debug
documentation/html
......
bsp/Vango_V85xx/.config 0 → 100644
浏览文件 @ 5e643ff6
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
CONFIG_RT_USING_TIMER_SOFT=y
CONFIG_RT_TIMER_THREAD_PRIO=4
CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
#
# kservice optimization
#
# CONFIG_RT_KSERVICE_USING_STDLIB is not set
# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
# CONFIG_RT_USING_ASM_MEMCPY is not set
CONFIG_RT_DEBUG=y
# CONFIG_RT_DEBUG_COLOR is not set
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart"
# CONFIG_RT_PRINTF_LONGLONG is not set
CONFIG_RT_VER_NUM=0x40004
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
# CONFIG_FINSH_USING_MSH_ONLY is not set
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
CONFIG_RT_USING_DFS=y
CONFIG_DFS_USING_WORKDIR=y
CONFIG_DFS_FILESYSTEMS_MAX=4
CONFIG_DFS_FILESYSTEM_TYPES_MAX=4
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_USING_SERIAL_V1=y
# CONFIG_RT_USING_SERIAL_V2 is not set
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_USING_POSIX=y
# CONFIG_RT_USING_POSIX_MMAP is not set
# CONFIG_RT_USING_POSIX_TERMIOS is not set
# CONFIG_RT_USING_POSIX_GETLINE is not set
# CONFIG_RT_USING_POSIX_AIO is not set
# CONFIG_RT_USING_MODULE is not set
CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_RT_LINK is not set
#
# RT-Thread Utestcases
#
# CONFIG_RT_USING_UTESTCASES is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
# CONFIG_PKG_USING_ZB_COORDINATOR is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
# CONFIG_PKG_USING_MAVLINK is not set
# CONFIG_PKG_USING_RAPIDJSON is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_AGILE_MODBUS is not set
# CONFIG_PKG_USING_AGILE_FTP is not set
# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
# CONFIG_PKG_USING_RT_LINK_HW is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
# CONFIG_PKG_USING_PIKASCRIPT is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_PDFGEN is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
# CONFIG_PKG_USING_NUEMWIN is not set
# CONFIG_PKG_USING_MP3PLAYER is not set
# CONFIG_PKG_USING_TINYJPEG is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
# CONFIG_PKG_USING_LWLOG is not set
# CONFIG_PKG_USING_ANV_TRACE is not set
# CONFIG_PKG_USING_ANV_MEMLEAK is not set
# CONFIG_PKG_USING_ANV_TESTSUIT is not set
# CONFIG_PKG_USING_ANV_BENCH is not set
# CONFIG_PKG_USING_DEVMEM is not set
# CONFIG_PKG_USING_REGEX is not set
# CONFIG_PKG_USING_MEM_SANDBOX is not set
# CONFIG_PKG_USING_SOLAR_TERMS is not set
# CONFIG_PKG_USING_GAN_ZHI is not set
#
# system packages
#
#
# acceleration: Assembly language or algorithmic acceleration packages
#
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_DFS_JFFS2 is not set
# CONFIG_PKG_USING_DFS_UFFS is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
# CONFIG_PKG_USING_LPM is not set
# CONFIG_PKG_USING_TLSF is not set
# CONFIG_PKG_USING_EVENT_RECORDER is not set
# CONFIG_PKG_USING_ARM_2D is not set
# CONFIG_PKG_USING_WCWIDTH is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
# CONFIG_PKG_USING_STM32WB55_SDK is not set
# CONFIG_PKG_USING_RDA58XX is not set
# CONFIG_PKG_USING_LIBNFC is not set
# CONFIG_PKG_USING_MFOC is not set
# CONFIG_PKG_USING_TMC51XX is not set
# CONFIG_PKG_USING_TCA9534 is not set
# CONFIG_PKG_USING_KOBUKI is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_MICRO_ROS is not set
# CONFIG_PKG_USING_MCP23008 is not set
# CONFIG_PKG_USING_BLUETRUM_SDK is not set
#
# AI packages
#
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_QUEST is not set
# CONFIG_PKG_USING_NAXOS is not set
#
# miscellaneous packages
#
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
#
# entertainment: terminal games and other interesting software packages
#
# CONFIG_PKG_USING_CMATRIX is not set
# CONFIG_PKG_USING_SL is not set
# CONFIG_PKG_USING_CAL is not set
# CONFIG_PKG_USING_ACLOCK is not set
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_SNAKE is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_LZMA is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_MINIZIP is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
# CONFIG_PKG_USING_MCURSES is not set
# CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_TERMBOX is not set
CONFIG_SOC_SERIES_V85XX=y
CONFIG_SOC_V85XX=y
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART=y
# CONFIG_BSP_USING_UART0 is not set
# CONFIG_BSP_USING_UART1 is not set
CONFIG_BSP_USING_UART2=y
# CONFIG_BSP_USING_UART3 is not set
# CONFIG_BSP_USING_UART4 is not set
# CONFIG_BSP_USING_ADC is not set
# CONFIG_BSP_USING_HWTIMER is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_RTC is not set
bsp/Vango_V85xx/.ignore_format.yml 0 → 100644
浏览文件 @ 5e643ff6
# files format check exclude path, please follow the instructions below to modify;
# If you need to exclude an entire folder, add the folder path in dir_path;
# If you need to exclude a file, add the path to the file in file_path.
dir_path:
- Libraries/VangoV85xx_standard_peripheral
bsp/Vango_V85xx/Kconfig 0 → 100644
浏览文件 @ 5e643ff6
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
# you can change the RTT_ROOT default: "rt-thread"
# example : default "F:/git_repositories/rt-thread"
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_SERIES_V85XX
bool
default y
config SOC_V85XX
bool
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
select SOC_SERIES_V85XX
default y
menu "On-chip Peripheral Drivers"
menuconfig BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
config BSP_USING_UART0
bool "using uart0"
default n
config BSP_USING_UART1
bool "using uart1"
default n
config BSP_USING_UART2
bool "using uart2"
default y
config BSP_USING_UART3
bool "using uart3"
default n
config BSP_USING_UART4
bool "using uart4"
default n
endif
menuconfig BSP_USING_ADC
bool "Enable ADC"
default n
select RT_USING_ADC
if BSP_USING_ADC
config BSP_USING_ADC0
bool "using adc0"
default n
config BSP_USING_ADC1
bool "using adc1"
default n
endif
menuconfig BSP_USING_HWTIMER
bool "Enable hwtimer"
default n
select RT_USING_HWTIMER
if BSP_USING_HWTIMER
config BSP_USING_HWTIMER0
bool "using hwtimer0"
default n
config BSP_USING_HWTIMER1
bool "using hwtimer1"
default n
config BSP_USING_HWTIMER2
bool "using hwtimer2"
default n
config BSP_USING_HWTIMER3
bool "using hwtimer3"
default n
config BSP_USING_HWTIMER4
bool "using hwtimer4"
default n
config BSP_USING_HWTIMER5
bool "using hwtimer5"
default n
config BSP_USING_HWTIMER6
bool "using hwtimer6"
default n
config BSP_USING_HWTIMER7
bool "using hwtimer7"
default n
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
config BSP_USING_RTC
bool "using internal rtc"
default n
select RT_USING_RTC
endmenu
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_CodeRAM.h 0 → 100644
浏览文件 @ 5e643ff6
/**
******************************************************************************
* @file lib_CodeRAM.h
* @author Application Team
* @version V4.4.0
* @date 2019-01-18
* @brief Codes executed in SRAM.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CODERAM_H
#define __LIB_CODERAM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "target.h"
#ifndef __GNUC__
#ifdef __ICCARM__ /* EWARM */
#define __RAM_FUNC __ramfunc
#endif
#ifdef __CC_ARM /* MDK-ARM */
#define __RAM_FUNC __attribute__((used))
#endif
/* Exported Functions ------------------------------------------------------- */
__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void);
#endif /* __GNUC__ */
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CODERAM_H */
/*********************************** END OF FILE ******************************/
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_LoadNVR.h 0 → 100644
浏览文件 @ 5e643ff6
/**
******************************************************************************
* @file lib_LoadNVR.h
* @author Application Team
* @version V4.7.0
* @date 2019-12-12
* @brief Load information from NVR.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_LOADNVR_H
#define __LIB_LOADNVR_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "target.h"
/* BAT measure result */
typedef struct
{
float BATRESResult; // BAT Resistor division Measure Result
float BATCAPResult; // BATRTC Cap division Measure Result
} NVR_BATMEARES;
/* Power Measure Result */
typedef struct
{
uint32_t AVCCMEAResult; // LDO33 Measure Result
uint32_t DVCCMEAResult; // LDO15 Measure Result
uint32_t BGPMEAResult; // BGP Measure Result
uint32_t RCLMEAResult; // RCL Measure Result
uint32_t RCHMEAResult; // RCH Measure Result
} NVR_MISCGain;
/* Chip ID */
typedef struct
{
uint32_t ChipID0; // ID word 0
uint32_t ChipID1; // ID word 1
} NVR_CHIPID;
/* Temperature information */
typedef struct
{
float TempOffset;
} NVR_TEMPINFO;
/* LCD information */
typedef struct
{
uint32_t MEALCDLDO; // Measure LCD LDO pre trim value
uint32_t MEALCDVol; // VLCD setting
} NVR_LCDINFO;
/* RTC(temp) information */
typedef struct
{
int16_t RTCTempP0; //P0
int16_t RTCTempP1; //P1
int32_t RTCTempP2; //P2
int16_t RTCTempP4; //P4
int16_t RTCTempP5; //P5
int16_t RTCTempP6; //P6
int16_t RTCTempP7; //P7
int16_t RTCTempK1; //K1
int16_t RTCTempK2; //K2
int16_t RTCTempK3; //K3
int16_t RTCTempK4; //K4
int16_t RTCTempK5; //K5
int16_t RTCACTI; //Center temperature
uint32_t RTCACKTemp; //section X temperature
int16_t RTCTempDelta; //Temperature delta
uint32_t RTCACF200; //RTC_ACF200
uint32_t APBClock; //APB clock
} NVR_RTCINFO;
/* ADC Voltage Parameters */
typedef struct
{
float aParameter;
float bParameter;
} NVR_ADCVOLPARA;
//Mode
#define NVR_3V_EXTERNAL_NODIV (0x000UL) // Power supply: 3.3V; Channel: External; Divider modeL: None
#define NVR_3V_EXTERNAL_RESDIV (0x001UL) // Power supply: 3.3V; Channel: External; Divider modeL: Resistive
#define NVR_3V_EXTERNAL_CAPDIV (0x002UL) // Power supply: 3.3V; Channel: External; Divider modeL: Capacitive
#define NVR_3V_VDD_RESDIV (0x003UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Resistive
#define NVR_3V_VDD_CAPDIV (0x004UL) // Power supply: 3.3V; Channel: VDD; Divider modeL: Capacitive
#define NVR_3V_BATRTC_RESDIV (0x005UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Resistive
#define NVR_3V_BATRTC_CAPDIV (0x006UL) // Power supply: 3.3V; Channel: BATRTC; Divider modeL: Capacitive
#define NVR_5V_EXTERNAL_NODIV (0x100UL) // Power supply: 5V; Channel: External; Divider modeL: None
#define NVR_5V_EXTERNAL_RESDIV (0x101UL) // Power supply: 5V; Channel: External; Divider modeL: Resistive
#define NVR_5V_EXTERNAL_CAPDIV (0x102UL) // Power supply: 5V; Channel: External; Divider modeL: Capacitive
#define NVR_5V_VDD_RESDIV (0x103UL) // Power supply: 5V; Channel: VDD; Divider modeL: Resistive
#define NVR_5V_VDD_CAPDIV (0x104UL) // Power supply: 5V; Channel: VDD; Divider modeL: Capacitive
#define NVR_5V_BATRTC_RESDIV (0x105UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Resistive
#define NVR_5V_BATRTC_CAPDIV (0x106UL) // Power supply: 5V; Channel: BATRTC; Divider modeL: Capacitive
#define IS_NVR_ADCVOL_MODE(__MODE__) (((__MODE__) == NVR_3V_EXTERNAL_NODIV) ||\
((__MODE__) == NVR_3V_EXTERNAL_RESDIV) ||\
((__MODE__) == NVR_3V_EXTERNAL_CAPDIV) ||\
((__MODE__) == NVR_3V_VDD_RESDIV) ||\
((__MODE__) == NVR_3V_VDD_CAPDIV) ||\
((__MODE__) == NVR_3V_BATRTC_RESDIV) ||\
((__MODE__) == NVR_3V_BATRTC_CAPDIV) ||\
((__MODE__) == NVR_5V_EXTERNAL_NODIV) ||\
((__MODE__) == NVR_5V_EXTERNAL_RESDIV) ||\
((__MODE__) == NVR_5V_EXTERNAL_CAPDIV) ||\
((__MODE__) == NVR_5V_VDD_RESDIV) ||\
((__MODE__) == NVR_5V_VDD_CAPDIV) ||\
((__MODE__) == NVR_5V_BATRTC_RESDIV) ||\
((__MODE__) == NVR_5V_BATRTC_CAPDIV))
/********** NVR Address **********/
//ADC Voltage Parameters
#define NVR_3VPARA_BASEADDR1 (__IO uint32_t *)(0x40400)
#define NVR_3VPARA_BASEADDR2 (__IO uint32_t *)(0x40440)
#define NVR_5VPARA_BASEADDR1 (__IO uint32_t *)(0x40480)
#define NVR_5VPARA_BASEADDR2 (__IO uint32_t *)(0x404C0)
//RTC DATA
//P4
#define NVR_RTC1_P4 (__IO uint32_t *)(0x40800)
#define NVR_RTC1_P4_CHKSUM (__IO uint32_t *)(0x40804)
#define NVR_RTC2_P4 (__IO uint32_t *)(0x40808)
#define NVR_RTC2_P4_CHKSUM (__IO uint32_t *)(0x4080C)
//ACK1~ACK5
#define NVR_RTC1_ACK1 (__IO uint32_t *)(0x40810)
#define NVR_RTC1_ACK2 (__IO uint32_t *)(0x40814)
#define NVR_RTC1_ACK3 (__IO uint32_t *)(0x40818)
#define NVR_RTC1_ACK4 (__IO uint32_t *)(0x4081C)
#define NVR_RTC1_ACK5 (__IO uint32_t *)(0x40820)
#define NVR_RTC1_ACK_CHKSUM (__IO uint32_t *)(0x40824)
#define NVR_RTC2_ACK1 (__IO uint32_t *)(0x40828)
#define NVR_RTC2_ACK2 (__IO uint32_t *)(0x4082C)
#define NVR_RTC2_ACK3 (__IO uint32_t *)(0x40830)
#define NVR_RTC2_ACK4 (__IO uint32_t *)(0x40834)
#define NVR_RTC2_ACK5 (__IO uint32_t *)(0x40838)
#define NVR_RTC2_ACK_CHKSUM (__IO uint32_t *)(0x4083C)
//ACTI
#define NVR_RTC1_ACTI (__IO uint32_t *)(0x40840)
#define NVR_RTC1_ACTI_CHKSUM (__IO uint32_t *)(0x40844)
#define NVR_RTC2_ACTI (__IO uint32_t *)(0x40848)
#define NVR_RTC2_ACTI_CHKSUM (__IO uint32_t *)(0x4084C)
//ACKTEMP
#define NVR_RTC1_ACKTEMP (__IO uint32_t *)(0x40850)
#define NVR_RTC1_ACKTEMP_CHKSUM (__IO uint32_t *)(0x40854)
#define NVR_RTC2_ACKTEMP (__IO uint32_t *)(0x40858)
#define NVR_RTC2_ACKTEMP_CHKSUM (__IO uint32_t *)(0x4085C)
//Analog trim data
#define NVR_ANA_TRIMDATA1 (__IO uint32_t *)(0x40DC0)
#define NVR_ANA_OPREG1 (__IO uint32_t *)(0x40DC4)
#define NVR_ANA_KEYREG1 (__IO uint32_t *)(0x40DC8)
#define NVR_ANA_CHECKSUM1 (__IO uint32_t *)(0x40DCC)
#define NVR_ANA_TRIMDATA2 (__IO uint32_t *)(0x40DD0)
#define NVR_ANA_OPREG2 (__IO uint32_t *)(0x40DD4)
#define NVR_ANA_KEYREG2 (__IO uint32_t *)(0x40DD8)
#define NVR_ANA_CHECKSUM2 (__IO uint32_t *)(0x40DDC)
//BAT Measure Result
#define NVR_BAT_R1 (__IO uint32_t *)(0x40CE0)
#define NVR_BAT_C1 (__IO uint32_t *)(0x40CE4)
#define NVR_BATMEA_CHECHSUM1 (__IO uint32_t *)(0x40CE8)
#define NVR_BAT_R2 (__IO uint32_t *)(0x40CF0)
#define NVR_BAT_C2 (__IO uint32_t *)(0x40CF4)
#define NVR_BATMEA_CHECHSUM2 (__IO uint32_t *)(0x40CF8)
//RTC AutoCal Px pramameters
#define NVR_RTC1_P1_P0 (__IO uint32_t *)(0x40D00)
#define NVR_RTC1_P2 (__IO uint32_t *)(0x40D04)
#define NVR_RTC1_P5_P4 (__IO uint32_t *)(0x40D08)
#define NVR_RTC1_P7_P6 (__IO uint32_t *)(0x40D0C)
#define NVR_RTC1_PCHECHSUM (__IO uint32_t *)(0x40D10)
#define NVR_RTC2_P1_P0 (__IO uint32_t *)(0x40D14)
#define NVR_RTC2_P2 (__IO uint32_t *)(0x40D18)
#define NVR_RTC2_P5_P4 (__IO uint32_t *)(0x40D1C)
#define NVR_RTC2_P7_P6 (__IO uint32_t *)(0x40D20)
#define NVR_RTC2_PCHECHSUM (__IO uint32_t *)(0x40D24)
//Power Measure Result
#define NVR_DVCC_MEA1 (__IO uint32_t *)(0x40D28)
#define NVR_AVCC_MEA1 (__IO uint32_t *)(0x40D2C)
#define NVR_BGP_MEA1 (__IO uint32_t *)(0x40D30)
#define NVR_RCL_MEA1 (__IO uint32_t *)(0x40D34)
#define NVR_RCH_MEA1 (__IO uint32_t *)(0x40D38)
#define NVR_PWR_CHECKSUM1 (__IO uint32_t *)(0x40D3C)
#define NVR_DVCC_MEA2 (__IO uint32_t *)(0x40D40)
#define NVR_AVCC_MEA2 (__IO uint32_t *)(0x40D44)
#define NVR_BGP_MEA2 (__IO uint32_t *)(0x40D48)
#define NVR_RCL_MEA2 (__IO uint32_t *)(0x40D4C)
#define NVR_RCH_MEA2 (__IO uint32_t *)(0x40D50)
#define NVR_PWR_CHECKSUM2 (__IO uint32_t *)(0x40D54)
//Chip ID
#define NVR_CHIP1_ID0 (__IO uint32_t *)(0x40D58)
#define NVR_CHIP1_ID1 (__IO uint32_t *)(0x40D5C)
#define NVR_CHIP1_CHECKSUM (__IO uint32_t *)(0x40D60)
#define NVR_CHIP2_ID0 (__IO uint32_t *)(0x40D64)
#define NVR_CHIP2_ID1 (__IO uint32_t *)(0x40D68)
#define NVR_CHIP2_CHECKSUM (__IO uint32_t *)(0x40D6C)
//Temperature information
#define NVR_REALTEMP1 (__IO uint32_t *)(0x40D70)
#define NVR_MEATEMP1 (__IO uint32_t *)(0x40D74)
#define NVR_TEMP_CHECKSUM1 (__IO uint32_t *)(0x40D78)
#define NVR_REALTEMP2 (__IO uint32_t *)(0x40D7C)
#define NVR_MEATEMP2 (__IO uint32_t *)(0x40D80)
#define NVR_TEMP_CHECKSUM2 (__IO uint32_t *)(0x40D84)
//LCD Information
#define NVR_LCD_LDO1 (__IO uint32_t *)(0x40D90)
#define NVR_LCD_VOL1 (__IO uint32_t *)(0x40D94)
#define NVR_LCD_CHECKSUM1 (__IO uint32_t *)(0x40D98)
#define NVR_LCD_LDO2 (__IO uint32_t *)(0x40D9C)
#define NVR_LCD_VOL2 (__IO uint32_t *)(0x40DA0)
#define NVR_LCD_CHECKSUM2 (__IO uint32_t *)(0x40DA4)
uint32_t NVR_LoadANADataManual(void);
uint32_t NVR_GetADCVoltageParameter(uint32_t Mode, NVR_ADCVOLPARA *Parameter);
uint32_t NVR_GetBATOffset(NVR_BATMEARES *MEAResult);
uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData);
uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult);
uint32_t NVR_GetChipID(NVR_CHIPID *ChipID);
uint32_t NVR_GetLCDInfo(NVR_LCDINFO *LCDInfo);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_LOADNVR_H */
/*********************************** END OF FILE ******************************/
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_conf.h 0 → 100644
浏览文件 @ 5e643ff6
/**
******************************************************************************
* @file lib_conf.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Dirver configuration.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CONF_H
#define __LIB_CONF_H
/* ########################## Assert Selection ############################## */
//#define ASSERT_NDEBUG 1
/* Includes ------------------------------------------------------------------*/
/**
* @brief Include module's header file
*/
#include "lib_ana.h"
#include "lib_adc.h"
#include "lib_adc_tiny.h"
#include "lib_clk.h"
#include "lib_comp.h"
#include "lib_crypt.h"
#include "lib_dma.h"
#include "lib_flash.h"
#include "lib_gpio.h"
#include "lib_i2c.h"
#include "lib_iso7816.h"
#include "lib_lcd.h"
#include "lib_misc.h"
#include "lib_pmu.h"
#include "lib_pwm.h"
#include "lib_rtc.h"
#include "lib_spi.h"
#include "lib_tmr.h"
#include "lib_u32k.h"
#include "lib_uart.h"
#include "lib_version.h"
#include "lib_wdt.h"
#include "lib_LoadNVR.h"
#include "lib_CodeRAM.h"
#include "lib_cortex.h"
/* Exported macro ------------------------------------------------------------*/
#ifndef ASSERT_NDEBUG
#define assert_parameters(expr) ((expr) ? (void)0U : assert_errhandler((uint8_t *)__FILE__, __LINE__))
/* Exported functions ------------------------------------------------------- */
void assert_errhandler(uint8_t* file, uint32_t line);
#else
#define assert_parameters(expr) ((void)0U)
#endif /* ASSERT_NDEBUG */
#endif
/*********************************** END OF FILE ******************************/
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/lib_cortex.h 0 → 100644
浏览文件 @ 5e643ff6
/**
******************************************************************************
* @file lib_Cortex.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Cortex module driver.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __LIB_CORTEX_H
#define __LIB_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "target.h"
#define IS_CORTEX_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
#define IS_CORTEX_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4)
/* Exported Functions ------------------------------------------------------- */
void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority);
void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn);
void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn);
uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn);
void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority);
void CORTEX_NVIC_SystemReset(void);
uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_CORTEX_H */
/*********************************** END OF FILE ******************************/
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/system_target.h 0 → 100644
浏览文件 @ 5e643ff6
/**
******************************************************************************
* @file system_target.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief system source file.
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __SYSTEM_TARGET_H
#define __SYSTEM_TARGET_H
#ifdef __cplusplus
extern "C" {
#endif
#include "type_def.h"
#define NVR_REGINFOCOUNT1 (0x80400)
#define NVR_REGINFOBAKOFFSET (0x100)
/* ########################### System Configuration ######################### */
extern void SystemInit(void);
extern void SystemUpdate(void);
#ifdef USE_TARGET_DRIVER
#include "lib_conf.h"
#endif /* USE_TARGET_DRIVER */
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_TARGET_H */
/*********************************** END OF FILE ******************************/
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Include/type_def.h 0 → 100644
浏览文件 @ 5e643ff6
/**
******************************************************************************
* @file type_def.h
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Typedef file
******************************************************************************
* @attention
*
******************************************************************************
*/
#ifndef __TYPE_DEF_H
#define __TYPE_DEF_H
#define ENABLE 1
#define DISABLE 0
#define IS_FUNCTIONAL_STATE(__STATE__) (((__STATE__) == DISABLE) || ((__STATE__) == ENABLE))
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
#if defined (__GNUC__) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || defined ( __GNUC__ )
/* ARM & GNUCompiler
----------------
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif
#endif /* __TYPE_DEF_H */
/*********************************** END OF FILE ******************************/
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/GCC/startup_target.S 0 → 100644
浏览文件 @ 5e643ff6
;/**
;* @file startup_target.s
;* @author Application Team
;* @version V1.1.0
;* @date 2019-10-28
;* @brief Target Devices vector table.
;******************************************************************************/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.equ __CHIPINITIAL, 1
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
/*************************************************************************
* Chip init.
* 1. Load flash configuration
* 2. Load ANA_REG(B/C/D/E) information
* 3. Load ANA_REG10 information
**************************************************************************/
.if (__CHIPINITIAL != 0)
.section .chipinit_section.__CHIP_INIT
__CHIP_INIT:
CONFIG1_START:
/*-------------------------------*/
/* 1. Load flash configuration */
/* Unlock flash */
LDR R0, =0x000FFFE0
LDR R1, =0x55AAAA55
STR R1, [R0]
/* Load configure word 0 to 7
Compare bit[7:0] */
LDR R0, =0x00080E00
LDR R1, =0x20
LDR R2, =0x000FFFE8
LDR R3, =0x000FFFF0
LDR R4, =0x0
LDR R7, =0x0FF
FLASH_CONF_START_1:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_AGAIN_1:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_1:
BNE FLASH_CONF_WHILELOOP_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_END_1:
/* Load configure word 8 to 11
Compare bit 31,24,23:16,8,7:0 */
LDR R1, =0x30
LDR R7, =0x81FF81FF
FLASH_CONF_START_2:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_AGAIN_2:
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_2:
BNE FLASH_CONF_WHILELOOP_2
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_END_2:
/* Lock flash */
LDR R0, =0x000FFFE0
LDR R1, =0x0
STR R1, [R0]
/*-------------------------------*/
/* 2. Load ANA_REG(B/C/D/E) information */
CONFIG2_START:
LDR R4, =0x4001422C
LDR R5, =0x40014230
LDR R6, =0x40014234
LDR R7, =0x40014238
LDR R0, =0x80DC0
LDR R0, [R0]
LDR R1, =0x80DC4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DCC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM1_OK
B ANADAT_CHECKSUM1_ERR
ANADAT_CHECKSUM1_OK:
/* ANA_REGB */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
/* ANA_REGC */
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
/* ANA_REGD */
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
/* ANA_REGE */
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM1_ERR:
LDR R0, =0x80DD0
LDR R0, [R0]
LDR R1, =0x80DD4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DDC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM2_OK
B ANADAT_CHECKSUM2_ERR
ANADAT_CHECKSUM2_OK:
/* ANA_REGB */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
/* ANA_REGC */
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
/* ANA_REGD */
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
/* ANA_REGE */
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM2_ERR:
B ANADAT_CHECKSUM2_ERR
/*-------------------------------*/
/* 3. Load ANA_REG10 information */
CONFIG3_START:
LDR R7, =0x40014240
LDR R0, =0x80DE0
LDR R0, [R0]
LDR R1, =0x80DE4
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM1_OK
B ANADAT10_CHECKSUM1_ERR
ANADAT10_CHECKSUM1_OK:
/* ANA_REG10 */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM1_ERR:
LDR R0, =0x80DE8
LDR R0, [R0]
LDR R1, =0x80DEC
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM2_OK
B ANADAT10_CHECKSUM2_ERR
ANADAT10_CHECKSUM2_OK:
/* ANA_REG10 */
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM2_ERR:
B ANADAT10_CHECKSUM2_ERR
.size __CHIP_INIT, .-__CHIP_INIT
.endif
.if (__CHIPINITIAL != 0)
.global __CHIP_INIT
.section .chipinit_section.Reset_Handler
.else
.section .text.Reset_Handler
.endif
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
.if (__CHIPINITIAL != 0)
/* Chip Initiliazation */
bl __CHIP_INIT
/* System Initiliazation */
bl SystemInit
.endif
/* set stack pointer */
ldr r0, =_estack
mov sp, r0
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
bl main
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
/* External Interrupts */
.word PMU_IRQHandler /* 0: PMU */
.word RTC_IRQHandler /* 1: RTC */
.word U32K0_IRQHandler /* 2: U32K0 */
.word U32K1_IRQHandler /* 3: U32K1 */
.word I2C_IRQHandler /* 4: I2C */
.word SPI1_IRQHandler /* 5: SPI1 */
.word UART0_IRQHandler /* 6: UART0 */
.word UART1_IRQHandler /* 7: UART1 */
.word UART2_IRQHandler /* 8: UART2 */
.word UART3_IRQHandler /* 9: UART3 */
.word UART4_IRQHandler /* 10: UART4 */
.word UART5_IRQHandler /* 11: UART5 */
.word ISO78160_IRQHandler /* 12: ISO78160 */
.word ISO78161_IRQHandler /* 13: ISO78161 */
.word TMR0_IRQHandler /* 14: TMR0 */
.word TMR1_IRQHandler /* 15: TMR1 */
.word TMR2_IRQHandler /* 16: TMR2 */
.word TMR3_IRQHandler /* 17: TMR3 */
.word PWM0_IRQHandler /* 18: PWM0 */
.word PWM1_IRQHandler /* 19: PWM1 */
.word PWM2_IRQHandler /* 20: PWM2 */
.word PWM3_IRQHandler /* 21: PWM3 */
.word DMA_IRQHandler /* 22: DMA */
.word FLASH_IRQHandler /* 23: FLASH */
.word ANA_IRQHandler /* 24: ANA */
.word 0 /* 25: Reserved */
.word 0 /* 26: Reserved */
.word SPI2_IRQHandler /* 27: SPI2 */
.word SPI3_IRQHandler /* 28: SPI3 */
.word 0 /* 29: Reserved */
.word 0 /* 30: Reserved */
.word 0 /* 31: Reserved */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak PMU_IRQHandler
.thumb_set PMU_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak U32K0_IRQHandler
.thumb_set U32K0_IRQHandler,Default_Handler
.weak U32K1_IRQHandler
.thumb_set U32K1_IRQHandler,Default_Handler
.weak I2C_IRQHandler
.thumb_set I2C_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak UART0_IRQHandler
.thumb_set UART0_IRQHandler,Default_Handler
.weak UART1_IRQHandler
.thumb_set UART1_IRQHandler,Default_Handler
.weak UART2_IRQHandler
.thumb_set UART2_IRQHandler,Default_Handler
.weak UART3_IRQHandler
.thumb_set UART3_IRQHandler,Default_Handler
.weak UART4_IRQHandler
.thumb_set UART4_IRQHandler,Default_Handler
.weak UART5_IRQHandler
.thumb_set UART5_IRQHandler,Default_Handler
.weak ISO78160_IRQHandler
.thumb_set ISO78160_IRQHandler,Default_Handler
.weak ISO78161_IRQHandler
.thumb_set ISO78161_IRQHandler,Default_Handler
.weak TMR0_IRQHandler
.thumb_set TMR0_IRQHandler,Default_Handler
.weak TMR1_IRQHandler
.thumb_set TMR1_IRQHandler,Default_Handler
.weak TMR2_IRQHandler
.thumb_set TMR2_IRQHandler,Default_Handler
.weak TMR3_IRQHandler
.thumb_set TMR3_IRQHandler,Default_Handler
.weak PWM0_IRQHandler
.thumb_set PWM0_IRQHandler,Default_Handler
.weak PWM1_IRQHandler
.thumb_set PWM1_IRQHandler,Default_Handler
.weak PWM2_IRQHandler
.thumb_set PWM2_IRQHandler,Default_Handler
.weak PWM3_IRQHandler
.thumb_set PWM3_IRQHandler,Default_Handler
.weak DMA_IRQHandler
.thumb_set DMA_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak ANA_IRQHandler
.thumb_set ANA_IRQHandler,Default_Handler
.weak SPI2_IRQHandler
.thumb_set SPI2_IRQHandler,Default_Handler
.weak SPI3_IRQHandler
.thumb_set SPI3_IRQHandler,Default_Handler
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/keil5/startup_target.S 0 → 100644
浏览文件 @ 5e643ff6
;/**
;* @file startup_target.s
;* @author Application Team
;* @version V1.1.0
;* @date 2019-10-28
;* @brief Target Devices vector table.
;******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
__CHIPINITIAL EQU 1
Stack_Size EQU 0x000001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PMU_IRQHandler ; 0: PMU
DCD RTC_IRQHandler ; 1: RTC
DCD U32K0_IRQHandler ; 2: U32K0
DCD U32K1_IRQHandler ; 3: U32K1
DCD I2C_IRQHandler ; 4: I2C
DCD SPI1_IRQHandler ; 5: SPI1
DCD UART0_IRQHandler ; 6: UART0
DCD UART1_IRQHandler ; 7: UART1
DCD UART2_IRQHandler ; 8: UART2
DCD UART3_IRQHandler ; 9: UART3
DCD UART4_IRQHandler ; 10: UART4
DCD UART5_IRQHandler ; 11: UART5
DCD ISO78160_IRQHandler ; 12: ISO78160
DCD ISO78161_IRQHandler ; 13: ISO78161
DCD TMR0_IRQHandler ; 14: TMR0
DCD TMR1_IRQHandler ; 15: TMR1
DCD TMR2_IRQHandler ; 16: TMR2
DCD TMR3_IRQHandler ; 17: TMR3
DCD PWM0_IRQHandler ; 18: PWM0
DCD PWM1_IRQHandler ; 19: PWM1
DCD PWM2_IRQHandler ; 20: PWM2
DCD PWM3_IRQHandler ; 21: PWM3
DCD DMA_IRQHandler ; 22: DMA
DCD FLASH_IRQHandler ; 23: FLASH
DCD ANA_IRQHandler ; 24: ANA
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD SPI2_IRQHandler ; 27: SPI2
DCD SPI3_IRQHandler ; 28: SPI3
DCD 0 ; 29: Reserved
DCD 0 ; 30: Reserved
DCD 0 ; 31: Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
IF (__CHIPINITIAL != 0)
AREA |.ARM.__AT_0xC0|, CODE, READONLY
ELSE
AREA |.text|, CODE, READONLY
ENDIF
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
IF (__CHIPINITIAL != 0)
LDR R0, =__CHIP_INIT
BLX R0
ENDIF
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
AREA |.text|, CODE, READONLY
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PMU_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT U32K0_IRQHandler [WEAK]
EXPORT U32K1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT ISO78160_IRQHandler [WEAK]
EXPORT ISO78161_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT PWM0_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT PWM2_IRQHandler [WEAK]
EXPORT PWM3_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT ANA_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
PMU_IRQHandler
RTC_IRQHandler
U32K0_IRQHandler
U32K1_IRQHandler
I2C_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
ISO78160_IRQHandler
ISO78161_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
PWM0_IRQHandler
PWM1_IRQHandler
PWM2_IRQHandler
PWM3_IRQHandler
DMA_IRQHandler
FLASH_IRQHandler
ANA_IRQHandler
SPI2_IRQHandler
SPI3_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Chip init.
;; 1. Load flash configuration
;; 2. Load ANA_REG(B/C/D/E) information
;; 3. Load ANA_REG10 information
IF (__CHIPINITIAL != 0)
AREA |.ARM.__AT_0xC0|, CODE, READONLY
__CHIP_INIT PROC
CONFIG1_START
;-------------------------------;
;; 1. Load flash configuration
; Unlock flash
LDR R0, =0x000FFFE0
LDR R1, =0x55AAAA55
STR R1, [R0]
; Load configure word 0 to 7
; Compare bit[7:0]
LDR R0, =0x00080E00
LDR R1, =0x20
LDR R2, =0x000FFFE8
LDR R3, =0x000FFFF0
LDR R4, =0x0
LDR R7, =0x0FF
FLASH_CONF_START_1
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_AGAIN_1
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_1
BNE FLASH_CONF_WHILELOOP_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_END_1
; Load configure word 8 to 11
; Compare bit 31,24,23:16,8,7:0
LDR R1, =0x30
LDR R7, =0x81FF81FF
FLASH_CONF_START_2
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_AGAIN_2
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_2
BNE FLASH_CONF_WHILELOOP_2
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_END_2
; Lock flash
LDR R0, =0x000FFFE0
LDR R1, =0x0
STR R1, [R0]
;-------------------------------;
;; 2. Load ANA_REG(B/C/D/E) information
CONFIG2_START
LDR R4, =0x4001422C
LDR R5, =0x40014230
LDR R6, =0x40014234
LDR R7, =0x40014238
LDR R0, =0x80DC0
LDR R0, [R0]
LDR R1, =0x80DC4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DCC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM1_OK
B ANADAT_CHECKSUM1_ERR
ANADAT_CHECKSUM1_OK
; ANA_REGB
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
; ANA_REGC
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
; ANA_REGD
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
; ANA_REGE
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM1_ERR
LDR R0, =0x80DD0
LDR R0, [R0]
LDR R1, =0x80DD4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DDC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM2_OK
B ANADAT_CHECKSUM2_ERR
ANADAT_CHECKSUM2_OK
; ANA_REGB
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
; ANA_REGC
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
; ANA_REGD
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
; ANA_REGE
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM2_ERR
B ANADAT_CHECKSUM2_ERR
;-------------------------------;
;; 2. Load ANA_REG10 information
CONFIG3_START
LDR R7, =0x40014240
LDR R0, =0x80DE0
LDR R0, [R0]
LDR R1, =0x80DE4
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM1_OK
B ANADAT10_CHECKSUM1_ERR
ANADAT10_CHECKSUM1_OK
; ANA_REG10
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM1_ERR
LDR R0, =0x80DE8
LDR R0, [R0]
LDR R1, =0x80DEC
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM2_OK
B ANADAT10_CHECKSUM2_ERR
ANADAT10_CHECKSUM2_OK
; ANA_REG10
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM2_ERR
B ANADAT10_CHECKSUM2_ERR
NOP
ENDP
ENDIF
END
/*********************************** END OF FILE ******************************/
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c 0 → 100644
浏览文件 @ 5e643ff6
/**
******************************************************************************
* @file lib_CodeRAM.c
* @author Application Team
* @version V4.4.0
* @date 2019-01-18
* @brief Codes executed in SRAM.
******************************************************************************
* @attention
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "lib_CodeRAM.h"
#ifndef __GNUC__
/**
* @brief Flash deep standby, enter idle mode.
* @note This function is executed in RAM.
* @param None
* @retval None
*/
__RAM_FUNC void PMU_EnterIdle_FlashDSTB(void)
{
/* Flash deep standby */
FLASH->PASS = 0x55AAAA55;
FLASH->DSTB = 0xAA5555AA;
/* Enter Idle mode */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
__WFI();
}
#endif
/*********************************** END OF FILE ******************************/
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c 0 → 100644
浏览文件 @ 5e643ff6
/**
******************************************************************************
* @file lib_LoadNVR.c
* @author Application Team
* @version V4.7.0
* @date 2019-12-12
* @brief Load information from NVR.
******************************************************************************
* @attention
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "lib_LoadNVR.h"
/**
* @breif Load Analog trim data from NVR manually.
* @note Successful Operation:
* - Load [0x40DC0] or [0x40DD0] to ANA registers(B C D E), return 0.
* Operation failed:
* - return 1.
* @param None
* @retval 0: Function succeeded.
1: Function failed(Checksum error).
*/
uint32_t NVR_LoadANADataManual(void)
{
uint32_t checksum;
uint32_t op_reg;
uint32_t ana_data;
uint32_t key_reg = 0xFFFFFFFF;
/* Get Analog data1 */
ana_data = *NVR_ANA_TRIMDATA1;
op_reg = *NVR_ANA_OPREG1;
/* Calculate checksum1 */
checksum = ~(ana_data + op_reg + key_reg);
/* Compare checksum1 */
if (checksum == (*NVR_ANA_CHECKSUM1))
{
ANA->REGB = (uint8_t)(ana_data);
ANA->REGC = (uint8_t)(ana_data >> 8);
ANA->REGD = (uint8_t)(ana_data >> 16);
ANA->REGE = (uint8_t)(ana_data >> 24);
return 0;
}
/* Get Analog data2 */
ana_data = *NVR_ANA_TRIMDATA2;
op_reg = *NVR_ANA_OPREG2;
/* Calculate checksum2 */
checksum = ~(ana_data + op_reg + key_reg);
/* Compare checksum2 */
if (checksum == (*NVR_ANA_CHECKSUM2))
{
ANA->REGB = (uint8_t)(ana_data);
ANA->REGC = (uint8_t)(ana_data >> 8);
ANA->REGD = (uint8_t)(ana_data >> 16);
ANA->REGE = (uint8_t)(ana_data >> 24);
return 0;
}
else
{
return 1;
}
}
/**
* @breif Get the parameters of ADC voltage measuring.
* @note Voltage(unit:V) = aParameter*ADC_DATA + bParameter
* ADC_DATA: ADC channel original data
* aParameter/bParameter: Get from this function
* @param [in]Mode:
* NVR_3V_EXTERNAL_NODIV
* NVR_3V_EXTERNAL_RESDIV
* NVR_3V_EXTERNAL_CAPDIV
* NVR_3V_VDD_RESDIV
* NVR_3V_VDD_CAPDIV
* NVR_3V_BATRTC_RESDIV
* NVR_3V_BATRTC_CAPDIV
* NVR_5V_EXTERNAL_NODIV
* NVR_5V_EXTERNAL_RESDIV
* NVR_5V_EXTERNAL_CAPDIV
* NVR_5V_VDD_RESDIV
* NVR_5V_VDD_CAPDIV
* NVR_5V_BATRTC_RESDIV
* NVR_5V_BATRTC_CAPDIV
* @param [out]Parameter: The parameters get from NVR
* @retval 0: Function succeeded.
1: Function failed(Checksum error).
*/
uint32_t NVR_GetADCVoltageParameter(uint32_t Mode, NVR_ADCVOLPARA *Parameter)
{
uint32_t checksum;
uint32_t i;
int32_t tmp_int;
/* Check the parameters */
assert_parameters(IS_NVR_ADCVOL_MODE(Mode));
/*----- Power supply: 5V -----*/
if (0x100UL & Mode)
{
checksum = 0UL;
for (i=0; i<14; i++)
checksum += *(NVR_5VPARA_BASEADDR1+i);
checksum = ~(checksum);
if (checksum != *(NVR_5VPARA_BASEADDR1+i)) /* Checksum1 error */
{
checksum = 0UL;
for (i=0; i<14; i++)
checksum += *(NVR_5VPARA_BASEADDR2+i);
checksum = ~(checksum);
if (checksum != *(NVR_5VPARA_BASEADDR2+i)) /* Checksum2 error */
{
return 1;
}
else
{
tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR2+2*(Mode-0x100UL));
Parameter->aParameter = (float)(tmp_int / 100000000.0);
tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR2+2*(Mode-0x100UL)+1);
Parameter->bParameter = (float)(tmp_int / 100000000.0);
return 0;
}
}
else
{
tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR1+2*(Mode-0x100UL));
Parameter->aParameter = (float)(tmp_int / 100000000.0);
tmp_int = (int32_t)*(NVR_5VPARA_BASEADDR1+2*(Mode-0x100UL)+1);
Parameter->bParameter = (float)(tmp_int / 100000000.0);
return 0;
}
}
/*----- Power supply: 3.3V -----*/
else
{
checksum = 0UL;
for (i=0; i<14; i++)
checksum += *(NVR_3VPARA_BASEADDR1+i);
checksum = ~(checksum);
if (checksum != *(NVR_3VPARA_BASEADDR1+i)) /* Checksum1 error */
{
checksum = 0UL;
for (i=0; i<14; i++)
checksum += *(NVR_3VPARA_BASEADDR2+i);
checksum = ~(checksum);
if (checksum != *(NVR_3VPARA_BASEADDR2+i)) /* Checksum2 error */
{
return 1;
}
else
{
tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR2+2*(Mode));
Parameter->aParameter = (float)(tmp_int / 100000000.0);
tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR2+2*(Mode)+1);
Parameter->bParameter = (float)(tmp_int / 100000000.0);
return 0;
}
}
else
{
tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR1+2*(Mode));
Parameter->aParameter = (float)(tmp_int / 100000000.0);
tmp_int = (int32_t)*(NVR_3VPARA_BASEADDR1+2*(Mode)+1);
Parameter->bParameter = (float)(tmp_int / 100000000.0);
return 0;
}
}
}
/**
* @breif Get BAT Measure result.
* @param [out]MEAResult The pointer to struct NVR_BATMEARES.
* @retval 0: Function succeeded.
1: Function failed(Checksum error).
*/
uint32_t NVR_GetBATOffset(NVR_BATMEARES *MEAResult)
{
uint32_t bat_r;
uint32_t bat_c;
uint32_t checksum;
bat_r = *NVR_BAT_R1;
bat_c = *NVR_BAT_C1;
/* Calculate checksum1 */
checksum = ~(bat_r + bat_c);
if (checksum == (*NVR_BATMEA_CHECHSUM1))
{
MEAResult->BATRESResult = (float)((int32_t)bat_r / 1000.0);
MEAResult->BATCAPResult = (float)((int32_t)bat_c / 1000.0);
return 0;
}
bat_r = *NVR_BAT_R2;
bat_c = *NVR_BAT_C2;
/* Calculate checksum2 */
checksum = ~(bat_r + bat_c);
if (checksum == (*NVR_BATMEA_CHECHSUM2))
{
MEAResult->BATRESResult = (float)((int32_t)bat_r / 1000.0);
MEAResult->BATCAPResult = (float)((int32_t)bat_c / 1000.0);
return 0;
}
else
{
return 1;
}
}
/**
* @breif Load RTC ACPx pramameters from NVR to RTC registers.
Get RTC pramameters.
* @param [out]RTCTempData The pointer to struct NVR_RTCINFO.
* @retval 0: Function succeeded.
!0: Function not succeeded, load default value to registers.
bit[0]=1: Temperature Measure delta information checksum error, default value is 0.
bit[1]=1: P paramters checksum error, default value as follows
[P0]-214, [P1]1060, [P2]-19746971, [P5]6444, [P6]1342, [P7]0
bit[2]=1: P4 checksum error, default value is 0
bit[3]=1: ACKx checksum error, default value as follows
[K1]20827, [K2]21496, [K3]22020, [K4]24517, [K5]25257
bit[4]=1: ACTI checksum error, default value is 0x1800(24.0)
bit[5]=1: ACKTEMP checksum error, defalut value is 0x3C2800EC
*/
uint32_t NVR_GetInfo_LoadRTCData(NVR_RTCINFO *RTCTempData)
{
uint32_t real_temp, mea_temp;
uint32_t rtc_data1, rtc_data2, rtc_data3, rtc_data4;
uint32_t rtc_p4;
uint32_t rtc_ack[5];
uint32_t rtc_acti;
uint32_t rtc_acktemp;
uint32_t checksum;
float pclk_mul;
int16_t TempDelta;
uint32_t retval = 0;
/*------------------------ Temperature Measure delta -------------------------*/
real_temp = *NVR_REALTEMP1;
mea_temp = *NVR_MEATEMP1;
/* Calculate checksum1 */
checksum = ~(real_temp + mea_temp);
if (checksum == (*NVR_TEMP_CHECKSUM1)) //checksum1 true
{
TempDelta = (int16_t)real_temp - (int16_t)mea_temp;
}
else
{
real_temp = *NVR_REALTEMP2;
mea_temp = *NVR_MEATEMP2;
/* Calculate checksum2 */
checksum = ~(real_temp + mea_temp);
if (checksum == (*NVR_TEMP_CHECKSUM2)) //checksum2 true
{
TempDelta = (int16_t)real_temp - (int16_t)mea_temp;
}
else
{
TempDelta = 0;
retval |= BIT0;
}
}
/* Get Measure delta information */
RTCTempData->RTCTempDelta = TempDelta;
/*------------------------------ P parameters --------------------------------*/
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
/* Disable RTC Registers write-protection */
RTC_WriteProtection(DISABLE);
/* Get PCLK */
RTCTempData->APBClock = CLK_GetPCLKFreq();
pclk_mul = RTCTempData->APBClock / 6553600.0;
rtc_data1 = *NVR_RTC1_P1_P0;
rtc_data2 = *NVR_RTC1_P2;
rtc_data3 = *NVR_RTC1_P5_P4;
rtc_data4 = *NVR_RTC1_P7_P6;
/* Calculate checksum1 */
checksum = ~(rtc_data1 + rtc_data2 + rtc_data3 + rtc_data4);
if (checksum == (*NVR_RTC1_PCHECHSUM)) //checksum1 true
{
/* Get information */
RTCTempData->RTCTempP0 = (int16_t)(rtc_data1);
RTCTempData->RTCTempP1 = (int16_t)(rtc_data1 >> 16);
RTCTempData->RTCTempP2 = (int32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256));
RTCTempData->RTCTempP5 = (int16_t)(rtc_data3 >> 16);
RTCTempData->RTCTempP6 = (int16_t)(rtc_data4 * pclk_mul);
RTCTempData->RTCTempP7 = (int16_t)(rtc_data4 >> 16);
/* Load data to ACPx register */
RTC->ACP0 = (uint16_t)(rtc_data1 & 0xFFFF);
RTC->ACP1 = (uint16_t)((rtc_data1 >> 16) & 0xFFFF);
RTC->ACP2 = (uint32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256));
RTC->ACP5 = (uint16_t)((rtc_data3 >> 16) & 0xFFFF);
RTC->ACP6 = (uint16_t)((int16_t)(rtc_data4 * pclk_mul));
RTC->ACP7 = (uint16_t)((rtc_data4 >> 16) & 0xFFFF);
}
else
{
rtc_data1 = *NVR_RTC2_P1_P0;
rtc_data2 = *NVR_RTC2_P2;
rtc_data3 = *NVR_RTC2_P5_P4;
rtc_data4 = *NVR_RTC2_P7_P6;
/* Calculate checksum2 */
checksum = ~(rtc_data1 + rtc_data2 + rtc_data3 + rtc_data4);
if (checksum == (*NVR_RTC2_PCHECHSUM)) //checksum2 true
{
/* Get information */
RTCTempData->RTCTempP0 = (int16_t)(rtc_data1);
RTCTempData->RTCTempP1 = (int16_t)(rtc_data1 >> 16);
RTCTempData->RTCTempP2 = (int32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256));
RTCTempData->RTCTempP5 = (int16_t)(rtc_data3 >> 16);
RTCTempData->RTCTempP6 = (int16_t)(rtc_data4 * pclk_mul);
RTCTempData->RTCTempP7 = (int16_t)(rtc_data4 >> 16);
/* Load data to ACPx register */
RTC->ACP0 = (uint16_t)(rtc_data1 & 0xFFFF);
RTC->ACP1 = (uint16_t)((rtc_data1 >> 16) & 0xFFFF);
RTC->ACP2 = (uint32_t)((int32_t)rtc_data2 + (((int32_t)TempDelta)*256));
RTC->ACP5 = (uint16_t)((rtc_data3 >> 16) & 0xFFFF);
RTC->ACP6 = (uint16_t)((int16_t)(rtc_data4 * pclk_mul));
RTC->ACP7 = (uint16_t)((rtc_data4 >> 16) & 0xFFFF);
}
else
{
/* Get information */
RTCTempData->RTCTempP0 = -214;
RTCTempData->RTCTempP1 = 1060;
RTCTempData->RTCTempP2 = -19746971 + (TempDelta*256);
RTCTempData->RTCTempP5 = 6444;
RTCTempData->RTCTempP6 = (uint32_t)((int32_t)(1342*pclk_mul));
RTCTempData->RTCTempP7 = 0;
/* Load data to ACPx register */
RTC->ACP0 = (uint16_t)(-214);
RTC->ACP1 = (uint16_t)(1060);
RTC->ACP2 = (uint32_t)(-19746971 + (TempDelta*256));
RTC->ACP5 = (uint16_t)(6444);
RTC->ACP6 = (uint16_t)((int32_t)(1342*pclk_mul));
RTC->ACP7 = (uint16_t)(0);
retval |= BIT1;
}
}
/*----------------------------------- P4 -------------------------------------*/
/* Calculate checksum1 */
rtc_p4 = *NVR_RTC1_P4;
checksum = ~rtc_p4;
if (checksum == (*NVR_RTC1_P4_CHKSUM))//checksum1 true
{
/* Get information */
RTCTempData->RTCTempP4 = (int16_t)(*NVR_RTC1_P4);
RTC->ACP4 = *NVR_RTC1_P4;
}
else
{
rtc_p4 = *NVR_RTC2_P4;
checksum = ~rtc_p4;
if (checksum == (*NVR_RTC2_P4_CHKSUM))//checksum2 true
{
/* Get information */
RTCTempData->RTCTempP4 = (int16_t)(*NVR_RTC1_P4);
RTC->ACP4 = *NVR_RTC1_P4;
}
else
{
RTCTempData->RTCTempP4 = 0;
RTC->ACP4 = 0;
retval |= BIT2;
}
}
/*-------------------------- RTC ACKx parameters -----------------------------*/
rtc_ack[0] = *NVR_RTC1_ACK1;
rtc_ack[1] = *NVR_RTC1_ACK2;
rtc_ack[2] = *NVR_RTC1_ACK3;
rtc_ack[3] = *NVR_RTC1_ACK4;
rtc_ack[4] = *NVR_RTC1_ACK5;
checksum = ~(rtc_ack[0] + rtc_ack[1] + rtc_ack[2] + rtc_ack[3] + rtc_ack[4]);
if (checksum == (*NVR_RTC1_ACK_CHKSUM))//checksum1 true
{
/* Get information */
RTCTempData->RTCTempK1 = rtc_ack[0];
RTCTempData->RTCTempK2 = rtc_ack[1];
RTCTempData->RTCTempK3 = rtc_ack[2];
RTCTempData->RTCTempK4 = rtc_ack[3];
RTCTempData->RTCTempK5 = rtc_ack[4];
/* Load data to ACKx register */
RTC->ACK1 = rtc_ack[0];
RTC->ACK2 = rtc_ack[1];
RTC->ACK3 = rtc_ack[2];
RTC->ACK4 = rtc_ack[3];
RTC->ACK5 = rtc_ack[4];
}
else
{
rtc_ack[0] = *NVR_RTC2_ACK1;
rtc_ack[1] = *NVR_RTC2_ACK2;
rtc_ack[2] = *NVR_RTC2_ACK3;
rtc_ack[3] = *NVR_RTC2_ACK4;
rtc_ack[4] = *NVR_RTC2_ACK5;
checksum = ~(rtc_ack[0] + rtc_ack[1] + rtc_ack[2] + rtc_ack[3] + rtc_ack[4]);
if (checksum == (*NVR_RTC2_ACK_CHKSUM))//checksum2 true
{
/* Get information */
RTCTempData->RTCTempK1 = rtc_ack[0];
RTCTempData->RTCTempK2 = rtc_ack[1];
RTCTempData->RTCTempK3 = rtc_ack[2];
RTCTempData->RTCTempK4 = rtc_ack[3];
RTCTempData->RTCTempK5 = rtc_ack[4];
/* Load data to ACKx register */
RTC->ACK1 = rtc_ack[0];
RTC->ACK2 = rtc_ack[1];
RTC->ACK3 = rtc_ack[2];
RTC->ACK4 = rtc_ack[3];
RTC->ACK5 = rtc_ack[4];
}
else
{
/* Get information */
RTCTempData->RTCTempK1 = 20827;
RTCTempData->RTCTempK2 = 21496;
RTCTempData->RTCTempK3 = 22020;
RTCTempData->RTCTempK4 = 24517;
RTCTempData->RTCTempK5 = 25257;
/* Load data to ACKx register */
RTC->ACK1 = 20827;
RTC->ACK2 = 21496;
RTC->ACK3 = 22020;
RTC->ACK4 = 24517;
RTC->ACK5 = 25257;
retval |= BIT3;
}
}
/*-------------------------- RTC ACTI parameters -----------------------------*/
rtc_acti = *NVR_RTC1_ACTI;
checksum = ~rtc_acti;
if (checksum == (*NVR_RTC1_ACTI_CHKSUM))
{
/* Get information */
RTCTempData->RTCACTI = rtc_acti;
/* Load data to ACKx register */
RTC->ACTI = rtc_acti;
}
else
{
rtc_acti = *NVR_RTC2_ACTI;
checksum = ~rtc_acti;
if (checksum == (*NVR_RTC2_ACTI_CHKSUM))
{
/* Get information */
RTCTempData->RTCACTI = rtc_acti;
/* Load data to ACKx register */
RTC->ACTI = rtc_acti;
}
else
{
/* Get information */
RTCTempData->RTCACTI = 0x1800;
RTC->ACTI = 0x1800;
retval |= BIT4;
}
}
/*------------------------- RTC ACKTemp parameters ---------------------------*/
rtc_acktemp = *NVR_RTC1_ACKTEMP;
checksum = ~rtc_acktemp;
if (checksum == (*NVR_RTC1_ACKTEMP_CHKSUM))
{
/* Get information */
RTCTempData->RTCACKTemp = rtc_acktemp;
/* Load data to ACKx register */
RTC->ACKTEMP = rtc_acktemp;
}
else
{
rtc_acktemp = *NVR_RTC2_ACKTEMP;
checksum = ~rtc_acktemp;
if (checksum == (*NVR_RTC2_ACKTEMP_CHKSUM))
{
/* Get information */
RTCTempData->RTCACKTemp = rtc_acktemp;
/* Load data to ACKx register */
RTC->ACKTEMP = rtc_acktemp;
}
else
{
/* Get information */
RTCTempData->RTCACKTemp = 0x3C2800EC;
RTC->ACKTEMP = 0x3C2800EC;
retval |= BIT5;
}
}
/*--------------------------------- ACF200 -----------------------------------*/
RTCTempData->RTCACF200 = (uint32_t)((int32_t)(pclk_mul*0x320000));
RTC->ACF200 = (uint32_t)((int32_t)(pclk_mul*0x320000));
/* Enable RTC Registers write-protection */
RTC_WriteProtection(ENABLE);
/* Wait until the RTC registers be synchronized */
RTC_WaitForSynchro();
return retval;
}
/**
* @breif Get Power/Clock Measure result.
* @param [out]MEAResult The pointer to struct NVR_PWRMEARES.
* @retval 0: Function succeeded.
1: Function failed(Checksum error).
*/
uint32_t NVR_GetMISCGain(NVR_MISCGain *MEAResult)
{
uint32_t avcc_data, dvcc_data, bgp_data, rcl_data, rch_data;
uint32_t checksum;
avcc_data = *NVR_AVCC_MEA1;
dvcc_data = *NVR_DVCC_MEA1;
bgp_data = *NVR_BGP_MEA1;
rcl_data = *NVR_RCL_MEA1;
rch_data = *NVR_RCH_MEA1;
/* Calculate checksum1 */
checksum = ~(avcc_data + dvcc_data + bgp_data + rcl_data + rch_data);
if (checksum == (*NVR_PWR_CHECKSUM1))
{
MEAResult->AVCCMEAResult = avcc_data;
MEAResult->DVCCMEAResult = dvcc_data;
MEAResult->BGPMEAResult = bgp_data;
MEAResult->RCLMEAResult = rcl_data;
MEAResult->RCHMEAResult = rch_data;
return 0;
}
avcc_data = *NVR_AVCC_MEA2;
dvcc_data = *NVR_DVCC_MEA2;
bgp_data = *NVR_BGP_MEA2;
rcl_data = *NVR_RCL_MEA2;
rch_data = *NVR_RCH_MEA2;
/* Calculate checksum2 */
checksum = ~(avcc_data + dvcc_data + bgp_data + rcl_data + rch_data);
if (checksum == (*NVR_PWR_CHECKSUM2))
{
MEAResult->AVCCMEAResult = avcc_data;
MEAResult->DVCCMEAResult = dvcc_data;
MEAResult->BGPMEAResult = bgp_data;
MEAResult->RCLMEAResult = rcl_data;
MEAResult->RCHMEAResult = rch_data;
return 0;
}
else
{
return 1;
}
}
/**
* @breif Get Chip ID.
* @param [out]ChipID The pointer to struct NVR_CHIPID.
* @retval 0: Function succeeded.
1: Function failed(Checksum error).
*/
uint32_t NVR_GetChipID(NVR_CHIPID *ChipID)
{
uint32_t id0, id1;
uint32_t checksum;
id0 = *NVR_CHIP1_ID0;
id1 = *NVR_CHIP1_ID1;
/* Calculate checksum1 */
checksum = ~(id0 + id1);
if (checksum == (*NVR_CHIP1_CHECKSUM))
{
ChipID->ChipID0 = id0;
ChipID->ChipID1 = id1;
return 0;
}
id0 = *NVR_CHIP2_ID0;
id1 = *NVR_CHIP2_ID1;
/* Calculate checksum2 */
checksum = ~(id0 + id1);
if (checksum == (*NVR_CHIP2_CHECKSUM))
{
ChipID->ChipID0 = id0;
ChipID->ChipID1 = id1;
return 0;
}
else
{
return 1;
}
}
/**
* @breif Get LCD information.
* @param [out]LCDInfo The pointer to struct NVR_LCDINFO.
* @retval 0: Function succeeded.
1: Function failed(Checksum error).
*/
uint32_t NVR_GetLCDInfo(NVR_LCDINFO *LCDInfo)
{
uint32_t lcd_ldo, lcd_vol;
uint32_t checksum;
lcd_ldo = *NVR_LCD_LDO1;
lcd_vol = *NVR_LCD_VOL1;
/* Calculate checksum1 */
checksum = ~(lcd_ldo + lcd_vol);
if (checksum == (*NVR_LCD_CHECKSUM1))
{
LCDInfo->MEALCDLDO = lcd_ldo;
LCDInfo->MEALCDVol = lcd_vol;
return 0;
}
lcd_ldo = *NVR_LCD_LDO2;
lcd_vol = *NVR_LCD_VOL2;
/* Calculate checksum2 */
checksum = ~(lcd_ldo + lcd_vol);
if (checksum == (*NVR_LCD_CHECKSUM2))
{
LCDInfo->MEALCDLDO = lcd_ldo;
LCDInfo->MEALCDVol = lcd_vol;
return 0;
}
else
{
return 1;
}
}
/*********************************** END OF FILE ******************************/
bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/lib_cortex.c 0 → 100644
浏览文件 @ 5e643ff6
/**
******************************************************************************
* @file lib_cortex.c
* @author Application Team
* @version V4.4.0
* @date 2018-09-27
* @brief Cortex module driver.
******************************************************************************
* @attention
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "lib_cortex.h"
#include "core_cm0.h"
/**
* @brief 1. Clears Pending of a device specific External Interrupt.
* 2. Sets Priority of a device specific External Interrupt.
* 3. Enables a device specific External Interrupt.
* @param IRQn: External interrupt number .
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to target.h file)
* @param Priority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 3.
* A lower priority value indicates a higher priority
* @retval None
*/
void CORTEX_SetPriority_ClearPending_EnableIRQ(IRQn_Type IRQn, uint32_t Priority)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
/* Clear Pending Interrupt */
NVIC_ClearPendingIRQ(IRQn);
/* Set Interrupt Priority */
NVIC_SetPriority(IRQn, Priority);
/* Enable Interrupt in NVIC */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Enables a device specific interrupt in the NVIC interrupt controller.
* @note To configure interrupts priority correctly before calling it.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval None
*/
void CORTEX_NVIC_EnableIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt in NVIC */
NVIC_EnableIRQ(IRQn);
}
/**
* @brief Disables a device specific interrupt in the NVIC interrupt controller.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval None
*/
void CORTEX_NVIC_DisableIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Disable interrupt in NVIC */
NVIC_DisableIRQ(IRQn);
}
/**
* @brief Initiates a system reset request to reset the MCU.
* @retval None
*/
void CORTEX_NVIC_SystemReset(void)
{
/* System Reset */
NVIC_SystemReset();
}
/**
* @brief Gets the Pending bit of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval 0 Interrupt status is not pending.
1 Interrupt status is pending.
*/
uint32_t CORTEX_NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Get priority for Cortex-M0 system or device specific interrupts */
return NVIC_GetPendingIRQ(IRQn);
}
/**
* @brief Sets Pending bit of an external interrupt.
* @param IRQn External interrupt number
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval None
*/
void CORTEX_NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Set interrupt pending */
NVIC_SetPendingIRQ(IRQn);
}
/**
* @brief Clears the pending bit of an external interrupt.
* @param IRQn External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval None
*/
void CORTEX_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_DEVICE_IRQ(IRQn));
/* Clear interrupt pending */
NVIC_ClearPendingIRQ(IRQn);
}
/**
* @brief Gets the priority of an interrupt.
* @param IRQn: External interrupt number.
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to the appropriate CMSIS device file (target.h))
* @retval Interrupt Priority. Value is aligned automatically to the implemented
* priority bits of the microcontroller.
*/
uint32_t CORTEX_NVIC_GetPriority(IRQn_Type IRQn)
{
/* Get priority for Cortex-M0 system or device specific interrupts */
return NVIC_GetPriority(IRQn);
}
/**
* @brief Sets the priority of an interrupt.
* @param IRQn: External interrupt number .
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete target Devices IRQ Channels list, please refer to target.h file)
* @param Priority: The preemption priority for the IRQn channel.
* This parameter can be a value between 0 and 3.
* A lower priority value indicates a higher priority
* @retval None
*/
void CORTEX_NVIC_SetPriority(IRQn_Type IRQn, uint32_t Priority)
{
/* Check parameters */
assert_parameters(IS_CORTEX_NVIC_PREEMPTION_PRIORITY(Priority));
/* Get priority for Cortex-M0 system or device specific interrupts */
NVIC_SetPriority(IRQn, Priority);
}
/**
* @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer.
* Counter is in free running mode to generate periodic interrupts.
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t CORTEX_SystemTick_Config(uint32_t TicksNum)
{
return SysTick_Config(TicksNum);
}
/*********************************** END OF FILE ******************************/
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/**
******************************************************************************
* @file system_target.c
* @author Application Team
* @version V1.1.0
* @date 2019-10-28
* @brief system source file.
******************************************************************************
* @attention
*
******************************************************************************
*/
#include "target.h"
#define NVR_REGINFOCOUNT1 (0x80400)
#define NVR_REGINFOBAKOFFSET (0x100)
/**
* @brief Setup the microcontroller system
* @note This function should be used only after reset.
* @param None
* @retval None
*/
void SystemInit(void)
{
uint32_t i,nCount,nValue,nAddress,nChecksum;
nCount = *(__IO uint32_t *)NVR_REGINFOCOUNT1;
nChecksum = nCount;
nChecksum = ~nChecksum;
if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+4))
{
nCount = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET);
nChecksum = nCount;
nChecksum = ~nChecksum;
if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+4))
{
while(1);
}
}
for(i=0; i<nCount; i++)
{
nAddress = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+8+i*12);
nValue = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+12+i*12);
nChecksum = nAddress + nValue;
nChecksum = ~nChecksum;
if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+16+i*12))
{
nAddress = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+8+i*12);
nValue = *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+12+i*12);
nChecksum = nAddress + nValue;
nChecksum = ~nChecksum;
if(nChecksum != *(__IO uint32_t *)(NVR_REGINFOCOUNT1+NVR_REGINFOBAKOFFSET+16+i*12))
{
while(1);
}
}
if((nAddress>=0x40014800) && (nAddress<=0x40015000))
{
RTC_WriteRegisters(nAddress, &nValue, 1);
}
else
{
*(__IO uint32_t *)(nAddress) = nValue;
}
}
}
/**
* @brief Initializes registers.
* @param None
* @retval None
*/
void SystemUpdate(void)
{
}
/*********************************** END OF FILE ******************************/
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/**************************************************************************//**
* @file cmsis_compiler.h
* @brief CMSIS compiler generic header file
* @version V5.0.4
* @date 10. January 2018
******************************************************************************/
/*
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __CMSIS_COMPILER_H
#define __CMSIS_COMPILER_H
#include <stdint.h>
/*
* Arm Compiler 4/5
*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*
* Arm Compiler 6 (armclang)
*/
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armclang.h"
/*
* GNU Compiler
*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*
* IAR Compiler
*/
#elif defined ( __ICCARM__ )
#include <cmsis_iccarm.h>
/*
* TI Arm Compiler
*/
#elif defined ( __TI_ARM__ )
#include <cmsis_ccs.h>
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed))
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __attribute__((aligned(x)))
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* TASKING Compiler
*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __packed__
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __packed__
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __packed__
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
struct __packed__ T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#define __ALIGNED(x) __align(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
/*
* COSMIC Compiler
*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#ifndef __ASM
#define __ASM _asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __STATIC_FORCEINLINE
#define __STATIC_FORCEINLINE __STATIC_INLINE
#endif
#ifndef __NO_RETURN
// NO RETURN is automatically detected hence no warning here
#define __NO_RETURN
#endif
#ifndef __USED
#warning No compiler specific solution for __USED. __USED is ignored.
#define __USED
#endif
#ifndef __WEAK
#define __WEAK __weak
#endif
#ifndef __PACKED
#define __PACKED @packed
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT @packed struct
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION @packed union
#endif
#ifndef __UNALIGNED_UINT32 /* deprecated */
@packed struct T_UINT32 { uint32_t v; };
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
#endif
#ifndef __UNALIGNED_UINT16_WRITE
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT16_READ
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
#endif
#ifndef __UNALIGNED_UINT32_WRITE
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
#endif
#ifndef __UNALIGNED_UINT32_READ
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
#endif
#ifndef __ALIGNED
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
#define __ALIGNED(x)
#endif
#ifndef __RESTRICT
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
#define __RESTRICT
#endif
#else
#error Unknown compiler.
#endif
#endif /* __CMSIS_COMPILER_H */
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bsp/Vango_V85xx/Libraries/CMSIS/cmsis_version.h 0 → 100644
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/**************************************************************************//**
* @file cmsis_version.h
* @brief CMSIS Core(M) Version definitions
* @version V5.0.2
* @date 19. April 2017
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined (__clang__)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CMSIS_VERSION_H
#define __CMSIS_VERSION_H
/* CMSIS Version definitions */
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
#define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
#endif
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bsp/Vango_V85xx/Libraries/CMSIS/core_cmFunc.h 0 → 100644
浏览文件 @ 5e643ff6
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return (__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return (__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return (__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return (__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return (__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return (__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return (__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return (__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return (__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return (__regfpscr);
#else
return (0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile("MRS %0, control" : "=r"(result));
return (result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile("MSR control, %0" : : "r"(control));
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, ipsr" : "=r"(result));
return (result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, apsr" : "=r"(result));
return (result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile("MRS %0, xpsr" : "=r"(result));
return (result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile("MRS %0, psp\n" : "=r"(result));
return (result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack));
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile("MRS %0, msp\n" : "=r"(result));
return (result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack));
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile("MRS %0, primask" : "=r"(result));
return (result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile("MSR primask, %0" : : "r"(priMask));
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile("MRS %0, basepri_max" : "=r"(result));
return (result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile("MSR basepri, %0" : : "r"(value));
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile("MRS %0, faultmask" : "=r"(result));
return (result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile("MSR faultmask, %0" : : "r"(faultMask));
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile("VMRS %0, fpscr" : "=r"(result));
return (result);
#else
return (0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile("VMSR fpscr, %0" : : "r"(fpscr));
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */
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import rtconfig
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Glob('VangoV85xx_standard_peripheral/Source/*.c')
src += [cwd + '/CMSIS/Vango/V85xx/Source/system_target.c']
src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c']
src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_cortex.c']
src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += [cwd + '/CMSIS/Vango/V85xx/Source/GCC/startup_target.S']
if rtconfig.CROSS_TOOL == 'keil':
src += [cwd + '/CMSIS/Vango/V85xx/Source/Keil5/startup_target.S']
path = [
cwd + '/CMSIS/Vango/V85xx/Include',
cwd + '/CMSIS',
cwd + '/VangoV85xx_standard_peripheral/Include',]
CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'V85xx','USE_TARGET_DRIVER']
group = DefineGroup('Vango_Lib', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
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/**
*******************************************************************************
* @file lib_version.h
* @author Application Team
* @version V4.5.0
* @date 2019-05-14
* @brief Version library.
*******************************************************************************/
#ifndef __LIB_VERSION_H
#define __LIB_VERSION_H
#ifdef __cplusplus
extern "C" {
#endif
#include "target.h"
#define DRIVER_VERSION(major,minor) (((major) << 8) | (minor))
/* Exported Functions ------------------------------------------------------- */
/**
* @brief Read receive data register.
* @param None
* @retval Version value
*/
uint16_t Target_GetDriveVersion(void);
#ifdef __cplusplus
}
#endif
#endif /* __LIB_VERSION_H */
/*********************************** END OF FILE ******************************/
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