1. 20 10月, 2011 1 次提交
  2. 05 10月, 2011 21 次提交
  3. 04 10月, 2011 2 次提交
  4. 01 10月, 2011 3 次提交
    • A
      ARM: OMAP: musb: Remove a redundant omap4430_phy_init call in usb_musb_init · b8e111a7
      Axel Lin 提交于
      Current code calls omap4430_phy_init() twice in usb_musb_init().
      Calling omap4430_phy_init() once is enough.
      This patch removes the first omap4430_phy_init() call, which using an
      uninitialized pointer as parameter.
      
      This patch elimates below build warning:
      arch/arm/mach-omap2/usb-musb.c: In function 'usb_musb_init':
      arch/arm/mach-omap2/usb-musb.c:141: warning: 'dev' may be used uninitialized in this function
      Signed-off-by: NAxel Lin <axel.lin@gmail.com>
      Bjarne Steinsbo <bsteinsbo@gmail.com>
      Acked-by: NFelipe Balbi <balbi@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      b8e111a7
    • T
      ARM: OMAP: Fix i2c init for twl4030 · bfd46a54
      Tony Lindgren 提交于
      Looks like 2600 kHz rate does not work reliably on 2430,
      so just use the 100 kHz rate.
      
      Otherwise the system often fails to boot properly with:
      
      omap_i2c omap_i2c.2: timeout waiting for bus ready
      omap_i2c omap_i2c.2: timeout waiting for bus ready
      twl: i2c_write failed to transfer all messages
      omap_i2c omap_i2c.2: timeout waiting for bus ready
      twl: i2c_write failed to transfer all messages
      omap_i2c omap_i2c.2: timeout waiting for bus ready
      twl: i2c_write failed to transfer all messages
      twl: clock init err [-110]
      omap_i2c omap_i2c.2: timeout waiting for bus ready
      twl: i2c_write failed to transfer all messages
      TWL4030 Unable to unlock IDCODE registers --110
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      bfd46a54
    • B
      ARM: OMAP4: MMC: fix power and audio issue, decouple USBC1 from MMC1 · 3696d303
      Bryan Buckley 提交于
      Remove OMAP4_USBC1_ICUSB_PWRDNZ_MASK during enable/disable PWRDNZ mode for
      MMC1_PBIAS and associated extended-drain MMC1 I/O cell. This is in accordance
      with the control module programming guide. This fixes a bug where if trying to
      use gpio_98 or gpio_99 and MMC1 at the same time the GPIO signal will be
      affected by a changing SDMMC1_VDDS.
      
      Software must keep MMC1_PBIAS cell and MMC1_IO cell PWRDNZ signals low whenever
      SDMMC1_VDDS ramps up/down or changes for cell protection purposes.
      
      MMC1 is based on SDMMC1_VDDS whereas USBC1 is based on SIM_VDDS therefore
      they can operate independently.
      Signed-off-by: NBryan Buckley <bryan.buckley@ti.com>
      Acked-by: NKishore Kadiyala <kishore.kadiyala@ti.com>
      Tested-by: NBalaji T K <balajitk@ti.com>
      Signed-off-by: NTony Lindgren <tony@atomide.com>
      3696d303
  5. 29 9月, 2011 1 次提交
  6. 28 9月, 2011 4 次提交
  7. 27 9月, 2011 8 次提交