This patch connects IPU and display encoder (HDMI, LVDS, MIPI)
device tree nodes, as well as parallel displays on the DISP0
and DISP1 outputs, using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt

The IPU ports correspond to the two display interfaces. The
order of endpoints in the ports is arbitrary.

Each encoder with an associated input multiplexer has multiple
input ports in the device tree. The order and reg property of
the ports must correspond to the multiplexer input order.

Since the imx-drm node now only needs to contain links to the
display interfaces, it can be moved to the SoC dtsi level. At
the board level, only connections between the display interface
ports and encoders or panels have to be added.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

Extracted from another patch by Fabio Estevam, this adds the DT
configuration for HDMI output on the IMX6 SoCs
Acked-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Reviewed-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>

This reverts commit b1d27c79.

Previously we switched the SSI scriprt to dual-fifo mode to reduce playback
underrun issue, which is only included by SDMA firmware version 2. However,
there are quite a lot people still using version 1 or default firmware in
the ROM code of SoC while these two kinds of firmwares do not support the
dual-fifo script and the audio function on their platform would be broken.

Thus this patch provisionally reverts the dual-fifo script to the original
single fifo script to meet all kinds of users' requirements, including the
version 1/2 or inner ROM firmware.
Reported-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NNicolin Chen <Guangyu.Chen@freescale.com>
Tested-by: NFabio Estevam <fabio.estevam@freescale.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

Use dual-fifo sdma scripts instead of shared scripts for ssi on i.MX series.
Signed-off-by: NNicolin Chen <b42378@freescale.com>
Acked-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NVinod Koul <vinod.koul@intel.com>

The spdif "rxtx5" clock option is being set to ipg clk (62) by mistake.
This causes an incorrect time keeping when spdif driver is running,
because ipg is ancestor clock for clocksource while spdif driver will
change the rate of this clock in certain circumstance.  Before the
correct clock for "rxtx5" option can be supplied, let's disable this
option for now by filling a dummy clock for it.
Reported-by: NRussell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add pcie device node for imx6qdl.
Signed-off-by: NSean Cross <xobs@kosagi.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This is needed for supporting ultra high speed cards like SD3.0 cards.
Signed-off-by: NDong Aisheng <b29396@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: NNicolin Chen <b42378@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The ocram on imx6q is 256 KiB while on imx6dl it's 128 KiB.  Let's
have separate node for imx6q and imx6dl.  It also changes imx6q size
0x3f000 to 0x40000 to match the hardware.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Acked-by: NLiu Ying <Ying.Liu@freescale.com>

Updates SSI nodes to adopt generic DMA bindings.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Mark ocotp as a syscon node and add tempmon for imx6q thermal support.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

After mxs-dma driver adopts generic DMA device tree binding, gpmi
channel interrupt number is defined in DMA controller node, and
channel ID is listed in "dmas" property.  So the DMA channel interrupt
number in gpmi node "interrupts" property and fsl,gpmi-dma-channel which
are used by old customized DMA binding can be removed now.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>

Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add the dma property for all the uart.

Note: Add the dma property does not mean we enable the dma for this
uart.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add the a new pinctrl for uart3. In the imx6q{dl}-sabreauto boards,
the uart3 is used for Bluetooth.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add more imx6q/dl pin groups for those supported boards, e.g. sabresd,
sabreauto, arm2.

IPU2 pin groups are added into imx6q.dtsi, since the block is only
available on imx6q.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The imx6q and imx6dl are two pin-to-pin compatible SoCs.  The same board
design can work with either chip plugged into the socket, e.g. sabresd
and sabreauto boards.

We currently define pin groups in imx6q.dtsi and imx6dl.dtsi
respectively because the pad macro names are different between two
chips.  This brings a maintenance burden on having the same label point
to the same pin group defined in two places.

The patch replaces prefix MX6Q_ and MX6DL_ with MX6QDL_ for both SoCs
pad macro names.  Then the pin groups becomes completely common between
imx6q and imx6dl and can just be moved into imx6qdl.dtsi, so that the
long term maintenance of imx6q/dt pin settings becomes easier.

Unfortunately, the change brings some dramatic diff stat, but it's all
about DTS file, and the ultimate net diff stat is good.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add the #dma-cells property for all the sdma in all the imx platforms.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

i.MX6DL does not have the second IPU, but the LVDS multiplexers can connect
either LVDS channel of the LDB to IPU1 DI0 or IPU1 DI1.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
[shawn.guo: remove "crtcs" property from imx6qdl.dtsi]
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This patch enables the On-Chip SRAM (OCRAM) on i.MX53 and i.MX6 SoCs.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

This allows to order the i2c and spi devices correctly.
While at it reorder the aliases entries alphabetically.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The i.MX6 gpt is handled by the i.MX31 gpt driver in the kernel,
so add a corresponding compatible entry.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add the clock and compatible information for the weim.
Also adds the weim label.
Signed-off-by: NHuang Shijie <b32955@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

There is a redundant ocotp node.  Remove it.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

There is a redundant label on usbmisc node.  Remove it.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Configure the data and tag latency for the L2 cache. This improves the
system performance.

This configuration is taken from Freescale's kernel patch

"ENGR00153601 [MX6]Adjust L2 cache parameter" [1]

which does

writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL));
writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL));

In this patch we are doing the same via the device tree.
Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

[1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1

The SRC in i.MX51 and i.MX53 is similar to the one in i.MX6q minus
the IPU2 reset line and multi core CPU reset/enable bits.
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: NStephen Warren <swarren@nvidia.com>
Reviewed-by: NMarek Vasut <marex@denx.de>
Reviewed-by: NPavel Machek <pavel@ucw.cz>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add ldb device tree node and clock lookups.
Signed-off-by: NSteffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

The i.MX6 already has a devicetree node for the GPT, but not yet
has the clocks. Add them.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Replace /include/ (dtc) with #include (C pre-processor) for all imx DT
files, so that gcc -E handles the entire include tree, and hence any of
those files can #include some other file e.g. for constant definitions.

This allows future use of #defines and header files in order to define
names for various constants, such as pinctrl settings. Use of those
features will increase the readability of the device tree files.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add ARM Cortex A9 Performance Monitor Unit (PMU) support.
On i.MX6 a combined interrupt on hardware line #126 is used
(i.MX6 TRM: Performance Unit interrupt).

For more details see Documentation/devicetree/bindings/arm/pmu.txt
Signed-off-by: NDirk Behme <dirk.behme@de.bosch.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

While booting from device tree, imx6q used to provide twd clock lookup
by calling clk_register_clkdev() in clock driver.  However, the commit
bd603455 (ARM: use device tree to get smp_twd clock) forces DT boot to
look up the clock from device tree.  It causes the failure below when
twd driver tries to get the clock, and hence kernel has to calibrate the
local timer frequency.

 smp_twd: clock not found -2
 ...
 Calibrating local timer... 396.13MHz.

Fix the regression by providing twd clock lookup from device tree, and
remove the unused twd clk_register_clkdev() call from clock driver.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

Add generic DMA device tree binding for mxs-dma.  The changes include:

 * Add channel interrupts into DMA controller nodes
 * Add properties '#dma-cells' and 'dma-channels' for DMA controller nodes
 * And properties 'dmas' and 'dma-names' for DMA client nodes
 * Update mxs-dma device tree binding doc
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Reviewed-by: NArnd Bergmann <arnd@arndb.de>

Add dtsi for imx6q and imx6dl with non-common blocks moved into there.
Major differences between imx6dl and imx6q:

 * Dual vs. Quad cores
 * single vs. dual IPU
 * 128 vs. 256 KB OCRAM
 * imx6q: ECSPI5, OpenVG (GC355), SATA
 * imx6dl: I2C4, PXP, EPDC, LCDIF
 * iomuxc/pads definition
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

i.MX6 Quad and i.MX6 DualLite is similar enough to share one dtsi
file, so rename imx6q.dtsi to imx6qdl.dtsi preparing for the addition
of imx6dl support.

Another member of i.MX6 series i.MX6 SoloLite is different enough
from the other two, so it will stand as a separate dtsi.  That's why
we rename to imx6qdl.dtsi not imx6.dtsi.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>

For ANATOP LDOs, vddcpu, vddsoc and vddpu
have step time settings in the misc2 register, need
to add necessary step time info for these three LDOs,
then regulator driver can add necessary delay based on
these settings.

offset 0x170:
bit [24-25]: vddcpu
bit [26-27]: vddpu
bit [28-29]: vddsoc

field definition:
0'b00: 64 cycles of 24M clock;
0'b01: 128 cycles of 24M clock;
0'b02: 256 cycles of 24M clock;
0'b03: 512 cycles of 24M clock;
Signed-off-by: NAnson Huang <b20788@freescale.com>
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>