- 08 7月, 2015 1 次提交
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由 Pankaj Dev 提交于
Incorrect register offset used for sthi407 clockgenC Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Fixes: 51306d56 ("clk: st: STiH407: Support for clockgenC0") Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 07 7月, 2015 3 次提交
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由 Pankaj Dev 提交于
Add the CLK_GET_RATE_NOCACHE flag to all the clocks with recalc ops, so that they reflect Hw rate after CPS wake-up when a clk_get_rate() is called Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Gabriel Fernandez 提交于
This patch fixes the value for disabling the FSYN channel clock. The 'is_enabled' returned value is also fixed. Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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由 Gabriel Fernandez 提交于
Remove this duplicated code due to a bad copy / paste. Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 15 5月, 2015 1 次提交
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由 Stephen Boyd 提交于
drivers/clk/st/clkgen-mux.c:134:4: warning: symbol 'clkgena_divmux_get_parent' was not declared. Should it be static? drivers/clk/st/clkgen-mux.c:171:15: warning: symbol 'clkgena_divmux_recalc_rate' was not declared. Should it be static? drivers/clk/st/clkgen-mux.c:218:12: warning: symbol 'clk_register_genamux' was not declared. Should it be static? drivers/clk/st/clkgen-mux.c:388:13: warning: symbol 'st_of_clkgena_divmux_setup' was not declared. Should it be static? drivers/clk/st/clkgen-mux.c:488:13: warning: symbol 'st_of_clkgena_prediv_setup' was not declared. Should it be static? drivers/clk/st/clkgen-mux.c:625:13: warning: symbol 'st_of_clkgen_mux_setup' was not declared. Should it be static? drivers/clk/st/clkgen-mux.c:702:13: warning: symbol 'st_of_clkgen_vcc_setup' was not declared. Should it be static? drivers/clk/st/clkgen-pll.c:273:15: warning: symbol 'recalc_stm_pll800c65' was not declared. Should it be static? drivers/clk/st/clkgen-pll.c:300:15: warning: symbol 'recalc_stm_pll1600c65' was not declared. Should it be static? drivers/clk/st/clkgen-pll.c:324:15: warning: symbol 'recalc_stm_pll3200c32' was not declared. Should it be static? drivers/clk/st/clkgen-pll.c:346:15: warning: symbol 'recalc_stm_pll1200c32' was not declared. Should it be static? drivers/clk/st/clkgen-pll.c:565:19: warning: incorrect type in assignment (different address spaces) drivers/clk/st/clkgen-pll.c:565:19: expected void [noderef] <asn:2>*reg drivers/clk/st/clkgen-pll.c:565:19: got void * drivers/clk/st/clkgen-pll.c:576:18: warning: incorrect type in assignment (different address spaces) drivers/clk/st/clkgen-pll.c:576:18: expected void [noderef] <asn:2>*reg drivers/clk/st/clkgen-pll.c:576:18: got void * drivers/clk/st/clkgen-pll.c:693:53: warning: incorrect type in argument 2 (different address spaces) drivers/clk/st/clkgen-pll.c:693:53: expected void *[noderef] <asn:2>reg drivers/clk/st/clkgen-pll.c:693:53: got void [noderef] <asn:2>*[assigned] pll_base drivers/clk/st/clkgen-fsyn.c:495:5: warning: symbol 'clk_fs660c32_vco_get_rate' was not declared. Should it be static? drivers/clk/st/clkgen-fsyn.c:522:5: warning: symbol 'clk_fs660c32_vco_get_params' was not declared. Should it be static? drivers/clk/st/clk-flexgen.c:119:15: warning: symbol 'flexgen_recalc_rate' was not declared. Should it be static? drivers/clk/st/clk-flexgen.c:177:12: warning: symbol 'clk_register_flexgen' was not declared. Should it be static? drivers/clk/st/clk-flexgen.c:263:13: warning: symbol 'st_of_flexgen_setup' was not declared. Should it be static? Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 02 4月, 2015 1 次提交
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由 Fabian Frederick 提交于
of_device_id is always used as const. (See driver.of_match_table and open firmware functions) __initdata updated to __initconst for static const struct of_device_id ti_clkdm_match_table[] Signed-off-by: NFabian Frederick <fabf@skynet.be> Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>
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- 29 7月, 2014 7 次提交
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由 Gabriel FERNANDEZ 提交于
This patch extend the range of possible frequencies of the fs432c65 and fs660c32 Quad frequency synthesizers. Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Acked-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Gabriel FERNANDEZ 提交于
The patch added support for ClockGenD0/D2/D3 It includes one 660 Quadfs. Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: NOlivier Bideau <olivier.bideau@st.com> Acked-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Gabriel FERNANDEZ 提交于
The patch added support for DT registration of ClockGenC0 It includes 2 c32 type PLL and a 660 Quadfs. Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: NOlivier Bideau <olivier.bideau@st.com> Acked-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Gabriel FERNANDEZ 提交于
This patch adds the support of quadfs reset handling. Signed-off-by: NOlivier Bideau <olivier.bideau@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Acked-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Gabriel FERNANDEZ 提交于
This patch introduces polarity indication for pll power up bit and for standby bit in order to have same code between stih416 and stih407 boards. Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Acked-by: NPeter Griffin <peter.griffin@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Gabriel FERNANDEZ 提交于
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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由 Gabriel FERNANDEZ 提交于
converts stm_fs tables into static const Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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- 26 3月, 2014 1 次提交
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由 Gabriel FERNANDEZ 提交于
The patch supports the 216/432/660 type Quad Frequency Synthesizers used by ClockGenB/C/D/E/F QUADFS clock : It includes support for all 216/432/660 type Quad Frequency Synthesizers : implemented as Fixed Parent / Rate / Gate clock, with clock rate calculated reading H/w settings done at BOOT. QuadFS have 4 outputs : chan0 chan1 chan2 chan3 Signed-off-by: NPankaj Dev <pankaj.dev@st.com> Signed-off-by: NGabriel Fernandez <gabriel.fernandez@st.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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