drivers: clk: st: Incorrect register offset used for lock_status

Incorrect register offset used for sthi407 clockgenC
Signed-off-by: NPankaj Dev <pankaj.dev@st.com>
Signed-off-by: NGabriel Fernandez <gabriel.fernandez@linaro.org>
Fixes: 51306d56 ("clk: st: STiH407: Support for clockgenC0")
Signed-off-by: NStephen Boyd <sboyd@codeaurora.org>

drivers/clk/st/clkgen-fsyn.c

@@ -340,7 +340,7 @@ static const struct clkgen_quadfs_data st_fs660c32_C_407 = {
 		    CLKGEN_FIELD(0x30c, 0xf, 20),
 		    CLKGEN_FIELD(0x310, 0xf, 20) },
 	.lockstatus_present = true,
-	.lock_status = CLKGEN_FIELD(0x2A0, 0x1, 24),
+	.lock_status = CLKGEN_FIELD(0x2f0, 0x1, 24),
 	.powerup_polarity = 1,
 	.standby_polarity = 1,
 	.pll_ops	= &st_quadfs_pll_c32_ops,