Use the cached values to calculate PLL rate instead of the register values.
This is required to prevent erroneous PLL rate return when the PLL rate
has been configured but the PLL is not prepared yet.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: NGaël PORTAY <gael.portay@gmail.com>
Tested-by: NGaël PORTAY <gael.portay@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

The AT91 PLL rate configuration is done by configuring a multiplier/divider
pair.
The previous calculation was over-complicated (and apparently buggy).
Simplify the implementation and add some comments to explain what is done
here.
Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: NGaël PORTAY <gael.portay@gmail.com>
Tested-by: NGaël PORTAY <gael.portay@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: NGaël PORTAY <gael.portay@gmail.com>
Tested-by: NGaël PORTAY <gael.portay@gmail.com>
Signed-off-by: NMike Turquette <mturquette@linaro.org>

This patch adds new at91 master clock implementation using common clk
framework.

The master clock layout describe the MCKR register layout.
There are 2 master clock layouts:
- at91rm9200
- at91sam9x5

Master clocks are given characteristics:
- min/max clock output rate

These characteristics are checked during rate change to avoid
over/underclocking.

These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>

This patch adds new at91 pll clock implementation using common clk framework.

The pll clock layout describe the PLLX register layout.
There are four pll clock layouts:
- at91rm9200
- at91sam9g20
- at91sam9g45
- sama5d3

PLL clocks are given characteristics:
- min/max clock source rate
- ranges of valid clock output rates
- values to set in out and icpll fields for each supported output range

These characteristics are checked during rate change to avoid
over/underclocking.

These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.
Signed-off-by: NBoris BREZILLON <b.brezillon@overkiz.com>
Acked-by: NMike Turquette <mturquette@linaro.org>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>