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由 Boris BREZILLON 提交于
The AT91 PLL rate configuration is done by configuring a multiplier/divider pair. The previous calculation was over-complicated (and apparently buggy). Simplify the implementation and add some comments to explain what is done here. Signed-off-by: NBoris BREZILLON <boris.brezillon@free-electrons.com> Reported-by: NGaël PORTAY <gael.portay@gmail.com> Tested-by: NGaël PORTAY <gael.portay@gmail.com> Signed-off-by: NMike Turquette <mturquette@linaro.org>
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