cpu-probe.c 27.1 KB
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/*
 * Processor capabilities determination functions.
 *
 * Copyright (C) xxxx  the Anonymous
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 * Copyright (C) 1994 - 2006 Ralf Baechle
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 * Copyright (C) 2003, 2004  Maciej W. Rozycki
 * Copyright (C) 2001, 2004  MIPS Inc.
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 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ptrace.h>
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#include <linux/smp.h>
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#include <linux/stddef.h>
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#include <linux/module.h>
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#include <asm/bugs.h>
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#include <asm/cpu.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/system.h>
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#include <asm/watch.h>
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#include <asm/elf.h>
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#include <asm/spram.h>
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#include <asm/uaccess.h>

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/*
 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
 * the implementation of the "wait" feature differs between CPU families. This
 * points to the function that implements CPU specific wait.
 * The wait instruction stops the pipeline and reduces the power consumption of
 * the CPU very much.
 */
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void (*cpu_wait)(void);
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EXPORT_SYMBOL(cpu_wait);
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static void r3081_wait(void)
{
	unsigned long cfg = read_c0_conf();
	write_c0_conf(cfg | R30XX_CONF_HALT);
}

static void r39xx_wait(void)
{
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	local_irq_disable();
	if (!need_resched())
		write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
	local_irq_enable();
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}

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extern void r4k_wait(void);
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/*
 * This variant is preferable as it allows testing need_resched and going to
 * sleep depending on the outcome atomically.  Unfortunately the "It is
 * implementation-dependent whether the pipeline restarts when a non-enabled
 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
 * using this version a gamble.
 */
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void r4k_wait_irqoff(void)
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{
	local_irq_disable();
	if (!need_resched())
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		__asm__("	.set	push		\n"
			"	.set	mips3		\n"
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			"	wait			\n"
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			"	.set	pop		\n");
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	local_irq_enable();
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	__asm__(" 	.globl __pastwait	\n"
		"__pastwait:			\n");
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}

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/*
 * The RM7000 variant has to handle erratum 38.  The workaround is to not
 * have any pending stores when the WAIT instruction is executed.
 */
static void rm7k_wait_irqoff(void)
{
	local_irq_disable();
	if (!need_resched())
		__asm__(
		"	.set	push					\n"
		"	.set	mips3					\n"
		"	.set	noat					\n"
		"	mfc0	$1, $12					\n"
		"	sync						\n"
		"	mtc0	$1, $12		# stalls until W stage	\n"
		"	wait						\n"
		"	mtc0	$1, $12		# stalls until W stage	\n"
		"	.set	pop					\n");
	local_irq_enable();
}

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/*
 * The Au1xxx wait is available only if using 32khz counter or
 * external timer source, but specifically not CP0 Counter.
 * alchemy/common/time.c may override cpu_wait!
 */
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static void au1k_wait(void)
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{
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	__asm__("	.set	mips3			\n"
		"	cache	0x14, 0(%0)		\n"
		"	cache	0x14, 32(%0)		\n"
		"	sync				\n"
		"	nop				\n"
		"	wait				\n"
		"	nop				\n"
		"	nop				\n"
		"	nop				\n"
		"	nop				\n"
		"	.set	mips0			\n"
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		: : "r" (au1k_wait));
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}

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static int __initdata nowait;
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static int __init wait_disable(char *s)
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{
	nowait = 1;

	return 1;
}

__setup("nowait", wait_disable);

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static int __cpuinitdata mips_fpu_disabled;

static int __init fpu_disable(char *s)
{
	cpu_data[0].options &= ~MIPS_CPU_FPU;
	mips_fpu_disabled = 1;

	return 1;
}

__setup("nofpu", fpu_disable);

int __cpuinitdata mips_dsp_disabled;

static int __init dsp_disable(char *s)
{
	cpu_data[0].ases &= ~MIPS_ASE_DSP;
	mips_dsp_disabled = 1;

	return 1;
}

__setup("nodsp", dsp_disable);

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void __init check_wait(void)
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{
	struct cpuinfo_mips *c = &current_cpu_data;

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	if (nowait) {
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		printk("Wait instruction disabled.\n");
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		return;
	}

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	switch (c->cputype) {
	case CPU_R3081:
	case CPU_R3081E:
		cpu_wait = r3081_wait;
		break;
	case CPU_TX3927:
		cpu_wait = r39xx_wait;
		break;
	case CPU_R4200:
/*	case CPU_R4300: */
	case CPU_R4600:
	case CPU_R4640:
	case CPU_R4650:
	case CPU_R4700:
	case CPU_R5000:
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	case CPU_R5500:
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	case CPU_NEVADA:
	case CPU_4KC:
	case CPU_4KEC:
	case CPU_4KSC:
	case CPU_5KC:
	case CPU_25KF:
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	case CPU_PR4450:
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	case CPU_BMIPS3300:
	case CPU_BMIPS4350:
	case CPU_BMIPS4380:
	case CPU_BMIPS5000:
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	case CPU_CAVIUM_OCTEON:
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	case CPU_CAVIUM_OCTEON_PLUS:
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	case CPU_CAVIUM_OCTEON2:
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	case CPU_JZRISC:
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		cpu_wait = r4k_wait;
		break;

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	case CPU_RM7000:
		cpu_wait = rm7k_wait_irqoff;
		break;

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	case CPU_24K:
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	case CPU_34K:
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	case CPU_1004K:
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		cpu_wait = r4k_wait;
		if (read_c0_config7() & MIPS_CONF7_WII)
			cpu_wait = r4k_wait_irqoff;
		break;

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	case CPU_74K:
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		cpu_wait = r4k_wait;
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		if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
			cpu_wait = r4k_wait_irqoff;
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		break;
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	case CPU_TX49XX:
		cpu_wait = r4k_wait_irqoff;
		break;
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	case CPU_ALCHEMY:
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		cpu_wait = au1k_wait;
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		break;
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	case CPU_20KC:
		/*
		 * WAIT on Rev1.0 has E1, E2, E3 and E16.
		 * WAIT on Rev2.0 and Rev3.0 has E16.
		 * Rev3.1 WAIT is nop, why bother
		 */
		if ((c->processor_id & 0xff) <= 0x64)
			break;

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		/*
		 * Another rev is incremeting c0_count at a reduced clock
		 * rate while in WAIT mode.  So we basically have the choice
		 * between using the cp0 timer as clocksource or avoiding
		 * the WAIT instruction.  Until more details are known,
		 * disable the use of WAIT for 20Kc entirely.
		   cpu_wait = r4k_wait;
		 */
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		break;
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	case CPU_RM9000:
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		if ((c->processor_id & 0x00ff) >= 0x40)
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			cpu_wait = r4k_wait;
		break;
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	default:
		break;
	}
}

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static inline void check_errata(void)
{
	struct cpuinfo_mips *c = &current_cpu_data;

	switch (c->cputype) {
	case CPU_34K:
		/*
		 * Erratum "RPS May Cause Incorrect Instruction Execution"
		 * This code only handles VPE0, any SMP/SMTC/RTOS code
		 * making use of VPE1 will be responsable for that VPE.
		 */
		if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
			write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
		break;
	default:
		break;
	}
}

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void __init check_bugs32(void)
{
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	check_errata();
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}

/*
 * Probe whether cpu has config register by trying to play with
 * alternate cache bit and see whether it matters.
 * It's used by cpu_probe to distinguish between R3000A and R3081.
 */
static inline int cpu_has_confreg(void)
{
#ifdef CONFIG_CPU_R3000
	extern unsigned long r3k_cache_size(unsigned long);
	unsigned long size1, size2;
	unsigned long cfg = read_c0_conf();

	size1 = r3k_cache_size(ST0_ISC);
	write_c0_conf(cfg ^ R30XX_CONF_AC);
	size2 = r3k_cache_size(ST0_ISC);
	write_c0_conf(cfg);
	return size1 != size2;
#else
	return 0;
#endif
}

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static inline void set_elf_platform(int cpu, const char *plat)
{
	if (cpu == 0)
		__elf_platform = plat;
}

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/*
 * Get the FPU Implementation/Revision.
 */
static inline unsigned long cpu_get_fpu_id(void)
{
	unsigned long tmp, fpu_id;

	tmp = read_c0_status();
	__enable_fpu();
	fpu_id = read_32bit_cp1_register(CP1_REVISION);
	write_c0_status(tmp);
	return fpu_id;
}

/*
 * Check the CPU has an FPU the official way.
 */
static inline int __cpu_has_fpu(void)
{
	return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
}

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static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
{
#ifdef __NEED_VMBITS_PROBE
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	write_c0_entryhi(0x3fffffffffffe000ULL);
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	back_to_back_c0_hazard();
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	c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
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#endif
}

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#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
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		| MIPS_CPU_COUNTER)

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static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
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{
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_R2000:
		c->cputype = CPU_R2000;
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		__cpu_name[cpu] = "R2000";
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		c->isa_level = MIPS_CPU_ISA_I;
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		c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
		             MIPS_CPU_NOFPUEX;
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		if (__cpu_has_fpu())
			c->options |= MIPS_CPU_FPU;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R3000:
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		if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
			if (cpu_has_confreg()) {
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				c->cputype = CPU_R3081E;
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				__cpu_name[cpu] = "R3081";
			} else {
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				c->cputype = CPU_R3000A;
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				__cpu_name[cpu] = "R3000A";
			}
			break;
		} else {
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			c->cputype = CPU_R3000;
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			__cpu_name[cpu] = "R3000";
		}
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		c->isa_level = MIPS_CPU_ISA_I;
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		c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
		             MIPS_CPU_NOFPUEX;
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		if (__cpu_has_fpu())
			c->options |= MIPS_CPU_FPU;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R4000:
		if (read_c0_config() & CONF_SC) {
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			if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
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				c->cputype = CPU_R4400PC;
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				__cpu_name[cpu] = "R4400PC";
			} else {
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				c->cputype = CPU_R4000PC;
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				__cpu_name[cpu] = "R4000PC";
			}
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		} else {
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			if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
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				c->cputype = CPU_R4400SC;
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				__cpu_name[cpu] = "R4400SC";
			} else {
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				c->cputype = CPU_R4000SC;
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				__cpu_name[cpu] = "R4000SC";
			}
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		}

		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_VCE |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_VR41XX:
		switch (c->processor_id & 0xf0) {
		case PRID_REV_VR4111:
			c->cputype = CPU_VR4111;
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			__cpu_name[cpu] = "NEC VR4111";
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			break;
		case PRID_REV_VR4121:
			c->cputype = CPU_VR4121;
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			__cpu_name[cpu] = "NEC VR4121";
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			break;
		case PRID_REV_VR4122:
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			if ((c->processor_id & 0xf) < 0x3) {
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				c->cputype = CPU_VR4122;
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				__cpu_name[cpu] = "NEC VR4122";
			} else {
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				c->cputype = CPU_VR4181A;
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				__cpu_name[cpu] = "NEC VR4181A";
			}
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			break;
		case PRID_REV_VR4130:
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			if ((c->processor_id & 0xf) < 0x4) {
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				c->cputype = CPU_VR4131;
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				__cpu_name[cpu] = "NEC VR4131";
			} else {
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				c->cputype = CPU_VR4133;
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				__cpu_name[cpu] = "NEC VR4133";
			}
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			break;
		default:
			printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
			c->cputype = CPU_VR41XX;
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			__cpu_name[cpu] = "NEC Vr41xx";
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			break;
		}
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R4300:
		c->cputype = CPU_R4300;
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		__cpu_name[cpu] = "R4300";
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		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R4600:
		c->cputype = CPU_R4600;
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		__cpu_name[cpu] = "R4600";
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		c->isa_level = MIPS_CPU_ISA_III;
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		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_LLSC;
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		c->tlbsize = 48;
		break;
	#if 0
 	case PRID_IMP_R4650:
		/*
		 * This processor doesn't have an MMU, so it's not
		 * "real easy" to run Linux on it. It is left purely
		 * for documentation.  Commented out because it shares
		 * it's c0_prid id number with the TX3900.
		 */
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		c->cputype = CPU_R4650;
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		__cpu_name[cpu] = "R4650";
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	 	c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
	        c->tlbsize = 48;
		break;
	#endif
	case PRID_IMP_TX39:
		c->isa_level = MIPS_CPU_ISA_I;
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		c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
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		if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
			c->cputype = CPU_TX3927;
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			__cpu_name[cpu] = "TX3927";
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			c->tlbsize = 64;
		} else {
			switch (c->processor_id & 0xff) {
			case PRID_REV_TX3912:
				c->cputype = CPU_TX3912;
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				__cpu_name[cpu] = "TX3912";
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				c->tlbsize = 32;
				break;
			case PRID_REV_TX3922:
				c->cputype = CPU_TX3922;
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				__cpu_name[cpu] = "TX3922";
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				c->tlbsize = 64;
				break;
			}
		}
		break;
	case PRID_IMP_R4700:
		c->cputype = CPU_R4700;
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		__cpu_name[cpu] = "R4700";
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		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_TX49:
		c->cputype = CPU_TX49XX;
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		__cpu_name[cpu] = "R49XX";
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		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS | MIPS_CPU_LLSC;
		if (!(c->processor_id & 0x08))
			c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5000:
		c->cputype = CPU_R5000;
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		__cpu_name[cpu] = "R5000";
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		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5432:
		c->cputype = CPU_R5432;
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		__cpu_name[cpu] = "R5432";
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		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R5500:
		c->cputype = CPU_R5500;
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		__cpu_name[cpu] = "R5500";
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		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_WATCH | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_NEVADA:
		c->cputype = CPU_NEVADA;
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		__cpu_name[cpu] = "Nevada";
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		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
		c->tlbsize = 48;
		break;
	case PRID_IMP_R6000:
		c->cputype = CPU_R6000;
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		__cpu_name[cpu] = "R6000";
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		c->isa_level = MIPS_CPU_ISA_II;
		c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_R6000A:
		c->cputype = CPU_R6000A;
544
		__cpu_name[cpu] = "R6000A";
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		c->isa_level = MIPS_CPU_ISA_II;
		c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
		             MIPS_CPU_LLSC;
		c->tlbsize = 32;
		break;
	case PRID_IMP_RM7000:
		c->cputype = CPU_RM7000;
552
		__cpu_name[cpu] = "RM7000";
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		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		/*
		 * Undocumented RM7000:  Bit 29 in the info register of
		 * the RM7000 v2.0 indicates if the TLB has 48 or 64
		 * entries.
		 *
		 * 29      1 =>    64 entry JTLB
		 *         0 =>    48 entry JTLB
		 */
		c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
		break;
	case PRID_IMP_RM9000:
		c->cputype = CPU_RM9000;
568
		__cpu_name[cpu] = "RM9000";
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		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		/*
		 * Bit 29 in the info register of the RM9000
		 * indicates if the TLB has 48 or 64 entries.
		 *
		 * 29      1 =>    64 entry JTLB
		 *         0 =>    48 entry JTLB
		 */
		c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
		break;
	case PRID_IMP_R8000:
		c->cputype = CPU_R8000;
583
		__cpu_name[cpu] = "RM8000";
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		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
		             MIPS_CPU_LLSC;
		c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
		break;
	case PRID_IMP_R10000:
		c->cputype = CPU_R10000;
592
		__cpu_name[cpu] = "R10000";
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		c->isa_level = MIPS_CPU_ISA_IV;
594
		c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
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		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
		             MIPS_CPU_LLSC;
		c->tlbsize = 64;
		break;
	case PRID_IMP_R12000:
		c->cputype = CPU_R12000;
602
		__cpu_name[cpu] = "R12000";
L
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		c->isa_level = MIPS_CPU_ISA_IV;
604
		c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
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		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
		             MIPS_CPU_LLSC;
		c->tlbsize = 64;
		break;
K
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	case PRID_IMP_R14000:
		c->cputype = CPU_R14000;
612
		__cpu_name[cpu] = "R14000";
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613 614 615 616 617 618 619
		c->isa_level = MIPS_CPU_ISA_IV;
		c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
		             MIPS_CPU_FPU | MIPS_CPU_32FPR |
			     MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
		             MIPS_CPU_LLSC;
		c->tlbsize = 64;
		break;
620 621
	case PRID_IMP_LOONGSON2:
		c->cputype = CPU_LOONGSON2;
622
		__cpu_name[cpu] = "ICT Loongson-2";
623 624 625 626 627 628 629 630 631 632

		switch (c->processor_id & PRID_REV_MASK) {
		case PRID_REV_LOONGSON2E:
			set_elf_platform(cpu, "loongson2e");
			break;
		case PRID_REV_LOONGSON2F:
			set_elf_platform(cpu, "loongson2f");
			break;
		}

633 634 635 636 637 638
		c->isa_level = MIPS_CPU_ISA_III;
		c->options = R4K_OPTS |
			     MIPS_CPU_FPU | MIPS_CPU_LLSC |
			     MIPS_CPU_32FPR;
		c->tlbsize = 64;
		break;
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	}
}

642
static char unknown_isa[] __cpuinitdata = KERN_ERR \
643 644
	"Unsupported ISA type, c0.config0: %d.";

645
static inline unsigned int decode_config0(struct cpuinfo_mips *c)
L
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{
647 648
	unsigned int config0;
	int isa;
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650 651 652
	config0 = read_c0_config();

	if (((config0 & MIPS_CONF_MT) >> 7) == 1)
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		c->options |= MIPS_CPU_TLB;
654 655 656
	isa = (config0 & MIPS_CONF_AT) >> 13;
	switch (isa) {
	case 0:
657
		switch ((config0 & MIPS_CONF_AR) >> 10) {
658 659 660 661 662 663 664 665 666
		case 0:
			c->isa_level = MIPS_CPU_ISA_M32R1;
			break;
		case 1:
			c->isa_level = MIPS_CPU_ISA_M32R2;
			break;
		default:
			goto unknown;
		}
667 668
		break;
	case 2:
669
		switch ((config0 & MIPS_CONF_AR) >> 10) {
670 671 672 673 674 675 676 677 678
		case 0:
			c->isa_level = MIPS_CPU_ISA_M64R1;
			break;
		case 1:
			c->isa_level = MIPS_CPU_ISA_M64R2;
			break;
		default:
			goto unknown;
		}
679 680
		break;
	default:
681
		goto unknown;
682 683 684
	}

	return config0 & MIPS_CONF_M;
685 686 687

unknown:
	panic(unknown_isa, config0);
688 689 690 691 692
}

static inline unsigned int decode_config1(struct cpuinfo_mips *c)
{
	unsigned int config1;
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	config1 = read_c0_config1();
695 696 697 698

	if (config1 & MIPS_CONF1_MD)
		c->ases |= MIPS_ASE_MDMX;
	if (config1 & MIPS_CONF1_WR)
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		c->options |= MIPS_CPU_WATCH;
700 701 702
	if (config1 & MIPS_CONF1_CA)
		c->ases |= MIPS_ASE_MIPS16;
	if (config1 & MIPS_CONF1_EP)
L
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		c->options |= MIPS_CPU_EJTAG;
704
	if (config1 & MIPS_CONF1_FP) {
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		c->options |= MIPS_CPU_FPU;
		c->options |= MIPS_CPU_32FPR;
	}
708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733
	if (cpu_has_tlb)
		c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;

	return config1 & MIPS_CONF_M;
}

static inline unsigned int decode_config2(struct cpuinfo_mips *c)
{
	unsigned int config2;

	config2 = read_c0_config2();

	if (config2 & MIPS_CONF2_SL)
		c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;

	return config2 & MIPS_CONF_M;
}

static inline unsigned int decode_config3(struct cpuinfo_mips *c)
{
	unsigned int config3;

	config3 = read_c0_config3();

	if (config3 & MIPS_CONF3_SM)
		c->ases |= MIPS_ASE_SMARTMIPS;
734 735
	if (config3 & MIPS_CONF3_DSP)
		c->ases |= MIPS_ASE_DSP;
736 737 738 739 740
	if (config3 & MIPS_CONF3_VINT)
		c->options |= MIPS_CPU_VINT;
	if (config3 & MIPS_CONF3_VEIC)
		c->options |= MIPS_CPU_VEIC;
	if (config3 & MIPS_CONF3_MT)
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Ralf Baechle 已提交
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	        c->ases |= MIPS_ASE_MIPSMT;
742 743
	if (config3 & MIPS_CONF3_ULRI)
		c->options |= MIPS_CPU_ULRI;
744 745 746 747

	return config3 & MIPS_CONF_M;
}

748 749 750 751 752 753 754 755 756 757
static inline unsigned int decode_config4(struct cpuinfo_mips *c)
{
	unsigned int config4;

	config4 = read_c0_config4();

	if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
	    && cpu_has_tlb)
		c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;

758 759
	c->kscratch_mask = (config4 >> 16) & 0xff;

760 761 762
	return config4 & MIPS_CONF_M;
}

763
static void __cpuinit decode_configs(struct cpuinfo_mips *c)
764
{
765 766
	int ok;

767
	/* MIPS32 or MIPS64 compliant CPU.  */
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Ralf Baechle 已提交
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	c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
	             MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
770

L
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	c->scache.flags = MIPS_CACHE_NOT_PRESENT;

773 774 775 776 777 778 779 780
	ok = decode_config0(c);			/* Read Config registers.  */
	BUG_ON(!ok);				/* Arch spec violation!  */
	if (ok)
		ok = decode_config1(c);
	if (ok)
		ok = decode_config2(c);
	if (ok)
		ok = decode_config3(c);
781 782
	if (ok)
		ok = decode_config4(c);
783 784

	mips_probe_watch_registers(c);
785 786 787

	if (cpu_has_mips_r2)
		c->core = read_c0_ebase() & 0x3ff;
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}

790
static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
L
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791
{
792
	decode_configs(c);
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	switch (c->processor_id & 0xff00) {
	case PRID_IMP_4KC:
		c->cputype = CPU_4KC;
796
		__cpu_name[cpu] = "MIPS 4Kc";
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		break;
	case PRID_IMP_4KEC:
799 800
	case PRID_IMP_4KECR2:
		c->cputype = CPU_4KEC;
801
		__cpu_name[cpu] = "MIPS 4KEc";
802
		break;
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	case PRID_IMP_4KSC:
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	case PRID_IMP_4KSD:
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		c->cputype = CPU_4KSC;
806
		__cpu_name[cpu] = "MIPS 4KSc";
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		break;
	case PRID_IMP_5KC:
		c->cputype = CPU_5KC;
810
		__cpu_name[cpu] = "MIPS 5Kc";
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		break;
	case PRID_IMP_20KC:
		c->cputype = CPU_20KC;
814
		__cpu_name[cpu] = "MIPS 20Kc";
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815 816
		break;
	case PRID_IMP_24K:
817
	case PRID_IMP_24KE:
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818
		c->cputype = CPU_24K;
819
		__cpu_name[cpu] = "MIPS 24Kc";
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		break;
	case PRID_IMP_25KF:
		c->cputype = CPU_25KF;
823
		__cpu_name[cpu] = "MIPS 25Kc";
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824
		break;
R
Ralf Baechle 已提交
825 826
	case PRID_IMP_34K:
		c->cputype = CPU_34K;
827
		__cpu_name[cpu] = "MIPS 34Kc";
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828
		break;
829 830
	case PRID_IMP_74K:
		c->cputype = CPU_74K;
831
		__cpu_name[cpu] = "MIPS 74Kc";
832
		break;
833 834
	case PRID_IMP_1004K:
		c->cputype = CPU_1004K;
835
		__cpu_name[cpu] = "MIPS 1004Kc";
836
		break;
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837
	}
C
Chris Dearman 已提交
838 839

	spram_config();
L
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840 841
}

842
static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
L
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843
{
844
	decode_configs(c);
L
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845 846 847
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_AU1_REV1:
	case PRID_IMP_AU1_REV2:
848
		c->cputype = CPU_ALCHEMY;
L
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849 850
		switch ((c->processor_id >> 24) & 0xff) {
		case 0:
851
			__cpu_name[cpu] = "Au1000";
L
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852 853
			break;
		case 1:
854
			__cpu_name[cpu] = "Au1500";
L
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855 856
			break;
		case 2:
857
			__cpu_name[cpu] = "Au1100";
L
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858 859
			break;
		case 3:
860
			__cpu_name[cpu] = "Au1550";
L
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861
			break;
P
Pete Popov 已提交
862
		case 4:
863
			__cpu_name[cpu] = "Au1200";
864
			if ((c->processor_id & 0xff) == 2)
865
				__cpu_name[cpu] = "Au1250";
866 867
			break;
		case 5:
868
			__cpu_name[cpu] = "Au1210";
P
Pete Popov 已提交
869
			break;
L
Linus Torvalds 已提交
870
		default:
871
			__cpu_name[cpu] = "Au1xxx";
L
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872 873 874 875 876 877
			break;
		}
		break;
	}
}

878
static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
L
Linus Torvalds 已提交
879
{
880
	decode_configs(c);
R
Ralf Baechle 已提交
881

L
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882 883 884
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_SB1:
		c->cputype = CPU_SB1;
885
		__cpu_name[cpu] = "SiByte SB1";
L
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886
		/* FPU in pass1 is known to have issues. */
887
		if ((c->processor_id & 0xff) < 0x02)
888
			c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
L
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889
		break;
A
Andrew Isaacson 已提交
890 891
	case PRID_IMP_SB1A:
		c->cputype = CPU_SB1A;
892
		__cpu_name[cpu] = "SiByte SB1A";
A
Andrew Isaacson 已提交
893
		break;
L
Linus Torvalds 已提交
894 895 896
	}
}

897
static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
L
Linus Torvalds 已提交
898
{
899
	decode_configs(c);
L
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900 901 902
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_SR71000:
		c->cputype = CPU_SR71000;
903
		__cpu_name[cpu] = "Sandcraft SR71000";
L
Linus Torvalds 已提交
904 905 906 907 908 909
		c->scache.ways = 8;
		c->tlbsize = 64;
		break;
	}
}

910
static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
911 912 913 914 915
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_PR4450:
		c->cputype = CPU_PR4450;
916
		__cpu_name[cpu] = "Philips PR4450";
917
		c->isa_level = MIPS_CPU_ISA_M32R1;
918 919 920 921
		break;
	}
}

922
static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
923 924 925
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
926 927
	case PRID_IMP_BMIPS32_REV4:
	case PRID_IMP_BMIPS32_REV8:
928 929
		c->cputype = CPU_BMIPS32;
		__cpu_name[cpu] = "Broadcom BMIPS32";
930
		set_elf_platform(cpu, "bmips32");
931 932 933 934 935 936
		break;
	case PRID_IMP_BMIPS3300:
	case PRID_IMP_BMIPS3300_ALT:
	case PRID_IMP_BMIPS3300_BUG:
		c->cputype = CPU_BMIPS3300;
		__cpu_name[cpu] = "Broadcom BMIPS3300";
937
		set_elf_platform(cpu, "bmips3300");
938 939 940 941 942 943 944 945
		break;
	case PRID_IMP_BMIPS43XX: {
		int rev = c->processor_id & 0xff;

		if (rev >= PRID_REV_BMIPS4380_LO &&
				rev <= PRID_REV_BMIPS4380_HI) {
			c->cputype = CPU_BMIPS4380;
			__cpu_name[cpu] = "Broadcom BMIPS4380";
946
			set_elf_platform(cpu, "bmips4380");
947 948 949
		} else {
			c->cputype = CPU_BMIPS4350;
			__cpu_name[cpu] = "Broadcom BMIPS4350";
950
			set_elf_platform(cpu, "bmips4350");
951
		}
952
		break;
953 954 955 956
	}
	case PRID_IMP_BMIPS5000:
		c->cputype = CPU_BMIPS5000;
		__cpu_name[cpu] = "Broadcom BMIPS5000";
957
		set_elf_platform(cpu, "bmips5000");
958
		c->options |= MIPS_CPU_ULRI;
959
		break;
960 961 962
	}
}

963 964 965 966 967 968 969
static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
{
	decode_configs(c);
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_CAVIUM_CN38XX:
	case PRID_IMP_CAVIUM_CN31XX:
	case PRID_IMP_CAVIUM_CN30XX:
970 971 972
		c->cputype = CPU_CAVIUM_OCTEON;
		__cpu_name[cpu] = "Cavium Octeon";
		goto platform;
973 974 975 976
	case PRID_IMP_CAVIUM_CN58XX:
	case PRID_IMP_CAVIUM_CN56XX:
	case PRID_IMP_CAVIUM_CN50XX:
	case PRID_IMP_CAVIUM_CN52XX:
977 978 979
		c->cputype = CPU_CAVIUM_OCTEON_PLUS;
		__cpu_name[cpu] = "Cavium Octeon+";
platform:
980
		set_elf_platform(cpu, "octeon");
981
		break;
982 983 984
	case PRID_IMP_CAVIUM_CN63XX:
		c->cputype = CPU_CAVIUM_OCTEON2;
		__cpu_name[cpu] = "Cavium Octeon II";
985
		set_elf_platform(cpu, "octeon2");
986
		break;
987 988 989 990 991 992 993
	default:
		printk(KERN_INFO "Unknown Octeon chip!\n");
		c->cputype = CPU_UNKNOWN;
		break;
	}
}

994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009
static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
{
	decode_configs(c);
	/* JZRISC does not implement the CP0 counter. */
	c->options &= ~MIPS_CPU_COUNTER;
	switch (c->processor_id & 0xff00) {
	case PRID_IMP_JZRISC:
		c->cputype = CPU_JZRISC;
		__cpu_name[cpu] = "Ingenic JZRISC";
		break;
	default:
		panic("Unknown Ingenic Processor ID!");
		break;
	}
}

1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062
static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
{
	decode_configs(c);

	c->options = (MIPS_CPU_TLB       |
			MIPS_CPU_4KEX    |
			MIPS_CPU_COUNTER |
			MIPS_CPU_DIVEC   |
			MIPS_CPU_WATCH   |
			MIPS_CPU_EJTAG   |
			MIPS_CPU_LLSC);

	switch (c->processor_id & 0xff00) {
	case PRID_IMP_NETLOGIC_XLR732:
	case PRID_IMP_NETLOGIC_XLR716:
	case PRID_IMP_NETLOGIC_XLR532:
	case PRID_IMP_NETLOGIC_XLR308:
	case PRID_IMP_NETLOGIC_XLR532C:
	case PRID_IMP_NETLOGIC_XLR516C:
	case PRID_IMP_NETLOGIC_XLR508C:
	case PRID_IMP_NETLOGIC_XLR308C:
		c->cputype = CPU_XLR;
		__cpu_name[cpu] = "Netlogic XLR";
		break;

	case PRID_IMP_NETLOGIC_XLS608:
	case PRID_IMP_NETLOGIC_XLS408:
	case PRID_IMP_NETLOGIC_XLS404:
	case PRID_IMP_NETLOGIC_XLS208:
	case PRID_IMP_NETLOGIC_XLS204:
	case PRID_IMP_NETLOGIC_XLS108:
	case PRID_IMP_NETLOGIC_XLS104:
	case PRID_IMP_NETLOGIC_XLS616B:
	case PRID_IMP_NETLOGIC_XLS608B:
	case PRID_IMP_NETLOGIC_XLS416B:
	case PRID_IMP_NETLOGIC_XLS412B:
	case PRID_IMP_NETLOGIC_XLS408B:
	case PRID_IMP_NETLOGIC_XLS404B:
		c->cputype = CPU_XLR;
		__cpu_name[cpu] = "Netlogic XLS";
		break;

	default:
		printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n",
		       c->processor_id);
		c->cputype = CPU_XLR;
		break;
	}

	c->isa_level = MIPS_CPU_ISA_M64R1;
	c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
}

1063 1064 1065 1066 1067 1068
#ifdef CONFIG_64BIT
/* For use by uaccess.h */
u64 __ua_limit;
EXPORT_SYMBOL(__ua_limit);
#endif

1069
const char *__cpu_name[NR_CPUS];
1070
const char *__elf_platform;
1071

1072
__cpuinit void cpu_probe(void)
L
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1073 1074
{
	struct cpuinfo_mips *c = &current_cpu_data;
1075
	unsigned int cpu = smp_processor_id();
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	c->processor_id	= PRID_IMP_UNKNOWN;
	c->fpu_id	= FPIR_IMP_NONE;
	c->cputype	= CPU_UNKNOWN;

	c->processor_id = read_c0_prid();
	switch (c->processor_id & 0xff0000) {
	case PRID_COMP_LEGACY:
1084
		cpu_probe_legacy(c, cpu);
L
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		break;
	case PRID_COMP_MIPS:
1087
		cpu_probe_mips(c, cpu);
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		break;
	case PRID_COMP_ALCHEMY:
1090
		cpu_probe_alchemy(c, cpu);
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		break;
	case PRID_COMP_SIBYTE:
1093
		cpu_probe_sibyte(c, cpu);
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		break;
1095
	case PRID_COMP_BROADCOM:
1096
		cpu_probe_broadcom(c, cpu);
1097
		break;
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1098
	case PRID_COMP_SANDCRAFT:
1099
		cpu_probe_sandcraft(c, cpu);
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		break;
1101
	case PRID_COMP_NXP:
1102
		cpu_probe_nxp(c, cpu);
1103
		break;
1104 1105 1106
	case PRID_COMP_CAVIUM:
		cpu_probe_cavium(c, cpu);
		break;
1107 1108 1109
	case PRID_COMP_INGENIC:
		cpu_probe_ingenic(c, cpu);
		break;
1110 1111 1112
	case PRID_COMP_NETLOGIC:
		cpu_probe_netlogic(c, cpu);
		break;
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	}
1114

1115 1116 1117
	BUG_ON(!__cpu_name[cpu]);
	BUG_ON(c->cputype == CPU_UNKNOWN);

1118 1119 1120 1121 1122 1123 1124
	/*
	 * Platform code can force the cpu type to optimize code
	 * generation. In that case be sure the cpu type is correctly
	 * manually setup otherwise it could trigger some nasty bugs.
	 */
	BUG_ON(current_cpu_type() != c->cputype);

1125 1126 1127 1128 1129 1130
	if (mips_fpu_disabled)
		c->options &= ~MIPS_CPU_FPU;

	if (mips_dsp_disabled)
		c->ases &= ~MIPS_ASE_DSP;

1131
	if (c->options & MIPS_CPU_FPU) {
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		c->fpu_id = cpu_get_fpu_id();
1133

1134
		if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1135 1136 1137
		    c->isa_level == MIPS_CPU_ISA_M32R2 ||
		    c->isa_level == MIPS_CPU_ISA_M64R1 ||
		    c->isa_level == MIPS_CPU_ISA_M64R2) {
1138 1139 1140 1141
			if (c->fpu_id & MIPS_FPIR_3D)
				c->ases |= MIPS_ASE_MIPS3D;
		}
	}
1142

R
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1143 1144 1145 1146
	if (cpu_has_mips_r2)
		c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
	else
		c->srsets = 1;
1147 1148

	cpu_probe_vmbits(c);
1149 1150 1151 1152 1153

#ifdef CONFIG_64BIT
	if (cpu == 0)
		__ua_limit = ~((1ull << cpu_vmbits) - 1);
#endif
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}

1156
__cpuinit void cpu_report(void)
L
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{
	struct cpuinfo_mips *c = &current_cpu_data;

1160 1161
	printk(KERN_INFO "CPU revision is: %08x (%s)\n",
	       c->processor_id, cpu_name_string());
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	if (c->options & MIPS_CPU_FPU)
1163
		printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
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}