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b4672d37
编写于
12月 08, 2005
作者:
R
Ralf Baechle
提交者:
1月 10, 2006
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电子邮件补丁
差异文件
MIPS: Introduce machinery for testing for MIPSxxR1/2.
Signed-off-by:
N
Ralf Baechle
<
ralf@linux-mips.org
>
上级
e7958bb9
变更
11
隐藏空白更改
内联
并排
Showing
11 changed file
with
95 addition
and
9 deletion
+95
-9
arch/mips/kernel/cpu-probe.c
arch/mips/kernel/cpu-probe.c
+30
-5
arch/mips/kernel/time.c
arch/mips/kernel/time.c
+3
-3
include/asm-mips/cpu-features.h
include/asm-mips/cpu-features.h
+24
-0
include/asm-mips/cpu.h
include/asm-mips/cpu.h
+3
-1
include/asm-mips/mach-ip22/cpu-feature-overrides.h
include/asm-mips/mach-ip22/cpu-feature-overrides.h
+5
-0
include/asm-mips/mach-ip27/cpu-feature-overrides.h
include/asm-mips/mach-ip27/cpu-feature-overrides.h
+5
-0
include/asm-mips/mach-ip32/cpu-feature-overrides.h
include/asm-mips/mach-ip32/cpu-feature-overrides.h
+5
-0
include/asm-mips/mach-ja/cpu-feature-overrides.h
include/asm-mips/mach-ja/cpu-feature-overrides.h
+5
-0
include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
+5
-0
include/asm-mips/mach-rm200/cpu-feature-overrides.h
include/asm-mips/mach-rm200/cpu-feature-overrides.h
+5
-0
include/asm-mips/mach-yosemite/cpu-feature-overrides.h
include/asm-mips/mach-yosemite/cpu-feature-overrides.h
+5
-0
未找到文件。
arch/mips/kernel/cpu-probe.c
浏览文件 @
b4672d37
...
...
@@ -435,6 +435,9 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
}
}
static
char
unknown_isa
[]
__initdata
=
KERN_ERR
\
"Unsupported ISA type, c0.config0: %d."
;
static
inline
unsigned
int
decode_config0
(
struct
cpuinfo_mips
*
c
)
{
unsigned
int
config0
;
...
...
@@ -447,16 +450,37 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
isa
=
(
config0
&
MIPS_CONF_AT
)
>>
13
;
switch
(
isa
)
{
case
0
:
c
->
isa_level
=
MIPS_CPU_ISA_M32R1
;
switch
((
config0
>>
10
)
&
7
)
{
case
0
:
c
->
isa_level
=
MIPS_CPU_ISA_M32R1
;
break
;
case
1
:
c
->
isa_level
=
MIPS_CPU_ISA_M32R2
;
break
;
default:
goto
unknown
;
}
break
;
case
2
:
c
->
isa_level
=
MIPS_CPU_ISA_M64R1
;
switch
((
config0
>>
10
)
&
7
)
{
case
0
:
c
->
isa_level
=
MIPS_CPU_ISA_M64R1
;
break
;
case
1
:
c
->
isa_level
=
MIPS_CPU_ISA_M64R2
;
break
;
default:
goto
unknown
;
}
break
;
default:
panic
(
"Unsupported ISA type, cp0.config0.at: %d."
,
isa
)
;
goto
unknown
;
}
return
config0
&
MIPS_CONF_M
;
unknown:
panic
(
unknown_isa
,
config0
);
}
static
inline
unsigned
int
decode_config1
(
struct
cpuinfo_mips
*
c
)
...
...
@@ -568,7 +592,6 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
break
;
case
PRID_IMP_34K
:
c
->
cputype
=
CPU_34K
;
c
->
isa_level
=
MIPS_CPU_ISA_M32R1
;
break
;
}
}
...
...
@@ -691,7 +714,9 @@ __init void cpu_probe(void)
c
->
fpu_id
=
cpu_get_fpu_id
();
if
(
c
->
isa_level
==
MIPS_CPU_ISA_M32R1
||
c
->
isa_level
==
MIPS_CPU_ISA_M64R1
)
{
c
->
isa_level
==
MIPS_CPU_ISA_M32R2
||
c
->
isa_level
==
MIPS_CPU_ISA_M64R1
||
c
->
isa_level
==
MIPS_CPU_ISA_M64R2
)
{
if
(
c
->
fpu_id
&
MIPS_FPIR_3D
)
c
->
ases
|=
MIPS_ASE_MIPS3D
;
}
...
...
arch/mips/kernel/time.c
浏览文件 @
b4672d37
...
...
@@ -628,9 +628,9 @@ void __init time_init(void)
mips_hpt_init
=
c0_hpt_init
;
}
if
(
(
current_cpu_data
.
isa_level
==
MIPS_CPU_ISA_M32R1
)
||
(
current_cpu_data
.
isa_level
==
MIPS_CPU_ISA_I
)
||
(
current_cpu_data
.
isa_level
==
MIPS_CPU_ISA_II
))
if
(
cpu_has_mips32r1
||
cpu_has_mips32r2
||
(
current_cpu_data
.
isa_level
==
MIPS_CPU_ISA_I
)
||
(
current_cpu_data
.
isa_level
==
MIPS_CPU_ISA_II
))
/*
* We need to calibrate the counter but we don't have
* 64-bit division.
...
...
include/asm-mips/cpu-features.h
浏览文件 @
b4672d37
...
...
@@ -144,6 +144,18 @@
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses 0
# endif
# ifndef cpu_has_mips32r1
# define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
# endif
# ifndef cpu_has_mips32r2
# define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
# endif
# ifndef cpu_has_mips64r1
# define cpu_has_mips64r1 0
# endif
# ifndef cpu_has_mips64r2
# define cpu_has_mips64r2 0
# endif
#endif
#ifdef CONFIG_64BIT
...
...
@@ -162,6 +174,18 @@
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses 1
# endif
# ifndef cpu_has_mips32r1
# define cpu_has_mips32r1 0
# endif
# ifndef cpu_has_mips32r2
# define cpu_has_mips32r2 0
# endif
# ifndef cpu_has_mips64r1
# define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
# endif
# ifndef cpu_has_mips64r2
# define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
# endif
#endif
#ifdef CONFIG_CPU_MIPSR2
...
...
include/asm-mips/cpu.h
浏览文件 @
b4672d37
...
...
@@ -210,7 +210,9 @@
#define MIPS_CPU_ISA_IV (0x00000004 | MIPS_CPU_ISA_64BIT)
#define MIPS_CPU_ISA_V (0x00000005 | MIPS_CPU_ISA_64BIT)
#define MIPS_CPU_ISA_M32R1 0x00000020
#define MIPS_CPU_ISA_M64R1 (0x00000040 | MIPS_CPU_ISA_64BIT)
#define MIPS_CPU_ISA_M32R2 0x00000040
#define MIPS_CPU_ISA_M64R1 (0x00000080 | MIPS_CPU_ISA_64BIT)
#define MIPS_CPU_ISA_M64R2 (0x00000100 | MIPS_CPU_ISA_64BIT)
/*
* CPU Option encodings
...
...
include/asm-mips/mach-ip22/cpu-feature-overrides.h
浏览文件 @
b4672d37
...
...
@@ -34,4 +34,9 @@
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif
/* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */
include/asm-mips/mach-ip27/cpu-feature-overrides.h
浏览文件 @
b4672d37
...
...
@@ -37,4 +37,9 @@
#define cpu_icache_line_size() 64
#define cpu_scache_line_size() 128
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif
/* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
include/asm-mips/mach-ip32/cpu-feature-overrides.h
浏览文件 @
b4672d37
...
...
@@ -39,4 +39,9 @@
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif
/* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
include/asm-mips/mach-ja/cpu-feature-overrides.h
浏览文件 @
b4672d37
...
...
@@ -37,4 +37,9 @@
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 32
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif
/* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
include/asm-mips/mach-ocelot3/cpu-feature-overrides.h
浏览文件 @
b4672d37
...
...
@@ -40,4 +40,9 @@
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 32
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif
/* __ASM_MACH_JA_CPU_FEATURE_OVERRIDES_H */
include/asm-mips/mach-rm200/cpu-feature-overrides.h
浏览文件 @
b4672d37
...
...
@@ -40,4 +40,9 @@
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 0
/* No S-cache on R5000 I think ... */
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif
/* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
include/asm-mips/mach-yosemite/cpu-feature-overrides.h
浏览文件 @
b4672d37
...
...
@@ -37,4 +37,9 @@
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 32
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
#define cpu_has_mips64r1 0
#define cpu_has_mips64r2 0
#endif
/* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
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