sky2.c 90.5 KB
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/*
 * New driver for Marvell Yukon 2 chipset.
 * Based on earlier sk98lin, and skge driver.
 *
 * This driver intentionally does not support all the features
 * of the original driver such as link fail-over and link management because
 * those should be done at higher levels.
 *
 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/config.h>
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#include <linux/crc32.h>
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#include <linux/kernel.h>
#include <linux/version.h>
#include <linux/module.h>
#include <linux/netdevice.h>
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#include <linux/dma-mapping.h>
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#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/pci.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/in.h>
#include <linux/delay.h>
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#include <linux/workqueue.h>
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#include <linux/if_vlan.h>
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#include <linux/prefetch.h>
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#include <linux/mii.h>
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#include <asm/irq.h>

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#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
#define SKY2_VLAN_TAG_USED 1
#endif

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#include "sky2.h"

#define DRV_NAME		"sky2"
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#define DRV_VERSION		"1.2"
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#define PFX			DRV_NAME " "

/*
 * The Yukon II chipset takes 64 bit command blocks (called list elements)
 * that are organized into three (receive, transmit, status) different rings
 * similar to Tigon3. A transmit can require several elements;
 * a receive requires one (or two if using 64 bit dma).
 */

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#define RX_LE_SIZE	    	512
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#define RX_LE_BYTES		(RX_LE_SIZE*sizeof(struct sky2_rx_le))
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#define RX_MAX_PENDING		(RX_LE_SIZE/2 - 2)
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#define RX_DEF_PENDING		RX_MAX_PENDING
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#define RX_SKB_ALIGN		8
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#define TX_RING_SIZE		512
#define TX_DEF_PENDING		(TX_RING_SIZE - 1)
#define TX_MIN_PENDING		64
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#define MAX_SKB_TX_LE		(4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
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#define STATUS_RING_SIZE	2048	/* 2 ports * (TX + 2*RX) */
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#define STATUS_LE_BYTES		(STATUS_RING_SIZE*sizeof(struct sky2_status_le))
#define ETH_JUMBO_MTU		9000
#define TX_WATCHDOG		(5 * HZ)
#define NAPI_WEIGHT		64
#define PHY_RETRIES		1000

static const u32 default_msg =
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    NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
    | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
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    | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
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static int debug = -1;		/* defaults above */
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module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

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static int copybreak __read_mostly = 256;
module_param(copybreak, int, 0);
MODULE_PARM_DESC(copybreak, "Receive copy threshold");

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static int disable_msi = 0;
module_param(disable_msi, int, 0);
MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");

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static const struct pci_device_id sky2_id_table[] = {
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	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
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	{ PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
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	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
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	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
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	{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
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	{ 0 }
};
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MODULE_DEVICE_TABLE(pci, sky2_id_table);

/* Avoid conditionals by using array */
static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
static const unsigned rxqaddr[] = { Q_R1, Q_R2 };

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/* This driver supports yukon2 chipset only */
static const char *yukon2_name[] = {
	"XL",		/* 0xb3 */
	"EC Ultra", 	/* 0xb4 */
	"UNKNOWN",	/* 0xb5 */
	"EC",		/* 0xb6 */
	"FE",		/* 0xb7 */
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};

/* Access to external PHY */
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static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
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{
	int i;

	gma_write16(hw, port, GM_SMI_DATA, val);
	gma_write16(hw, port, GM_SMI_CTRL,
		    GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));

	for (i = 0; i < PHY_RETRIES; i++) {
		if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
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			return 0;
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		udelay(1);
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	}
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	printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
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	return -ETIMEDOUT;
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}

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static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
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{
	int i;

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	gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
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		    | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);

	for (i = 0; i < PHY_RETRIES; i++) {
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		if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
			*val = gma_read16(hw, port, GM_SMI_DATA);
			return 0;
		}

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		udelay(1);
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	}

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	return -ETIMEDOUT;
}

static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
{
	u16 v;

	if (__gm_phy_read(hw, port, reg, &v) != 0)
		printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
	return v;
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}

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static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
{
	u16 power_control;
	u32 reg1;
	int vaux;
	int ret = 0;

	pr_debug("sky2_set_power_state %d\n", state);
	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);

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	power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
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	vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
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		(power_control & PCI_PM_CAP_PME_D3cold);

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	power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
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	power_control |= PCI_PM_CTRL_PME_STATUS;
	power_control &= ~(PCI_PM_CTRL_STATE_MASK);

	switch (state) {
	case PCI_D0:
		/* switch power to VCC (WA for VAUX problem) */
		sky2_write8(hw, B0_POWER_CTRL,
			    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);

		/* disable Core Clock Division, */
		sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);

		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
			/* enable bits are inverted */
			sky2_write8(hw, B2_Y2_CLK_GATE,
				    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
				    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
				    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
		else
			sky2_write8(hw, B2_Y2_CLK_GATE, 0);

		/* Turn off phy power saving */
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		reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
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		reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);

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		/* looks like this XL is back asswards .. */
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		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
			reg1 |= PCI_Y2_PHY1_COMA;
			if (hw->ports > 1)
				reg1 |= PCI_Y2_PHY2_COMA;
		}
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		if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
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			sky2_pci_write32(hw, PCI_DEV_REG3, 0);
			reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
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			reg1 &= P_ASPM_CONTROL_MSK;
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			sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
			sky2_pci_write32(hw, PCI_DEV_REG5, 0);
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		}

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		sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
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		break;

	case PCI_D3hot:
	case PCI_D3cold:
		/* Turn on phy power saving */
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		reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
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		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
			reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
		else
			reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
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		sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
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		if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
			sky2_write8(hw, B2_Y2_CLK_GATE, 0);
		else
			/* enable bits are inverted */
			sky2_write8(hw, B2_Y2_CLK_GATE,
				    Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
				    Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
				    Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);

		/* switch power to VAUX */
		if (vaux && state != PCI_D3cold)
			sky2_write8(hw, B0_POWER_CTRL,
				    (PC_VAUX_ENA | PC_VCC_ENA |
				     PC_VAUX_ON | PC_VCC_OFF));
		break;
	default:
		printk(KERN_ERR PFX "Unknown power state %d\n", state);
		ret = -1;
	}

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	sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
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	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
	return ret;
}

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static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
{
	u16 reg;

	/* disable all GMAC IRQ's */
	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
	/* disable PHY IRQs */
	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
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	gma_write16(hw, port, GM_MC_ADDR_H1, 0);	/* clear MC hash */
	gma_write16(hw, port, GM_MC_ADDR_H2, 0);
	gma_write16(hw, port, GM_MC_ADDR_H3, 0);
	gma_write16(hw, port, GM_MC_ADDR_H4, 0);

	reg = gma_read16(hw, port, GM_RX_CTRL);
	reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
	gma_write16(hw, port, GM_RX_CTRL, reg);
}

static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
{
	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
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	u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
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	if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
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		u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);

		ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
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			   PHY_M_EC_MAC_S_MSK);
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		ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);

		if (hw->chip_id == CHIP_ID_YUKON_EC)
			ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
		else
			ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);

		gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
	}

	ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
	if (hw->copper) {
		if (hw->chip_id == CHIP_ID_YUKON_FE) {
			/* enable automatic crossover */
			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
		} else {
			/* disable energy detect */
			ctrl &= ~PHY_M_PC_EN_DET_MSK;

			/* enable automatic crossover */
			ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);

			if (sky2->autoneg == AUTONEG_ENABLE &&
			    hw->chip_id == CHIP_ID_YUKON_XL) {
				ctrl &= ~PHY_M_PC_DSC_MSK;
				ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
			}
		}
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
	} else {
		/* workaround for deviation #4.88 (CRC errors) */
		/* disable Automatic Crossover */

		ctrl &= ~PHY_M_PC_MDIX_MSK;
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

		if (hw->chip_id == CHIP_ID_YUKON_XL) {
			/* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
			gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
			ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
			ctrl &= ~PHY_M_MAC_MD_MSK;
			ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
			gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);

			/* select page 1 to access Fiber registers */
			gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
		}
	}

	ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
	if (sky2->autoneg == AUTONEG_DISABLE)
		ctrl &= ~PHY_CT_ANE;
	else
		ctrl |= PHY_CT_ANE;

	ctrl |= PHY_CT_RESET;
	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

	ctrl = 0;
	ct1000 = 0;
	adv = PHY_AN_CSMA;

	if (sky2->autoneg == AUTONEG_ENABLE) {
		if (hw->copper) {
			if (sky2->advertising & ADVERTISED_1000baseT_Full)
				ct1000 |= PHY_M_1000C_AFD;
			if (sky2->advertising & ADVERTISED_1000baseT_Half)
				ct1000 |= PHY_M_1000C_AHD;
			if (sky2->advertising & ADVERTISED_100baseT_Full)
				adv |= PHY_M_AN_100_FD;
			if (sky2->advertising & ADVERTISED_100baseT_Half)
				adv |= PHY_M_AN_100_HD;
			if (sky2->advertising & ADVERTISED_10baseT_Full)
				adv |= PHY_M_AN_10_FD;
			if (sky2->advertising & ADVERTISED_10baseT_Half)
				adv |= PHY_M_AN_10_HD;
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		} else		/* special defines for FIBER (88E1011S only) */
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			adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;

		/* Set Flow-control capabilities */
		if (sky2->tx_pause && sky2->rx_pause)
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			adv |= PHY_AN_PAUSE_CAP;	/* symmetric */
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		else if (sky2->rx_pause && !sky2->tx_pause)
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			adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
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		else if (!sky2->rx_pause && sky2->tx_pause)
			adv |= PHY_AN_PAUSE_ASYM;	/* local */

		/* Restart Auto-negotiation */
		ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
	} else {
		/* forced speed/duplex settings */
		ct1000 = PHY_M_1000C_MSE;

		if (sky2->duplex == DUPLEX_FULL)
			ctrl |= PHY_CT_DUP_MD;

		switch (sky2->speed) {
		case SPEED_1000:
			ctrl |= PHY_CT_SP1000;
			break;
		case SPEED_100:
			ctrl |= PHY_CT_SP100;
			break;
		}

		ctrl |= PHY_CT_RESET;
	}

	if (hw->chip_id != CHIP_ID_YUKON_FE)
		gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);

	gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
	gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);

	/* Setup Phy LED's */
	ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
	ledover = 0;

	switch (hw->chip_id) {
	case CHIP_ID_YUKON_FE:
		/* on 88E3082 these bits are at 11..9 (shifted left) */
		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;

		ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);

		/* delete ACT LED control bits */
		ctrl &= ~PHY_M_FELP_LED1_MSK;
		/* change ACT LED control to blink mode */
		ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
		gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
		break;

	case CHIP_ID_YUKON_XL:
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		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
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		/* select page 3 to access LED control register */
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);

		/* set LED Function Control register */
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		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) |	/* LINK/ACT */
							   PHY_M_LEDC_INIT_CTRL(7) |	/* 10 Mbps */
							   PHY_M_LEDC_STA1_CTRL(7) |	/* 100 Mbps */
							   PHY_M_LEDC_STA0_CTRL(7)));	/* 1000 Mbps */
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		/* set Polarity Control register */
		gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
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			     (PHY_M_POLC_LS1_P_MIX(4) |
			      PHY_M_POLC_IS0_P_MIX(4) |
			      PHY_M_POLC_LOS_CTRL(2) |
			      PHY_M_POLC_INIT_CTRL(2) |
			      PHY_M_POLC_STA1_CTRL(2) |
			      PHY_M_POLC_STA0_CTRL(2)));
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		/* restore page register */
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		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
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		break;

	default:
		/* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
		ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
		/* turn off the Rx LED (LED_RX) */
		ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
	}

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	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
		/* apply fixes in PHY AFE */
		gm_phy_write(hw, port, 22, 255);
		/* increase differential signal amplitude in 10BASE-T */
		gm_phy_write(hw, port, 24, 0xaa99);
		gm_phy_write(hw, port, 23, 0x2011);
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		/* fix for IEEE A/B Symmetry failure in 1000BASE-T */
		gm_phy_write(hw, port, 24, 0xa204);
		gm_phy_write(hw, port, 23, 0x2002);

		/* set page register to 0 */
		gm_phy_write(hw, port, 22, 0);
	} else {
		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
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		if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
			/* turn on 100 Mbps LED (LED_LINK100) */
			ledover |= PHY_M_LED_MO_100(MO_LED_ON);
		}
490

491 492 493 494
		if (ledover)
			gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);

	}
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	/* Enable phy interrupt on auto-negotiation complete (or link up) */
496 497 498 499 500 501
	if (sky2->autoneg == AUTONEG_ENABLE)
		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
	else
		gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
}

502 503 504
/* Force a renegotiation */
static void sky2_phy_reinit(struct sky2_port *sky2)
{
505
	spin_lock_bh(&sky2->phy_lock);
506
	sky2_phy_init(sky2->hw, sky2->port);
507
	spin_unlock_bh(&sky2->phy_lock);
508 509
}

510 511 512 513 514 515 516
static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
{
	struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
	u16 reg;
	int i;
	const u8 *addr = hw->dev[port]->dev_addr;

517 518
	sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
	sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
519 520 521

	sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);

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522
	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541
		/* WA DEV_472 -- looks like crossed wires on port 2 */
		/* clear GMAC 1 Control reset */
		sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
		do {
			sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
			sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
		} while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
			 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
			 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
	}

	if (sky2->autoneg == AUTONEG_DISABLE) {
		reg = gma_read16(hw, port, GM_GP_CTRL);
		reg |= GM_GPCR_AU_ALL_DIS;
		gma_write16(hw, port, GM_GP_CTRL, reg);
		gma_read16(hw, port, GM_GP_CTRL);

		switch (sky2->speed) {
		case SPEED_1000:
542
			reg &= ~GM_GPCR_SPEED_100;
543
			reg |= GM_GPCR_SPEED_1000;
544
			break;
545
		case SPEED_100:
546
			reg &= ~GM_GPCR_SPEED_1000;
547
			reg |= GM_GPCR_SPEED_100;
548 549 550 551
			break;
		case SPEED_10:
			reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
			break;
552 553 554 555 556 557 558 559 560
		}

		if (sky2->duplex == DUPLEX_FULL)
			reg |= GM_GPCR_DUP_FULL;
	} else
		reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;

	if (!sky2->tx_pause && !sky2->rx_pause) {
		sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
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		reg |=
		    GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
	} else if (sky2->tx_pause && !sky2->rx_pause) {
564 565 566 567 568 569
		/* disable Rx flow-control */
		reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
	}

	gma_write16(hw, port, GM_GP_CTRL, reg);

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570
	sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
571

572
	spin_lock_bh(&sky2->phy_lock);
573
	sky2_phy_init(hw, port);
574
	spin_unlock_bh(&sky2->phy_lock);
575 576 577 578 579

	/* MIB clear */
	reg = gma_read16(hw, port, GM_PHY_ADDR);
	gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);

580 581
	for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
		gma_read16(hw, port, i);
582 583 584 585 586 587 588
	gma_write16(hw, port, GM_PHY_ADDR, reg);

	/* transmit control */
	gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));

	/* receive control reg: unicast + multicast + no FCS  */
	gma_write16(hw, port, GM_RX_CTRL,
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589
		    GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
590 591 592 593 594 595 596 597 598 599 600 601 602

	/* transmit flow control */
	gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);

	/* transmit parameter */
	gma_write16(hw, port, GM_TX_PARAM,
		    TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
		    TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
		    TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
		    TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));

	/* serial mode register */
	reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
603
		GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
604

605
	if (hw->dev[port]->mtu > ETH_DATA_LEN)
606 607 608 609 610 611 612
		reg |= GM_SMOD_JUMBO_ENA;

	gma_write16(hw, port, GM_SERIAL_MODE, reg);

	/* virtual address for data */
	gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);

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613 614 615 616
	/* physical address: used for pause frames */
	gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);

	/* ignore counter overflows */
617 618 619 620 621 622
	gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
	gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
	gma_write16(hw, port, GM_TR_IRQ_MSK, 0);

	/* Configure Rx MAC FIFO */
	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
623 624
	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
		     GMF_OPER_ON | GMF_RX_F_FL_ON);
625

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	/* Flush Rx MAC FIFO on any flow control or error */
627
	sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
628

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629 630
	/* Set threshold to 0xa (64 bytes)
	 *  ASF disabled so no need to do WA dev #4.30
631 632 633 634 635 636
	 */
	sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);

	/* Configure Tx MAC FIFO */
	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
	sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
637 638 639 640 641 642 643 644 645 646 647 648

	if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
		sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
		sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
		if (hw->dev[port]->mtu > ETH_DATA_LEN) {
			/* set Tx GMAC FIFO Almost Empty Threshold */
			sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
			/* Disable Store & Forward mode for TX */
			sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
		}
	}

649 650
}

651 652 653 654 655
/* Assign Ram Buffer allocation.
 * start and end are in units of 4k bytes
 * ram registers are in units of 64bit words
 */
static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
656
{
657
	u32 start, end;
658

659 660
	start = startk * 4096/8;
	end = (endk * 4096/8) - 1;
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661

662 663 664 665 666 667 668
	sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
	sky2_write32(hw, RB_ADDR(q, RB_START), start);
	sky2_write32(hw, RB_ADDR(q, RB_END), end);
	sky2_write32(hw, RB_ADDR(q, RB_WP), start);
	sky2_write32(hw, RB_ADDR(q, RB_RP), start);

	if (q == Q_R1 || q == Q_R2) {
669 670
		u32 space = (endk - startk) * 4096/8;
		u32 tp = space - space/4;
S
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671

672 673 674 675 676 677
		/* On receive queue's set the thresholds
		 * give receiver priority when > 3/4 full
		 * send pause when down to 2K
		 */
		sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
		sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
S
Stephen Hemminger 已提交
678

679 680 681
		tp = space - 2048/8;
		sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
		sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
682 683 684 685 686 687 688 689
	} else {
		/* Enable store & forward on Tx queue's because
		 * Tx FIFO is only 1K on Yukon
		 */
		sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
	}

	sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
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Stephen Hemminger 已提交
690
	sky2_read8(hw, RB_ADDR(q, RB_CTRL));
691 692 693
}

/* Setup Bus Memory Interface */
694
static void sky2_qset(struct sky2_hw *hw, u16 q)
695 696 697 698
{
	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
	sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
699
	sky2_write32(hw, Q_ADDR(q, Q_WM),  BMU_WM_DEFAULT);
700 701 702 703 704
}

/* Setup prefetch unit registers. This is the interface between
 * hardware and driver list elements
 */
705
static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
706 707 708 709 710 711 712 713
				      u64 addr, u32 last)
{
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
	sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
	sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
S
Stephen Hemminger 已提交
714 715

	sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
716 717
}

S
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718 719 720 721 722 723 724
static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
{
	struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;

	sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
	return le;
}
725

726 727
/* Update chip's next pointer */
static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
728
{
729
	wmb();
730
	sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
731
	mmiowb();
732 733
}

S
Stephen Hemminger 已提交
734

735 736 737 738 739 740 741
static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
{
	struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
	sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
	return le;
}

742 743 744
/* Return high part of DMA address (could be 32 or 64 bit) */
static inline u32 high32(dma_addr_t a)
{
745
	return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
746 747
}

S
Stephen Hemminger 已提交
748
/* Build description to hardware about buffer */
749
static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
750 751
{
	struct sky2_rx_le *le;
752 753
	u32 hi = high32(map);
	u16 len = sky2->rx_bufsize;
754

S
Stephen Hemminger 已提交
755
	if (sky2->rx_addr64 != hi) {
756
		le = sky2_next_rx(sky2);
S
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757
		le->addr = cpu_to_le32(hi);
758 759
		le->ctrl = 0;
		le->opcode = OP_ADDR64 | HW_OWNER;
760
		sky2->rx_addr64 = high32(map + len);
761
	}
S
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762

763
	le = sky2_next_rx(sky2);
764 765
	le->addr = cpu_to_le32((u32) map);
	le->length = cpu_to_le16(len);
766 767 768 769
	le->ctrl = 0;
	le->opcode = OP_PACKET | HW_OWNER;
}

S
Stephen Hemminger 已提交
770

771 772 773 774
/* Tell chip where to start receive checksum.
 * Actually has two checksums, but set both same to avoid possible byte
 * order problems.
 */
S
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775
static void rx_set_checksum(struct sky2_port *sky2)
776 777 778 779
{
	struct sky2_rx_le *le;

	le = sky2_next_rx(sky2);
S
Stephen Hemminger 已提交
780
	le->addr = (ETH_HLEN << 16) | ETH_HLEN;
781 782
	le->ctrl = 0;
	le->opcode = OP_TCPSTART | HW_OWNER;
S
Stephen Hemminger 已提交
783 784 785 786

	sky2_write32(sky2->hw,
		     Q_ADDR(rxqaddr[sky2->port], Q_CSR),
		     sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
787 788 789

}

790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821
/*
 * The RX Stop command will not work for Yukon-2 if the BMU does not
 * reach the end of packet and since we can't make sure that we have
 * incoming data, we must reset the BMU while it is not doing a DMA
 * transfer. Since it is possible that the RX path is still active,
 * the RX RAM buffer will be stopped first, so any possible incoming
 * data will not trigger a DMA. After the RAM buffer is stopped, the
 * BMU is polled until any DMA in progress is ended and only then it
 * will be reset.
 */
static void sky2_rx_stop(struct sky2_port *sky2)
{
	struct sky2_hw *hw = sky2->hw;
	unsigned rxq = rxqaddr[sky2->port];
	int i;

	/* disable the RAM Buffer receive queue */
	sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);

	for (i = 0; i < 0xffff; i++)
		if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
		    == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
			goto stopped;

	printk(KERN_WARNING PFX "%s: receiver stop failed\n",
	       sky2->netdev->name);
stopped:
	sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);

	/* reset the Rx prefetch unit */
	sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
}
S
Stephen Hemminger 已提交
822

S
shemminger@osdl.org 已提交
823
/* Clean out receive buffer area, assumes receiver hardware stopped */
824 825 826 827 828
static void sky2_rx_clean(struct sky2_port *sky2)
{
	unsigned i;

	memset(sky2->rx_le, 0, RX_LE_BYTES);
S
Stephen Hemminger 已提交
829
	for (i = 0; i < sky2->rx_pending; i++) {
830 831 832
		struct ring_info *re = sky2->rx_ring + i;

		if (re->skb) {
S
Stephen Hemminger 已提交
833
			pci_unmap_single(sky2->hw->pdev,
834
					 re->mapaddr, sky2->rx_bufsize,
835 836 837 838 839 840 841
					 PCI_DMA_FROMDEVICE);
			kfree_skb(re->skb);
			re->skb = NULL;
		}
	}
}

842 843 844 845 846 847 848 849 850 851 852
/* Basic MII support */
static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
	struct mii_ioctl_data *data = if_mii(ifr);
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	int err = -EOPNOTSUPP;

	if (!netif_running(dev))
		return -ENODEV;	/* Phy still in reset */

853
	switch (cmd) {
854 855 856 857 858 859
	case SIOCGMIIPHY:
		data->phy_id = PHY_ADDR_MARV;

		/* fallthru */
	case SIOCGMIIREG: {
		u16 val = 0;
860

861
		spin_lock_bh(&sky2->phy_lock);
862
		err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
863
		spin_unlock_bh(&sky2->phy_lock);
864

865 866 867 868 869 870 871 872
		data->val_out = val;
		break;
	}

	case SIOCSMIIREG:
		if (!capable(CAP_NET_ADMIN))
			return -EPERM;

873
		spin_lock_bh(&sky2->phy_lock);
874 875
		err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
				   data->val_in);
876
		spin_unlock_bh(&sky2->phy_lock);
877 878 879 880 881
		break;
	}
	return err;
}

882 883 884 885 886 887 888
#ifdef SKY2_VLAN_TAG_USED
static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	u16 port = sky2->port;

889
	spin_lock_bh(&sky2->tx_lock);
890 891 892 893 894

	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
	sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
	sky2->vlgrp = grp;

895
	spin_unlock_bh(&sky2->tx_lock);
896 897 898 899 900 901 902 903
}

static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	u16 port = sky2->port;

904
	spin_lock_bh(&sky2->tx_lock);
905 906 907 908 909 910

	sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
	sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
	if (sky2->vlgrp)
		sky2->vlgrp->vlan_devices[vid] = NULL;

911
	spin_unlock_bh(&sky2->tx_lock);
912 913 914
}
#endif

915 916 917 918 919 920 921 922 923 924 925 926 927
/*
 * It appears the hardware has a bug in the FIFO logic that
 * cause it to hang if the FIFO gets overrun and the receive buffer
 * is not aligned. ALso alloc_skb() won't align properly if slab
 * debugging is enabled.
 */
static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
{
	struct sk_buff *skb;

	skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
	if (likely(skb)) {
		unsigned long p	= (unsigned long) skb->data;
928
		skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
929 930 931 932 933
	}

	return skb;
}

934 935 936 937 938 939
/*
 * Allocate and setup receiver buffer pool.
 * In case of 64 bit dma, there are 2X as many list elements
 * available as ring entries
 * and need to reserve one list element so we don't wrap around.
 */
940
static int sky2_rx_start(struct sky2_port *sky2)
941
{
942 943 944
	struct sky2_hw *hw = sky2->hw;
	unsigned rxq = rxqaddr[sky2->port];
	int i;
945

946
	sky2->rx_put = sky2->rx_next = 0;
947
	sky2_qset(hw, rxq);
948 949 950 951 952 953

	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
		/* MAC Rx RAM Read is controlled by hardware */
		sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
	}

954 955 956
	sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);

	rx_set_checksum(sky2);
S
Stephen Hemminger 已提交
957
	for (i = 0; i < sky2->rx_pending; i++) {
958 959
		struct ring_info *re = sky2->rx_ring + i;

960
		re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
961 962 963
		if (!re->skb)
			goto nomem;

964
		re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
965 966
					     sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
		sky2_rx_add(sky2, re->mapaddr);
967 968
	}

969 970 971 972
 	/* Truncate oversize frames */
 	sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8);
 	sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);

973 974
	/* Tell chip about available buffers */
	sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
975 976 977 978 979 980 981 982 983 984 985 986
	return 0;
nomem:
	sky2_rx_clean(sky2);
	return -ENOMEM;
}

/* Bring up network interface. */
static int sky2_up(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
987
	u32 ramsize, rxspace, imask;
988 989 990 991 992 993 994
	int err = -ENOMEM;

	if (netif_msg_ifup(sky2))
		printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);

	/* must be power of 2 */
	sky2->tx_le = pci_alloc_consistent(hw->pdev,
S
Stephen Hemminger 已提交
995 996
					   TX_RING_SIZE *
					   sizeof(struct sky2_tx_le),
997 998 999 1000
					   &sky2->tx_le_map);
	if (!sky2->tx_le)
		goto err_out;

1001
	sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012
				GFP_KERNEL);
	if (!sky2->tx_ring)
		goto err_out;
	sky2->tx_prod = sky2->tx_cons = 0;

	sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
					   &sky2->rx_le_map);
	if (!sky2->rx_le)
		goto err_out;
	memset(sky2->rx_le, 0, RX_LE_BYTES);

1013
	sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1014 1015 1016 1017 1018 1019
				GFP_KERNEL);
	if (!sky2->rx_ring)
		goto err_out;

	sky2_mac_init(hw, port);

1020 1021 1022 1023 1024 1025 1026 1027 1028 1029
	/* Determine available ram buffer space (in 4K blocks).
	 * Note: not sure about the FE setting below yet
	 */
	if (hw->chip_id == CHIP_ID_YUKON_FE)
		ramsize = 4;
	else
		ramsize = sky2_read8(hw, B2_E_0);

	/* Give transmitter one third (rounded up) */
	rxspace = ramsize - (ramsize + 2) / 3;
1030 1031

	sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1032
	sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1033

S
Stephen Hemminger 已提交
1034 1035 1036 1037
	/* Make sure SyncQ is disabled */
	sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
		    RB_RST_SET);

1038
	sky2_qset(hw, txqaddr[port]);
1039

1040 1041 1042
	/* Set almost empty threshold */
	if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
		sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1043

1044 1045
	sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
			   TX_RING_SIZE - 1);
1046

1047
	err = sky2_rx_start(sky2);
1048 1049 1050 1051
	if (err)
		goto err_out;

	/* Enable interrupts from phy/mac for port */
1052 1053 1054 1055
	imask = sky2_read32(hw, B0_IMSK);
	imask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
	sky2_write32(hw, B0_IMSK, imask);

1056 1057 1058
	return 0;

err_out:
1059
	if (sky2->rx_le) {
1060 1061
		pci_free_consistent(hw->pdev, RX_LE_BYTES,
				    sky2->rx_le, sky2->rx_le_map);
1062 1063 1064
		sky2->rx_le = NULL;
	}
	if (sky2->tx_le) {
1065 1066 1067
		pci_free_consistent(hw->pdev,
				    TX_RING_SIZE * sizeof(struct sky2_tx_le),
				    sky2->tx_le, sky2->tx_le_map);
1068 1069 1070 1071
		sky2->tx_le = NULL;
	}
	kfree(sky2->tx_ring);
	kfree(sky2->rx_ring);
1072

1073 1074
	sky2->tx_ring = NULL;
	sky2->rx_ring = NULL;
1075 1076 1077
	return err;
}

S
Stephen Hemminger 已提交
1078 1079 1080
/* Modular subtraction in ring */
static inline int tx_dist(unsigned tail, unsigned head)
{
1081
	return (head - tail) % TX_RING_SIZE;
S
Stephen Hemminger 已提交
1082
}
1083

S
Stephen Hemminger 已提交
1084 1085
/* Number of list elements available for next tx */
static inline int tx_avail(const struct sky2_port *sky2)
1086
{
S
Stephen Hemminger 已提交
1087
	return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1088 1089
}

S
Stephen Hemminger 已提交
1090
/* Estimate of number of transmit list elements required */
1091
static unsigned tx_le_req(const struct sk_buff *skb)
1092
{
S
Stephen Hemminger 已提交
1093 1094 1095 1096 1097 1098 1099 1100
	unsigned count;

	count = sizeof(dma_addr_t) / sizeof(u32);
	count += skb_shinfo(skb)->nr_frags * count;

	if (skb_shinfo(skb)->tso_size)
		++count;

1101
	if (skb->ip_summed == CHECKSUM_HW)
S
Stephen Hemminger 已提交
1102 1103 1104
		++count;

	return count;
1105 1106
}

S
Stephen Hemminger 已提交
1107 1108 1109 1110 1111
/*
 * Put one packet in ring for transmit.
 * A single packet can generate multiple list elements, and
 * the number of ring elements will probably be less than the number
 * of list elements used.
1112 1113
 *
 * No BH disabling for tx_lock here (like tg3)
S
Stephen Hemminger 已提交
1114
 */
1115 1116 1117 1118
static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
1119
	struct sky2_tx_le *le = NULL;
1120
	struct tx_ring_info *re;
1121
	unsigned i, len;
1122
	int avail;
1123 1124 1125 1126 1127
	dma_addr_t mapping;
	u32 addr64;
	u16 mss;
	u8 ctrl;

1128 1129 1130 1131
	/* No BH disabling for tx_lock here.  We are running in BH disabled
	 * context and TX reclaim runs via poll inside of a software
	 * interrupt, and no related locks in IRQ processing.
	 */
1132
	if (!spin_trylock(&sky2->tx_lock))
1133 1134
		return NETDEV_TX_LOCKED;

S
Stephen Hemminger 已提交
1135
	if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1136 1137 1138 1139 1140
		/* There is a known but harmless race with lockless tx
		 * and netif_stop_queue.
		 */
		if (!netif_queue_stopped(dev)) {
			netif_stop_queue(dev);
1141 1142 1143
			if (net_ratelimit())
				printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
				       dev->name);
1144
		}
1145
		spin_unlock(&sky2->tx_lock);
1146 1147 1148 1149

		return NETDEV_TX_BUSY;
	}

S
Stephen Hemminger 已提交
1150
	if (unlikely(netif_msg_tx_queued(sky2)))
1151 1152 1153 1154 1155
		printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
		       dev->name, sky2->tx_prod, skb->len);

	len = skb_headlen(skb);
	mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1156
	addr64 = high32(mapping);
S
Stephen Hemminger 已提交
1157 1158 1159

	re = sky2->tx_ring + sky2->tx_prod;

1160 1161
	/* Send high bits if changed or crosses boundary */
	if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
S
Stephen Hemminger 已提交
1162 1163 1164 1165
		le = get_tx_le(sky2);
		le->tx.addr = cpu_to_le32(addr64);
		le->ctrl = 0;
		le->opcode = OP_ADDR64 | HW_OWNER;
1166
		sky2->tx_addr64 = high32(mapping + len);
S
Stephen Hemminger 已提交
1167
	}
1168 1169 1170

	/* Check for TCP Segmentation Offload */
	mss = skb_shinfo(skb)->tso_size;
S
Stephen Hemminger 已提交
1171
	if (mss != 0) {
1172 1173 1174
		/* just drop the packet if non-linear expansion fails */
		if (skb_header_cloned(skb) &&
		    pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1175
			dev_kfree_skb(skb);
S
Stephen Hemminger 已提交
1176
			goto out_unlock;
1177 1178 1179 1180 1181
		}

		mss += ((skb->h.th->doff - 5) * 4);	/* TCP options */
		mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
		mss += ETH_HLEN;
S
Stephen Hemminger 已提交
1182
	}
1183

S
Stephen Hemminger 已提交
1184
	if (mss != sky2->tx_last_mss) {
1185 1186
		le = get_tx_le(sky2);
		le->tx.tso.size = cpu_to_le16(mss);
S
Stephen Hemminger 已提交
1187
		le->tx.tso.rsvd = 0;
1188 1189
		le->opcode = OP_LRGLEN | HW_OWNER;
		le->ctrl = 0;
S
Stephen Hemminger 已提交
1190
		sky2->tx_last_mss = mss;
1191 1192 1193
	}

	ctrl = 0;
1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209
#ifdef SKY2_VLAN_TAG_USED
	/* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
	if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
		if (!le) {
			le = get_tx_le(sky2);
			le->tx.addr = 0;
			le->opcode = OP_VLAN|HW_OWNER;
			le->ctrl = 0;
		} else
			le->opcode |= OP_VLAN;
		le->length = cpu_to_be16(vlan_tx_tag_get(skb));
		ctrl |= INS_VLAN;
	}
#endif

	/* Handle TCP checksum offload */
1210
	if (skb->ip_summed == CHECKSUM_HW) {
S
Stephen Hemminger 已提交
1211 1212
		u16 hdr = skb->h.raw - skb->data;
		u16 offset = hdr + skb->csum;
1213 1214 1215 1216 1217 1218 1219

		ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
		if (skb->nh.iph->protocol == IPPROTO_UDP)
			ctrl |= UDPTCP;

		le = get_tx_le(sky2);
		le->tx.csum.start = cpu_to_le16(hdr);
S
Stephen Hemminger 已提交
1220 1221
		le->tx.csum.offset = cpu_to_le16(offset);
		le->length = 0;	/* initial checksum value */
1222
		le->ctrl = 1;	/* one packet */
S
Stephen Hemminger 已提交
1223
		le->opcode = OP_TCPLISW | HW_OWNER;
1224 1225 1226 1227 1228 1229
	}

	le = get_tx_le(sky2);
	le->tx.addr = cpu_to_le32((u32) mapping);
	le->length = cpu_to_le16(len);
	le->ctrl = ctrl;
S
Stephen Hemminger 已提交
1230
	le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1231

S
Stephen Hemminger 已提交
1232
	/* Record the transmit mapping info */
1233
	re->skb = skb;
1234
	pci_unmap_addr_set(re, mapaddr, mapping);
1235 1236 1237

	for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1238
		struct tx_ring_info *fre;
1239 1240 1241

		mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
				       frag->size, PCI_DMA_TODEVICE);
1242
		addr64 = high32(mapping);
S
Stephen Hemminger 已提交
1243 1244 1245 1246 1247 1248
		if (addr64 != sky2->tx_addr64) {
			le = get_tx_le(sky2);
			le->tx.addr = cpu_to_le32(addr64);
			le->ctrl = 0;
			le->opcode = OP_ADDR64 | HW_OWNER;
			sky2->tx_addr64 = addr64;
1249 1250 1251 1252 1253 1254
		}

		le = get_tx_le(sky2);
		le->tx.addr = cpu_to_le32((u32) mapping);
		le->length = cpu_to_le16(frag->size);
		le->ctrl = ctrl;
S
Stephen Hemminger 已提交
1255
		le->opcode = OP_BUFFER | HW_OWNER;
1256

S
Stephen Hemminger 已提交
1257 1258
		fre = sky2->tx_ring
		    + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1259
		pci_unmap_addr_set(fre, mapaddr, mapping);
1260
	}
1261

S
Stephen Hemminger 已提交
1262
	re->idx = sky2->tx_prod;
1263 1264
	le->ctrl |= EOP;

1265 1266 1267 1268 1269 1270 1271
	avail = tx_avail(sky2);
	if (mss != 0 || avail < TX_MIN_PENDING) {
 		le->ctrl |= FRC_STAT;
		if (avail <= MAX_SKB_TX_LE)
			netif_stop_queue(dev);
	}

1272
	sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1273

S
Stephen Hemminger 已提交
1274
out_unlock:
1275
	spin_unlock(&sky2->tx_lock);
1276 1277 1278 1279 1280 1281

	dev->trans_start = jiffies;
	return NETDEV_TX_OK;
}

/*
S
Stephen Hemminger 已提交
1282 1283 1284
 * Free ring elements from starting at tx_cons until "done"
 *
 * NB: the hardware will tell us about partial completion of multi-part
S
shemminger@osdl.org 已提交
1285
 *     buffers; these are deferred until completion.
1286
 */
1287
static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1288
{
1289
	struct net_device *dev = sky2->netdev;
1290 1291
	struct pci_dev *pdev = sky2->hw->pdev;
	u16 nxt, put;
S
Stephen Hemminger 已提交
1292
	unsigned i;
1293

1294
	BUG_ON(done >= TX_RING_SIZE);
1295

1296
	if (unlikely(netif_msg_tx_done(sky2)))
S
shemminger@osdl.org 已提交
1297
		printk(KERN_DEBUG "%s: tx done, up to %u\n",
1298
		       dev->name, done);
1299

1300 1301 1302
	for (put = sky2->tx_cons; put != done; put = nxt) {
		struct tx_ring_info *re = sky2->tx_ring + put;
		struct sk_buff *skb = re->skb;
1303

1304
		nxt = re->idx;
1305
		BUG_ON(nxt >= TX_RING_SIZE);
S
Stephen Hemminger 已提交
1306
		prefetch(sky2->tx_ring + nxt);
1307

S
Stephen Hemminger 已提交
1308
		/* Check for partial status */
1309 1310
		if (tx_dist(put, done) < tx_dist(put, nxt))
			break;
S
Stephen Hemminger 已提交
1311 1312

		skb = re->skb;
1313
		pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1314
				 skb_headlen(skb), PCI_DMA_TODEVICE);
S
Stephen Hemminger 已提交
1315 1316

		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1317
			struct tx_ring_info *fre;
1318 1319
			fre = sky2->tx_ring + (put + i + 1) % TX_RING_SIZE;
			pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1320
				       skb_shinfo(skb)->frags[i].size,
1321
				       PCI_DMA_TODEVICE);
1322 1323
		}

1324
		dev_kfree_skb(skb);
S
Stephen Hemminger 已提交
1325 1326
	}

1327
	sky2->tx_cons = put;
1328
	if (tx_avail(sky2) > MAX_SKB_TX_LE)
1329 1330 1331 1332
		netif_wake_queue(dev);
}

/* Cleanup all untransmitted buffers, assume transmitter not running */
1333
static void sky2_tx_clean(struct sky2_port *sky2)
1334
{
1335
	spin_lock_bh(&sky2->tx_lock);
1336
	sky2_tx_complete(sky2, sky2->tx_prod);
1337
	spin_unlock_bh(&sky2->tx_lock);
1338 1339 1340 1341 1342 1343 1344 1345 1346
}

/* Network shutdown */
static int sky2_down(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	u16 ctrl;
1347
	u32 imask;
1348

1349 1350 1351 1352
	/* Never really got started! */
	if (!sky2->tx_le)
		return 0;

1353 1354 1355
	if (netif_msg_ifdown(sky2))
		printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);

1356
	/* Stop more packets from being queued */
1357 1358
	netif_stop_queue(dev);

S
Stephen Hemminger 已提交
1359 1360
	sky2_phy_reset(hw, port);

1361 1362 1363 1364 1365
	/* Stop transmitter */
	sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
	sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));

	sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
S
Stephen Hemminger 已提交
1366
		     RB_RST_SET | RB_DIS_OP_MD);
1367 1368

	ctrl = gma_read16(hw, port, GM_GP_CTRL);
S
Stephen Hemminger 已提交
1369
	ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1370 1371 1372 1373 1374
	gma_write16(hw, port, GM_GP_CTRL, ctrl);

	sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);

	/* Workaround shared GMAC reset */
S
Stephen Hemminger 已提交
1375 1376
	if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
	      && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387
		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);

	/* Disable Force Sync bit and Enable Alloc bit */
	sky2_write8(hw, SK_REG(port, TXA_CTRL),
		    TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);

	/* Stop Interval Timer and Limit Counter of Tx Arbiter */
	sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
	sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);

	/* Reset the PCI FIFO of the async Tx queue */
S
Stephen Hemminger 已提交
1388 1389
	sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
		     BMU_RST_SET | BMU_FIFO_RST);
1390 1391 1392 1393 1394 1395 1396

	/* Reset the Tx prefetch units */
	sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
		     PREF_UNIT_RST_SET);

	sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);

1397
	sky2_rx_stop(sky2);
1398 1399 1400 1401

	sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
	sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);

1402 1403 1404 1405 1406
	/* Disable port IRQ */
	imask = sky2_read32(hw, B0_IMSK);
	imask &= ~(sky2->port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
	sky2_write32(hw, B0_IMSK, imask);

S
shemminger@osdl.org 已提交
1407
	/* turn off LED's */
1408 1409
	sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);

1410 1411
	synchronize_irq(hw->pdev->irq);

1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423
	sky2_tx_clean(sky2);
	sky2_rx_clean(sky2);

	pci_free_consistent(hw->pdev, RX_LE_BYTES,
			    sky2->rx_le, sky2->rx_le_map);
	kfree(sky2->rx_ring);

	pci_free_consistent(hw->pdev,
			    TX_RING_SIZE * sizeof(struct sky2_tx_le),
			    sky2->tx_le, sky2->tx_le_map);
	kfree(sky2->tx_ring);

1424 1425 1426 1427 1428 1429
	sky2->tx_le = NULL;
	sky2->rx_le = NULL;

	sky2->rx_ring = NULL;
	sky2->tx_ring = NULL;

1430 1431 1432 1433 1434
	return 0;
}

static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
{
S
Stephen Hemminger 已提交
1435 1436 1437
	if (!hw->copper)
		return SPEED_1000;

1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457
	if (hw->chip_id == CHIP_ID_YUKON_FE)
		return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;

	switch (aux & PHY_M_PS_SPEED_MSK) {
	case PHY_M_PS_SPEED_1000:
		return SPEED_1000;
	case PHY_M_PS_SPEED_100:
		return SPEED_100;
	default:
		return SPEED_10;
	}
}

static void sky2_link_up(struct sky2_port *sky2)
{
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	u16 reg;

	/* Enable Transmit FIFO Underrun */
S
Stephen Hemminger 已提交
1458
	sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1459 1460

	reg = gma_read16(hw, port, GM_GP_CTRL);
1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483
	if (sky2->autoneg == AUTONEG_DISABLE) {
		reg |= GM_GPCR_AU_ALL_DIS;

		/* Is write/read necessary?  Copied from sky2_mac_init */
		gma_write16(hw, port, GM_GP_CTRL, reg);
		gma_read16(hw, port, GM_GP_CTRL);

		switch (sky2->speed) {
		case SPEED_1000:
			reg &= ~GM_GPCR_SPEED_100;
			reg |= GM_GPCR_SPEED_1000;
			break;
		case SPEED_100:
			reg &= ~GM_GPCR_SPEED_1000;
			reg |= GM_GPCR_SPEED_100;
			break;
		case SPEED_10:
			reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
			break;
		}
	} else
		reg &= ~GM_GPCR_AU_ALL_DIS;

1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497
	if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
		reg |= GM_GPCR_DUP_FULL;

	/* enable Rx/Tx */
	reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
	gma_write16(hw, port, GM_GP_CTRL, reg);
	gma_read16(hw, port, GM_GP_CTRL);

	gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);

	netif_carrier_on(sky2->netdev);
	netif_wake_queue(sky2->netdev);

	/* Turn on link LED */
S
Stephen Hemminger 已提交
1498
	sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1499 1500
		    LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);

S
Stephen Hemminger 已提交
1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514
	if (hw->chip_id == CHIP_ID_YUKON_XL) {
		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);

		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) |	/* LINK/ACT */
			     PHY_M_LEDC_INIT_CTRL(sky2->speed ==
						  SPEED_10 ? 7 : 0) |
			     PHY_M_LEDC_STA1_CTRL(sky2->speed ==
						  SPEED_100 ? 7 : 0) |
			     PHY_M_LEDC_STA0_CTRL(sky2->speed ==
						  SPEED_1000 ? 7 : 0));
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
	}

1515 1516
	if (netif_msg_link(sky2))
		printk(KERN_INFO PFX
S
shemminger@osdl.org 已提交
1517
		       "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1518 1519 1520
		       sky2->netdev->name, sky2->speed,
		       sky2->duplex == DUPLEX_FULL ? "full" : "half",
		       (sky2->tx_pause && sky2->rx_pause) ? "both" :
S
Stephen Hemminger 已提交
1521
		       sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539
}

static void sky2_link_down(struct sky2_port *sky2)
{
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	u16 reg;

	gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);

	reg = gma_read16(hw, port, GM_GP_CTRL);
	reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
	gma_write16(hw, port, GM_GP_CTRL, reg);
	gma_read16(hw, port, GM_GP_CTRL);	/* PCI post */

	if (sky2->rx_pause && !sky2->tx_pause) {
		/* restore Asymmetric Pause bit */
		gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
S
Stephen Hemminger 已提交
1540 1541
			     gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
			     | PHY_M_AN_ASP);
1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554
	}

	netif_carrier_off(sky2->netdev);
	netif_stop_queue(sky2->netdev);

	/* Turn on link LED */
	sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);

	if (netif_msg_link(sky2))
		printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
	sky2_phy_init(hw, port);
}

S
Stephen Hemminger 已提交
1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599
static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
{
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	u16 lpa;

	lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);

	if (lpa & PHY_M_AN_RF) {
		printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
		return -1;
	}

	if (hw->chip_id != CHIP_ID_YUKON_FE &&
	    gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
		printk(KERN_ERR PFX "%s: master/slave fault",
		       sky2->netdev->name);
		return -1;
	}

	if (!(aux & PHY_M_PS_SPDUP_RES)) {
		printk(KERN_ERR PFX "%s: speed/duplex mismatch",
		       sky2->netdev->name);
		return -1;
	}

	sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;

	sky2->speed = sky2_phy_speed(hw, aux);

	/* Pause bits are offset (9..8) */
	if (hw->chip_id == CHIP_ID_YUKON_XL)
		aux >>= 6;

	sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
	sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;

	if ((sky2->tx_pause || sky2->rx_pause)
	    && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
	else
		sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);

	return 0;
}
1600

1601 1602
/* Interrupt from PHY */
static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1603
{
1604 1605
	struct net_device *dev = hw->dev[port];
	struct sky2_port *sky2 = netdev_priv(dev);
1606 1607
	u16 istatus, phystat;

1608 1609 1610 1611 1612 1613
	spin_lock(&sky2->phy_lock);
	istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
	phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);

	if (!netif_running(dev))
		goto out;
1614 1615 1616 1617 1618 1619

	if (netif_msg_intr(sky2))
		printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
		       sky2->netdev->name, istatus, phystat);

	if (istatus & PHY_M_IS_AN_COMPL) {
S
Stephen Hemminger 已提交
1620 1621 1622 1623
		if (sky2_autoneg_done(sky2, phystat) == 0)
			sky2_link_up(sky2);
		goto out;
	}
1624

S
Stephen Hemminger 已提交
1625 1626
	if (istatus & PHY_M_IS_LSP_CHANGE)
		sky2->speed = sky2_phy_speed(hw, phystat);
1627

S
Stephen Hemminger 已提交
1628 1629 1630
	if (istatus & PHY_M_IS_DUP_CHANGE)
		sky2->duplex =
		    (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1631

S
Stephen Hemminger 已提交
1632 1633
	if (istatus & PHY_M_IS_LST_CHANGE) {
		if (phystat & PHY_M_PS_LINK_UP)
1634
			sky2_link_up(sky2);
S
Stephen Hemminger 已提交
1635 1636
		else
			sky2_link_down(sky2);
1637
	}
S
Stephen Hemminger 已提交
1638
out:
1639
	spin_unlock(&sky2->phy_lock);
1640 1641
}

1642 1643 1644 1645

/* Transmit timeout is only called if we are running, carries is up
 * and tx queue is full (stopped).
 */
1646 1647 1648
static void sky2_tx_timeout(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
1649 1650
	struct sky2_hw *hw = sky2->hw;
	unsigned txq = txqaddr[sky2->port];
1651
	u16 report, done;
1652 1653 1654 1655

	if (netif_msg_timer(sky2))
		printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);

1656 1657
	report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
	done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1658

1659 1660 1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675
	printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
	       dev->name,
	       sky2->tx_cons, sky2->tx_prod, report, done);

	if (report != done) {
		printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");

		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
	} else if (report != sky2->tx_cons) {
		printk(KERN_INFO PFX "status report lost?\n");

		spin_lock_bh(&sky2->tx_lock);
		sky2_tx_complete(sky2, report);
		spin_unlock_bh(&sky2->tx_lock);
	} else {
		printk(KERN_INFO PFX "hardware hung? flushing\n");
1676

1677 1678 1679 1680 1681 1682 1683 1684
		sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
		sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);

		sky2_tx_clean(sky2);

		sky2_qset(hw, txq);
		sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
	}
1685 1686
}

1687

1688 1689 1690
/* Want receive buffer size to be multiple of 64 bits
 * and incl room for vlan and truncation
 */
1691 1692
static inline unsigned sky2_buf_size(int mtu)
{
1693
	return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1694 1695
}

1696 1697
static int sky2_change_mtu(struct net_device *dev, int new_mtu)
{
1698 1699 1700 1701
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	int err;
	u16 ctl, mode;
1702
	u32 imask;
1703 1704 1705 1706

	if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
		return -EINVAL;

1707 1708 1709
	if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
		return -EINVAL;

1710 1711 1712 1713 1714
	if (!netif_running(dev)) {
		dev->mtu = new_mtu;
		return 0;
	}

1715
	imask = sky2_read32(hw, B0_IMSK);
1716 1717
	sky2_write32(hw, B0_IMSK, 0);

1718 1719 1720 1721
	dev->trans_start = jiffies;	/* prevent tx timeout */
	netif_stop_queue(dev);
	netif_poll_disable(hw->dev[0]);

1722 1723
	synchronize_irq(hw->pdev->irq);

1724 1725 1726 1727
	ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
	gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
	sky2_rx_stop(sky2);
	sky2_rx_clean(sky2);
1728 1729

	dev->mtu = new_mtu;
1730
	sky2->rx_bufsize = sky2_buf_size(new_mtu);
1731 1732 1733 1734 1735 1736 1737
	mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
		GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);

	if (dev->mtu > ETH_DATA_LEN)
		mode |= GM_SMOD_JUMBO_ENA;

	gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1738

1739
	sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1740

1741
	err = sky2_rx_start(sky2);
1742
	sky2_write32(hw, B0_IMSK, imask);
1743

1744 1745 1746 1747 1748 1749 1750 1751 1752
	if (err)
		dev_close(dev);
	else {
		gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);

		netif_poll_enable(hw->dev[0]);
		netif_wake_queue(dev);
	}

1753 1754 1755 1756 1757 1758
	return err;
}

/*
 * Receive one packet.
 * For small packets or errors, just reuse existing skb.
S
shemminger@osdl.org 已提交
1759
 * For larger packets, get new buffer.
1760
 */
1761
static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1762 1763 1764
				    u16 length, u32 status)
{
	struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1765
	struct sk_buff *skb = NULL;
1766 1767 1768

	if (unlikely(netif_msg_rx_status(sky2)))
		printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1769
		       sky2->netdev->name, sky2->rx_next, status, length);
1770

S
Stephen Hemminger 已提交
1771
	sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
S
Stephen Hemminger 已提交
1772
	prefetch(sky2->rx_ring + sky2->rx_next);
1773

1774
	if (status & GMR_FS_ANY_ERR)
1775 1776
		goto error;

1777 1778 1779
	if (!(status & GMR_FS_RX_OK))
		goto resubmit;

1780
	if (length > sky2->netdev->mtu + ETH_HLEN)
1781 1782
		goto oversize;

1783
	if (length < copybreak) {
1784 1785
		skb = alloc_skb(length + 2, GFP_ATOMIC);
		if (!skb)
S
Stephen Hemminger 已提交
1786 1787
			goto resubmit;

1788
		skb_reserve(skb, 2);
S
Stephen Hemminger 已提交
1789 1790
		pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
					    length, PCI_DMA_FROMDEVICE);
1791
		memcpy(skb->data, re->skb->data, length);
1792 1793
		skb->ip_summed = re->skb->ip_summed;
		skb->csum = re->skb->csum;
S
Stephen Hemminger 已提交
1794 1795 1796
		pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
					       length, PCI_DMA_FROMDEVICE);
	} else {
1797 1798
		struct sk_buff *nskb;

1799
		nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
S
Stephen Hemminger 已提交
1800 1801
		if (!nskb)
			goto resubmit;
1802

S
Stephen Hemminger 已提交
1803
		skb = re->skb;
1804
		re->skb = nskb;
S
Stephen Hemminger 已提交
1805
		pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1806
				 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
S
Stephen Hemminger 已提交
1807
		prefetch(skb->data);
1808

S
Stephen Hemminger 已提交
1809
		re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1810
					     sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
S
Stephen Hemminger 已提交
1811
	}
1812

1813
	skb_put(skb, length);
S
Stephen Hemminger 已提交
1814
resubmit:
1815
	re->skb->ip_summed = CHECKSUM_NONE;
1816
	sky2_rx_add(sky2, re->mapaddr);
1817

1818
	/* Tell receiver about new buffers. */
1819
	sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put);
1820

1821 1822
	return skb;

1823 1824 1825 1826
oversize:
	++sky2->net_stats.rx_over_errors;
	goto resubmit;

1827
error:
1828 1829
	++sky2->net_stats.rx_errors;

1830
	if (netif_msg_rx_err(sky2) && net_ratelimit())
1831 1832
		printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
		       sky2->netdev->name, status, length);
S
Stephen Hemminger 已提交
1833 1834

	if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1835 1836 1837 1838 1839
		sky2->net_stats.rx_length_errors++;
	if (status & GMR_FS_FRAGMENT)
		sky2->net_stats.rx_frame_errors++;
	if (status & GMR_FS_CRC_ERR)
		sky2->net_stats.rx_crc_errors++;
S
Stephen Hemminger 已提交
1840 1841
	if (status & GMR_FS_RX_FF_OV)
		sky2->net_stats.rx_fifo_errors++;
1842

S
Stephen Hemminger 已提交
1843
	goto resubmit;
1844 1845
}

1846 1847
/* Transmit complete */
static inline void sky2_tx_done(struct net_device *dev, u16 last)
1848
{
1849
	struct sky2_port *sky2 = netdev_priv(dev);
1850

1851 1852 1853 1854
	if (netif_running(dev)) {
		spin_lock(&sky2->tx_lock);
		sky2_tx_complete(sky2, last);
		spin_unlock(&sky2->tx_lock);
1855
	}
1856 1857
}

1858 1859
/* Process status response ring */
static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1860
{
1861
	int work_done = 0;
1862

1863
	rmb();
1864

1865
	for(;;) {
1866 1867
		struct sky2_status_le *le  = hw->st_le + hw->st_idx;
		struct net_device *dev;
1868
		struct sky2_port *sky2;
1869 1870 1871
		struct sk_buff *skb;
		u32 status;
		u16 length;
1872 1873 1874 1875 1876 1877
		u8  link, opcode;

		opcode = le->opcode;
		if (!opcode)
			break;
		opcode &= ~HW_OWNER;
1878

1879
		hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1880
		le->opcode = 0;
1881

1882 1883 1884
		link = le->link;
		BUG_ON(link >= 2);
		dev = hw->dev[link];
1885 1886

		sky2 = netdev_priv(dev);
1887 1888
		length = le->length;
		status = le->status;
1889

1890
		switch (opcode) {
1891
		case OP_RXSTAT:
1892
			skb = sky2_receive(sky2, length, status);
1893 1894
			if (!skb)
				break;
1895 1896 1897 1898 1899

			skb->dev = dev;
			skb->protocol = eth_type_trans(skb, dev);
			dev->last_rx = jiffies;

1900 1901 1902 1903 1904 1905 1906
#ifdef SKY2_VLAN_TAG_USED
			if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
				vlan_hwaccel_receive_skb(skb,
							 sky2->vlgrp,
							 be16_to_cpu(sky2->rx_tag));
			} else
#endif
1907
				netif_receive_skb(skb);
1908 1909 1910

			if (++work_done >= to_do)
				goto exit_loop;
1911 1912
			break;

1913 1914 1915 1916 1917 1918 1919 1920 1921
#ifdef SKY2_VLAN_TAG_USED
		case OP_RXVLAN:
			sky2->rx_tag = length;
			break;

		case OP_RXCHKSVLAN:
			sky2->rx_tag = length;
			/* fall through */
#endif
1922
		case OP_RXCHKS:
1923 1924 1925
			skb = sky2->rx_ring[sky2->rx_next].skb;
			skb->ip_summed = CHECKSUM_HW;
			skb->csum = le16_to_cpu(status);
1926 1927 1928
			break;

		case OP_TXINDEXLE:
1929
			/* TX index reports status for both ports */
1930 1931 1932 1933 1934
			sky2_tx_done(hw->dev[0], status & 0xffff);
			if (hw->dev[1])
				sky2_tx_done(hw->dev[1],
				     ((status >> 24) & 0xff)
					     | (u16)(length & 0xf) << 8);
1935 1936 1937 1938
			break;

		default:
			if (net_ratelimit())
S
Stephen Hemminger 已提交
1939
				printk(KERN_WARNING PFX
1940
				       "unknown status opcode 0x%x\n", opcode);
1941 1942
			break;
		}
1943
	}
1944

1945
exit_loop:
1946
	return work_done;
1947 1948 1949 1950 1951 1952
}

static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
{
	struct net_device *dev = hw->dev[port];

1953 1954 1955
	if (net_ratelimit())
		printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
		       dev->name, status);
1956 1957

	if (status & Y2_IS_PAR_RD1) {
1958 1959 1960
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: ram data read parity error\n",
			       dev->name);
1961 1962 1963 1964 1965
		/* Clear IRQ */
		sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
	}

	if (status & Y2_IS_PAR_WR1) {
1966 1967 1968
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: ram data write parity error\n",
			       dev->name);
1969 1970 1971 1972 1973

		sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
	}

	if (status & Y2_IS_PAR_MAC1) {
1974 1975
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1976 1977 1978 1979
		sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
	}

	if (status & Y2_IS_PAR_RX1) {
1980 1981
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1982 1983 1984 1985
		sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
	}

	if (status & Y2_IS_TCP_TXA1) {
1986 1987 1988
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: TCP segmentation error\n",
			       dev->name);
1989 1990 1991 1992 1993 1994 1995 1996
		sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
	}
}

static void sky2_hw_intr(struct sky2_hw *hw)
{
	u32 status = sky2_read32(hw, B0_HWE_ISRC);

S
Stephen Hemminger 已提交
1997
	if (status & Y2_IS_TIST_OV)
1998 1999 2000
		sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);

	if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
S
Stephen Hemminger 已提交
2001 2002
		u16 pci_err;

2003
		pci_err = sky2_pci_read16(hw, PCI_STATUS);
2004 2005 2006
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
			       pci_name(hw->pdev), pci_err);
2007 2008

		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2009
		sky2_pci_write16(hw, PCI_STATUS,
S
Stephen Hemminger 已提交
2010
				      pci_err | PCI_STATUS_ERROR_BITS);
2011 2012 2013 2014
		sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
	}

	if (status & Y2_IS_PCI_EXP) {
S
shemminger@osdl.org 已提交
2015
		/* PCI-Express uncorrectable Error occurred */
S
Stephen Hemminger 已提交
2016 2017
		u32 pex_err;

2018
		pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2019

2020 2021 2022
		if (net_ratelimit())
			printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
			       pci_name(hw->pdev), pex_err);
2023 2024 2025

		/* clear the interrupt */
		sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2026
		sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
S
Stephen Hemminger 已提交
2027
				       0xffffffffUL);
2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064
		sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

		if (pex_err & PEX_FATAL_ERRORS) {
			u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
			hwmsk &= ~Y2_IS_PCI_EXP;
			sky2_write32(hw, B0_HWE_IMSK, hwmsk);
		}
	}

	if (status & Y2_HWE_L1_MASK)
		sky2_hw_error(hw, 0, status);
	status >>= 8;
	if (status & Y2_HWE_L1_MASK)
		sky2_hw_error(hw, 1, status);
}

static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
{
	struct net_device *dev = hw->dev[port];
	struct sky2_port *sky2 = netdev_priv(dev);
	u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));

	if (netif_msg_intr(sky2))
		printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
		       dev->name, status);

	if (status & GM_IS_RX_FF_OR) {
		++sky2->net_stats.rx_fifo_errors;
		sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
	}

	if (status & GM_IS_TX_FF_UR) {
		++sky2->net_stats.tx_fifo_errors;
		sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
	}
}

2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085
/* This should never happen it is a fatal situation */
static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
				  const char *rxtx, u32 mask)
{
	struct net_device *dev = hw->dev[port];
	struct sky2_port *sky2 = netdev_priv(dev);
	u32 imask;

	printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
	       dev ? dev->name : "<not registered>", rxtx);

	imask = sky2_read32(hw, B0_IMSK);
	imask &= ~mask;
	sky2_write32(hw, B0_IMSK, imask);

	if (dev) {
		spin_lock(&sky2->phy_lock);
		sky2_link_down(sky2);
		spin_unlock(&sky2->phy_lock);
	}
}
2086

2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100
/* If idle then force a fake soft NAPI poll once a second
 * to work around cases where sharing an edge triggered interrupt.
 */
static void sky2_idle(unsigned long arg)
{
	struct net_device *dev = (struct net_device *) arg;

	local_irq_disable();
	if (__netif_rx_schedule_prep(dev))
		__netif_rx_schedule(dev);
	local_irq_enable();
}


2101
static int sky2_poll(struct net_device *dev0, int *budget)
2102
{
2103 2104 2105
	struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
	int work_limit = min(dev0->quota, *budget);
	int work_done = 0;
2106
	u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2107

2108
 restart_poll:
2109 2110 2111 2112 2113 2114
	if (unlikely(status & ~Y2_IS_STAT_BMU)) {
		if (status & Y2_IS_HW_ERR)
			sky2_hw_intr(hw);

		if (status & Y2_IS_IRQ_PHY1)
			sky2_phy_intr(hw, 0);
2115

2116 2117
		if (status & Y2_IS_IRQ_PHY2)
			sky2_phy_intr(hw, 1);
2118

2119 2120
		if (status & Y2_IS_IRQ_MAC1)
			sky2_mac_intr(hw, 0);
2121

2122 2123
		if (status & Y2_IS_IRQ_MAC2)
			sky2_mac_intr(hw, 1);
2124

2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136
		if (status & Y2_IS_CHK_RX1)
			sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);

		if (status & Y2_IS_CHK_RX2)
			sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);

		if (status & Y2_IS_CHK_TXA1)
			sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);

		if (status & Y2_IS_CHK_TXA2)
			sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
	}
2137

2138
	if (status & Y2_IS_STAT_BMU) {
2139
		work_done += sky2_status_intr(hw, work_limit - work_done);
2140 2141 2142 2143 2144 2145 2146 2147 2148
		*budget -= work_done;
		dev0->quota -= work_done;

		if (work_done >= work_limit)
			return 1;

		sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
	}

2149 2150
	mod_timer(&hw->idle_timer, jiffies + HZ);

2151 2152
	local_irq_disable();
	__netif_rx_complete(dev0);
2153

2154
	status = sky2_read32(hw, B0_Y2_SP_LISR);
2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166

	if (unlikely(status)) {
		/* More work pending, try and keep going */
		if (__netif_rx_schedule_prep(dev0)) {
			__netif_rx_reschedule(dev0, work_done);
			status = sky2_read32(hw, B0_Y2_SP_EISR);
			local_irq_enable();
			goto restart_poll;
		}
	}

	local_irq_enable();
2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179
	return 0;
}

static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
{
	struct sky2_hw *hw = dev_id;
	struct net_device *dev0 = hw->dev[0];
	u32 status;

	/* Reading this mask interrupts as side effect */
	status = sky2_read32(hw, B0_Y2_SP_ISRC2);
	if (status == 0 || status == ~0)
		return IRQ_NONE;
S
Stephen Hemminger 已提交
2180

2181 2182 2183
	prefetch(&hw->st_le[hw->st_idx]);
	if (likely(__netif_rx_schedule_prep(dev0)))
		__netif_rx_schedule(dev0);
S
Stephen Hemminger 已提交
2184

2185 2186 2187 2188 2189 2190 2191 2192
	return IRQ_HANDLED;
}

#ifdef CONFIG_NET_POLL_CONTROLLER
static void sky2_netpoll(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);

S
Stephen Hemminger 已提交
2193
	sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
2194 2195 2196 2197
}
#endif

/* Chip internal frequency for clock calculations */
2198
static inline u32 sky2_mhz(const struct sky2_hw *hw)
2199
{
S
Stephen Hemminger 已提交
2200
	switch (hw->chip_id) {
2201
	case CHIP_ID_YUKON_EC:
2202
	case CHIP_ID_YUKON_EC_U:
2203
		return 125;	/* 125 Mhz */
2204
	case CHIP_ID_YUKON_FE:
2205
		return 100;	/* 100 Mhz */
S
Stephen Hemminger 已提交
2206
	default:		/* YUKON_XL */
2207
		return 156;	/* 156 Mhz */
2208 2209 2210
	}
}

2211
static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2212
{
2213
	return sky2_mhz(hw) * us;
2214 2215
}

2216
static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2217
{
2218
	return clk / sky2_mhz(hw);
2219 2220
}

2221

2222
static int __devinit sky2_reset(struct sky2_hw *hw)
2223 2224 2225
{
	u16 status;
	u8 t8, pmd_type;
2226
	int i;
2227 2228

	sky2_write8(hw, B0_CTST, CS_RST_CLR);
2229

2230 2231 2232 2233 2234 2235 2236
	hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
	if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
		printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
		       pci_name(hw->pdev), hw->chip_id);
		return -EOPNOTSUPP;
	}

2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253
	hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;

	/* This rev is really old, and requires untested workarounds */
	if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
		printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
		       pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
		       hw->chip_id, hw->chip_rev);
		return -EOPNOTSUPP;
	}

	/* This chip is new and not tested yet */
	if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
		pr_info(PFX "%s: is a version of Yukon 2 chipset that has not been tested yet.\n",
			pci_name(hw->pdev));
		pr_info("Please report success/failure to maintainer <shemminger@osdl.org>\n");
	}

2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264
	/* disable ASF */
	if (hw->chip_id <= CHIP_ID_YUKON_EC) {
		sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
		sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
	}

	/* do a SW reset */
	sky2_write8(hw, B0_CTST, CS_RST_SET);
	sky2_write8(hw, B0_CTST, CS_RST_CLR);

	/* clear PCI errors, if any */
2265
	status = sky2_pci_read16(hw, PCI_STATUS);
2266

2267
	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2268 2269
	sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);

2270 2271 2272 2273

	sky2_write8(hw, B0_CTST, CS_MRST_CLR);

	/* clear any PEX errors */
2274
	if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2275 2276
		sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);

2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287

	pmd_type = sky2_read8(hw, B2_PMD_TYP);
	hw->copper = !(pmd_type == 'L' || pmd_type == 'S');

	hw->ports = 1;
	t8 = sky2_read8(hw, B2_Y2_HW_RES);
	if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
		if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
			++hw->ports;
	}

2288
	sky2_set_power_state(hw, PCI_D0);
2289 2290 2291 2292 2293 2294 2295 2296

	for (i = 0; i < hw->ports; i++) {
		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
		sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
	}

	sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);

S
Stephen Hemminger 已提交
2297 2298
	/* Clear I2C IRQ noise */
	sky2_write32(hw, B2_I2C_IRQ, 1);
2299 2300 2301 2302

	/* turn off hardware timer (unused) */
	sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
	sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
S
Stephen Hemminger 已提交
2303

2304 2305
	sky2_write8(hw, B0_Y2LED, LED_STAT_ON);

2306 2307
	/* Turn off descriptor polling */
	sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2308 2309 2310

	/* Turn off receive timestamp */
	sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
S
Stephen Hemminger 已提交
2311
	sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2312 2313 2314 2315 2316 2317 2318

	/* enable the Tx Arbiters */
	for (i = 0; i < hw->ports; i++)
		sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);

	/* Initialize ram interface */
	for (i = 0; i < hw->ports; i++) {
S
Stephen Hemminger 已提交
2319
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346

		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
		sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
	}

	sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);

	for (i = 0; i < hw->ports; i++)
		sky2_phy_reset(hw, i);

	memset(hw->st_le, 0, STATUS_LE_BYTES);
	hw->st_idx = 0;

	sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
	sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);

	sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
S
Stephen Hemminger 已提交
2347
	sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2348 2349

	/* Set the list last index */
S
Stephen Hemminger 已提交
2350
	sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2351

2352 2353
	sky2_write16(hw, STAT_TX_IDX_TH, 10);
	sky2_write8(hw, STAT_FIFO_WM, 16);
2354

2355 2356 2357 2358 2359
	/* set Status-FIFO ISR watermark */
	if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
		sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
	else
		sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2360

2361
	sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2362 2363
	sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
	sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2364

S
Stephen Hemminger 已提交
2365
	/* enable status unit */
2366 2367 2368 2369 2370 2371 2372 2373 2374
	sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);

	sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
	sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
	sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);

	return 0;
}

2375
static u32 sky2_supported_modes(const struct sky2_hw *hw)
2376 2377 2378
{
	u32 modes;
	if (hw->copper) {
S
Stephen Hemminger 已提交
2379 2380 2381 2382 2383
		modes = SUPPORTED_10baseT_Half
		    | SUPPORTED_10baseT_Full
		    | SUPPORTED_100baseT_Half
		    | SUPPORTED_100baseT_Full
		    | SUPPORTED_Autoneg | SUPPORTED_TP;
2384 2385 2386

		if (hw->chip_id != CHIP_ID_YUKON_FE)
			modes |= SUPPORTED_1000baseT_Half
S
Stephen Hemminger 已提交
2387
			    | SUPPORTED_1000baseT_Full;
2388 2389
	} else
		modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
S
Stephen Hemminger 已提交
2390
		    | SUPPORTED_Autoneg;
2391 2392 2393
	return modes;
}

S
Stephen Hemminger 已提交
2394
static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2395 2396 2397 2398 2399 2400 2401 2402 2403
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;

	ecmd->transceiver = XCVR_INTERNAL;
	ecmd->supported = sky2_supported_modes(hw);
	ecmd->phy_address = PHY_ADDR_MARV;
	if (hw->copper) {
		ecmd->supported = SUPPORTED_10baseT_Half
S
Stephen Hemminger 已提交
2404 2405 2406 2407 2408 2409
		    | SUPPORTED_10baseT_Full
		    | SUPPORTED_100baseT_Half
		    | SUPPORTED_100baseT_Full
		    | SUPPORTED_1000baseT_Half
		    | SUPPORTED_1000baseT_Full
		    | SUPPORTED_Autoneg | SUPPORTED_TP;
2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433
		ecmd->port = PORT_TP;
	} else
		ecmd->port = PORT_FIBRE;

	ecmd->advertising = sky2->advertising;
	ecmd->autoneg = sky2->autoneg;
	ecmd->speed = sky2->speed;
	ecmd->duplex = sky2->duplex;
	return 0;
}

static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	const struct sky2_hw *hw = sky2->hw;
	u32 supported = sky2_supported_modes(hw);

	if (ecmd->autoneg == AUTONEG_ENABLE) {
		ecmd->advertising = supported;
		sky2->duplex = -1;
		sky2->speed = -1;
	} else {
		u32 setting;

S
Stephen Hemminger 已提交
2434
		switch (ecmd->speed) {
2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473
		case SPEED_1000:
			if (ecmd->duplex == DUPLEX_FULL)
				setting = SUPPORTED_1000baseT_Full;
			else if (ecmd->duplex == DUPLEX_HALF)
				setting = SUPPORTED_1000baseT_Half;
			else
				return -EINVAL;
			break;
		case SPEED_100:
			if (ecmd->duplex == DUPLEX_FULL)
				setting = SUPPORTED_100baseT_Full;
			else if (ecmd->duplex == DUPLEX_HALF)
				setting = SUPPORTED_100baseT_Half;
			else
				return -EINVAL;
			break;

		case SPEED_10:
			if (ecmd->duplex == DUPLEX_FULL)
				setting = SUPPORTED_10baseT_Full;
			else if (ecmd->duplex == DUPLEX_HALF)
				setting = SUPPORTED_10baseT_Half;
			else
				return -EINVAL;
			break;
		default:
			return -EINVAL;
		}

		if ((setting & supported) == 0)
			return -EINVAL;

		sky2->speed = ecmd->speed;
		sky2->duplex = ecmd->duplex;
	}

	sky2->autoneg = ecmd->autoneg;
	sky2->advertising = ecmd->advertising;

2474 2475
	if (netif_running(dev))
		sky2_phy_reinit(sky2);
2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491

	return 0;
}

static void sky2_get_drvinfo(struct net_device *dev,
			     struct ethtool_drvinfo *info)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	strcpy(info->driver, DRV_NAME);
	strcpy(info->version, DRV_VERSION);
	strcpy(info->fw_version, "N/A");
	strcpy(info->bus_info, pci_name(sky2->hw->pdev));
}

static const struct sky2_stat {
S
Stephen Hemminger 已提交
2492 2493
	char name[ETH_GSTRING_LEN];
	u16 offset;
2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504
} sky2_stats[] = {
	{ "tx_bytes",	   GM_TXO_OK_HI },
	{ "rx_bytes",	   GM_RXO_OK_HI },
	{ "tx_broadcast",  GM_TXF_BC_OK },
	{ "rx_broadcast",  GM_RXF_BC_OK },
	{ "tx_multicast",  GM_TXF_MC_OK },
	{ "rx_multicast",  GM_RXF_MC_OK },
	{ "tx_unicast",    GM_TXF_UC_OK },
	{ "rx_unicast",    GM_RXF_UC_OK },
	{ "tx_mac_pause",  GM_TXF_MPAUSE },
	{ "rx_mac_pause",  GM_RXF_MPAUSE },
2505
	{ "collisions",    GM_TXF_COL },
2506 2507
	{ "late_collision",GM_TXF_LAT_COL },
	{ "aborted", 	   GM_TXF_ABO_COL },
2508
	{ "single_collisions", GM_TXF_SNG_COL },
2509
	{ "multi_collisions", GM_TXF_MUL_COL },
2510

2511
	{ "rx_short",      GM_RXF_SHT },
2512
	{ "rx_runt", 	   GM_RXE_FRAG },
2513 2514 2515 2516 2517 2518 2519
	{ "rx_64_byte_packets", GM_RXF_64B },
	{ "rx_65_to_127_byte_packets", GM_RXF_127B },
	{ "rx_128_to_255_byte_packets", GM_RXF_255B },
	{ "rx_256_to_511_byte_packets", GM_RXF_511B },
	{ "rx_512_to_1023_byte_packets", GM_RXF_1023B },
	{ "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
	{ "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2520
	{ "rx_too_long",   GM_RXF_LNG_ERR },
2521 2522
	{ "rx_fifo_overflow", GM_RXE_FIFO_OV },
	{ "rx_jabber",     GM_RXF_JAB_PKT },
2523
	{ "rx_fcs_error",   GM_RXF_FCS_ERR },
2524 2525 2526 2527 2528 2529 2530 2531 2532

	{ "tx_64_byte_packets", GM_TXF_64B },
	{ "tx_65_to_127_byte_packets", GM_TXF_127B },
	{ "tx_128_to_255_byte_packets", GM_TXF_255B },
	{ "tx_256_to_511_byte_packets", GM_TXF_511B },
	{ "tx_512_to_1023_byte_packets", GM_TXF_1023B },
	{ "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
	{ "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
	{ "tx_fifo_underrun", GM_TXE_FIFO_UR },
2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546
};

static u32 sky2_get_rx_csum(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	return sky2->rx_csum;
}

static int sky2_set_rx_csum(struct net_device *dev, u32 data)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	sky2->rx_csum = data;
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Stephen Hemminger 已提交
2547

2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559
	sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
		     data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);

	return 0;
}

static u32 sky2_get_msglevel(struct net_device *netdev)
{
	struct sky2_port *sky2 = netdev_priv(netdev);
	return sky2->msg_enable;
}

2560 2561 2562 2563 2564 2565 2566
static int sky2_nway_reset(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	if (sky2->autoneg != AUTONEG_ENABLE)
		return -EINVAL;

2567
	sky2_phy_reinit(sky2);
2568 2569 2570 2571

	return 0;
}

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2572
static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2573 2574 2575 2576 2577 2578
{
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	int i;

	data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
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2579
	    | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2580
	data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
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2581
	    | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2582

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2583
	for (i = 2; i < count; i++)
2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598
		data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
}

static void sky2_set_msglevel(struct net_device *netdev, u32 value)
{
	struct sky2_port *sky2 = netdev_priv(netdev);
	sky2->msg_enable = value;
}

static int sky2_get_stats_count(struct net_device *dev)
{
	return ARRAY_SIZE(sky2_stats);
}

static void sky2_get_ethtool_stats(struct net_device *dev,
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2599
				   struct ethtool_stats *stats, u64 * data)
2600 2601 2602
{
	struct sky2_port *sky2 = netdev_priv(dev);

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2603
	sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2604 2605
}

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2606
static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625
{
	int i;

	switch (stringset) {
	case ETH_SS_STATS:
		for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
			memcpy(data + i * ETH_GSTRING_LEN,
			       sky2_stats[i].name, ETH_GSTRING_LEN);
		break;
	}
}

/* Use hardware MIB variables for critical path statistics and
 * transmit feedback not reported at interrupt.
 * Other errors are accounted for in interrupt handler.
 */
static struct net_device_stats *sky2_get_stats(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
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2626
	u64 data[13];
2627

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2628
	sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2629 2630 2631 2632 2633

	sky2->net_stats.tx_bytes = data[0];
	sky2->net_stats.rx_bytes = data[1];
	sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
	sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
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2634
	sky2->net_stats.multicast = data[3] + data[5];
2635 2636 2637 2638 2639 2640 2641 2642 2643
	sky2->net_stats.collisions = data[10];
	sky2->net_stats.tx_aborted_errors = data[12];

	return &sky2->net_stats;
}

static int sky2_set_mac_address(struct net_device *dev, void *p)
{
	struct sky2_port *sky2 = netdev_priv(dev);
2644 2645 2646
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	const struct sockaddr *addr = p;
2647 2648 2649 2650 2651

	if (!is_valid_ether_addr(addr->sa_data))
		return -EADDRNOTAVAIL;

	memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2652
	memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2653
		    dev->dev_addr, ETH_ALEN);
2654
	memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2655
		    dev->dev_addr, ETH_ALEN);
2656

2657 2658 2659 2660 2661
	/* virtual address for data */
	gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);

	/* physical address: used for pause frames */
	gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2662 2663

	return 0;
2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679
}

static void sky2_set_multicast(struct net_device *dev)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
	struct dev_mc_list *list = dev->mc_list;
	u16 reg;
	u8 filter[8];

	memset(filter, 0, sizeof(filter));

	reg = gma_read16(hw, port, GM_RX_CTRL);
	reg |= GM_RXCR_UCF_ENA;

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	if (dev->flags & IFF_PROMISC)	/* promiscuous */
2681
		reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
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2682
	else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16)	/* all multicast */
2683
		memset(filter, 0xff, sizeof(filter));
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Stephen Hemminger 已提交
2684
	else if (dev->mc_count == 0)	/* no multicast */
2685 2686 2687 2688 2689 2690 2691
		reg &= ~GM_RXCR_MCF_ENA;
	else {
		int i;
		reg |= GM_RXCR_MCF_ENA;

		for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
			u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
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2692
			filter[bit / 8] |= 1 << (bit % 8);
2693 2694 2695 2696
		}
	}

	gma_write16(hw, port, GM_MC_ADDR_H1,
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2697
		    (u16) filter[0] | ((u16) filter[1] << 8));
2698
	gma_write16(hw, port, GM_MC_ADDR_H2,
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2699
		    (u16) filter[2] | ((u16) filter[3] << 8));
2700
	gma_write16(hw, port, GM_MC_ADDR_H3,
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2701
		    (u16) filter[4] | ((u16) filter[5] << 8));
2702
	gma_write16(hw, port, GM_MC_ADDR_H4,
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2703
		    (u16) filter[6] | ((u16) filter[7] << 8));
2704 2705 2706 2707 2708 2709 2710

	gma_write16(hw, port, GM_RX_CTRL, reg);
}

/* Can have one global because blinking is controlled by
 * ethtool and that is always under RTNL mutex
 */
2711
static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2712
{
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2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730
	u16 pg;

	switch (hw->chip_id) {
	case CHIP_ID_YUKON_XL:
		pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
			     on ? (PHY_M_LEDC_LOS_CTRL(1) |
				   PHY_M_LEDC_INIT_CTRL(7) |
				   PHY_M_LEDC_STA1_CTRL(7) |
				   PHY_M_LEDC_STA0_CTRL(7))
			     : 0);

		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
		break;

	default:
		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2731
		gm_phy_write(hw, port, PHY_MARV_LED_OVER,
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2732 2733 2734
			     on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
			     PHY_M_LED_MO_10(MO_LED_ON) |
			     PHY_M_LED_MO_100(MO_LED_ON) |
2735
			     PHY_M_LED_MO_1000(MO_LED_ON) |
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2736 2737 2738 2739
			     PHY_M_LED_MO_RX(MO_LED_ON)
			     : PHY_M_LED_MO_DUP(MO_LED_OFF) |
			     PHY_M_LED_MO_10(MO_LED_OFF) |
			     PHY_M_LED_MO_100(MO_LED_OFF) |
2740 2741 2742
			     PHY_M_LED_MO_1000(MO_LED_OFF) |
			     PHY_M_LED_MO_RX(MO_LED_OFF));

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Stephen Hemminger 已提交
2743
	}
2744 2745 2746 2747 2748 2749 2750 2751
}

/* blink LED's for finding board */
static int sky2_phys_id(struct net_device *dev, u32 data)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
	unsigned port = sky2->port;
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2752
	u16 ledctrl, ledover = 0;
2753
	long ms;
2754
	int interrupted;
2755 2756
	int onoff = 1;

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2757
	if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2758 2759 2760 2761 2762
		ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
	else
		ms = data * 1000;

	/* save initial values */
2763
	spin_lock_bh(&sky2->phy_lock);
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2764 2765 2766 2767 2768 2769 2770 2771 2772
	if (hw->chip_id == CHIP_ID_YUKON_XL) {
		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
		ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
	} else {
		ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
		ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
	}
2773

2774 2775
	interrupted = 0;
	while (!interrupted && ms > 0) {
2776 2777 2778
		sky2_led(hw, port, onoff);
		onoff = !onoff;

2779
		spin_unlock_bh(&sky2->phy_lock);
2780
		interrupted = msleep_interruptible(250);
2781
		spin_lock_bh(&sky2->phy_lock);
2782

2783 2784 2785 2786
		ms -= 250;
	}

	/* resume regularly scheduled programming */
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2787 2788 2789 2790 2791 2792 2793 2794 2795
	if (hw->chip_id == CHIP_ID_YUKON_XL) {
		u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
		gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
		gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
	} else {
		gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
		gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
	}
2796
	spin_unlock_bh(&sky2->phy_lock);
2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820

	return 0;
}

static void sky2_get_pauseparam(struct net_device *dev,
				struct ethtool_pauseparam *ecmd)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	ecmd->tx_pause = sky2->tx_pause;
	ecmd->rx_pause = sky2->rx_pause;
	ecmd->autoneg = sky2->autoneg;
}

static int sky2_set_pauseparam(struct net_device *dev,
			       struct ethtool_pauseparam *ecmd)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	int err = 0;

	sky2->autoneg = ecmd->autoneg;
	sky2->tx_pause = ecmd->tx_pause != 0;
	sky2->rx_pause = ecmd->rx_pause != 0;

2821
	sky2_phy_reinit(sky2);
2822 2823 2824 2825

	return err;
}

2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865
static int sky2_get_coalesce(struct net_device *dev,
			     struct ethtool_coalesce *ecmd)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;

	if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
		ecmd->tx_coalesce_usecs = 0;
	else {
		u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
		ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
	}
	ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);

	if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
		ecmd->rx_coalesce_usecs = 0;
	else {
		u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
		ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
	}
	ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);

	if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
		ecmd->rx_coalesce_usecs_irq = 0;
	else {
		u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
		ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
	}

	ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);

	return 0;
}

/* Note: this affect both ports */
static int sky2_set_coalesce(struct net_device *dev,
			     struct ethtool_coalesce *ecmd)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	struct sky2_hw *hw = sky2->hw;
2866
	const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
2867

2868 2869 2870
	if (ecmd->tx_coalesce_usecs > tmax ||
	    ecmd->rx_coalesce_usecs > tmax ||
	    ecmd->rx_coalesce_usecs_irq > tmax)
2871 2872
		return -EINVAL;

2873
	if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2874
		return -EINVAL;
2875
	if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2876
		return -EINVAL;
2877
	if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900
		return -EINVAL;

	if (ecmd->tx_coalesce_usecs == 0)
		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
	else {
		sky2_write32(hw, STAT_TX_TIMER_INI,
			     sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
		sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
	}
	sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);

	if (ecmd->rx_coalesce_usecs == 0)
		sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
	else {
		sky2_write32(hw, STAT_LEV_TIMER_INI,
			     sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
		sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
	}
	sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);

	if (ecmd->rx_coalesce_usecs_irq == 0)
		sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
	else {
2901
		sky2_write32(hw, STAT_ISR_TIMER_INI,
2902 2903 2904 2905 2906 2907 2908
			     sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
		sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
	}
	sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
	return 0;
}

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2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942
static void sky2_get_ringparam(struct net_device *dev,
			       struct ethtool_ringparam *ering)
{
	struct sky2_port *sky2 = netdev_priv(dev);

	ering->rx_max_pending = RX_MAX_PENDING;
	ering->rx_mini_max_pending = 0;
	ering->rx_jumbo_max_pending = 0;
	ering->tx_max_pending = TX_RING_SIZE - 1;

	ering->rx_pending = sky2->rx_pending;
	ering->rx_mini_pending = 0;
	ering->rx_jumbo_pending = 0;
	ering->tx_pending = sky2->tx_pending;
}

static int sky2_set_ringparam(struct net_device *dev,
			      struct ethtool_ringparam *ering)
{
	struct sky2_port *sky2 = netdev_priv(dev);
	int err = 0;

	if (ering->rx_pending > RX_MAX_PENDING ||
	    ering->rx_pending < 8 ||
	    ering->tx_pending < MAX_SKB_TX_LE ||
	    ering->tx_pending > TX_RING_SIZE - 1)
		return -EINVAL;

	if (netif_running(dev))
		sky2_down(dev);

	sky2->rx_pending = ering->rx_pending;
	sky2->tx_pending = ering->tx_pending;

2943
	if (netif_running(dev)) {
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Stephen Hemminger 已提交
2944
		err = sky2_up(dev);
2945 2946
		if (err)
			dev_close(dev);
2947 2948
		else
			sky2_set_multicast(dev);
2949
	}
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2950 2951 2952 2953 2954 2955

	return err;
}

static int sky2_get_regs_len(struct net_device *dev)
{
2956
	return 0x4000;
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2957 2958 2959 2960
}

/*
 * Returns copy of control register region
2961
 * Note: access to the RAM address register set will cause timeouts.
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2962 2963 2964 2965 2966 2967 2968
 */
static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
			  void *p)
{
	const struct sky2_port *sky2 = netdev_priv(dev);
	const void __iomem *io = sky2->hw->regs;

2969
	BUG_ON(regs->len < B3_RI_WTO_R1);
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2970
	regs->version = 1;
2971
	memset(p, 0, regs->len);
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2972

2973 2974 2975 2976 2977
	memcpy_fromio(p, io, B3_RAM_ADDR);

	memcpy_fromio(p + B3_RI_WTO_R1,
		      io + B3_RI_WTO_R1,
		      regs->len - B3_RI_WTO_R1);
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2978
}
2979 2980

static struct ethtool_ops sky2_ethtool_ops = {
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2981 2982 2983 2984 2985
	.get_settings = sky2_get_settings,
	.set_settings = sky2_set_settings,
	.get_drvinfo = sky2_get_drvinfo,
	.get_msglevel = sky2_get_msglevel,
	.set_msglevel = sky2_set_msglevel,
2986
	.nway_reset   = sky2_nway_reset,
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2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998
	.get_regs_len = sky2_get_regs_len,
	.get_regs = sky2_get_regs,
	.get_link = ethtool_op_get_link,
	.get_sg = ethtool_op_get_sg,
	.set_sg = ethtool_op_set_sg,
	.get_tx_csum = ethtool_op_get_tx_csum,
	.set_tx_csum = ethtool_op_set_tx_csum,
	.get_tso = ethtool_op_get_tso,
	.set_tso = ethtool_op_set_tso,
	.get_rx_csum = sky2_get_rx_csum,
	.set_rx_csum = sky2_set_rx_csum,
	.get_strings = sky2_get_strings,
2999 3000
	.get_coalesce = sky2_get_coalesce,
	.set_coalesce = sky2_set_coalesce,
S
Stephen Hemminger 已提交
3001 3002
	.get_ringparam = sky2_get_ringparam,
	.set_ringparam = sky2_set_ringparam,
3003 3004
	.get_pauseparam = sky2_get_pauseparam,
	.set_pauseparam = sky2_set_pauseparam,
S
Stephen Hemminger 已提交
3005
	.phys_id = sky2_phys_id,
3006 3007
	.get_stats_count = sky2_get_stats_count,
	.get_ethtool_stats = sky2_get_ethtool_stats,
3008
	.get_perm_addr	= ethtool_op_get_perm_addr,
3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024
};

/* Initialize network device */
static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
						     unsigned port, int highmem)
{
	struct sky2_port *sky2;
	struct net_device *dev = alloc_etherdev(sizeof(*sky2));

	if (!dev) {
		printk(KERN_ERR "sky2 etherdev alloc failed");
		return NULL;
	}

	SET_MODULE_OWNER(dev);
	SET_NETDEV_DEV(dev, &hw->pdev->dev);
3025
	dev->irq = hw->pdev->irq;
3026 3027
	dev->open = sky2_up;
	dev->stop = sky2_down;
3028
	dev->do_ioctl = sky2_ioctl;
3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051
	dev->hard_start_xmit = sky2_xmit_frame;
	dev->get_stats = sky2_get_stats;
	dev->set_multicast_list = sky2_set_multicast;
	dev->set_mac_address = sky2_set_mac_address;
	dev->change_mtu = sky2_change_mtu;
	SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
	dev->tx_timeout = sky2_tx_timeout;
	dev->watchdog_timeo = TX_WATCHDOG;
	if (port == 0)
		dev->poll = sky2_poll;
	dev->weight = NAPI_WEIGHT;
#ifdef CONFIG_NET_POLL_CONTROLLER
	dev->poll_controller = sky2_netpoll;
#endif

	sky2 = netdev_priv(dev);
	sky2->netdev = dev;
	sky2->hw = hw;
	sky2->msg_enable = netif_msg_init(debug, default_msg);

	spin_lock_init(&sky2->tx_lock);
	/* Auto speed and flow control */
	sky2->autoneg = AUTONEG_ENABLE;
3052
	sky2->tx_pause = 1;
3053 3054 3055 3056
	sky2->rx_pause = 1;
	sky2->duplex = -1;
	sky2->speed = -1;
	sky2->advertising = sky2_supported_modes(hw);
3057

3058
	/* Receive checksum disabled for Yukon XL
3059 3060 3061 3062 3063
	 * because of observed problems with incorrect
	 * values when multiple packets are received in one interrupt
	 */
	sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL);

3064
	spin_lock_init(&sky2->phy_lock);
S
Stephen Hemminger 已提交
3065
	sky2->tx_pending = TX_DEF_PENDING;
3066
	sky2->rx_pending = RX_DEF_PENDING;
3067
	sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3068 3069 3070 3071 3072

	hw->dev[port] = dev;

	sky2->port = port;

3073 3074 3075
	dev->features |= NETIF_F_LLTX;
	if (hw->chip_id != CHIP_ID_YUKON_EC_U)
		dev->features |= NETIF_F_TSO;
3076 3077
	if (highmem)
		dev->features |= NETIF_F_HIGHDMA;
S
Stephen Hemminger 已提交
3078
	dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3079

3080 3081 3082 3083 3084 3085
#ifdef SKY2_VLAN_TAG_USED
	dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
	dev->vlan_rx_register = sky2_vlan_rx_register;
	dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
#endif

3086
	/* read the mac address */
S
Stephen Hemminger 已提交
3087
	memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3088
	memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3089 3090 3091 3092 3093 3094 3095 3096

	/* device is off until link detection */
	netif_carrier_off(dev);
	netif_stop_queue(dev);

	return dev;
}

3097
static void __devinit sky2_show_addr(struct net_device *dev)
3098 3099 3100 3101 3102 3103 3104 3105 3106 3107
{
	const struct sky2_port *sky2 = netdev_priv(dev);

	if (netif_msg_probe(sky2))
		printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
		       dev->name,
		       dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
		       dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
}

3108 3109 3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167
/* Handle software interrupt used during MSI test */
static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
					    struct pt_regs *regs)
{
	struct sky2_hw *hw = dev_id;
	u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);

	if (status == 0)
		return IRQ_NONE;

	if (status & Y2_IS_IRQ_SW) {
		hw->msi_detected = 1;
		wake_up(&hw->msi_wait);
		sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
	}
	sky2_write32(hw, B0_Y2_SP_ICR, 2);

	return IRQ_HANDLED;
}

/* Test interrupt path by forcing a a software IRQ */
static int __devinit sky2_test_msi(struct sky2_hw *hw)
{
	struct pci_dev *pdev = hw->pdev;
	int err;

	sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);

	err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw);
	if (err) {
		printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
		       pci_name(pdev), pdev->irq);
		return err;
	}

	init_waitqueue_head (&hw->msi_wait);

	sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
	wmb();

	wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);

	if (!hw->msi_detected) {
		/* MSI test failed, go back to INTx mode */
		printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
		       "switching to INTx mode. Please report this failure to "
		       "the PCI maintainer and include system chipset information.\n",
		       pci_name(pdev));

		err = -EOPNOTSUPP;
		sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
	}

	sky2_write32(hw, B0_IMSK, 0);

	free_irq(pdev->irq, hw);

	return err;
}

3168 3169 3170
static int __devinit sky2_probe(struct pci_dev *pdev,
				const struct pci_device_id *ent)
{
S
Stephen Hemminger 已提交
3171
	struct net_device *dev, *dev1 = NULL;
3172
	struct sky2_hw *hw;
3173
	int err, pm_cap, using_dac = 0;
3174

S
Stephen Hemminger 已提交
3175 3176
	err = pci_enable_device(pdev);
	if (err) {
3177 3178 3179 3180 3181
		printk(KERN_ERR PFX "%s cannot enable PCI device\n",
		       pci_name(pdev));
		goto err_out;
	}

S
Stephen Hemminger 已提交
3182 3183
	err = pci_request_regions(pdev, DRV_NAME);
	if (err) {
3184 3185
		printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
		       pci_name(pdev));
S
Stephen Hemminger 已提交
3186
		goto err_out;
3187 3188 3189 3190
	}

	pci_set_master(pdev);

3191 3192 3193 3194 3195 3196 3197 3198 3199
	/* Find power-management capability. */
	pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
	if (pm_cap == 0) {
		printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
		       "aborting.\n");
		err = -EIO;
		goto err_out_free_regions;
	}

3200 3201 3202 3203 3204 3205 3206 3207 3208
	if (sizeof(dma_addr_t) > sizeof(u32) &&
	    !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
		using_dac = 1;
		err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
		if (err < 0) {
			printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
			       "for consistent allocations\n", pci_name(pdev));
			goto err_out_free_regions;
		}
3209

3210
	} else {
3211 3212 3213 3214 3215 3216 3217
		err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
		if (err) {
			printk(KERN_ERR PFX "%s no usable DMA configuration\n",
			       pci_name(pdev));
			goto err_out_free_regions;
		}
	}
3218

3219
	err = -ENOMEM;
S
Stephen Hemminger 已提交
3220
	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3221 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231 3232 3233 3234
	if (!hw) {
		printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
		       pci_name(pdev));
		goto err_out_free_regions;
	}

	hw->pdev = pdev;

	hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
	if (!hw->regs) {
		printk(KERN_ERR PFX "%s: cannot map device registers\n",
		       pci_name(pdev));
		goto err_out_free_hw;
	}
3235
	hw->pm_cap = pm_cap;
3236

3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247
#ifdef __BIG_ENDIAN
	/* byte swap descriptors in hardware */
	{
		u32 reg;

		reg = sky2_pci_read32(hw, PCI_DEV_REG2);
		reg |= PCI_REV_DESC;
		sky2_pci_write32(hw, PCI_DEV_REG2, reg);
	}
#endif

3248 3249 3250 3251 3252 3253
	/* ring for status responses */
	hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
					 &hw->st_dma);
	if (!hw->st_le)
		goto err_out_iounmap;

3254 3255
	err = sky2_reset(hw);
	if (err)
S
Stephen Hemminger 已提交
3256
		goto err_out_iounmap;
3257

3258 3259
	printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
	       DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
3260
	       yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
S
Stephen Hemminger 已提交
3261
	       hw->chip_id, hw->chip_rev);
3262

S
Stephen Hemminger 已提交
3263 3264
	dev = sky2_init_netdev(hw, 0, using_dac);
	if (!dev)
3265 3266
		goto err_out_free_pci;

S
Stephen Hemminger 已提交
3267 3268
	err = register_netdev(dev);
	if (err) {
3269 3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280
		printk(KERN_ERR PFX "%s: cannot register net device\n",
		       pci_name(pdev));
		goto err_out_free_netdev;
	}

	sky2_show_addr(dev);

	if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
		if (register_netdev(dev1) == 0)
			sky2_show_addr(dev1);
		else {
			/* Failure to register second port need not be fatal */
S
Stephen Hemminger 已提交
3281 3282
			printk(KERN_WARNING PFX
			       "register of second port failed\n");
3283 3284 3285 3286 3287
			hw->dev[1] = NULL;
			free_netdev(dev1);
		}
	}

3288 3289 3290 3291 3292 3293 3294 3295 3296
	if (!disable_msi && pci_enable_msi(pdev) == 0) {
		err = sky2_test_msi(hw);
		if (err == -EOPNOTSUPP)
 			pci_disable_msi(pdev);
		else if (err)
			goto err_out_unregister;
 	}

	err = request_irq(pdev->irq,  sky2_intr, SA_SHIRQ, DRV_NAME, hw);
S
Stephen Hemminger 已提交
3297 3298 3299 3300 3301 3302
	if (err) {
		printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
		       pci_name(pdev), pdev->irq);
		goto err_out_unregister;
	}

3303
	sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
S
Stephen Hemminger 已提交
3304

3305 3306
	setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) dev);

S
Stephen Hemminger 已提交
3307 3308
	pci_set_drvdata(pdev, hw);

3309 3310
	return 0;

S
Stephen Hemminger 已提交
3311
err_out_unregister:
3312
	pci_disable_msi(pdev);
S
Stephen Hemminger 已提交
3313 3314 3315 3316 3317
	if (dev1) {
		unregister_netdev(dev1);
		free_netdev(dev1);
	}
	unregister_netdev(dev);
3318 3319 3320
err_out_free_netdev:
	free_netdev(dev);
err_out_free_pci:
S
Stephen Hemminger 已提交
3321
	sky2_write8(hw, B0_CTST, CS_RST_SET);
3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335
	pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
err_out_iounmap:
	iounmap(hw->regs);
err_out_free_hw:
	kfree(hw);
err_out_free_regions:
	pci_release_regions(pdev);
	pci_disable_device(pdev);
err_out:
	return err;
}

static void __devexit sky2_remove(struct pci_dev *pdev)
{
S
Stephen Hemminger 已提交
3336
	struct sky2_hw *hw = pci_get_drvdata(pdev);
3337 3338
	struct net_device *dev0, *dev1;

S
Stephen Hemminger 已提交
3339
	if (!hw)
3340 3341
		return;

3342 3343 3344
	del_timer_sync(&hw->idle_timer);

	sky2_write32(hw, B0_IMSK, 0);
3345
	dev0 = hw->dev[0];
S
Stephen Hemminger 已提交
3346 3347 3348
	dev1 = hw->dev[1];
	if (dev1)
		unregister_netdev(dev1);
3349 3350
	unregister_netdev(dev0);

3351
	sky2_set_power_state(hw, PCI_D3hot);
3352
	sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
S
Stephen Hemminger 已提交
3353
	sky2_write8(hw, B0_CTST, CS_RST_SET);
3354
	sky2_read8(hw, B0_CTST);
3355 3356

	free_irq(pdev->irq, hw);
3357
	pci_disable_msi(pdev);
S
Stephen Hemminger 已提交
3358
	pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3359 3360
	pci_release_regions(pdev);
	pci_disable_device(pdev);
S
Stephen Hemminger 已提交
3361

3362 3363 3364 3365 3366
	if (dev1)
		free_netdev(dev1);
	free_netdev(dev0);
	iounmap(hw->regs);
	kfree(hw);
3367

3368 3369 3370 3371 3372 3373
	pci_set_drvdata(pdev, NULL);
}

#ifdef CONFIG_PM
static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
{
S
Stephen Hemminger 已提交
3374
	struct sky2_hw *hw = pci_get_drvdata(pdev);
3375
	int i;
3376 3377 3378 3379 3380

	for (i = 0; i < 2; i++) {
		struct net_device *dev = hw->dev[i];

		if (dev) {
3381 3382 3383 3384
			if (!netif_running(dev))
				continue;

			sky2_down(dev);
3385 3386 3387 3388
			netif_device_detach(dev);
		}
	}

3389
	return sky2_set_power_state(hw, pci_choose_state(pdev, state));
3390 3391 3392 3393
}

static int sky2_resume(struct pci_dev *pdev)
{
S
Stephen Hemminger 已提交
3394
	struct sky2_hw *hw = pci_get_drvdata(pdev);
3395
	int i, err;
3396 3397 3398

	pci_restore_state(pdev);
	pci_enable_wake(pdev, PCI_D0, 0);
3399 3400 3401
	err = sky2_set_power_state(hw, PCI_D0);
	if (err)
		goto out;
3402

3403 3404 3405
	err = sky2_reset(hw);
	if (err)
		goto out;
3406 3407 3408

	for (i = 0; i < 2; i++) {
		struct net_device *dev = hw->dev[i];
3409 3410 3411 3412 3413 3414 3415 3416
		if (dev && netif_running(dev)) {
			netif_device_attach(dev);
			err = sky2_up(dev);
			if (err) {
				printk(KERN_ERR PFX "%s: could not up: %d\n",
				       dev->name, err);
				dev_close(dev);
				break;
3417
			}
3418 3419
		}
	}
3420 3421
out:
	return err;
3422 3423 3424 3425
}
#endif

static struct pci_driver sky2_driver = {
S
Stephen Hemminger 已提交
3426 3427 3428 3429
	.name = DRV_NAME,
	.id_table = sky2_id_table,
	.probe = sky2_probe,
	.remove = __devexit_p(sky2_remove),
3430
#ifdef CONFIG_PM
S
Stephen Hemminger 已提交
3431 3432
	.suspend = sky2_suspend,
	.resume = sky2_resume,
3433 3434 3435 3436 3437
#endif
};

static int __init sky2_init_module(void)
{
3438
	return pci_register_driver(&sky2_driver);
3439 3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451
}

static void __exit sky2_cleanup_module(void)
{
	pci_unregister_driver(&sky2_driver);
}

module_init(sky2_init_module);
module_exit(sky2_cleanup_module);

MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
MODULE_LICENSE("GPL");
3452
MODULE_VERSION(DRV_VERSION);