iwl-tx.c 42.6 KB
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/******************************************************************************
 *
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 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
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 *
 * Portions of this file are derived from the ipw3945 project, as well
 * as portions of the ieee80211 subsystem header files.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
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 *  Intel Linux Wireless <ilw@linux.intel.com>
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 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/

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#include <linux/etherdevice.h>
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#include <net/mac80211.h>
#include "iwl-eeprom.h"
#include "iwl-dev.h"
#include "iwl-core.h"
#include "iwl-sta.h"
#include "iwl-io.h"
#include "iwl-helpers.h"

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static const u16 default_tid_to_tx_fifo[] = {
	IWL_TX_FIFO_AC1,
	IWL_TX_FIFO_AC0,
	IWL_TX_FIFO_AC0,
	IWL_TX_FIFO_AC1,
	IWL_TX_FIFO_AC2,
	IWL_TX_FIFO_AC2,
	IWL_TX_FIFO_AC3,
	IWL_TX_FIFO_AC3,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_AC3
};

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static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
				    struct iwl_dma_ptr *ptr, size_t size)
{
	ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma);
	if (!ptr->addr)
		return -ENOMEM;
	ptr->size = size;
	return 0;
}

static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
				    struct iwl_dma_ptr *ptr)
{
	if (unlikely(!ptr->addr))
		return;

	pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma);
	memset(ptr, 0, sizeof(*ptr));
}

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/**
 * iwl_txq_update_write_ptr - Send new write index to hardware
 */
int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
{
	u32 reg = 0;
	int ret = 0;
	int txq_id = txq->q.id;

	if (txq->need_update == 0)
		return ret;

	/* if we're trying to save power */
	if (test_bit(STATUS_POWER_PMI, &priv->status)) {
		/* wake up nic if it's powered down ...
		 * uCode will wake up, and interrupt us again, so next
		 * time we'll skip this part. */
		reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);

		if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
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			IWL_DEBUG_INFO(priv, "Requesting wakeup, GP1 = 0x%x\n", reg);
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			iwl_set_bit(priv, CSR_GP_CNTRL,
				    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
			return ret;
		}

		iwl_write_direct32(priv, HBUS_TARG_WRPTR,
				     txq->q.write_ptr | (txq_id << 8));

	/* else not in power-save mode, uCode will never sleep when we're
	 * trying to tx (during RFKILL, we're not trying to tx). */
	} else
		iwl_write32(priv, HBUS_TARG_WRPTR,
			    txq->q.write_ptr | (txq_id << 8));

	txq->need_update = 0;

	return ret;
}
EXPORT_SYMBOL(iwl_txq_update_write_ptr);


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/**
 * iwl_tx_queue_free - Deallocate DMA queue.
 * @txq: Transmit queue to deallocate.
 *
 * Empty queue by removing and destroying all BD's.
 * Free all buffers.
 * 0-fill, but do not free "txq" descriptor structure.
 */
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void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
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{
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	struct iwl_tx_queue *txq = &priv->txq[txq_id];
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	struct iwl_queue *q = &txq->q;
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	struct pci_dev *dev = priv->pci_dev;
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	int i, len;
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	if (q->n_bd == 0)
		return;

	/* first, empty all BD's */
	for (; q->write_ptr != q->read_ptr;
	     q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
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		priv->cfg->ops->lib->txq_free_tfd(priv, txq);
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	len = sizeof(struct iwl_device_cmd) * q->n_window;
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	/* De-alloc array of command/tx buffers */
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	for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
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		kfree(txq->cmd[i]);
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	/* De-alloc circular buffer of TFDs */
	if (txq->q.n_bd)
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		pci_free_consistent(dev, priv->hw_params.tfd_size *
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				    txq->q.n_bd, txq->tfds, txq->q.dma_addr);
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	/* De-alloc array of per-TFD driver data */
	kfree(txq->txb);
	txq->txb = NULL;

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	/* deallocate arrays */
	kfree(txq->cmd);
	kfree(txq->meta);
	txq->cmd = NULL;
	txq->meta = NULL;

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	/* 0-fill queue descriptor structure */
	memset(txq, 0, sizeof(*txq));
}
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EXPORT_SYMBOL(iwl_tx_queue_free);
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/**
 * iwl_cmd_queue_free - Deallocate DMA queue.
 * @txq: Transmit queue to deallocate.
 *
 * Empty queue by removing and destroying all BD's.
 * Free all buffers.
 * 0-fill, but do not free "txq" descriptor structure.
 */
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void iwl_cmd_queue_free(struct iwl_priv *priv)
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{
	struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
	struct iwl_queue *q = &txq->q;
	struct pci_dev *dev = priv->pci_dev;
	int i, len;

	if (q->n_bd == 0)
		return;

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	len = sizeof(struct iwl_device_cmd) * q->n_window;
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	len += IWL_MAX_SCAN_SIZE;

	/* De-alloc array of command/tx buffers */
	for (i = 0; i <= TFD_CMD_SLOTS; i++)
		kfree(txq->cmd[i]);

	/* De-alloc circular buffer of TFDs */
	if (txq->q.n_bd)
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		pci_free_consistent(dev, priv->hw_params.tfd_size *
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				    txq->q.n_bd, txq->tfds, txq->q.dma_addr);
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	/* 0-fill queue descriptor structure */
	memset(txq, 0, sizeof(*txq));
}
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EXPORT_SYMBOL(iwl_cmd_queue_free);

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/*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
 * DMA services
 *
 * Theory of operation
 *
 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
 * of buffer descriptors, each of which points to one or more data buffers for
 * the device to read from or fill.  Driver and device exchange status of each
 * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
 * entries in each circular buffer, to protect against confusing empty and full
 * queue states.
 *
 * The device reads or writes the data in the queues via the device's several
 * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
 *
 * For Tx queue, there are low mark and high mark limits. If, after queuing
 * the packet for Tx, free space become < low mark, Tx queue stopped. When
 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
 * Tx queue resumed.
 *
 * See more detailed info in iwl-4965-hw.h.
 ***************************************************/

int iwl_queue_space(const struct iwl_queue *q)
{
	int s = q->read_ptr - q->write_ptr;

	if (q->read_ptr > q->write_ptr)
		s -= q->n_bd;

	if (s <= 0)
		s += q->n_window;
	/* keep some reserve to not confuse empty and full situations */
	s -= 2;
	if (s < 0)
		s = 0;
	return s;
}
EXPORT_SYMBOL(iwl_queue_space);


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/**
 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 */
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static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
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			  int count, int slots_num, u32 id)
{
	q->n_bd = count;
	q->n_window = slots_num;
	q->id = id;

	/* count must be power-of-two size, otherwise iwl_queue_inc_wrap
	 * and iwl_queue_dec_wrap are broken. */
	BUG_ON(!is_power_of_2(count));

	/* slots_num must be power-of-two size, otherwise
	 * get_cmd_index is broken. */
	BUG_ON(!is_power_of_2(slots_num));

	q->low_mark = q->n_window / 4;
	if (q->low_mark < 4)
		q->low_mark = 4;

	q->high_mark = q->n_window / 8;
	if (q->high_mark < 2)
		q->high_mark = 2;

	q->write_ptr = q->read_ptr = 0;

	return 0;
}

/**
 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
 */
static int iwl_tx_queue_alloc(struct iwl_priv *priv,
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			      struct iwl_tx_queue *txq, u32 id)
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{
	struct pci_dev *dev = priv->pci_dev;
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	size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
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	/* Driver private data, only for Tx (not command) queues,
	 * not shared with device. */
	if (id != IWL_CMD_QUEUE_NUM) {
		txq->txb = kmalloc(sizeof(txq->txb[0]) *
				   TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
		if (!txq->txb) {
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			IWL_ERR(priv, "kmalloc for auxiliary BD "
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				  "structures failed\n");
			goto error;
		}
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	} else {
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		txq->txb = NULL;
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	}
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	/* Circular buffer of transmit frame descriptors (TFDs),
	 * shared with device */
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	txq->tfds = pci_alloc_consistent(dev, tfd_sz, &txq->q.dma_addr);
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	if (!txq->tfds) {
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		IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
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		goto error;
	}
	txq->q.id = id;

	return 0;

 error:
	kfree(txq->txb);
	txq->txb = NULL;

	return -ENOMEM;
}

/**
 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
 */
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int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
		      int slots_num, u32 txq_id)
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{
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	int i, len;
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	int ret;
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	int actual_slots = slots_num;
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	/*
	 * Alloc buffer array for commands (Tx or other types of commands).
	 * For the command queue (#4), allocate command space + one big
	 * command for scan, since scan command is very huge; the system will
	 * not have two scans at the same time, so only one is needed.
	 * For normal Tx queues (all other queues), no super-size command
	 * space is needed.
	 */
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	if (txq_id == IWL_CMD_QUEUE_NUM)
		actual_slots++;

	txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
			    GFP_KERNEL);
	txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
			   GFP_KERNEL);

	if (!txq->meta || !txq->cmd)
		goto out_free_arrays;

	len = sizeof(struct iwl_device_cmd);
	for (i = 0; i < actual_slots; i++) {
		/* only happens for cmd queue */
		if (i == slots_num)
			len += IWL_MAX_SCAN_SIZE;
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		txq->cmd[i] = kmalloc(len, GFP_KERNEL);
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		if (!txq->cmd[i])
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			goto err;
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	}
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	/* Alloc driver data array and TFD circular buffer */
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	ret = iwl_tx_queue_alloc(priv, txq, txq_id);
	if (ret)
		goto err;
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	txq->need_update = 0;

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	/* aggregation TX queues will get their ID when aggregation begins */
	if (txq_id <= IWL_TX_FIFO_AC3)
		txq->swq_id = txq_id;

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	/* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
	 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
	BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));

	/* Initialize queue's high/low-water marks, and head/tail indexes */
	iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);

	/* Tell device where to find queue */
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	priv->cfg->ops->lib->txq_init(priv, txq);
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	return 0;
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err:
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	for (i = 0; i < actual_slots; i++)
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		kfree(txq->cmd[i]);
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out_free_arrays:
	kfree(txq->meta);
	kfree(txq->cmd);
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	return -ENOMEM;
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}
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EXPORT_SYMBOL(iwl_tx_queue_init);

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/**
 * iwl_hw_txq_ctx_free - Free TXQ Context
 *
 * Destroy all TX DMA queues and structures
 */
void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
{
	int txq_id;

	/* Tx queues */
	for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
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		if (txq_id == IWL_CMD_QUEUE_NUM)
			iwl_cmd_queue_free(priv);
		else
			iwl_tx_queue_free(priv, txq_id);
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	iwl_free_dma_ptr(priv, &priv->kw);

	iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
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}
EXPORT_SYMBOL(iwl_hw_txq_ctx_free);

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/**
 * iwl_txq_ctx_reset - Reset TX queue context
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 * Destroys all DMA structures and initialize them again
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 *
 * @param priv
 * @return error code
 */
int iwl_txq_ctx_reset(struct iwl_priv *priv)
{
	int ret = 0;
	int txq_id, slots_num;
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	unsigned long flags;
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	/* Free all tx/cmd queues and keep-warm buffer */
	iwl_hw_txq_ctx_free(priv);

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	ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
				priv->hw_params.scd_bc_tbls_size);
	if (ret) {
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		IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
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		goto error_bc_tbls;
	}
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	/* Alloc keep-warm buffer */
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	ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
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	if (ret) {
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		IWL_ERR(priv, "Keep Warm allocation failed\n");
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		goto error_kw;
	}
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	spin_lock_irqsave(&priv->lock, flags);
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	/* Turn off all Tx DMA fifos */
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	priv->cfg->ops->lib->txq_set_sched(priv, 0);

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	/* Tell NIC where to find the "keep warm" buffer */
	iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);

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	spin_unlock_irqrestore(&priv->lock, flags);

	/* Alloc and init all Tx queues, including the command queue (#4) */
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	for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
		slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
					TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
		ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
				       txq_id);
		if (ret) {
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			IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
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			goto error;
		}
	}

	return ret;

 error:
	iwl_hw_txq_ctx_free(priv);
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	iwl_free_dma_ptr(priv, &priv->kw);
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 error_kw:
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	iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
 error_bc_tbls:
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	return ret;
}
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/**
 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
 */
void iwl_txq_ctx_stop(struct iwl_priv *priv)
{
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	int ch;
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	unsigned long flags;

	/* Turn off all Tx DMA fifos */
	spin_lock_irqsave(&priv->lock, flags);

	priv->cfg->ops->lib->txq_set_sched(priv, 0);

	/* Stop each Tx DMA channel, and wait for it to be idle */
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	for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
		iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
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		iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
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				    FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
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				    1000);
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	}
	spin_unlock_irqrestore(&priv->lock, flags);

	/* Deallocate memory for all Tx queues */
	iwl_hw_txq_ctx_free(priv);
}
EXPORT_SYMBOL(iwl_txq_ctx_stop);
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/*
 * handle build REPLY_TX command notification.
 */
static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
				  struct iwl_tx_cmd *tx_cmd,
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				  struct ieee80211_tx_info *info,
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				  struct ieee80211_hdr *hdr,
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				  u8 std_id)
510
{
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	__le16 fc = hdr->frame_control;
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	__le32 tx_flags = tx_cmd->tx_flags;

	tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
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	if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
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		tx_flags |= TX_CMD_FLG_ACK_MSK;
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		if (ieee80211_is_mgmt(fc))
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			tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
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		if (ieee80211_is_probe_resp(fc) &&
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		    !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
			tx_flags |= TX_CMD_FLG_TSF_MSK;
	} else {
		tx_flags &= (~TX_CMD_FLG_ACK_MSK);
		tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
	}

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	if (ieee80211_is_back_req(fc))
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		tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;


	tx_cmd->sta_id = std_id;
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	if (ieee80211_has_morefrags(fc))
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		tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;

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	if (ieee80211_is_data_qos(fc)) {
		u8 *qc = ieee80211_get_qos_ctl(hdr);
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		tx_cmd->tid_tspec = qc[0] & 0xf;
		tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
	} else {
		tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
	}

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	priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
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	if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
		tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;

	tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
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	if (ieee80211_is_mgmt(fc)) {
		if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
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			tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
		else
			tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
	} else {
		tx_cmd->timeout.pm_frame_timeout = 0;
	}

	tx_cmd->driver_txop = 0;
	tx_cmd->tx_flags = tx_flags;
	tx_cmd->next_frame_len = 0;
}

#define RTS_HCCA_RETRY_LIMIT		3
#define RTS_DFAULT_RETRY_LIMIT		60

static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
			      struct iwl_tx_cmd *tx_cmd,
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			      struct ieee80211_tx_info *info,
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			      __le16 fc, int sta_id,
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			      int is_hcca)
{
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	u32 rate_flags = 0;
	int rate_idx;
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	u8 rts_retry_limit = 0;
	u8 data_retry_limit = 0;
	u8 rate_plcp;
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	rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
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			IWL_RATE_COUNT - 1);
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	rate_plcp = iwl_rates[rate_idx].plcp;

	rts_retry_limit = (is_hcca) ?
	    RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;

	if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
		rate_flags |= RATE_MCS_CCK_MSK;


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	if (ieee80211_is_probe_resp(fc)) {
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		data_retry_limit = 3;
		if (data_retry_limit < rts_retry_limit)
			rts_retry_limit = data_retry_limit;
	} else
		data_retry_limit = IWL_DEFAULT_TX_RETRY;

	if (priv->data_retry_limit != -1)
		data_retry_limit = priv->data_retry_limit;


	if (ieee80211_is_data(fc)) {
		tx_cmd->initial_rate_index = 0;
		tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
	} else {
605 606 607 608 609
		switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
		case cpu_to_le16(IEEE80211_STYPE_AUTH):
		case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
		case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
		case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
610 611 612 613 614 615 616 617 618
			if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
				tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
				tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
			}
			break;
		default:
			break;
		}

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Tomas Winkler 已提交
619 620
		priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
		rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
621 622 623 624
	}

	tx_cmd->rts_retry_limit = rts_retry_limit;
	tx_cmd->data_retry_limit = data_retry_limit;
625
	tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
626 627 628
}

static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
629
				      struct ieee80211_tx_info *info,
630 631 632 633
				      struct iwl_tx_cmd *tx_cmd,
				      struct sk_buff *skb_frag,
				      int sta_id)
{
634
	struct ieee80211_key_conf *keyconf = info->control.hw_key;
635

636
	switch (keyconf->alg) {
637 638
	case ALG_CCMP:
		tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
639
		memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
640
		if (info->flags & IEEE80211_TX_CTL_AMPDU)
641
			tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
642
		IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
643 644 645 646
		break;

	case ALG_TKIP:
		tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
647
		ieee80211_get_tkip_key(keyconf, skb_frag,
648
			IEEE80211_TKIP_P2_KEY, tx_cmd->key);
649
		IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
650 651 652 653
		break;

	case ALG_WEP:
		tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
654 655 656 657 658 659
			(keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);

		if (keyconf->keylen == WEP_KEY_LEN_128)
			tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;

		memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
660

661
		IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
662
			     "with key %d\n", keyconf->keyidx);
663 664 665
		break;

	default:
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666
		IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
667 668 669 670 671 672 673
		break;
	}
}

/*
 * start REPLY_TX command process
 */
674
int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
675 676
{
	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
677
	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
T
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678 679
	struct iwl_tx_queue *txq;
	struct iwl_queue *q;
J
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680 681
	struct iwl_device_cmd *out_cmd;
	struct iwl_cmd_meta *out_meta;
T
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682 683
	struct iwl_tx_cmd *tx_cmd;
	int swq_id, txq_id;
684 685 686
	dma_addr_t phys_addr;
	dma_addr_t txcmd_phys;
	dma_addr_t scratch_phys;
687
	u16 len, len_org;
688
	u16 seq_number = 0;
689
	__le16 fc;
690
	u8 hdr_len;
T
Tomas Winkler 已提交
691
	u8 sta_id;
692 693 694 695 696 697 698 699
	u8 wait_write_ptr = 0;
	u8 tid = 0;
	u8 *qc = NULL;
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&priv->lock, flags);
	if (iwl_is_rfkill(priv)) {
700
		IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
701 702 703
		goto drop_unlock;
	}

704
	if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
705
	     IWL_INVALID_RATE) {
706
		IWL_ERR(priv, "ERROR: No TX rate available.\n");
707 708 709
		goto drop_unlock;
	}

710
	fc = hdr->frame_control;
711 712 713

#ifdef CONFIG_IWLWIFI_DEBUG
	if (ieee80211_is_auth(fc))
714
		IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
715
	else if (ieee80211_is_assoc_req(fc))
716
		IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
717
	else if (ieee80211_is_reassoc_req(fc))
718
		IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
719 720
#endif

721
	/* drop all non-injected data frame if we are not associated */
722
	if (ieee80211_is_data(fc) &&
723
	    !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
724
	    (!iwl_is_associated(priv) ||
725
	     ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
726
	     !priv->assoc_station_added)) {
727
		IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
728 729 730
		goto drop_unlock;
	}

731
	hdr_len = ieee80211_hdrlen(fc);
732 733

	/* Find (or create) index into station table for destination station */
734 735 736 737
	if (info->flags & IEEE80211_TX_CTL_INJECTED)
		sta_id = priv->hw_params.bcast_sta_id;
	else
		sta_id = iwl_get_sta_id(priv, hdr);
738
	if (sta_id == IWL_INVALID_STATION) {
739
		IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
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740
			       hdr->addr1);
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741
		goto drop_unlock;
742 743
	}

744
	IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
745

746
	txq_id = skb_get_queue_mapping(skb);
747 748
	if (ieee80211_is_data_qos(fc)) {
		qc = ieee80211_get_qos_ctl(hdr);
749
		tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
750 751
		if (unlikely(tid >= MAX_TID_COUNT))
			goto drop_unlock;
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		seq_number = priv->stations[sta_id].tid[tid].seq_number;
		seq_number &= IEEE80211_SCTL_SEQ;
		hdr->seq_ctrl = hdr->seq_ctrl &
755
				cpu_to_le16(IEEE80211_SCTL_FRAG);
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		hdr->seq_ctrl |= cpu_to_le16(seq_number);
757 758
		seq_number += 0x10;
		/* aggregation is on for this <sta,tid> */
759
		if (info->flags & IEEE80211_TX_CTL_AMPDU)
760 761 762 763
			txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
	}

	txq = &priv->txq[txq_id];
764
	swq_id = txq->swq_id;
765 766
	q = &txq->q;

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	if (unlikely(iwl_queue_space(q) < q->high_mark))
		goto drop_unlock;

	if (ieee80211_is_data_qos(fc))
		priv->stations[sta_id].tid[tid].tfds_in_queue++;
772 773 774 775 776 777

	/* Set up driver data for this TFD */
	memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
	txq->txb[q->write_ptr].skb[0] = skb;

	/* Set up first empty entry in queue's array of Tx/cmd buffers */
778
	out_cmd = txq->cmd[q->write_ptr];
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779
	out_meta = &txq->meta[q->write_ptr];
780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795 796
	tx_cmd = &out_cmd->cmd.tx;
	memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
	memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));

	/*
	 * Set up the Tx-command (not MAC!) header.
	 * Store the chosen Tx queue and TFD index within the sequence field;
	 * after Tx, uCode's Tx response will return this value so driver can
	 * locate the frame within the tx queue and do post-tx processing.
	 */
	out_cmd->hdr.cmd = REPLY_TX;
	out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
				INDEX_TO_SEQ(q->write_ptr)));

	/* Copy MAC header from skb into command buffer */
	memcpy(tx_cmd->hdr, hdr, hdr_len);

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	/* Total # bytes to be transmitted */
	len = (u16)skb->len;
	tx_cmd->len = cpu_to_le16(len);

	if (info->control.hw_key)
		iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);

	/* TODO need this for burst mode later on */
	iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
807
	iwl_dbg_log_tx_data_frame(priv, len, hdr);
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808 809 810 811

	/* set is_hcca to 0; it probably will never be implemented */
	iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);

812
	iwl_update_stats(priv, true, fc, len);
813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832
	/*
	 * Use the first empty entry in this queue's command buffer array
	 * to contain the Tx command and MAC header concatenated together
	 * (payload data will be in another buffer).
	 * Size of this varies, due to varying MAC header length.
	 * If end is not dword aligned, we'll have 2 extra bytes at the end
	 * of the MAC header (device reads on dword boundaries).
	 * We'll tell device about this padding later.
	 */
	len = sizeof(struct iwl_tx_cmd) +
		sizeof(struct iwl_cmd_header) + hdr_len;

	len_org = len;
	len = (len + 3) & ~3;

	if (len_org != len)
		len_org = 1;
	else
		len_org = 0;

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833 834 835 836
	/* Tell NIC about any 2-byte padding after MAC header */
	if (len_org)
		tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;

837 838
	/* Physical address of this Tx command's header (not MAC header!),
	 * within command buffer array. */
T
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839
	txcmd_phys = pci_map_single(priv->pci_dev,
R
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840
				    &out_cmd->hdr, len,
841
				    PCI_DMA_BIDIRECTIONAL);
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842 843
	pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
	pci_unmap_len_set(out_meta, len, len);
844 845
	/* Add buffer containing Tx command and MAC(!) header to TFD's
	 * first entry */
846 847
	priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
						   txcmd_phys, len, 1, 0);
848

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	if (!ieee80211_has_morefrags(hdr->frame_control)) {
		txq->need_update = 1;
		if (qc)
			priv->stations[sta_id].tid[tid].seq_number = seq_number;
	} else {
		wait_write_ptr = 1;
		txq->need_update = 0;
	}
857 858 859 860 861 862 863

	/* Set up TFD's 2nd entry to point directly to remainder of skb,
	 * if any (802.11 null frames have no payload). */
	len = skb->len - hdr_len;
	if (len) {
		phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
					   len, PCI_DMA_TODEVICE);
864 865 866
		priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
							   phys_addr, len,
							   0, 0);
867 868 869
	}

	scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
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				offsetof(struct iwl_tx_cmd, scratch);

	len = sizeof(struct iwl_tx_cmd) +
		sizeof(struct iwl_cmd_header) + hdr_len;
	/* take back ownership of DMA buffer to enable update */
	pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
				    len, PCI_DMA_BIDIRECTIONAL);
877
	tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
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878
	tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
879

880 881 882
	IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
		     le16_to_cpu(out_cmd->hdr.sequence));
	IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
883 884
	iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
	iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
885 886

	/* Set up entry for this TFD in Tx byte-count array */
887 888
	if (info->flags & IEEE80211_TX_CTL_AMPDU)
		priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
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889 890 891 892
						     le16_to_cpu(tx_cmd->len));

	pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
				       len, PCI_DMA_BIDIRECTIONAL);
893 894 895 896 897 898 899 900 901

	/* Tell device the write index *just past* this latest filled TFD */
	q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
	ret = iwl_txq_update_write_ptr(priv, txq);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (ret)
		return ret;

902
	if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
903 904 905 906 907
		if (wait_write_ptr) {
			spin_lock_irqsave(&priv->lock, flags);
			txq->need_update = 1;
			iwl_txq_update_write_ptr(priv, txq);
			spin_unlock_irqrestore(&priv->lock, flags);
908
		} else {
909
			iwl_stop_queue(priv, txq->swq_id);
910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932 933 934 935
		}
	}

	return 0;

drop_unlock:
	spin_unlock_irqrestore(&priv->lock, flags);
	return -1;
}
EXPORT_SYMBOL(iwl_tx_skb);

/*************** HOST COMMAND QUEUE FUNCTIONS   *****/

/**
 * iwl_enqueue_hcmd - enqueue a uCode command
 * @priv: device private data point
 * @cmd: a point to the ucode command structure
 *
 * The function returns < 0 values to indicate the operation is
 * failed. On success, it turns the index (> 0) of command in the
 * command queue.
 */
int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
{
	struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
	struct iwl_queue *q = &txq->q;
J
Johannes Berg 已提交
936 937
	struct iwl_device_cmd *out_cmd;
	struct iwl_cmd_meta *out_meta;
938 939
	dma_addr_t phys_addr;
	unsigned long flags;
T
Tomas Winkler 已提交
940 941 942
	int len, ret;
	u32 idx;
	u16 fix_size;
943 944 945 946 947 948 949 950

	cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
	fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));

	/* If any of the command structures end up being larger than
	 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
	 * we will need to increase the size of the TFD entries */
	BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
J
Johannes Berg 已提交
951
	       !(cmd->flags & CMD_SIZE_HUGE));
952 953

	if (iwl_is_rfkill(priv)) {
954
		IWL_DEBUG_INFO(priv, "Not sending command - RF KILL\n");
955 956 957
		return -EIO;
	}

J
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958
	if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
959
		IWL_ERR(priv, "No space for Tx\n");
960 961 962 963 964
		return -ENOSPC;
	}

	spin_lock_irqsave(&priv->hcmd_lock, flags);

J
Johannes Berg 已提交
965
	idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
966
	out_cmd = txq->cmd[idx];
J
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967 968
	out_meta = &txq->meta[idx];

969
	memset(out_meta, 0, sizeof(*out_meta));	/* re-initialize to NULL */
J
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970 971 972 973 974
	out_meta->flags = cmd->flags;
	if (cmd->flags & CMD_WANT_SKB)
		out_meta->source = cmd;
	if (cmd->flags & CMD_ASYNC)
		out_meta->callback = cmd->callback;
975 976 977 978 979 980 981 982 983 984

	out_cmd->hdr.cmd = cmd->id;
	memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);

	/* At this point, the out_cmd now has all of the incoming cmd
	 * information */

	out_cmd->hdr.flags = 0;
	out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
			INDEX_TO_SEQ(q->write_ptr));
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985
	if (cmd->flags & CMD_SIZE_HUGE)
986
		out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
J
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987
	len = sizeof(struct iwl_device_cmd);
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988
	len += (idx == TFD_CMD_SLOTS) ?  IWL_MAX_SCAN_SIZE : 0;
T
Tomas Winkler 已提交
989

990

991 992 993 994
#ifdef CONFIG_IWLWIFI_DEBUG
	switch (out_cmd->hdr.cmd) {
	case REPLY_TX_LINK_QUALITY_CMD:
	case SENSITIVITY_CMD:
995
		IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
996 997 998 999 1000 1001 1002
				"%d bytes at %d[%d]:%d\n",
				get_cmd_string(out_cmd->hdr.cmd),
				out_cmd->hdr.cmd,
				le16_to_cpu(out_cmd->hdr.sequence), fix_size,
				q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
				break;
	default:
1003
		IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
1004 1005 1006 1007 1008 1009 1010
				"%d bytes at %d[%d]:%d\n",
				get_cmd_string(out_cmd->hdr.cmd),
				out_cmd->hdr.cmd,
				le16_to_cpu(out_cmd->hdr.sequence), fix_size,
				q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
	}
#endif
1011 1012
	txq->need_update = 1;

1013 1014 1015
	if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
		/* Set up entry in queue's byte count circular buffer */
		priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1016

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1017 1018
	phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
				   fix_size, PCI_DMA_BIDIRECTIONAL);
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1019 1020
	pci_unmap_addr_set(out_meta, mapping, phys_addr);
	pci_unmap_len_set(out_meta, len, fix_size);
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1021 1022 1023 1024 1025

	priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
						   phys_addr, fix_size, 1,
						   U32_PAD(cmd->len));

1026 1027 1028 1029 1030 1031 1032 1033
	/* Increment and update queue's write index */
	q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
	ret = iwl_txq_update_write_ptr(priv, txq);

	spin_unlock_irqrestore(&priv->hcmd_lock, flags);
	return ret ? ret : idx;
}

1034 1035 1036 1037 1038 1039 1040 1041
int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
{
	struct iwl_tx_queue *txq = &priv->txq[txq_id];
	struct iwl_queue *q = &txq->q;
	struct iwl_tx_info *tx_info;
	int nfreed = 0;

	if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1042
		IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1043 1044 1045 1046 1047
			  "is out of range [0-%d] %d %d.\n", txq_id,
			  index, q->n_bd, q->write_ptr, q->read_ptr);
		return 0;
	}

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	for (index = iwl_queue_inc_wrap(index, q->n_bd);
	     q->read_ptr != index;
	     q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1051 1052 1053 1054 1055

		tx_info = &txq->txb[txq->q.read_ptr];
		ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
		tx_info->skb[0] = NULL;

1056 1057 1058
		if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
			priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);

1059
		priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073
		nfreed++;
	}
	return nfreed;
}
EXPORT_SYMBOL(iwl_tx_queue_reclaim);


/**
 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
 *
 * When FW advances 'R' index, all entries between old and new 'R' index
 * need to be reclaimed. As result, some free space forms.  If there is
 * enough free space (> low mark), wake the stack that feeds us.
 */
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static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
				   int idx, int cmd_idx)
1076 1077 1078 1079 1080
{
	struct iwl_tx_queue *txq = &priv->txq[txq_id];
	struct iwl_queue *q = &txq->q;
	int nfreed = 0;

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1081
	if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1082
		IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1083
			  "is out of range [0-%d] %d %d.\n", txq_id,
T
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1084
			  idx, q->n_bd, q->write_ptr, q->read_ptr);
1085 1086 1087
		return;
	}

T
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1088
	pci_unmap_single(priv->pci_dev,
J
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1089 1090
		pci_unmap_addr(&txq->meta[cmd_idx], mapping),
		pci_unmap_len(&txq->meta[cmd_idx], len),
1091
		PCI_DMA_BIDIRECTIONAL);
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1092 1093 1094

	for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
	     q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1095

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		if (nfreed++ > 0) {
1097
			IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
1098 1099 1100
					q->write_ptr, q->read_ptr);
			queue_work(priv->workqueue, &priv->restart);
		}
1101

1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119
	}
}

/**
 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
 * @rxb: Rx buffer to reclaim
 *
 * If an Rx buffer has an async callback associated with it the callback
 * will be executed.  The attached skb (if present) will only be freed
 * if the callback returns 1
 */
void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
{
	struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
	u16 sequence = le16_to_cpu(pkt->hdr.sequence);
	int txq_id = SEQ_TO_QUEUE(sequence);
	int index = SEQ_TO_INDEX(sequence);
	int cmd_index;
1120
	bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
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	struct iwl_device_cmd *cmd;
	struct iwl_cmd_meta *meta;
1123 1124 1125 1126

	/* If a Tx command is being handled and it isn't in the actual
	 * command queue then there a command routing bug has been introduced
	 * in the queue management code. */
1127
	if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1128 1129 1130 1131
		 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
		  txq_id, sequence,
		  priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
		  priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1132
		iwl_print_hex_error(priv, pkt, 32);
1133
		return;
1134
	}
1135 1136

	cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1137
	cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
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	meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index];
1139 1140

	/* Input error checking is done when commands are added to queue. */
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	if (meta->flags & CMD_WANT_SKB) {
		meta->source->reply_skb = rxb->skb;
1143
		rxb->skb = NULL;
1144 1145
	} else if (meta->callback)
		meta->callback(priv, cmd, rxb->skb);
1146

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	iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1148

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	if (!(meta->flags & CMD_ASYNC)) {
1150 1151 1152 1153 1154 1155
		clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
		wake_up_interruptible(&priv->wait_command_queue);
	}
}
EXPORT_SYMBOL(iwl_tx_cmd_complete);

1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185
/*
 * Find first available (lowest unused) Tx Queue, mark it "active".
 * Called only when finding queue for aggregation.
 * Should never return anything < 7, because they should already
 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
 */
static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
{
	int txq_id;

	for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
		if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
			return txq_id;
	return -1;
}

int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
{
	int sta_id;
	int tx_fifo;
	int txq_id;
	int ret;
	unsigned long flags;
	struct iwl_tid_data *tid_data;

	if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
		tx_fifo = default_tid_to_tx_fifo[tid];
	else
		return -EINVAL;

1186
	IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
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			__func__, ra, tid);
1188 1189

	sta_id = iwl_find_station(priv, ra);
1190 1191
	if (sta_id == IWL_INVALID_STATION) {
		IWL_ERR(priv, "Start AGG on invalid station\n");
1192
		return -ENXIO;
1193
	}
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	if (unlikely(tid >= MAX_TID_COUNT))
		return -EINVAL;
1196 1197

	if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1198
		IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1199 1200 1201 1202
		return -ENXIO;
	}

	txq_id = iwl_txq_ctx_activate_free(priv);
1203 1204
	if (txq_id == -1) {
		IWL_ERR(priv, "No free aggregation queue available\n");
1205
		return -ENXIO;
1206
	}
1207 1208 1209 1210 1211

	spin_lock_irqsave(&priv->sta_lock, flags);
	tid_data = &priv->stations[sta_id].tid[tid];
	*ssn = SEQ_TO_SN(tid_data->seq_number);
	tid_data->agg.txq_id = txq_id;
1212
	priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id);
1213 1214 1215 1216 1217 1218 1219 1220
	spin_unlock_irqrestore(&priv->sta_lock, flags);

	ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
						  sta_id, tid, *ssn);
	if (ret)
		return ret;

	if (tid_data->tfds_in_queue == 0) {
1221
		IWL_DEBUG_HT(priv, "HW queue is empty\n");
1222 1223 1224
		tid_data->agg.state = IWL_AGG_ON;
		ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
	} else {
1225
		IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240
			     tid_data->tfds_in_queue);
		tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
	}
	return ret;
}
EXPORT_SYMBOL(iwl_tx_agg_start);

int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
{
	int tx_fifo_id, txq_id, sta_id, ssn = -1;
	struct iwl_tid_data *tid_data;
	int ret, write_ptr, read_ptr;
	unsigned long flags;

	if (!ra) {
1241
		IWL_ERR(priv, "ra = NULL\n");
1242 1243 1244
		return -EINVAL;
	}

1245 1246 1247
	if (unlikely(tid >= MAX_TID_COUNT))
		return -EINVAL;

1248 1249 1250 1251 1252 1253 1254
	if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
		tx_fifo_id = default_tid_to_tx_fifo[tid];
	else
		return -EINVAL;

	sta_id = iwl_find_station(priv, ra);

1255 1256
	if (sta_id == IWL_INVALID_STATION) {
		IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1257
		return -ENXIO;
1258
	}
1259 1260

	if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1261
		IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n");
1262 1263 1264 1265 1266 1267 1268 1269 1270

	tid_data = &priv->stations[sta_id].tid[tid];
	ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
	txq_id = tid_data->agg.txq_id;
	write_ptr = priv->txq[txq_id].q.write_ptr;
	read_ptr = priv->txq[txq_id].q.read_ptr;

	/* The queue is not empty */
	if (write_ptr != read_ptr) {
1271
		IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1272 1273 1274 1275 1276
		priv->stations[sta_id].tid[tid].agg.state =
				IWL_EMPTYING_HW_QUEUE_DELBA;
		return 0;
	}

1277
	IWL_DEBUG_HT(priv, "HW queue is empty\n");
1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303
	priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;

	spin_lock_irqsave(&priv->lock, flags);
	ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
						   tx_fifo_id);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (ret)
		return ret;

	ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);

	return 0;
}
EXPORT_SYMBOL(iwl_tx_agg_stop);

int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
{
	struct iwl_queue *q = &priv->txq[txq_id].q;
	u8 *addr = priv->stations[sta_id].sta.sta.addr;
	struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];

	switch (priv->stations[sta_id].tid[tid].agg.state) {
	case IWL_EMPTYING_HW_QUEUE_DELBA:
		/* We are reclaiming the last packet of the */
		/* aggregated HW queue */
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		if ((txq_id  == tid_data->agg.txq_id) &&
		    (q->read_ptr == q->write_ptr)) {
1306 1307
			u16 ssn = SEQ_TO_SN(tid_data->seq_number);
			int tx_fifo = default_tid_to_tx_fifo[tid];
1308
			IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1309 1310 1311 1312 1313 1314 1315 1316 1317
			priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
							     ssn, tx_fifo);
			tid_data->agg.state = IWL_AGG_OFF;
			ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
		}
		break;
	case IWL_EMPTYING_HW_QUEUE_ADDBA:
		/* We are reclaiming the last packet of the queue */
		if (tid_data->tfds_in_queue == 0) {
1318
			IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1319 1320 1321 1322 1323 1324 1325 1326 1327
			tid_data->agg.state = IWL_AGG_ON;
			ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
		}
		break;
	}
	return 0;
}
EXPORT_SYMBOL(iwl_txq_check_empty);

1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346
/**
 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
 *
 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
 * ACK vs. not.  This gets sent to mac80211, then to rate scaling algo.
 */
static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
				 struct iwl_ht_agg *agg,
				 struct iwl_compressed_ba_resp *ba_resp)

{
	int i, sh, ack;
	u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
	u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
	u64 bitmap;
	int successes = 0;
	struct ieee80211_tx_info *info;

	if (unlikely(!agg->wait_for_ba))  {
1347
		IWL_ERR(priv, "Received BA when not expected\n");
1348 1349 1350 1351 1352
		return -EINVAL;
	}

	/* Mark that the expected block-ack response arrived */
	agg->wait_for_ba = 0;
1353
	IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1354 1355

	/* Calculate shift to align block-ack bits with our Tx window bits */
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	sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1357 1358 1359 1360 1361 1362 1363
	if (sh < 0) /* tbw something is wrong with indices */
		sh += 0x100;

	/* don't use 64-bit values for now */
	bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;

	if (agg->frame_count > (64 - sh)) {
1364
		IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1365 1366 1367 1368 1369 1370 1371 1372 1373 1374
		return -1;
	}

	/* check for success or failure according to the
	 * transmitted bitmap and block-ack bitmap */
	bitmap &= agg->bitmap;

	/* For each frame attempted in aggregation,
	 * update driver's record of tx frame's status. */
	for (i = 0; i < agg->frame_count ; i++) {
1375
		ack = bitmap & (1ULL << i);
1376
		successes += !!ack;
1377
		IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1378
			ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389
			agg->start_idx + i);
	}

	info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
	memset(&info->status, 0, sizeof(info->status));
	info->flags = IEEE80211_TX_STAT_ACK;
	info->flags |= IEEE80211_TX_STAT_AMPDU;
	info->status.ampdu_ack_map = successes;
	info->status.ampdu_ack_len = agg->frame_count;
	iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);

1390
	IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407

	return 0;
}

/**
 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
 *
 * Handles block-acknowledge notification from device, which reports success
 * of frames sent via aggregation.
 */
void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
					   struct iwl_rx_mem_buffer *rxb)
{
	struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
	struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
	struct iwl_tx_queue *txq = NULL;
	struct iwl_ht_agg *agg;
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	int index;
	int sta_id;
	int tid;
1411 1412 1413 1414 1415 1416 1417 1418 1419

	/* "flow" corresponds to Tx queue */
	u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);

	/* "ssn" is start of block-ack Tx window, corresponds to index
	 * (in Tx queue's circular buffer) of first TFD/frame in window */
	u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);

	if (scd_flow >= priv->hw_params.max_txq_num) {
1420 1421
		IWL_ERR(priv,
			"BUG_ON scd_flow is bigger than number of queues\n");
1422 1423 1424 1425
		return;
	}

	txq = &priv->txq[scd_flow];
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1426 1427 1428
	sta_id = ba_resp->sta_id;
	tid = ba_resp->tid;
	agg = &priv->stations[sta_id].tid[tid].agg;
1429 1430 1431 1432 1433 1434

	/* Find index just before block-ack window */
	index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);

	/* TODO: Need to get this copy more safely - now good for debug */

1435
	IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1436 1437
			   "sta_id = %d\n",
			   agg->wait_for_ba,
J
Johannes Berg 已提交
1438
			   (u8 *) &ba_resp->sta_addr_lo32,
1439
			   ba_resp->sta_id);
1440
	IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1441 1442 1443 1444 1445 1446
			   "%d, scd_ssn = %d\n",
			   ba_resp->tid,
			   ba_resp->seq_ctl,
			   (unsigned long long)le64_to_cpu(ba_resp->bitmap),
			   ba_resp->scd_flow,
			   ba_resp->scd_ssn);
1447
	IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n",
1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459
			   agg->start_idx,
			   (unsigned long long)agg->bitmap);

	/* Update driver's record of ACK vs. not for each frame in window */
	iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);

	/* Release all TFDs before the SSN, i.e. all TFDs in front of
	 * block-ack window (we assume that they've been successfully
	 * transmitted ... if not, it's too late anyway). */
	if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
		/* calculate mac80211 ampdu sw queue to wake */
		int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
T
Tomas Winkler 已提交
1460 1461 1462 1463 1464
		priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;

		if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
		    priv->mac80211_registered &&
		    (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1465
			iwl_wake_queue(priv, txq->swq_id);
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1466 1467

		iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1468 1469 1470 1471
	}
}
EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);

1472
#ifdef CONFIG_IWLWIFI_DEBUG
1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501
#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x

const char *iwl_get_tx_fail_reason(u32 status)
{
	switch (status & TX_STATUS_MSK) {
	case TX_STATUS_SUCCESS:
		return "SUCCESS";
		TX_STATUS_ENTRY(SHORT_LIMIT);
		TX_STATUS_ENTRY(LONG_LIMIT);
		TX_STATUS_ENTRY(FIFO_UNDERRUN);
		TX_STATUS_ENTRY(MGMNT_ABORT);
		TX_STATUS_ENTRY(NEXT_FRAG);
		TX_STATUS_ENTRY(LIFE_EXPIRE);
		TX_STATUS_ENTRY(DEST_PS);
		TX_STATUS_ENTRY(ABORTED);
		TX_STATUS_ENTRY(BT_RETRY);
		TX_STATUS_ENTRY(STA_INVALID);
		TX_STATUS_ENTRY(FRAG_DROPPED);
		TX_STATUS_ENTRY(TID_DISABLE);
		TX_STATUS_ENTRY(FRAME_FLUSHED);
		TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
		TX_STATUS_ENTRY(TX_LOCKED);
		TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
	}

	return "UNKNOWN";
}
EXPORT_SYMBOL(iwl_get_tx_fail_reason);
#endif /* CONFIG_IWLWIFI_DEBUG */