iwl-tx.c 41.8 KB
Newer Older
1 2
/******************************************************************************
 *
3
 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
 *
 * Portions of this file are derived from the ipw3945 project, as well
 * as portions of the ieee80211 subsystem header files.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
25
 *  Intel Linux Wireless <ilw@linux.intel.com>
26 27 28 29
 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *
 *****************************************************************************/

30
#include <linux/etherdevice.h>
31 32 33 34 35 36 37 38
#include <net/mac80211.h>
#include "iwl-eeprom.h"
#include "iwl-dev.h"
#include "iwl-core.h"
#include "iwl-sta.h"
#include "iwl-io.h"
#include "iwl-helpers.h"

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58
static const u16 default_tid_to_tx_fifo[] = {
	IWL_TX_FIFO_AC1,
	IWL_TX_FIFO_AC0,
	IWL_TX_FIFO_AC0,
	IWL_TX_FIFO_AC1,
	IWL_TX_FIFO_AC2,
	IWL_TX_FIFO_AC2,
	IWL_TX_FIFO_AC3,
	IWL_TX_FIFO_AC3,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_NONE,
	IWL_TX_FIFO_AC3
};

59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78
static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
				    struct iwl_dma_ptr *ptr, size_t size)
{
	ptr->addr = pci_alloc_consistent(priv->pci_dev, size, &ptr->dma);
	if (!ptr->addr)
		return -ENOMEM;
	ptr->size = size;
	return 0;
}

static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
				    struct iwl_dma_ptr *ptr)
{
	if (unlikely(!ptr->addr))
		return;

	pci_free_consistent(priv->pci_dev, ptr->size, ptr->addr, ptr->dma);
	memset(ptr, 0, sizeof(*ptr));
}

79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
/**
 * iwl_txq_update_write_ptr - Send new write index to hardware
 */
int iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
{
	u32 reg = 0;
	int ret = 0;
	int txq_id = txq->q.id;

	if (txq->need_update == 0)
		return ret;

	/* if we're trying to save power */
	if (test_bit(STATUS_POWER_PMI, &priv->status)) {
		/* wake up nic if it's powered down ...
		 * uCode will wake up, and interrupt us again, so next
		 * time we'll skip this part. */
		reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);

		if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
99
			IWL_DEBUG_INFO(priv, "Requesting wakeup, GP1 = 0x%x\n", reg);
100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
			iwl_set_bit(priv, CSR_GP_CNTRL,
				    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
			return ret;
		}

		/* restore this queue's parameters in nic hardware. */
		ret = iwl_grab_nic_access(priv);
		if (ret)
			return ret;
		iwl_write_direct32(priv, HBUS_TARG_WRPTR,
				     txq->q.write_ptr | (txq_id << 8));
		iwl_release_nic_access(priv);

	/* else not in power-save mode, uCode will never sleep when we're
	 * trying to tx (during RFKILL, we're not trying to tx). */
	} else
		iwl_write32(priv, HBUS_TARG_WRPTR,
			    txq->q.write_ptr | (txq_id << 8));

	txq->need_update = 0;

	return ret;
}
EXPORT_SYMBOL(iwl_txq_update_write_ptr);


126 127 128 129 130 131 132 133
/**
 * iwl_tx_queue_free - Deallocate DMA queue.
 * @txq: Transmit queue to deallocate.
 *
 * Empty queue by removing and destroying all BD's.
 * Free all buffers.
 * 0-fill, but do not free "txq" descriptor structure.
 */
134
void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
135
{
136
	struct iwl_tx_queue *txq = &priv->txq[txq_id];
137
	struct iwl_queue *q = &txq->q;
138
	struct pci_dev *dev = priv->pci_dev;
139
	int i, len;
140 141 142 143 144 145 146

	if (q->n_bd == 0)
		return;

	/* first, empty all BD's */
	for (; q->write_ptr != q->read_ptr;
	     q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
147
		priv->cfg->ops->lib->txq_free_tfd(priv, txq);
148 149 150 151

	len = sizeof(struct iwl_cmd) * q->n_window;

	/* De-alloc array of command/tx buffers */
152
	for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
153
		kfree(txq->cmd[i]);
154 155 156

	/* De-alloc circular buffer of TFDs */
	if (txq->q.n_bd)
157
		pci_free_consistent(dev, priv->hw_params.tfd_size *
T
Tomas Winkler 已提交
158
				    txq->q.n_bd, txq->tfds, txq->q.dma_addr);
159 160 161 162 163 164 165 166

	/* De-alloc array of per-TFD driver data */
	kfree(txq->txb);
	txq->txb = NULL;

	/* 0-fill queue descriptor structure */
	memset(txq, 0, sizeof(*txq));
}
167
EXPORT_SYMBOL(iwl_tx_queue_free);
168 169 170 171 172 173 174 175 176

/**
 * iwl_cmd_queue_free - Deallocate DMA queue.
 * @txq: Transmit queue to deallocate.
 *
 * Empty queue by removing and destroying all BD's.
 * Free all buffers.
 * 0-fill, but do not free "txq" descriptor structure.
 */
177
void iwl_cmd_queue_free(struct iwl_priv *priv)
178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195
{
	struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
	struct iwl_queue *q = &txq->q;
	struct pci_dev *dev = priv->pci_dev;
	int i, len;

	if (q->n_bd == 0)
		return;

	len = sizeof(struct iwl_cmd) * q->n_window;
	len += IWL_MAX_SCAN_SIZE;

	/* De-alloc array of command/tx buffers */
	for (i = 0; i <= TFD_CMD_SLOTS; i++)
		kfree(txq->cmd[i]);

	/* De-alloc circular buffer of TFDs */
	if (txq->q.n_bd)
196
		pci_free_consistent(dev, priv->hw_params.tfd_size *
T
Tomas Winkler 已提交
197
				    txq->q.n_bd, txq->tfds, txq->q.dma_addr);
198 199 200 201

	/* 0-fill queue descriptor structure */
	memset(txq, 0, sizeof(*txq));
}
202 203
EXPORT_SYMBOL(iwl_cmd_queue_free);

204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244
/*************** DMA-QUEUE-GENERAL-FUNCTIONS  *****
 * DMA services
 *
 * Theory of operation
 *
 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
 * of buffer descriptors, each of which points to one or more data buffers for
 * the device to read from or fill.  Driver and device exchange status of each
 * queue via "read" and "write" pointers.  Driver keeps minimum of 2 empty
 * entries in each circular buffer, to protect against confusing empty and full
 * queue states.
 *
 * The device reads or writes the data in the queues via the device's several
 * DMA/FIFO channels.  Each queue is mapped to a single DMA channel.
 *
 * For Tx queue, there are low mark and high mark limits. If, after queuing
 * the packet for Tx, free space become < low mark, Tx queue stopped. When
 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
 * Tx queue resumed.
 *
 * See more detailed info in iwl-4965-hw.h.
 ***************************************************/

int iwl_queue_space(const struct iwl_queue *q)
{
	int s = q->read_ptr - q->write_ptr;

	if (q->read_ptr > q->write_ptr)
		s -= q->n_bd;

	if (s <= 0)
		s += q->n_window;
	/* keep some reserve to not confuse empty and full situations */
	s -= 2;
	if (s < 0)
		s = 0;
	return s;
}
EXPORT_SYMBOL(iwl_queue_space);


245 246 247
/**
 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
 */
248
static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279
			  int count, int slots_num, u32 id)
{
	q->n_bd = count;
	q->n_window = slots_num;
	q->id = id;

	/* count must be power-of-two size, otherwise iwl_queue_inc_wrap
	 * and iwl_queue_dec_wrap are broken. */
	BUG_ON(!is_power_of_2(count));

	/* slots_num must be power-of-two size, otherwise
	 * get_cmd_index is broken. */
	BUG_ON(!is_power_of_2(slots_num));

	q->low_mark = q->n_window / 4;
	if (q->low_mark < 4)
		q->low_mark = 4;

	q->high_mark = q->n_window / 8;
	if (q->high_mark < 2)
		q->high_mark = 2;

	q->write_ptr = q->read_ptr = 0;

	return 0;
}

/**
 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
 */
static int iwl_tx_queue_alloc(struct iwl_priv *priv,
280
			      struct iwl_tx_queue *txq, u32 id)
281 282
{
	struct pci_dev *dev = priv->pci_dev;
283
	size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
284 285 286 287 288 289 290

	/* Driver private data, only for Tx (not command) queues,
	 * not shared with device. */
	if (id != IWL_CMD_QUEUE_NUM) {
		txq->txb = kmalloc(sizeof(txq->txb[0]) *
				   TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
		if (!txq->txb) {
291
			IWL_ERR(priv, "kmalloc for auxiliary BD "
292 293 294
				  "structures failed\n");
			goto error;
		}
295
	} else {
296
		txq->txb = NULL;
297
	}
298 299 300

	/* Circular buffer of transmit frame descriptors (TFDs),
	 * shared with device */
301
	txq->tfds = pci_alloc_consistent(dev, tfd_sz, &txq->q.dma_addr);
302

T
Tomas Winkler 已提交
303
	if (!txq->tfds) {
304
		IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320
		goto error;
	}
	txq->q.id = id;

	return 0;

 error:
	kfree(txq->txb);
	txq->txb = NULL;

	return -ENOMEM;
}

/**
 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
 */
321 322
int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
		      int slots_num, u32 txq_id)
323
{
324
	int i, len;
325
	int ret;
326 327 328 329 330 331 332 333 334

	/*
	 * Alloc buffer array for commands (Tx or other types of commands).
	 * For the command queue (#4), allocate command space + one big
	 * command for scan, since scan command is very huge; the system will
	 * not have two scans at the same time, so only one is needed.
	 * For normal Tx queues (all other queues), no super-size command
	 * space is needed.
	 */
335 336 337 338 339 340 341 342 343
	len = sizeof(struct iwl_cmd);
	for (i = 0; i <= slots_num; i++) {
		if (i == slots_num) {
			if (txq_id == IWL_CMD_QUEUE_NUM)
				len += IWL_MAX_SCAN_SIZE;
			else
				continue;
		}

344
		txq->cmd[i] = kmalloc(len, GFP_KERNEL);
345
		if (!txq->cmd[i])
346
			goto err;
347
	}
348 349

	/* Alloc driver data array and TFD circular buffer */
350 351 352
	ret = iwl_tx_queue_alloc(priv, txq, txq_id);
	if (ret)
		goto err;
353 354 355 356 357 358 359 360 361 362 363

	txq->need_update = 0;

	/* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
	 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
	BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));

	/* Initialize queue's high/low-water marks, and head/tail indexes */
	iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);

	/* Tell device where to find queue */
364
	priv->cfg->ops->lib->txq_init(priv, txq);
365 366

	return 0;
367 368 369 370 371 372 373 374 375 376 377
err:
	for (i = 0; i < slots_num; i++) {
		kfree(txq->cmd[i]);
		txq->cmd[i] = NULL;
	}

	if (txq_id == IWL_CMD_QUEUE_NUM) {
		kfree(txq->cmd[slots_num]);
		txq->cmd[slots_num] = NULL;
	}
	return -ENOMEM;
378
}
379 380
EXPORT_SYMBOL(iwl_tx_queue_init);

381 382 383 384 385 386 387 388 389 390 391
/**
 * iwl_hw_txq_ctx_free - Free TXQ Context
 *
 * Destroy all TX DMA queues and structures
 */
void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
{
	int txq_id;

	/* Tx queues */
	for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
392 393 394 395
		if (txq_id == IWL_CMD_QUEUE_NUM)
			iwl_cmd_queue_free(priv);
		else
			iwl_tx_queue_free(priv, txq_id);
396

397 398 399
	iwl_free_dma_ptr(priv, &priv->kw);

	iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
400 401 402
}
EXPORT_SYMBOL(iwl_hw_txq_ctx_free);

403 404
/**
 * iwl_txq_ctx_reset - Reset TX queue context
T
Tomas Winkler 已提交
405
 * Destroys all DMA structures and initialize them again
406 407 408 409 410 411 412 413
 *
 * @param priv
 * @return error code
 */
int iwl_txq_ctx_reset(struct iwl_priv *priv)
{
	int ret = 0;
	int txq_id, slots_num;
414
	unsigned long flags;
415 416 417 418

	/* Free all tx/cmd queues and keep-warm buffer */
	iwl_hw_txq_ctx_free(priv);

419 420 421
	ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
				priv->hw_params.scd_bc_tbls_size);
	if (ret) {
422
		IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
423 424
		goto error_bc_tbls;
	}
425
	/* Alloc keep-warm buffer */
426
	ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
427
	if (ret) {
428
		IWL_ERR(priv, "Keep Warm allocation failed\n");
429 430
		goto error_kw;
	}
431 432 433 434 435 436
	spin_lock_irqsave(&priv->lock, flags);
	ret = iwl_grab_nic_access(priv);
	if (unlikely(ret)) {
		spin_unlock_irqrestore(&priv->lock, flags);
		goto error_reset;
	}
437 438

	/* Turn off all Tx DMA fifos */
439 440
	priv->cfg->ops->lib->txq_set_sched(priv, 0);

441 442 443
	/* Tell NIC where to find the "keep warm" buffer */
	iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);

444 445 446 447
	iwl_release_nic_access(priv);
	spin_unlock_irqrestore(&priv->lock, flags);

	/* Alloc and init all Tx queues, including the command queue (#4) */
448 449 450 451 452 453
	for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
		slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
					TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
		ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
				       txq_id);
		if (ret) {
454
			IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
455 456 457 458 459 460 461 462 463
			goto error;
		}
	}

	return ret;

 error:
	iwl_hw_txq_ctx_free(priv);
 error_reset:
464
	iwl_free_dma_ptr(priv, &priv->kw);
465
 error_kw:
466 467
	iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
 error_bc_tbls:
468 469
	return ret;
}
470

471 472 473 474 475
/**
 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
 */
void iwl_txq_ctx_stop(struct iwl_priv *priv)
{
476
	int ch;
477 478 479 480 481 482 483 484 485 486 487 488
	unsigned long flags;

	/* Turn off all Tx DMA fifos */
	spin_lock_irqsave(&priv->lock, flags);
	if (iwl_grab_nic_access(priv)) {
		spin_unlock_irqrestore(&priv->lock, flags);
		return;
	}

	priv->cfg->ops->lib->txq_set_sched(priv, 0);

	/* Stop each Tx DMA channel, and wait for it to be idle */
489 490
	for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
		iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
491
		iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
492
				    FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
493
				    1000);
494 495 496 497 498 499 500 501
	}
	iwl_release_nic_access(priv);
	spin_unlock_irqrestore(&priv->lock, flags);

	/* Deallocate memory for all Tx queues */
	iwl_hw_txq_ctx_free(priv);
}
EXPORT_SYMBOL(iwl_txq_ctx_stop);
502 503 504 505 506 507

/*
 * handle build REPLY_TX command notification.
 */
static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
				  struct iwl_tx_cmd *tx_cmd,
508
				  struct ieee80211_tx_info *info,
509
				  struct ieee80211_hdr *hdr,
510
				  u8 std_id)
511
{
512
	__le16 fc = hdr->frame_control;
513 514 515
	__le32 tx_flags = tx_cmd->tx_flags;

	tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
516
	if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
517
		tx_flags |= TX_CMD_FLG_ACK_MSK;
518
		if (ieee80211_is_mgmt(fc))
519
			tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
520
		if (ieee80211_is_probe_resp(fc) &&
521 522 523 524 525 526 527
		    !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
			tx_flags |= TX_CMD_FLG_TSF_MSK;
	} else {
		tx_flags &= (~TX_CMD_FLG_ACK_MSK);
		tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
	}

528
	if (ieee80211_is_back_req(fc))
529 530 531 532
		tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;


	tx_cmd->sta_id = std_id;
533
	if (ieee80211_has_morefrags(fc))
534 535
		tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;

536 537
	if (ieee80211_is_data_qos(fc)) {
		u8 *qc = ieee80211_get_qos_ctl(hdr);
538 539 540 541 542 543
		tx_cmd->tid_tspec = qc[0] & 0xf;
		tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
	} else {
		tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
	}

544
	priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
545 546 547 548 549

	if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
		tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;

	tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
550 551
	if (ieee80211_is_mgmt(fc)) {
		if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568
			tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
		else
			tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
	} else {
		tx_cmd->timeout.pm_frame_timeout = 0;
	}

	tx_cmd->driver_txop = 0;
	tx_cmd->tx_flags = tx_flags;
	tx_cmd->next_frame_len = 0;
}

#define RTS_HCCA_RETRY_LIMIT		3
#define RTS_DFAULT_RETRY_LIMIT		60

static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
			      struct iwl_tx_cmd *tx_cmd,
569
			      struct ieee80211_tx_info *info,
570
			      __le16 fc, int sta_id,
571 572
			      int is_hcca)
{
T
Tomas Winkler 已提交
573 574
	u32 rate_flags = 0;
	int rate_idx;
575 576 577
	u8 rts_retry_limit = 0;
	u8 data_retry_limit = 0;
	u8 rate_plcp;
578

579
	rate_idx = min(ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xffff,
580
			IWL_RATE_COUNT - 1);
581 582 583 584 585 586 587 588 589 590

	rate_plcp = iwl_rates[rate_idx].plcp;

	rts_retry_limit = (is_hcca) ?
	    RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;

	if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
		rate_flags |= RATE_MCS_CCK_MSK;


591
	if (ieee80211_is_probe_resp(fc)) {
592 593 594 595 596 597 598 599 600 601 602 603 604 605
		data_retry_limit = 3;
		if (data_retry_limit < rts_retry_limit)
			rts_retry_limit = data_retry_limit;
	} else
		data_retry_limit = IWL_DEFAULT_TX_RETRY;

	if (priv->data_retry_limit != -1)
		data_retry_limit = priv->data_retry_limit;


	if (ieee80211_is_data(fc)) {
		tx_cmd->initial_rate_index = 0;
		tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
	} else {
606 607 608 609 610
		switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
		case cpu_to_le16(IEEE80211_STYPE_AUTH):
		case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
		case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
		case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
611 612 613 614 615 616 617 618 619
			if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
				tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
				tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
			}
			break;
		default:
			break;
		}

T
Tomas Winkler 已提交
620 621
		priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
		rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
622 623 624 625
	}

	tx_cmd->rts_retry_limit = rts_retry_limit;
	tx_cmd->data_retry_limit = data_retry_limit;
626
	tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
627 628 629
}

static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
630
				      struct ieee80211_tx_info *info,
631 632 633 634
				      struct iwl_tx_cmd *tx_cmd,
				      struct sk_buff *skb_frag,
				      int sta_id)
{
635
	struct ieee80211_key_conf *keyconf = info->control.hw_key;
636

637
	switch (keyconf->alg) {
638 639
	case ALG_CCMP:
		tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
640
		memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
641
		if (info->flags & IEEE80211_TX_CTL_AMPDU)
642
			tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
643
		IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
644 645 646 647
		break;

	case ALG_TKIP:
		tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
648
		ieee80211_get_tkip_key(keyconf, skb_frag,
649
			IEEE80211_TKIP_P2_KEY, tx_cmd->key);
650
		IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
651 652 653 654
		break;

	case ALG_WEP:
		tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
655 656 657 658 659 660
			(keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);

		if (keyconf->keylen == WEP_KEY_LEN_128)
			tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;

		memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
661

662
		IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
663
			     "with key %d\n", keyconf->keyidx);
664 665 666
		break;

	default:
T
Tomas Winkler 已提交
667
		IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
668 669 670 671 672 673 674 675 676 677 678 679 680 681 682
		break;
	}
}

static void iwl_update_tx_stats(struct iwl_priv *priv, u16 fc, u16 len)
{
	/* 0 - mgmt, 1 - cnt, 2 - data */
	int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
	priv->tx_stats[idx].cnt++;
	priv->tx_stats[idx].bytes += len;
}

/*
 * start REPLY_TX command process
 */
683
int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
684 685
{
	struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
686
	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
T
Tomas Winkler 已提交
687 688 689 690 691
	struct iwl_tx_queue *txq;
	struct iwl_queue *q;
	struct iwl_cmd *out_cmd;
	struct iwl_tx_cmd *tx_cmd;
	int swq_id, txq_id;
692 693 694
	dma_addr_t phys_addr;
	dma_addr_t txcmd_phys;
	dma_addr_t scratch_phys;
695
	u16 len, len_org;
696
	u16 seq_number = 0;
697
	__le16 fc;
698
	u8 hdr_len;
T
Tomas Winkler 已提交
699
	u8 sta_id;
700 701 702 703 704 705 706 707
	u8 wait_write_ptr = 0;
	u8 tid = 0;
	u8 *qc = NULL;
	unsigned long flags;
	int ret;

	spin_lock_irqsave(&priv->lock, flags);
	if (iwl_is_rfkill(priv)) {
708
		IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
709 710 711
		goto drop_unlock;
	}

712
	if ((ieee80211_get_tx_rate(priv->hw, info)->hw_value & 0xFF) ==
713
	     IWL_INVALID_RATE) {
714
		IWL_ERR(priv, "ERROR: No TX rate available.\n");
715 716 717
		goto drop_unlock;
	}

718
	fc = hdr->frame_control;
719 720 721

#ifdef CONFIG_IWLWIFI_DEBUG
	if (ieee80211_is_auth(fc))
722
		IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
723
	else if (ieee80211_is_assoc_req(fc))
724
		IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
725
	else if (ieee80211_is_reassoc_req(fc))
726
		IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
727 728 729
#endif

	/* drop all data frame if we are not associated */
730
	if (ieee80211_is_data(fc) &&
731
	    (priv->iw_mode != NL80211_IFTYPE_MONITOR ||
732 733
	    !(info->flags & IEEE80211_TX_CTL_INJECTED)) && /* packet injection */
	    (!iwl_is_associated(priv) ||
734
	     ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
735
	     !priv->assoc_station_added)) {
736
		IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
737 738 739 740 741
		goto drop_unlock;
	}

	spin_unlock_irqrestore(&priv->lock, flags);

742
	hdr_len = ieee80211_hdrlen(fc);
743 744 745 746

	/* Find (or create) index into station table for destination station */
	sta_id = iwl_get_sta_id(priv, hdr);
	if (sta_id == IWL_INVALID_STATION) {
747
		IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
J
Johannes Berg 已提交
748
			       hdr->addr1);
749 750 751
		goto drop;
	}

752
	IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
753

T
Tomas Winkler 已提交
754 755
	swq_id = skb_get_queue_mapping(skb);
	txq_id = swq_id;
756 757
	if (ieee80211_is_data_qos(fc)) {
		qc = ieee80211_get_qos_ctl(hdr);
758
		tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
T
Tomas Winkler 已提交
759 760 761
		seq_number = priv->stations[sta_id].tid[tid].seq_number;
		seq_number &= IEEE80211_SCTL_SEQ;
		hdr->seq_ctrl = hdr->seq_ctrl &
762
				cpu_to_le16(IEEE80211_SCTL_FRAG);
T
Tomas Winkler 已提交
763
		hdr->seq_ctrl |= cpu_to_le16(seq_number);
764 765
		seq_number += 0x10;
		/* aggregation is on for this <sta,tid> */
766
		if (info->flags & IEEE80211_TX_CTL_AMPDU) {
767
			txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
768 769
			swq_id = iwl_virtual_agg_queue_num(swq_id, txq_id);
		}
770 771 772 773 774
		priv->stations[sta_id].tid[tid].tfds_in_queue++;
	}

	txq = &priv->txq[txq_id];
	q = &txq->q;
T
Tomas Winkler 已提交
775
	txq->swq_id = swq_id;
776 777 778 779 780 781 782 783

	spin_lock_irqsave(&priv->lock, flags);

	/* Set up driver data for this TFD */
	memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
	txq->txb[q->write_ptr].skb[0] = skb;

	/* Set up first empty entry in queue's array of Tx/cmd buffers */
784
	out_cmd = txq->cmd[q->write_ptr];
785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823
	tx_cmd = &out_cmd->cmd.tx;
	memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
	memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));

	/*
	 * Set up the Tx-command (not MAC!) header.
	 * Store the chosen Tx queue and TFD index within the sequence field;
	 * after Tx, uCode's Tx response will return this value so driver can
	 * locate the frame within the tx queue and do post-tx processing.
	 */
	out_cmd->hdr.cmd = REPLY_TX;
	out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
				INDEX_TO_SEQ(q->write_ptr)));

	/* Copy MAC header from skb into command buffer */
	memcpy(tx_cmd->hdr, hdr, hdr_len);

	/*
	 * Use the first empty entry in this queue's command buffer array
	 * to contain the Tx command and MAC header concatenated together
	 * (payload data will be in another buffer).
	 * Size of this varies, due to varying MAC header length.
	 * If end is not dword aligned, we'll have 2 extra bytes at the end
	 * of the MAC header (device reads on dword boundaries).
	 * We'll tell device about this padding later.
	 */
	len = sizeof(struct iwl_tx_cmd) +
		sizeof(struct iwl_cmd_header) + hdr_len;

	len_org = len;
	len = (len + 3) & ~3;

	if (len_org != len)
		len_org = 1;
	else
		len_org = 0;

	/* Physical address of this Tx command's header (not MAC header!),
	 * within command buffer array. */
T
Tomas Winkler 已提交
824 825
	txcmd_phys = pci_map_single(priv->pci_dev,
				    out_cmd, sizeof(struct iwl_cmd),
826
				    PCI_DMA_BIDIRECTIONAL);
T
Tomas Winkler 已提交
827 828
	pci_unmap_addr_set(&out_cmd->meta, mapping, txcmd_phys);
	pci_unmap_len_set(&out_cmd->meta, len, sizeof(struct iwl_cmd));
829 830
	/* Add buffer containing Tx command and MAC(!) header to TFD's
	 * first entry */
T
Tomas Winkler 已提交
831
	txcmd_phys += offsetof(struct iwl_cmd, hdr);
832 833
	priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
						   txcmd_phys, len, 1, 0);
834

835
	if (info->control.hw_key)
836
		iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
837 838 839 840 841 842 843

	/* Set up TFD's 2nd entry to point directly to remainder of skb,
	 * if any (802.11 null frames have no payload). */
	len = skb->len - hdr_len;
	if (len) {
		phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
					   len, PCI_DMA_TODEVICE);
844 845 846
		priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
							   phys_addr, len,
							   0, 0);
847 848 849 850 851 852 853 854 855 856
	}

	/* Tell NIC about any 2-byte padding after MAC header */
	if (len_org)
		tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;

	/* Total # bytes to be transmitted */
	len = (u16)skb->len;
	tx_cmd->len = cpu_to_le16(len);
	/* TODO need this for burst mode later on */
857
	iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
858 859

	/* set is_hcca to 0; it probably will never be implemented */
860
	iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, sta_id, 0);
861

862
	iwl_update_tx_stats(priv, le16_to_cpu(fc), len);
863 864 865 866

	scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
		offsetof(struct iwl_tx_cmd, scratch);
	tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
T
Tomas Winkler 已提交
867
	tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
868

869
	if (!ieee80211_has_morefrags(hdr->frame_control)) {
870 871 872 873 874 875 876 877
		txq->need_update = 1;
		if (qc)
			priv->stations[sta_id].tid[tid].seq_number = seq_number;
	} else {
		wait_write_ptr = 1;
		txq->need_update = 0;
	}

878 879 880
	IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
		     le16_to_cpu(out_cmd->hdr.sequence));
	IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
881 882 883 884 885 886 887 888 889 890 891 892 893 894
	iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
	iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);

	/* Set up entry for this TFD in Tx byte-count array */
	priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, len);

	/* Tell device the write index *just past* this latest filled TFD */
	q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
	ret = iwl_txq_update_write_ptr(priv, txq);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (ret)
		return ret;

895
	if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
896 897 898 899 900
		if (wait_write_ptr) {
			spin_lock_irqsave(&priv->lock, flags);
			txq->need_update = 1;
			iwl_txq_update_write_ptr(priv, txq);
			spin_unlock_irqrestore(&priv->lock, flags);
901
		} else {
902
			iwl_stop_queue(priv, txq->swq_id);
903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932
		}
	}

	return 0;

drop_unlock:
	spin_unlock_irqrestore(&priv->lock, flags);
drop:
	return -1;
}
EXPORT_SYMBOL(iwl_tx_skb);

/*************** HOST COMMAND QUEUE FUNCTIONS   *****/

/**
 * iwl_enqueue_hcmd - enqueue a uCode command
 * @priv: device private data point
 * @cmd: a point to the ucode command structure
 *
 * The function returns < 0 values to indicate the operation is
 * failed. On success, it turns the index (> 0) of command in the
 * command queue.
 */
int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
{
	struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
	struct iwl_queue *q = &txq->q;
	struct iwl_cmd *out_cmd;
	dma_addr_t phys_addr;
	unsigned long flags;
T
Tomas Winkler 已提交
933 934 935
	int len, ret;
	u32 idx;
	u16 fix_size;
936 937 938 939 940 941 942 943 944 945 946

	cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
	fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));

	/* If any of the command structures end up being larger than
	 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
	 * we will need to increase the size of the TFD entries */
	BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
	       !(cmd->meta.flags & CMD_SIZE_HUGE));

	if (iwl_is_rfkill(priv)) {
947
		IWL_DEBUG_INFO(priv, "Not sending command - RF KILL");
948 949 950 951
		return -EIO;
	}

	if (iwl_queue_space(q) < ((cmd->meta.flags & CMD_ASYNC) ? 2 : 1)) {
952
		IWL_ERR(priv, "No space for Tx\n");
953 954 955 956 957 958
		return -ENOSPC;
	}

	spin_lock_irqsave(&priv->hcmd_lock, flags);

	idx = get_cmd_index(q, q->write_ptr, cmd->meta.flags & CMD_SIZE_HUGE);
959
	out_cmd = txq->cmd[idx];
960 961 962 963 964 965 966 967 968 969 970 971

	out_cmd->hdr.cmd = cmd->id;
	memcpy(&out_cmd->meta, &cmd->meta, sizeof(cmd->meta));
	memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);

	/* At this point, the out_cmd now has all of the incoming cmd
	 * information */

	out_cmd->hdr.flags = 0;
	out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
			INDEX_TO_SEQ(q->write_ptr));
	if (out_cmd->meta.flags & CMD_SIZE_HUGE)
972
		out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
973 974
	len = (idx == TFD_CMD_SLOTS) ?
			IWL_MAX_SCAN_SIZE : sizeof(struct iwl_cmd);
T
Tomas Winkler 已提交
975 976

	phys_addr = pci_map_single(priv->pci_dev, out_cmd,
977
				   len, PCI_DMA_BIDIRECTIONAL);
T
Tomas Winkler 已提交
978 979
	pci_unmap_addr_set(&out_cmd->meta, mapping, phys_addr);
	pci_unmap_len_set(&out_cmd->meta, len, len);
980
	phys_addr += offsetof(struct iwl_cmd, hdr);
T
Tomas Winkler 已提交
981

982
	priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
983 984
						   phys_addr, fix_size, 1,
						   U32_PAD(cmd->len));
985

986 987 988 989
#ifdef CONFIG_IWLWIFI_DEBUG
	switch (out_cmd->hdr.cmd) {
	case REPLY_TX_LINK_QUALITY_CMD:
	case SENSITIVITY_CMD:
990
		IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
991 992 993 994 995 996 997
				"%d bytes at %d[%d]:%d\n",
				get_cmd_string(out_cmd->hdr.cmd),
				out_cmd->hdr.cmd,
				le16_to_cpu(out_cmd->hdr.sequence), fix_size,
				q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
				break;
	default:
998
		IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
999 1000 1001 1002 1003 1004 1005
				"%d bytes at %d[%d]:%d\n",
				get_cmd_string(out_cmd->hdr.cmd),
				out_cmd->hdr.cmd,
				le16_to_cpu(out_cmd->hdr.sequence), fix_size,
				q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
	}
#endif
1006 1007
	txq->need_update = 1;

1008 1009 1010
	if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
		/* Set up entry in queue's byte count circular buffer */
		priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1011 1012 1013 1014 1015 1016 1017 1018 1019

	/* Increment and update queue's write index */
	q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
	ret = iwl_txq_update_write_ptr(priv, txq);

	spin_unlock_irqrestore(&priv->hcmd_lock, flags);
	return ret ? ret : idx;
}

1020 1021 1022 1023 1024 1025 1026 1027
int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
{
	struct iwl_tx_queue *txq = &priv->txq[txq_id];
	struct iwl_queue *q = &txq->q;
	struct iwl_tx_info *tx_info;
	int nfreed = 0;

	if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1028
		IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1029 1030 1031 1032 1033
			  "is out of range [0-%d] %d %d.\n", txq_id,
			  index, q->n_bd, q->write_ptr, q->read_ptr);
		return 0;
	}

T
Tomas Winkler 已提交
1034 1035 1036
	for (index = iwl_queue_inc_wrap(index, q->n_bd);
	     q->read_ptr != index;
	     q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1037 1038 1039 1040 1041

		tx_info = &txq->txb[txq->q.read_ptr];
		ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
		tx_info->skb[0] = NULL;

1042 1043 1044
		if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
			priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);

1045
		priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059
		nfreed++;
	}
	return nfreed;
}
EXPORT_SYMBOL(iwl_tx_queue_reclaim);


/**
 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
 *
 * When FW advances 'R' index, all entries between old and new 'R' index
 * need to be reclaimed. As result, some free space forms.  If there is
 * enough free space (> low mark), wake the stack that feeds us.
 */
T
Tomas Winkler 已提交
1060 1061
static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
				   int idx, int cmd_idx)
1062 1063 1064 1065 1066
{
	struct iwl_tx_queue *txq = &priv->txq[txq_id];
	struct iwl_queue *q = &txq->q;
	int nfreed = 0;

T
Tomas Winkler 已提交
1067
	if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1068
		IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1069
			  "is out of range [0-%d] %d %d.\n", txq_id,
T
Tomas Winkler 已提交
1070
			  idx, q->n_bd, q->write_ptr, q->read_ptr);
1071 1072 1073
		return;
	}

T
Tomas Winkler 已提交
1074 1075 1076
	pci_unmap_single(priv->pci_dev,
		pci_unmap_addr(&txq->cmd[cmd_idx]->meta, mapping),
		pci_unmap_len(&txq->cmd[cmd_idx]->meta, len),
1077
		PCI_DMA_BIDIRECTIONAL);
T
Tomas Winkler 已提交
1078 1079 1080

	for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
	     q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1081

T
Tomas Winkler 已提交
1082
		if (nfreed++ > 0) {
1083
			IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
1084 1085 1086
					q->write_ptr, q->read_ptr);
			queue_work(priv->workqueue, &priv->restart);
		}
1087

1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105
	}
}

/**
 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
 * @rxb: Rx buffer to reclaim
 *
 * If an Rx buffer has an async callback associated with it the callback
 * will be executed.  The attached skb (if present) will only be freed
 * if the callback returns 1
 */
void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
{
	struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
	u16 sequence = le16_to_cpu(pkt->hdr.sequence);
	int txq_id = SEQ_TO_QUEUE(sequence);
	int index = SEQ_TO_INDEX(sequence);
	int cmd_index;
1106
	bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1107 1108 1109 1110 1111
	struct iwl_cmd *cmd;

	/* If a Tx command is being handled and it isn't in the actual
	 * command queue then there a command routing bug has been introduced
	 * in the queue management code. */
1112
	if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1113 1114 1115 1116 1117
		 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
		  txq_id, sequence,
		  priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
		  priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
		iwl_print_hex_dump(priv, IWL_DL_INFO , rxb, 32);
1118
		return;
1119
	}
1120 1121

	cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1122
	cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1123 1124 1125 1126 1127 1128 1129 1130 1131

	/* Input error checking is done when commands are added to queue. */
	if (cmd->meta.flags & CMD_WANT_SKB) {
		cmd->meta.source->u.skb = rxb->skb;
		rxb->skb = NULL;
	} else if (cmd->meta.u.callback &&
		   !cmd->meta.u.callback(priv, cmd, rxb->skb))
		rxb->skb = NULL;

T
Tomas Winkler 已提交
1132
	iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1133 1134 1135 1136 1137 1138 1139 1140

	if (!(cmd->meta.flags & CMD_ASYNC)) {
		clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
		wake_up_interruptible(&priv->wait_command_queue);
	}
}
EXPORT_SYMBOL(iwl_tx_cmd_complete);

1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170
/*
 * Find first available (lowest unused) Tx Queue, mark it "active".
 * Called only when finding queue for aggregation.
 * Should never return anything < 7, because they should already
 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
 */
static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
{
	int txq_id;

	for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
		if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
			return txq_id;
	return -1;
}

int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
{
	int sta_id;
	int tx_fifo;
	int txq_id;
	int ret;
	unsigned long flags;
	struct iwl_tid_data *tid_data;

	if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
		tx_fifo = default_tid_to_tx_fifo[tid];
	else
		return -EINVAL;

1171
	IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
J
Johannes Berg 已提交
1172
			__func__, ra, tid);
1173 1174 1175 1176 1177 1178

	sta_id = iwl_find_station(priv, ra);
	if (sta_id == IWL_INVALID_STATION)
		return -ENXIO;

	if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1179
		IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1180 1181 1182 1183 1184 1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198
		return -ENXIO;
	}

	txq_id = iwl_txq_ctx_activate_free(priv);
	if (txq_id == -1)
		return -ENXIO;

	spin_lock_irqsave(&priv->sta_lock, flags);
	tid_data = &priv->stations[sta_id].tid[tid];
	*ssn = SEQ_TO_SN(tid_data->seq_number);
	tid_data->agg.txq_id = txq_id;
	spin_unlock_irqrestore(&priv->sta_lock, flags);

	ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
						  sta_id, tid, *ssn);
	if (ret)
		return ret;

	if (tid_data->tfds_in_queue == 0) {
T
Tomas Winkler 已提交
1199
		IWL_ERR(priv, "HW queue is empty\n");
1200 1201 1202
		tid_data->agg.state = IWL_AGG_ON;
		ieee80211_start_tx_ba_cb_irqsafe(priv->hw, ra, tid);
	} else {
1203
		IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218
			     tid_data->tfds_in_queue);
		tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
	}
	return ret;
}
EXPORT_SYMBOL(iwl_tx_agg_start);

int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
{
	int tx_fifo_id, txq_id, sta_id, ssn = -1;
	struct iwl_tid_data *tid_data;
	int ret, write_ptr, read_ptr;
	unsigned long flags;

	if (!ra) {
1219
		IWL_ERR(priv, "ra = NULL\n");
1220 1221 1222 1223 1224 1225 1226 1227 1228 1229
		return -EINVAL;
	}

	if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
		tx_fifo_id = default_tid_to_tx_fifo[tid];
	else
		return -EINVAL;

	sta_id = iwl_find_station(priv, ra);

1230 1231
	if (sta_id == IWL_INVALID_STATION) {
		IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1232
		return -ENXIO;
1233
	}
1234 1235

	if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1236
		IWL_WARN(priv, "Stopping AGG while state not IWL_AGG_ON\n");
1237 1238 1239 1240 1241 1242 1243 1244 1245

	tid_data = &priv->stations[sta_id].tid[tid];
	ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
	txq_id = tid_data->agg.txq_id;
	write_ptr = priv->txq[txq_id].q.write_ptr;
	read_ptr = priv->txq[txq_id].q.read_ptr;

	/* The queue is not empty */
	if (write_ptr != read_ptr) {
1246
		IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1247 1248 1249 1250 1251
		priv->stations[sta_id].tid[tid].agg.state =
				IWL_EMPTYING_HW_QUEUE_DELBA;
		return 0;
	}

1252
	IWL_DEBUG_HT(priv, "HW queue is empty\n");
1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278
	priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;

	spin_lock_irqsave(&priv->lock, flags);
	ret = priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
						   tx_fifo_id);
	spin_unlock_irqrestore(&priv->lock, flags);

	if (ret)
		return ret;

	ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, ra, tid);

	return 0;
}
EXPORT_SYMBOL(iwl_tx_agg_stop);

int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
{
	struct iwl_queue *q = &priv->txq[txq_id].q;
	u8 *addr = priv->stations[sta_id].sta.sta.addr;
	struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];

	switch (priv->stations[sta_id].tid[tid].agg.state) {
	case IWL_EMPTYING_HW_QUEUE_DELBA:
		/* We are reclaiming the last packet of the */
		/* aggregated HW queue */
T
Tomas Winkler 已提交
1279 1280
		if ((txq_id  == tid_data->agg.txq_id) &&
		    (q->read_ptr == q->write_ptr)) {
1281 1282
			u16 ssn = SEQ_TO_SN(tid_data->seq_number);
			int tx_fifo = default_tid_to_tx_fifo[tid];
1283
			IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1284 1285 1286 1287 1288 1289 1290 1291 1292
			priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
							     ssn, tx_fifo);
			tid_data->agg.state = IWL_AGG_OFF;
			ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
		}
		break;
	case IWL_EMPTYING_HW_QUEUE_ADDBA:
		/* We are reclaiming the last packet of the queue */
		if (tid_data->tfds_in_queue == 0) {
1293
			IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1294 1295 1296 1297 1298 1299 1300 1301 1302
			tid_data->agg.state = IWL_AGG_ON;
			ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
		}
		break;
	}
	return 0;
}
EXPORT_SYMBOL(iwl_txq_check_empty);

1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321
/**
 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
 *
 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
 * ACK vs. not.  This gets sent to mac80211, then to rate scaling algo.
 */
static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
				 struct iwl_ht_agg *agg,
				 struct iwl_compressed_ba_resp *ba_resp)

{
	int i, sh, ack;
	u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
	u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
	u64 bitmap;
	int successes = 0;
	struct ieee80211_tx_info *info;

	if (unlikely(!agg->wait_for_ba))  {
1322
		IWL_ERR(priv, "Received BA when not expected\n");
1323 1324 1325 1326 1327
		return -EINVAL;
	}

	/* Mark that the expected block-ack response arrived */
	agg->wait_for_ba = 0;
1328
	IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1329 1330

	/* Calculate shift to align block-ack bits with our Tx window bits */
T
Tomas Winkler 已提交
1331
	sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1332 1333 1334 1335 1336 1337 1338
	if (sh < 0) /* tbw something is wrong with indices */
		sh += 0x100;

	/* don't use 64-bit values for now */
	bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;

	if (agg->frame_count > (64 - sh)) {
1339
		IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1340 1341 1342 1343 1344 1345 1346 1347 1348 1349
		return -1;
	}

	/* check for success or failure according to the
	 * transmitted bitmap and block-ack bitmap */
	bitmap &= agg->bitmap;

	/* For each frame attempted in aggregation,
	 * update driver's record of tx frame's status. */
	for (i = 0; i < agg->frame_count ; i++) {
1350
		ack = bitmap & (1ULL << i);
1351
		successes += !!ack;
1352
		IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1353
			ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364
			agg->start_idx + i);
	}

	info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
	memset(&info->status, 0, sizeof(info->status));
	info->flags = IEEE80211_TX_STAT_ACK;
	info->flags |= IEEE80211_TX_STAT_AMPDU;
	info->status.ampdu_ack_map = successes;
	info->status.ampdu_ack_len = agg->frame_count;
	iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);

1365
	IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382

	return 0;
}

/**
 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
 *
 * Handles block-acknowledge notification from device, which reports success
 * of frames sent via aggregation.
 */
void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
					   struct iwl_rx_mem_buffer *rxb)
{
	struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
	struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
	struct iwl_tx_queue *txq = NULL;
	struct iwl_ht_agg *agg;
T
Tomas Winkler 已提交
1383 1384 1385
	int index;
	int sta_id;
	int tid;
1386 1387 1388 1389 1390 1391 1392 1393 1394

	/* "flow" corresponds to Tx queue */
	u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);

	/* "ssn" is start of block-ack Tx window, corresponds to index
	 * (in Tx queue's circular buffer) of first TFD/frame in window */
	u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);

	if (scd_flow >= priv->hw_params.max_txq_num) {
1395 1396
		IWL_ERR(priv,
			"BUG_ON scd_flow is bigger than number of queues\n");
1397 1398 1399 1400
		return;
	}

	txq = &priv->txq[scd_flow];
T
Tomas Winkler 已提交
1401 1402 1403
	sta_id = ba_resp->sta_id;
	tid = ba_resp->tid;
	agg = &priv->stations[sta_id].tid[tid].agg;
1404 1405 1406 1407 1408 1409

	/* Find index just before block-ack window */
	index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);

	/* TODO: Need to get this copy more safely - now good for debug */

1410
	IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1411 1412
			   "sta_id = %d\n",
			   agg->wait_for_ba,
J
Johannes Berg 已提交
1413
			   (u8 *) &ba_resp->sta_addr_lo32,
1414
			   ba_resp->sta_id);
1415
	IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1416 1417 1418 1419 1420 1421
			   "%d, scd_ssn = %d\n",
			   ba_resp->tid,
			   ba_resp->seq_ctl,
			   (unsigned long long)le64_to_cpu(ba_resp->bitmap),
			   ba_resp->scd_flow,
			   ba_resp->scd_ssn);
1422
	IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n",
1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434
			   agg->start_idx,
			   (unsigned long long)agg->bitmap);

	/* Update driver's record of ACK vs. not for each frame in window */
	iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);

	/* Release all TFDs before the SSN, i.e. all TFDs in front of
	 * block-ack window (we assume that they've been successfully
	 * transmitted ... if not, it's too late anyway). */
	if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
		/* calculate mac80211 ampdu sw queue to wake */
		int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
T
Tomas Winkler 已提交
1435 1436 1437 1438 1439
		priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;

		if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
		    priv->mac80211_registered &&
		    (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1440
			iwl_wake_queue(priv, txq->swq_id);
T
Tomas Winkler 已提交
1441 1442

		iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1443 1444 1445 1446
	}
}
EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);

1447
#ifdef CONFIG_IWLWIFI_DEBUG
1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474 1475 1476
#define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x

const char *iwl_get_tx_fail_reason(u32 status)
{
	switch (status & TX_STATUS_MSK) {
	case TX_STATUS_SUCCESS:
		return "SUCCESS";
		TX_STATUS_ENTRY(SHORT_LIMIT);
		TX_STATUS_ENTRY(LONG_LIMIT);
		TX_STATUS_ENTRY(FIFO_UNDERRUN);
		TX_STATUS_ENTRY(MGMNT_ABORT);
		TX_STATUS_ENTRY(NEXT_FRAG);
		TX_STATUS_ENTRY(LIFE_EXPIRE);
		TX_STATUS_ENTRY(DEST_PS);
		TX_STATUS_ENTRY(ABORTED);
		TX_STATUS_ENTRY(BT_RETRY);
		TX_STATUS_ENTRY(STA_INVALID);
		TX_STATUS_ENTRY(FRAG_DROPPED);
		TX_STATUS_ENTRY(TID_DISABLE);
		TX_STATUS_ENTRY(FRAME_FLUSHED);
		TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
		TX_STATUS_ENTRY(TX_LOCKED);
		TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
	}

	return "UNKNOWN";
}
EXPORT_SYMBOL(iwl_get_tx_fail_reason);
#endif /* CONFIG_IWLWIFI_DEBUG */