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未验证 提交 36346218 编写于 作者: mysterywolf's avatar mysterywolf 提交者： GitHub
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Merge pull request #2 from RT-Thread/master 

update
上级 7d0b8341 9dc0bbb8
展开全部 隐藏空白更改
内联 并排
Showing with 26220 addition and 1132 deletion
.travis.yml
浏览文件 @ 36346218
......@@ -138,6 +138,7 @@ env:
- RTT_BSP='xplorer4330/M4' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='at32/at32f403a-start' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='at32/at32f407-start' RTT_TOOL_CHAIN='sourcery-arm'
- RTT_BSP='smartfusion2' RTT_TOOL_CHAIN='sourcery-arm'
stage: compile
script:
......
bsp/imxrt/imxrt1052-nxp-evk/.config
浏览文件 @ 36346218
......@@ -7,6 +7,7 @@
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
......@@ -63,7 +64,8 @@ CONFIG_RT_USING_DEVICE=y
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40001
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
......@@ -108,6 +110,7 @@ CONFIG_FINSH_ARG_MAX=10
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
# CONFIG_RT_SERIAL_USING_DMA is not set
CONFIG_RT_SERIAL_RB_BUFSZ=64
......@@ -115,12 +118,13 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_HWTIMER is not set
CONFIG_RT_USING_CPUTIME=y
# CONFIG_RT_USING_I2C is not set
CONFIG_RT_USING_PHY=y
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_MTD is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
......@@ -128,10 +132,10 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
#
# Using WiFi
#
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
......@@ -145,6 +149,7 @@ CONFIG_RT_USING_PIN=y
#
CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_PTHREADS is not set
# CONFIG_RT_USING_MODULE is not set
#
# Network
......@@ -156,14 +161,25 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_RT_USING_SAL is not set
#
# light weight TCP/IP stack
# Network interface device
#
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
#
# Modbus master and slave stack
# light weight TCP/IP stack
#
# CONFIG_RT_USING_MODBUS is not set
# CONFIG_RT_USING_LWIP is not set
# CONFIG_RT_USING_LWIP141 is not set
# CONFIG_RT_USING_LWIP202 is not set
# CONFIG_RT_USING_LWIP212 is not set
#
# AT commands
......@@ -178,7 +194,6 @@ CONFIG_RT_USING_LIBC=y
#
# Utilities
#
# CONFIG_RT_USING_LOGTRACE is not set
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
......@@ -230,13 +245,12 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_TENCENT_IOTKIT is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
#
# security packages
......@@ -294,6 +308,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_AP3216C is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
......@@ -310,7 +325,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
#
# miscellaneous packages
......@@ -354,10 +368,13 @@ CONFIG_BSP_USING_LPUART=y
CONFIG_BSP_USING_LPUART1=y
# CONFIG_BSP_LPUART1_RX_USING_DMA is not set
# CONFIG_BSP_LPUART1_TX_USING_DMA is not set
# CONFIG_BSP_USING_LPUART3 is not set
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_SDRAM is not set
# CONFIG_BSP_USING_ETH is not set
#
# Board extended module Drivers
......
bsp/imxrt/imxrt1052-nxp-evk/SConstruct
浏览文件 @ 36346218
......@@ -67,5 +67,8 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SCons
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
# include peripherals
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'peripherals', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)
bsp/imxrt/imxrt1052-nxp-evk/board/Kconfig
浏览文件 @ 36346218
......@@ -96,19 +96,41 @@ menu "Onboard Peripheral Drivers"
menuconfig BSP_USING_ETH
bool "Enable Ethernet"
select PHY_USING_KSZ8081
select RT_USING_NETDEV
default n
if BSP_USING_ETH
config PHY_USING_KSZ8081
bool "i.MX RT1050EVKB uses ksz8081 phy"
config BSP_USING_PHY
select RT_USING_PHY
bool "Enable ethernet phy"
default y
config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
bool "Enable the PHY ksz8081 RMII50M mode"
depends on PHY_USING_KSZ8081
default y
if BSP_USING_PHY
config PHY_DEVICE_ADDRESS
int "Specify address of phy device"
default 2
config PHY_USING_KSZ8081
bool "i.MX RT1064EVK uses ksz8081 phy"
default y
if PHY_USING_KSZ8081
config PHY_RESET_PORT
int "indicate port of reset"
default 1
config PHY_RESET_PIN
int "indicate pin of reset"
default 9
config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
bool "Enable the PHY ksz8081 RMII50M mode"
depends on PHY_USING_KSZ8081
default y
endif
endif
endif
endmenu
......
bsp/imxrt/imxrt1052-nxp-evk/board/SConscript
浏览文件 @ 36346218
......@@ -12,10 +12,6 @@ MCUX_Config/pin_mux.c
CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
CPPDEFINES = ['CPU_MIMXRT1052DVL6B', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1']
if GetDepend(['PHY_USING_KSZ8081']):
src += Glob('ports/phyksz8081/fsl_phy.c')
CPPPATH += [cwd + '/ports/phyksz8081']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH, CPPDEFINES=CPPDEFINES)
Return('group')
bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.c 已删除 100644 → 0
浏览文件 @ 7d0b8341
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_phy.h"
#include <rtthread.h>
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Defines the timeout macro. */
#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the ENET instance from peripheral base address.
*
* @param base ENET peripheral base address.
* @return ENET instance.
*/
extern uint32_t ENET_GetInstance(ENET_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to enet clocks for each instance. */
extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
{
uint32_t bssReg;
uint32_t counter = PHY_TIMEOUT_COUNT;
uint32_t idReg = 0;
status_t result = kStatus_Success;
uint32_t instance = ENET_GetInstance(base);
uint32_t timeDelay;
uint32_t ctlReg = 0;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Set SMI first. */
CLOCK_EnableClock(s_enetClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
ENET_SetSMI(base, srcClock_Hz, false);
/* Initialization after PHY stars to work. */
while ((idReg != PHY_CONTROL_ID1) && (counter != 0))
{
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
counter --;
}
if (!counter)
{
return kStatus_Fail;
}
/* Reset PHY. */
counter = PHY_TIMEOUT_COUNT;
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
if (result == kStatus_Success)
{
#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
uint32_t data = 0;
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
if ( result != kStatus_Success)
{
return result;
}
result = PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK));
if (result != kStatus_Success)
{
return result;
}
#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
/* Set the negotiation. */
result = PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG,
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
if (result == kStatus_Success)
{
result = PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG,
(PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
if (result == kStatus_Success)
{
/* Check auto negotiation complete. */
while (counter --)
{
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &bssReg);
if ( result == kStatus_Success)
{
PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
if (((bssReg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctlReg & PHY_LINK_READY_MASK))
{
/* Wait a moment for Phy status stable. */
for (timeDelay = 0; timeDelay < PHY_TIMEOUT_COUNT; timeDelay ++)
{
__ASM("nop");
}
break;
}
}
if (!counter)
{
return kStatus_PHY_AutoNegotiateFail;
}
}
}
}
}
return result;
}
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
{
uint32_t counter;
/* Clear the SMI interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
/* Starts a SMI write command. */
ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
/* Wait for SMI complete. */
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
{
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
{
break;
}
}
/* Check for timeout. */
if (!counter)
{
return kStatus_PHY_SMIVisitTimeout;
}
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
return kStatus_Success;
}
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
{
assert(dataPtr);
uint32_t counter;
/* Clear the MII interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
/* Starts a SMI read command operation. */
ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
/* Wait for MII complete. */
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
{
if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
{
break;
}
}
/* Check for timeout. */
if (!counter)
{
return kStatus_PHY_SMIVisitTimeout;
}
/* Get data from MII register. */
*dataPtr = ENET_ReadSMIData(base);
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
return kStatus_Success;
}
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable)
{
status_t result;
uint32_t data = 0;
/* Set the loop mode. */
if (enable)
{
if (mode == kPHY_LocalLoop)
{
if (speed == kPHY_Speed100M)
{
data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
}
else
{
data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
}
return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, data);
}
else
{
/* First read the current status in control register. */
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
if (result == kStatus_Success)
{
return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
}
}
}
else
{
/* Disable the loop mode. */
if (mode == kPHY_LocalLoop)
{
/* First read the current status in control register. */
result = PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, &data);
if (result == kStatus_Success)
{
data &= ~PHY_BCTL_LOOP_MASK;
return PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK));
}
}
else
{
/* First read the current status in control one register. */
result = PHY_Read(base, phyAddr, PHY_CONTROL2_REG, &data);
if (result == kStatus_Success)
{
return PHY_Write(base, phyAddr, PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
}
}
}
return result;
}
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
{
assert(status);
status_t result = kStatus_Success;
uint32_t data;
/* Read the basic status register. */
result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, &data);
if (result == kStatus_Success)
{
if (!(PHY_BSTATUS_LINKSTATUS_MASK & data))
{
/* link down. */
*status = false;
}
else
{
/* link up. */
*status = true;
}
}
return result;
}
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
{
assert(duplex);
status_t result = kStatus_Success;
uint32_t data, ctlReg;
/* Read the control two register. */
result = PHY_Read(base, phyAddr, PHY_CONTROL1_REG, &ctlReg);
if (result == kStatus_Success)
{
data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
{
/* Full duplex. */
*duplex = kPHY_FullDuplex;
}
else
{
/* Half duplex. */
*duplex = kPHY_HalfDuplex;
}
data = ctlReg & PHY_CTL1_SPEEDUPLX_MASK;
if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
{
/* 100M speed. */
*speed = kPHY_Speed100M;
}
else
{ /* 10M speed. */
*speed = kPHY_Speed10M;
}
}
return result;
}
bsp/imxrt/imxrt1052-nxp-evk/board/ports/phyksz8081/fsl_phy.h 已删除 100644 → 0
浏览文件 @ 7d0b8341
/*
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_PHY_H_
#define _FSL_PHY_H_
#include "fsl_enet.h"
/*!
* @addtogroup phy_driver
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief PHY driver version */
#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
/*! @brief Defines the PHY registers. */
#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */
#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */
#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/
/*! @brief Defines the mask flag in basic control register. */
#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */
/*!@brief Defines the mask flag of operation mode in control two register*/
#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */
#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */
#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */
#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */
#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
/*! @brief Defines the mask flag in basic status register. */
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
/*! @brief Defines the PHY status. */
enum _phy_status
{
kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */
kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */
};
/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
typedef enum _phy_speed
{
kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
kPHY_Speed100M /*!< ENET PHY 100M speed. */
} phy_speed_t;
/*! @brief Defines the PHY link duplex. */
typedef enum _phy_duplex
{
kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
kPHY_FullDuplex /*!< ENET PHY full duplex. */
} phy_duplex_t;
/*! @brief Defines the PHY loopback mode. */
typedef enum _phy_loop
{
kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */
kPHY_RemoteLoop /*!< ENET PHY remote loopback. */
} phy_loop_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name PHY Driver
* @{
*/
/*!
* @brief Initializes PHY.
*
* This function initialize the SMI interface and initialize PHY.
* The SMI is the MII management interface between PHY and MAC, which should be
* firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
* @retval kStatus_Success PHY initialize success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
*/
status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
/*!
* @brief PHY Write function. This function write data over the SMI to
* the specified PHY register. This function is called by all PHY interfaces.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param phyReg The PHY register.
* @param data The data written to the PHY register.
* @retval kStatus_Success PHY write success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
/*!
* @brief PHY Read function. This interface read data over the SMI from the
* specified PHY register. This function is called by all PHY interfaces.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param phyReg The PHY register.
* @param dataPtr The address to store the data read from the PHY register.
* @retval kStatus_Success PHY read success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
/*!
* @brief Enables/disables PHY loopback.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param mode The loopback mode to be enabled, please see "phy_loop_t".
* the two loopback mode should not be both set. when one loopback mode is set
* the other one should be disabled.
* @param speed PHY speed for loopback mode.
* @param enable True to enable, false to disable.
* @retval kStatus_Success PHY loopback success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable);
/*!
* @brief Gets the PHY link status.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param status The link up or down status of the PHY.
* - true the link is up.
* - false the link is down.
* @retval kStatus_Success PHY get link status success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
/*!
* @brief Gets the PHY link speed and duplex.
*
* @param base ENET peripheral base address.
* @param phyAddr The PHY address.
* @param speed The address of PHY link speed.
* @param duplex The link duplex of PHY.
* @retval kStatus_Success PHY get link speed and duplex success
* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
*/
status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_PHY_H_ */
bsp/imxrt/imxrt1052-nxp-evk/rtconfig.h
浏览文件 @ 36346218
......@@ -40,7 +40,7 @@
#define RT_USING_CONSOLE
#define RT_CONSOLEBUF_SIZE 128
#define RT_CONSOLE_DEVICE_NAME "uart1"
#define RT_VER_NUM 0x40001
#define RT_VER_NUM 0x40003
/* RT-Thread Components */
......@@ -78,11 +78,9 @@
#define RT_USING_SERIAL
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_CPUTIME
#define RT_USING_PHY
#define RT_USING_PIN
/* Using WiFi */
/* Using USB */
......@@ -95,10 +93,17 @@
/* Socket abstraction layer */
/* light weight TCP/IP stack */
/* Network interface device */
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
/* Modbus master and slave stack */
/* light weight TCP/IP stack */
/* AT commands */
......@@ -163,6 +168,7 @@
/* Onboard Peripheral Drivers */
/* Board extended module Drivers */
......
bsp/imxrt/imxrt1064-nxp-evk/README.md
浏览文件 @ 36346218
......@@ -39,7 +39,7 @@
| :----------------- | :----------: | :------------------------------------- |
| USB 转串口 | 支持 | |
| SPI Flash | 支持 | |
| 以太网 | 暂不支持 | |
| 以太网 | 支持 | |
| SD卡 | 暂不支持 | |
| CAN | 暂不支持 | |
| **片上外设** | **支持情况** | **备注** |
......
bsp/imxrt/imxrt1064-nxp-evk/SConstruct
浏览文件 @ 36346218
......@@ -66,5 +66,8 @@ objs.extend(SConscript(os.path.join(libraries_path_prefix, imxrt_library, 'SCons
# include drivers
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'drivers', 'SConscript')))
# include peripherals
objs.extend(SConscript(os.path.join(libraries_path_prefix, 'peripherals', 'SConscript')))
# make a building
DoBuilding(TARGET, objs)
bsp/imxrt/imxrt1064-nxp-evk/applications/main.c
浏览文件 @ 36346218
......@@ -18,6 +18,7 @@
int main(void)
{
#ifndef PHY_USING_KSZ8081
/* set LED0 pin mode to output */
rt_pin_mode(LED0_PIN, PIN_MODE_OUTPUT);
......@@ -28,6 +29,7 @@ int main(void)
rt_pin_write(LED0_PIN, PIN_LOW);
rt_thread_mdelay(500);
}
#endif
}
void reboot(void)
......
bsp/imxrt/imxrt1064-nxp-evk/board/Kconfig
浏览文件 @ 36346218
......@@ -37,7 +37,49 @@ menu "On-chip Peripheral Drivers"
endmenu
menu "Onboard Peripheral Drivers"
config BSP_USING_SDRAM
bool "Enable SDRAM"
default n
menuconfig BSP_USING_ETH
bool "Enable Ethernet"
select RT_USING_NETDEV
default n
if BSP_USING_ETH
config BSP_USING_PHY
select RT_USING_PHY
bool "Enable ethernet phy"
default y
if BSP_USING_PHY
config PHY_DEVICE_ADDRESS
int "Specify address of phy device"
default 2
config PHY_USING_KSZ8081
bool "i.MX RT1064EVK uses ksz8081 phy"
default y
if PHY_USING_KSZ8081
config PHY_RESET_PORT
int "indicate port of reset"
default 1
config PHY_RESET_PIN
int "indicate pin of reset"
default 9
config FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE
bool "Enable the PHY ksz8081 RMII50M mode"
depends on PHY_USING_KSZ8081
default y
endif
endif
endif
endmenu
menu "Board extended module Drivers"
......
bsp/imxrt/imxrt1064-nxp-evk/board/MCUX_Config/clock_config.c
浏览文件 @ 36346218
/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* How to setup clock using clock driver functions:
*
......@@ -15,15 +22,15 @@
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
product: Clocks v5.0
product: Clocks v4.1
processor: MIMXRT1064xxxxA
package_id: MIMXRT1064DVL6A
mcu_data: ksdk2_0
processor_version: 5.0.1
processor_version: 0.0.0
board: MIMXRT1064-EVK
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
#include "clock_config.h"
#include "fsl_iomuxc.h"
/*******************************************************************************
* Definitions
......@@ -57,35 +64,23 @@ outputs:
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 264 MHz}
- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 2880/11 MHz}
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 2880/11 MHz}
- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5/7 MHz}
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
......@@ -95,10 +90,10 @@ outputs:
settings:
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
- {id: CCM.FLEXSPI2_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
- {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true}
- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
- {id: CCM.LCDIF_PODF.scale, value: '8', locked: true}
- {id: CCM.LCDIF_PRED.scale, value: '7', locked: true}
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
......@@ -107,6 +102,7 @@ settings:
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
- {id: CCM_ANALOG.PLL2.div, value: '22'}
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
......@@ -182,6 +178,77 @@ void BOARD_BootClockRUN(void)
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
{
}
/* Init ARM PLL. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
#endif
/* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
/* Disable Usb1 PLL output for USBPHY1. */
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* DeInit Video PLL. */
CLOCK_DeinitVideoPll();
/* Bypass Video PLL. */
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
/* Set divider for Video PLL. */
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
/* Enable Video PLL output. */
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
/* DeInit Enet PLL. */
CLOCK_DeinitEnetPll();
/* Bypass Enet PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
/* Set Enet output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
/* Enable Enet output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
/* Set Enet2 output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
/* Enable Enet2 output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
/* Enable Enet25M output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
/* DeInit Usb2 PLL. */
CLOCK_DeinitUsb2Pll();
/* Bypass Usb2 PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
/* Enable Usb2 PLL output. */
CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
/* Set AHB_PODF. */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
/* Disable IPG clock gate. */
......@@ -193,8 +260,14 @@ void BOARD_BootClockRUN(void)
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
/* Set ARM_PODF. */
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set PERIPH_CLK2_PODF. */
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Disable PERCLK clock gate. */
CLOCK_DisableClock(kCLOCK_Gpt1);
CLOCK_DisableClock(kCLOCK_Gpt1S);
......@@ -203,6 +276,8 @@ void BOARD_BootClockRUN(void)
CLOCK_DisableClock(kCLOCK_Pit);
/* Set PERCLK_PODF. */
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Disable USDHC1 clock gate. */
CLOCK_DisableClock(kCLOCK_Usdhc1);
/* Set USDHC1_PODF. */
......@@ -241,9 +316,9 @@ void BOARD_BootClockRUN(void)
/* Disable Flexspi2 clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi2);
/* Set FLEXSPI2_PODF. */
CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
CLOCK_SetDiv(kCLOCK_Flexspi2Div, 0);
/* Set Flexspi2 clock source. */
CLOCK_SetMux(kCLOCK_Flexspi2Mux, 3);
CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
#endif
/* Disable CSI clock gate. */
CLOCK_DisableClock(kCLOCK_Csi);
......@@ -325,9 +400,9 @@ void BOARD_BootClockRUN(void)
/* Disable LCDIF clock gate. */
CLOCK_DisableClock(kCLOCK_LcdPixel);
/* Set LCDIF_PRED. */
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 6);
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
/* Set LCDIF_CLK_PODF. */
CLOCK_SetDiv(kCLOCK_LcdifDiv, 7);
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
/* Set Lcdif pre clock source. */
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
/* Disable SPDIF clock gate. */
......@@ -356,85 +431,6 @@ void BOARD_BootClockRUN(void)
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
/* Set Pll3 sw clock source. */
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
/* Init ARM PLL. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
* With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
* Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
/* Init System pfd1. */
CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
/* Init System pfd2. */
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
#endif
/* In SDK projects, external flash (configured by FLEXSPI2) will be initialized by dcd.
* With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI2 clock source in SDK projects) will be left unchanged.
* Note: If another clock source is selected for FLEXSPI2, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
/* Init Usb1 pfd0. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
/* Init Usb1 pfd1. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
/* Init Usb1 pfd2. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
/* Init Usb1 pfd3. */
CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
/* Disable Usb1 PLL output for USBPHY1. */
CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
#endif
/* DeInit Audio PLL. */
CLOCK_DeinitAudioPll();
/* Bypass Audio PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
/* Set divider for Audio PLL. */
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
/* DeInit Video PLL. */
CLOCK_DeinitVideoPll();
/* Bypass Video PLL. */
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
/* Set divider for Video PLL. */
CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
/* Enable Video PLL output. */
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
/* DeInit Enet PLL. */
CLOCK_DeinitEnetPll();
/* Bypass Enet PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
/* Set Enet output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
/* Enable Enet output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
/* Set Enet2 output divider. */
CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
/* Enable Enet2 output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
/* Enable Enet25M output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
/* DeInit Usb2 PLL. */
CLOCK_DeinitUsb2Pll();
/* Bypass Usb2 PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
/* Enable Usb2 PLL output. */
CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
/* Set preperiph clock source. */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
/* Set periph clock source. */
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
/* Set periph clock2 clock source. */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set lvds1 clock source. */
CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
/* Set clock out1 divider. */
......@@ -451,26 +447,6 @@ void BOARD_BootClockRUN(void)
CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
/* Disable clock out2. */
CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
/* Set SAI1 MCLK1 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
/* Set SAI1 MCLK2 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
/* Set SAI1 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
/* Set SAI2 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
/* Set SAI3 MCLK3 clock source. */
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
/* Set ENET1 Tx clock source. */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
/* Set ENET2 Tx clock source. */
IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false);
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
}
......
bsp/imxrt/imxrt1064-nxp-evk/board/SConscript
浏览文件 @ 36346218
......@@ -13,7 +13,7 @@ MCUX_Config/pin_mux.c
CPPPATH = [cwd,cwd + '/MCUX_Config',cwd + '/ports']
CPPDEFINES = ['CPU_MIMXRT1064DVL6A', 'STD=C99', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1']
CPPDEFINES = ['CPU_MIMXRT1064DVL6A', 'SKIP_SYSCLK_INIT', 'EVK_MCIMXRM', 'FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL=1','XIP_EXTERNAL_FLASH=1', 'XIP_BOOT_HEADER_ENABLE=1', 'XIP_BOOT_HEADER_DCD_ENABLE=1']
if rtconfig.CROSS_TOOL == 'keil':
CPPDEFINES.append('__FPU_PRESENT=1')
......
bsp/imxrt/imxrt1064-nxp-evk/board/board.c
浏览文件 @ 36346218
......@@ -12,6 +12,8 @@
#include <rtthread.h>
#include "board.h"
#include "pin_mux.h"
#include "fsl_iomuxc.h"
#include "fsl_gpio.h"
#ifdef BSP_USING_DMA
#include "fsl_dmamux.h"
......@@ -109,6 +111,347 @@ void imxrt_dma_init(void)
EDMA_Init(DMA0, &config);
}
#endif
#ifdef BSP_USING_LPUART
void imxrt_uart_pins_init(void)
{
#ifdef BSP_USING_LPUART1
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 is configured as LPUART1_TX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 is configured as LPUART1_RX */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_12_LPUART1_TX, /* GPIO_AD_B0_12 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_13_LPUART1_RX, /* GPIO_AD_B0_13 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
#endif
#ifdef BSP_USING_LPUART2
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_02_LPUART2_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_03_LPUART2_RX,
0x10B0u);
#endif
#ifdef BSP_USING_LPUART3
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_06_LPUART3_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_07_LPUART3_RX,
0x10B0u);
#endif
#ifdef BSP_USING_LPUART4
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_00_LPUART4_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_01_LPUART4_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_00_LPUART4_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_01_LPUART4_RX,
0x10B0u);
#endif
#ifdef BSP_USING_LPUART5
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_12_LPUART5_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_13_LPUART5_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_12_LPUART5_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_13_LPUART5_RX,
0x10B0u);
#endif
#ifdef BSP_USING_LPUART6
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_02_LPUART6_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_03_LPUART6_RX,
0x10B0u);
#endif
#ifdef BSP_USING_LPUART7
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_31_LPUART7_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_32_LPUART7_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_31_LPUART7_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_32_LPUART7_RX,
0x10B0u);
#endif
#ifdef BSP_USING_LPUART8
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
0U);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_10_LPUART8_TX,
0x10B0u);
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B1_11_LPUART8_RX,
0x10B0u);
#endif
}
#endif /* BSP_USING_LPUART */
#ifdef BSP_USING_ETH
void imxrt_enet_pins_init(void)
{
CLOCK_EnableClock(kCLOCK_Iomuxc); /* iomuxc clock (iomuxc_clk_enable): 0x03u */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 is configured as GPIO1_IO10 */
0U);
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 is configured as ENET_RX_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 is configured as ENET_RX_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 is configured as ENET_RX_EN */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 is configured as ENET_TX_DATA00 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 is configured as ENET_TX_DATA01 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 is configured as ENET_TX_EN */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 is configured as ENET_REF_CLK */
1U); /* Software Input On Field: Force input path of pad GPIO_B1_10 */
IOMUXC_SetPinMux(
IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 is configured as ENET_RX_ER */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 is configured as ENET_MDC */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinMux(
IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 is configured as ENET_MDIO */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 PAD functional properties : */
0xB0A9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, /* GPIO_AD_B0_10 PAD functional properties : */
0xB0A9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_04_ENET_RX_DATA00, /* GPIO_B1_04 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_05_ENET_RX_DATA01, /* GPIO_B1_05 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_06_ENET_RX_EN, /* GPIO_B1_06 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_07_ENET_TX_DATA00, /* GPIO_B1_07 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_08_ENET_TX_DATA01, /* GPIO_B1_08 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_09_ENET_TX_EN, /* GPIO_B1_09 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_10_ENET_REF_CLK, /* GPIO_B1_10 PAD functional properties : */
0x31u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/6
Speed Field: low(50MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Disabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_B1_11_ENET_RX_ER, /* GPIO_B1_11 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_40_ENET_MDC, /* GPIO_EMC_40 PAD functional properties : */
0xB0E9u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: max(200MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_EMC_41_ENET_MDIO, /* GPIO_EMC_41 PAD functional properties : */
0xB829u); /* Slew Rate Field: Fast Slew Rate
Drive Strength Field: R0/5
Speed Field: low(50MHz)
Open Drain Enable Field: Open Drain Enabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Pull
Pull Up / Down Config. Field: 100K Ohm Pull Up
Hyst. Enable Field: Hysteresis Disabled */
}
#ifndef BSP_USING_PHY
void imxrt_enet_phy_reset_by_gpio(void)
{
gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
GPIO_PinInit(GPIO1, 9, &gpio_config);
GPIO_PinInit(GPIO1, 10, &gpio_config);
/* pull up the ENET_INT before RESET. */
GPIO_WritePinOutput(GPIO1, 10, 1);
GPIO_WritePinOutput(GPIO1, 9, 0);
rt_thread_delay(100);
GPIO_WritePinOutput(GPIO1, 9, 1);
}
#endif /* BSP_USING_PHY */
#endif /* BSP_USING_ETH */
#ifdef BSP_USING_PHY
void imxrt_phy_pins_init( void )
{
IOMUXC_SetPinMux(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_AD_B0_09 is configured as GPIO1_IO09 */
0U); /* Software Input On Field: Input Path is determined by functionality */
IOMUXC_SetPinConfig(
IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, /* GPIO_B0_00 PAD functional properties : */
0x10B0u); /* Slew Rate Field: Slow Slew Rate
Drive Strength Field: R0/6
Speed Field: medium(100MHz)
Open Drain Enable Field: Open Drain Disabled
Pull / Keep Enable Field: Pull/Keeper Enabled
Pull / Keep Select Field: Keeper
Pull Up / Down Config. Field: 100K Ohm Pull Down
Hyst. Enable Field: Hysteresis Disabled */
}
#endif /* BSP_USING_PHY */
/**
* This function will initial rt1050 board.
*/
......@@ -121,6 +464,18 @@ void rt_hw_board_init()
NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
#ifdef BSP_USING_LPUART
imxrt_uart_pins_init();
#endif
#ifdef BSP_USING_ETH
imxrt_enet_pins_init();
#endif
#ifdef BSP_USING_PHY
imxrt_phy_pins_init();
#endif
#ifdef BSP_USING_DMA
imxrt_dma_init();
#endif
......
bsp/imxrt/imxrt1064-nxp-evk/board/board.h
浏览文件 @ 36346218
......@@ -45,5 +45,11 @@ extern int heap_end;
void rt_hw_board_init(void);
#ifdef BSP_USING_ETH
void imxrt_enet_pins_init(void);
void imxrt_enet_phy_reset_by_gpio(void);
#endif
#endif
bsp/imxrt/imxrt1064-nxp-evk/board/linker_scripts/link.sct
浏览文件 @ 36346218
......@@ -66,6 +66,8 @@
#define m_data3_start 0x00000000 ; ITCM 128KB
#define m_data3_size 0x00020000
#define m_ncache_start 0x81E00000
#define m_ncache_size 0x00200000
/* Sizes */
#if (defined(__stack_size__))
......@@ -124,7 +126,7 @@ LR_IROM1 m_text_start m_text_size
RTT_HEAP +0 EMPTY RTT_HEAP_SIZE{}
; ncache RW data
RW_m_ncache m_data2_start m_data2_size
RW_m_ncache m_ncache_start m_ncache_size
{
* (NonCacheable.init)
* (NonCacheable)
......
bsp/imxrt/imxrt1064-nxp-evk/board/ports/sdram_port.h 0 → 100644
浏览文件 @ 36346218
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2018-12-05 zylx The first version for STM32F4xx
* 2019-4-25 misonyo port to IMXRT
*/
#ifndef SDRAM_PORT_H__
#define SDRAM_PORT_H__
/* parameters for sdram peripheral */
#define SDRAM_BANK_ADDR ((uint32_t)0x80000000U)
/* region#0/1/2/3: kSEMC_SDRAM_CS0/1/2/3 */
#define SDRAM_REGION kSEMC_SDRAM_CS0
/* CS pin: kSEMC_MUXCSX0/1/2/3 */
#define SDRAM_CS_PIN kSEMC_MUXCSX0
/* size(kbyte):32MB = 32*1024*1KBytes */
#define SDRAM_SIZE ((uint32_t)0x8000)
/* data width: kSEMC_PortSize8Bit,kSEMC_PortSize16Bit */
#define SDRAM_DATA_WIDTH kSEMC_PortSize16Bit
/* column bit numbers: kSEMC_SdramColunm_9/10/11/12bit */
#define SDRAM_COLUMN_BITS kSEMC_SdramColunm_9bit
/* cas latency clock number: kSEMC_LatencyOne/Two/Three */
#define SDRAM_CAS_LATENCY kSEMC_LatencyThree
/* Timing configuration for W9825G6KH */
/* TRP:precharge to active command time (ns) */
#define SDRAM_TRP 18
/* TRCD:active to read/write command delay time (ns) */
#define SDRAM_TRCD 18
/* The time between two refresh commands,Use the maximum of the (Trfc , Txsr).(ns) */
#define SDRAM_REFRESH_RECOVERY 67
/* TWR:write recovery time (ns). */
#define SDRAM_TWR 12
/* TRAS:active to precharge command time (ns). */
#define SDRAM_TRAS 42
/* TRC time (ns). */
#define SDRAM_TRC 60
/* active to active time (ns). */
#define SDRAM_ACT2ACT 60
/* refresh time (ns). 64ms */
#define SDRAM_REFRESH_ROW 64 * 1000000 / 8192
#endif /* SDRAM_PORT_H__ */
bsp/imxrt/imxrt1064-nxp-evk/rtconfig.py
浏览文件 @ 36346218
......@@ -48,7 +48,7 @@ if PLATFORM == 'gcc':
DEVICE = ' -mcpu=' + CPU + ' -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections'
CFLAGS = DEVICE + ' -Wall -D__FPU_PRESENT -eentry'
AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb -D__START=entry'
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds'
LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds -Xlinker -print-memory-usage'
CPATH = ''
LPATH = ''
......@@ -57,8 +57,8 @@ if PLATFORM == 'gcc':
AFLAGS += ' -D__STARTUP_CLEAR_BSS'
if BUILD == 'debug':
CFLAGS += ' -gdwarf-2'
AFLAGS += ' -gdwarf-2'
CFLAGS += ' -g'
AFLAGS += ' -g'
CFLAGS += ' -O0'
else:
CFLAGS += ' -O2 -Os'
......
bsp/imxrt/libraries/drivers/SConscript
浏览文件 @ 36346218
......@@ -44,6 +44,9 @@ if GetDepend('BSP_USING_LCD'):
if GetDepend('BSP_USING_ETH'):
src += ['drv_eth.c']
if GetDepend('BSP_USING_PHY'):
src += ['drv_mdio.c']
if GetDepend('BSP_USING_USB_DEVICE'):
src += ['drv_usbd.c']
......
bsp/imxrt/libraries/drivers/drv_eth.c
浏览文件 @ 36346218
......@@ -7,6 +7,7 @@
* Date Author Notes
* 2017-10-10 Tanek the first version
* 2019-5-10 misonyo add DMA TX and RX function
* 2020-10-14 wangqiang use phy device in phy monitor thread
*/
#include <rtthread.h>
......@@ -19,7 +20,6 @@
#include "fsl_enet.h"
#include "fsl_gpio.h"
#include "fsl_phy.h"
#include "fsl_cache.h"
#include "fsl_iomuxc.h"
#include "fsl_common.h"
......@@ -537,31 +537,47 @@ struct pbuf *rt_imxrt_eth_rx(rt_device_t dev)
return NULL;
}
#ifdef BSP_USING_PHY
static struct rt_phy_device *phy_dev = RT_NULL;
static void phy_monitor_thread_entry(void *parameter)
{
phy_speed_t speed;
phy_duplex_t duplex;
bool link = false;
rt_uint32_t speed;
rt_uint32_t duplex;
rt_bool_t link = RT_FALSE;
imxrt_enet_phy_reset_by_gpio();
PHY_Init(imxrt_eth_device.enet_base, PHY_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk));
phy_dev = (struct rt_phy_device *)rt_device_find("rtt-phy");
if ((RT_NULL == phy_dev) || (RT_NULL == phy_dev->ops))
{
// TODO print warning information
LOG_E("Can not find phy device called \"rtt-phy\"");
return ;
}
if (RT_NULL == phy_dev->ops->init)
{
LOG_E("phy driver error!");
return ;
}
rt_phy_status status = phy_dev->ops->init(imxrt_eth_device.enet_base, PHY_DEVICE_ADDRESS, CLOCK_GetFreq(kCLOCK_AhbClk));
if (PHY_STATUS_OK != status)
{
LOG_E("Phy device initialize unsuccessful!\n");
return ;
}
while (1)
{
bool new_link = false;
status_t status = PHY_GetLinkStatus(imxrt_eth_device.enet_base, PHY_ADDRESS, &new_link);
rt_bool_t new_link = RT_FALSE;
rt_phy_status status = phy_dev->ops->get_link_status(&new_link);
if ((status == kStatus_Success) && (link != new_link))
if ((PHY_STATUS_OK == status) && (link != new_link))
{
link = new_link;
if (link) // link up
if (link) // link up
{
PHY_GetLinkSpeedDuplex(imxrt_eth_device.enet_base,
PHY_ADDRESS, &speed, &duplex);
phy_dev->ops->get_link_speed_duplex(&speed, &duplex);
if (kPHY_Speed10M == speed)
if (PHY_SPEED_10M == speed)
{
dbg_log(DBG_LOG, "10M\n");
}
......@@ -570,7 +586,7 @@ static void phy_monitor_thread_entry(void *parameter)
dbg_log(DBG_LOG, "100M\n");
}
if (kPHY_HalfDuplex == duplex)
if (PHY_HALF_DUPLEX == duplex)
{
dbg_log(DBG_LOG, "half dumplex\n");
}
......@@ -579,8 +595,7 @@ static void phy_monitor_thread_entry(void *parameter)
dbg_log(DBG_LOG, "full dumplex\n");
}
if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed)
|| (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex))
if ((imxrt_eth_device.speed != (enet_mii_speed_t)speed) || (imxrt_eth_device.duplex != (enet_mii_duplex_t)duplex))
{
imxrt_eth_device.speed = (enet_mii_speed_t)speed;
imxrt_eth_device.duplex = (enet_mii_duplex_t)duplex;
......@@ -605,6 +620,7 @@ static void phy_monitor_thread_entry(void *parameter)
rt_thread_delay(RT_TICK_PER_SECOND * 2);
}
}
#endif
static int rt_hw_imxrt_eth_init(void)
{
......@@ -657,6 +673,7 @@ static int rt_hw_imxrt_eth_init(void)
/* start phy monitor */
{
#ifdef BSP_USING_PHY
rt_thread_t tid;
tid = rt_thread_create("phy",
phy_monitor_thread_entry,
......@@ -666,6 +683,7 @@ static int rt_hw_imxrt_eth_init(void)
2);
if (tid != RT_NULL)
rt_thread_startup(tid);
#endif
}
return state;
......@@ -673,50 +691,47 @@ static int rt_hw_imxrt_eth_init(void)
INIT_DEVICE_EXPORT(rt_hw_imxrt_eth_init);
#endif
#ifdef RT_USING_FINSH
#if defined(RT_USING_FINSH) && defined(RT_USING_PHY)
#include <finsh.h>
void phy_read(uint32_t phyReg)
void phy_read(rt_uint32_t phy_reg)
{
uint32_t data;
status_t status;
rt_uint32_t data;
status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, &data);
if (kStatus_Success == status)
rt_phy_status status = phy_dev->ops->read(phy_reg, &data);
if (PHY_STATUS_OK == status)
{
rt_kprintf("PHY_Read: %02X --> %08X", phyReg, data);
rt_kprintf("PHY_Read: %02X --> %08X", phy_reg, data);
}
else
{
rt_kprintf("PHY_Read: %02X --> faild", phyReg);
rt_kprintf("PHY_Read: %02X --> faild", phy_reg);
}
}
void phy_write(uint32_t phyReg, uint32_t data)
void phy_write(rt_uint32_t phy_reg, rt_uint32_t data)
{
status_t status;
status = PHY_Write(imxrt_eth_device.enet_base, PHY_ADDRESS, phyReg, data);
if (kStatus_Success == status)
rt_phy_status status = phy_dev->ops->write(phy_reg, data);
if (PHY_STATUS_OK == status)
{
rt_kprintf("PHY_Write: %02X --> %08X\n", phyReg, data);
rt_kprintf("PHY_Write: %02X --> %08X\n", phy_reg, data);
}
else
{
rt_kprintf("PHY_Write: %02X --> faild\n", phyReg);
rt_kprintf("PHY_Write: %02X --> faild\n", phy_reg);
}
}
void phy_dump(void)
{
uint32_t data;
status_t status;
rt_uint32_t data;
rt_phy_status status;
int i;
for (i = 0; i < 32; i++)
{
status = PHY_Read(imxrt_eth_device.enet_base, PHY_ADDRESS, i, &data);
if (kStatus_Success != status)
status = phy_dev->ops->read(i, &data);
if (PHY_STATUS_OK != status)
{
rt_kprintf("phy_dump: %02X --> faild", i);
break;
......@@ -730,10 +745,11 @@ void phy_dump(void)
{
rt_kprintf("%02X --> %08X\n", i, data);
}
}
}
#endif
#if defined(RT_USING_FINSH) && defined(RT_USING_LWIP)
void enet_reg_dump(void)
{
ENET_Type *enet_base = imxrt_eth_device.enet_base;
......
bsp/imxrt/libraries/drivers/drv_mdio.c 0 → 100644
浏览文件 @ 36346218
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-09-29 WangQiang the first version
*
*/
#include <rtthread.h>
#ifdef BSP_USING_PHY
#define LOG_TAG "drv.mdio"
#include <drv_log.h>
#include <rtdevice.h>
#include "drv_mdio.h"
/*! @brief Defines the timeout macro. */
#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
/*!
* @brief Get the ENET instance from peripheral base address.
*
* @param base ENET peripheral base address.
* @return ENET instance.
*/
extern uint32_t ENET_GetInstance(ENET_Type *base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to enet clocks for each instance. */
extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
static rt_bool_t rt_hw_mdio_init(void *bus, rt_uint32_t src_clock_hz)
{
struct rt_mdio_bus *bus_obj = (struct rt_mdio_bus *)bus;
uint32_t instance = ENET_GetInstance((ENET_Type *)(bus_obj->hw_obj));
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Set SMI first. */
CLOCK_EnableClock(s_enetClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
ENET_SetSMI((ENET_Type *)(bus_obj->hw_obj), src_clock_hz, RT_FALSE);
return RT_TRUE;
}
static rt_size_t rt_hw_mdio_read(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
{
RT_ASSERT(data);
struct rt_mdio_bus *bus_obj = (struct rt_mdio_bus *)bus;
rt_uint32_t counter;
rt_uint32_t *data_ptr = (rt_uint32_t *)data;
if (4 != size)
{
return 0;
}
/* Clear the MII interrupt event. */
ENET_ClearInterruptStatus((ENET_Type *)(bus_obj->hw_obj), ENET_EIR_MII_MASK);
/* Starts a SMI read command operation. */
ENET_StartSMIRead((ENET_Type *)(bus_obj->hw_obj), addr, reg, kENET_MiiReadValidFrame);
/* Wait for MII complete. */
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
{
if (ENET_GetInterruptStatus((ENET_Type *)(bus_obj->hw_obj)) & ENET_EIR_MII_MASK)
{
break;
}
}
/* Check for timeout. */
if (!counter)
{
// return kStatus_PHY_SMIVisitTimeout;
return 0;
}
/* Get data from MII register. */
*data_ptr = ENET_ReadSMIData((ENET_Type *)(bus_obj->hw_obj));
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus((ENET_Type *)bus_obj->hw_obj, ENET_EIR_MII_MASK);
return 4;
}
static rt_size_t rt_hw_mdio_write(void *bus, rt_uint32_t addr, rt_uint32_t reg, void *data, rt_uint32_t size)
{
struct rt_mdio_bus *bus_obj = (struct rt_mdio_bus *)bus;
uint32_t counter;
rt_uint32_t *data_ptr = (rt_uint32_t *)data;
if (4 != size)
{
return 0;
}
/* Clear the SMI interrupt event. */
ENET_ClearInterruptStatus((ENET_Type *)(bus_obj->hw_obj), ENET_EIR_MII_MASK);
/* Starts a SMI write command. */
ENET_StartSMIWrite((ENET_Type *)(bus_obj->hw_obj), addr, reg, kENET_MiiWriteValidFrame, *data_ptr);
/* Wait for SMI complete. */
for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
{
if (ENET_GetInterruptStatus((ENET_Type *)(bus_obj->hw_obj)) & ENET_EIR_MII_MASK)
{
break;
}
}
/* Check for timeout. */
if (!counter)
{
return 0;
}
/* Clear MII interrupt event. */
ENET_ClearInterruptStatus((ENET_Type *)(bus_obj->hw_obj), ENET_EIR_MII_MASK);
return size;
}
static struct rt_mdio_bus_ops imxrt_mdio_ops =
{
.init = rt_hw_mdio_init,
.read = rt_hw_mdio_read,
.write = rt_hw_mdio_write,
.uninit = RT_NULL,
};
static rt_mdio_t mdio_bus;
rt_mdio_t *rt_hw_mdio_register(void *hw_obj, char *name)
{
mdio_bus.hw_obj = hw_obj;
mdio_bus.name = name;
mdio_bus.ops = &imxrt_mdio_ops;
return &mdio_bus;
}
rt_mdio_t *rt_hw_mdio_get(void)
{
return &mdio_bus;
}
#endif
bsp/imxrt/libraries/drivers/drv_mdio.h 0 → 100644
浏览文件 @ 36346218
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-09-29 WangQiang the first version
*
*/
#ifndef DRV_MDIO_H__
#define DRV_MDIO_H__
#include <rtdevice.h>
#include "fsl_enet.h"
rt_mdio_t *rt_hw_mdio_register(void *hw_obj, char *name);
rt_mdio_t *rt_hw_mdio_get(void);
#endif /*DRV_MDIO_H__*/
bsp/imxrt/libraries/peripherals/SConscript 0 → 100644
浏览文件 @ 36346218
from building import *
src = []
cwd = []
CPPDEFINES = []
cwd = GetCurrentDir()
if GetDepend('BSP_USING_PHY') and GetDepend('PHY_USING_KSZ8081'):
src += ['phyksz8081.c']
path = [cwd]
group = DefineGroup('Peripherals', src, depend = [''], CPPPATH = path, CPPDEFINES=CPPDEFINES)
Return('group')
bsp/imxrt/libraries/peripherals/phyksz8081.c 0 → 100644
浏览文件 @ 36346218
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-10-14 wangqiang the first version
*/
#include <rtthread.h>
#ifdef PHY_USING_KSZ8081
#include <rtdevice.h>
#include "drv_gpio.h"
#include "drv_mdio.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief Defines the PHY registers. */
#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */
#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */
#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/
/*! @brief Defines the mask flag in basic control register. */
#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */
/*!@brief Defines the mask flag of operation mode in control two register*/
#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */
#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */
#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */
#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */
#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
/*! @brief Defines the mask flag in basic status register. */
#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
/*! @brief Defines the timeout macro. */
#define PHY_TIMEOUT_COUNT 0x3FFFFFFU
/* defined the Reset pin, PORT and PIN config by menuconfig */
#define RESET_PIN GET_PIN(PHY_RESET_PORT, PHY_RESET_PIN)
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Variables
******************************************************************************/
static struct rt_phy_device phy_ksz8081;
/*******************************************************************************
* Code
******************************************************************************/
static inline rt_bool_t read_reg(rt_mdio_t *bus, rt_uint32_t addr, rt_uint32_t reg_id, rt_uint32_t *value)
{
if (4 != bus->ops->read(bus, addr, reg_id, value, 4))
{
return RT_FALSE;
}
return RT_TRUE;
}
static inline rt_bool_t write_reg(rt_mdio_t *bus, rt_uint32_t addr, rt_uint32_t reg_id, rt_uint32_t value)
{
if (4 != bus->ops->write(bus, addr, reg_id, &value, 4))
{
return RT_FALSE;
}
return RT_TRUE;
}
static rt_phy_status rt_phy_init(void *object, rt_uint32_t phy_addr, rt_uint32_t src_clock_hz)
{
rt_bool_t ret;
rt_phy_status result;
rt_uint32_t counter = PHY_TIMEOUT_COUNT;
rt_uint32_t id_reg = 0;
rt_uint32_t time_delay;
rt_uint32_t bss_reg;
rt_uint32_t ctl_reg = 0;
// reset phy device by gpio
rt_pin_mode(RESET_PIN, PIN_MODE_OUTPUT);
rt_pin_write(RESET_PIN, PIN_LOW);
rt_thread_mdelay(100);
rt_pin_write(RESET_PIN, PIN_HIGH);
rt_mdio_t *mdio_bus = rt_hw_mdio_register(object, "phy_mdio");
if (RT_NULL == mdio_bus)
{
return PHY_STATUS_FAIL;
}
phy_ksz8081.bus = mdio_bus;
phy_ksz8081.addr = phy_addr;
ret = mdio_bus->ops->init(mdio_bus, src_clock_hz);
if ( !ret )
{
return PHY_STATUS_FAIL;
}
/* Initialization after PHY stars to work. */
while ((id_reg != PHY_CONTROL_ID1) && (counter != 0))
{
phy_ksz8081.ops->read(PHY_ID1_REG, &id_reg);
counter--;
}
if (!counter)
{
return PHY_STATUS_FAIL;
}
/* Reset PHY. */
counter = PHY_TIMEOUT_COUNT;
result = phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
if (PHY_STATUS_OK == result)
{
#if defined(FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE)
rt_uint32_t data = 0;
result = phy_ksz8081.ops->read(PHY_CONTROL2_REG, &data);
if (PHY_STATUS_FAIL == result)
{
return PHY_STATUS_FAIL;
}
result = phy_ksz8081.ops->write(PHY_CONTROL2_REG, (data | PHY_CTL2_REFCLK_SELECT_MASK));
if (PHY_STATUS_FAIL == result)
{
return PHY_STATUS_FAIL;
}
#endif /* FSL_FEATURE_PHYKSZ8081_USE_RMII50M_MODE */
/* Set the negotiation. */
result = phy_ksz8081.ops->write(PHY_AUTONEG_ADVERTISE_REG,
(PHY_100BASETX_FULLDUPLEX_MASK | PHY_100BASETX_HALFDUPLEX_MASK |
PHY_10BASETX_FULLDUPLEX_MASK | PHY_10BASETX_HALFDUPLEX_MASK | 0x1U));
if (PHY_STATUS_OK == result)
{
result = phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
if (PHY_STATUS_OK == result)
{
/* Check auto negotiation complete. */
while (counter--)
{
result = phy_ksz8081.ops->read(PHY_BASICSTATUS_REG, &bss_reg);
if (PHY_STATUS_OK == result)
{
phy_ksz8081.ops->read(PHY_CONTROL1_REG, &ctl_reg);
if (((bss_reg & PHY_BSTATUS_AUTONEGCOMP_MASK) != 0) && (ctl_reg & PHY_LINK_READY_MASK))
{
/* Wait a moment for Phy status stable. */
for (time_delay = 0; time_delay < PHY_TIMEOUT_COUNT; time_delay++)
{
__ASM("nop");
}
break;
}
}
if (!counter)
{
return PHY_STATUS_FAIL;
}
}
}
}
}
return PHY_STATUS_OK;
}
static rt_phy_status rt_phy_read(rt_uint32_t reg, rt_uint32_t *data)
{
rt_mdio_t *mdio_bus = phy_ksz8081.bus;
rt_uint32_t device_id = phy_ksz8081.addr;
if (read_reg(mdio_bus, device_id, reg, data))
{
return PHY_STATUS_OK;
}
return PHY_STATUS_FAIL;
}
static rt_phy_status rt_phy_write(rt_uint32_t reg, rt_uint32_t data)
{
rt_mdio_t *mdio_bus = phy_ksz8081.bus;
rt_uint32_t device_id = phy_ksz8081.addr;
if (write_reg(mdio_bus, device_id, reg, data))
{
return PHY_STATUS_OK;
}
return PHY_STATUS_FAIL;
}
static rt_phy_status rt_phy_loopback(rt_uint32_t mode, rt_uint32_t speed, rt_bool_t enable)
{
rt_uint32_t data = 0;
rt_phy_status result;
/* Set the loop mode. */
if (enable)
{
if (PHY_LOCAL_LOOP == mode)
{
if (PHY_SPEED_100M == speed)
{
data = PHY_BCTL_SPEED_100M_MASK | PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
}
else
{
data = PHY_BCTL_DUPLEX_MASK | PHY_BCTL_LOOP_MASK;
}
return phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, data);
}
else
{
/* First read the current status in control register. */
result = phy_ksz8081.ops->read(PHY_CONTROL2_REG, &data);
if (PHY_STATUS_OK == result)
{
return phy_ksz8081.ops->write(PHY_CONTROL2_REG, (data | PHY_CTL2_REMOTELOOP_MASK));
}
}
}
else
{
/* Disable the loop mode. */
if (PHY_LOCAL_LOOP == mode)
{
/* First read the current status in control register. */
result = phy_ksz8081.ops->read(PHY_BASICCONTROL_REG, &data);
if (PHY_STATUS_OK == result)
{
data &= ~PHY_BCTL_LOOP_MASK;
return phy_ksz8081.ops->write(PHY_BASICCONTROL_REG, (data | PHY_BCTL_RESTART_AUTONEG_MASK));
}
}
else
{
/* First read the current status in control one register. */
result = phy_ksz8081.ops->read(PHY_CONTROL2_REG, &data);
if (PHY_STATUS_OK == result)
{
return phy_ksz8081.ops->write(PHY_CONTROL2_REG, (data & ~PHY_CTL2_REMOTELOOP_MASK));
}
}
}
return result;
}
static rt_phy_status get_link_status(rt_bool_t *status)
{
rt_phy_status result;
rt_uint32_t data;
/* Read the basic status register. */
result = phy_ksz8081.ops->read(PHY_BASICSTATUS_REG, &data);
if (PHY_STATUS_OK == result)
{
if (!(PHY_BSTATUS_LINKSTATUS_MASK & data))
{
/* link down. */
*status = RT_FALSE;
}
else
{
/* link up. */
*status = RT_TRUE;
}
}
return result;
}
static rt_phy_status get_link_speed_duplex(rt_uint32_t *speed, rt_uint32_t *duplex)
{
rt_phy_status result = PHY_STATUS_OK;
rt_uint32_t data, ctl_reg;
/* Read the control two register. */
result = phy_ksz8081.ops->read(PHY_CONTROL1_REG, &ctl_reg);
if (PHY_STATUS_OK == result)
{
data = ctl_reg & PHY_CTL1_SPEEDUPLX_MASK;
if ((PHY_CTL1_10FULLDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
{
/* Full duplex. */
*duplex = PHY_FULL_DUPLEX;
}
else
{
/* Half duplex. */
*duplex = PHY_HALF_DUPLEX;
}
data = ctl_reg & PHY_CTL1_SPEEDUPLX_MASK;
if ((PHY_CTL1_100HALFDUPLEX_MASK == data) || (PHY_CTL1_100FULLDUPLEX_MASK == data))
{
/* 100M speed. */
*speed = PHY_SPEED_100M;
}
else
{ /* 10M speed. */
*speed = PHY_SPEED_10M;
}
}
return result;
}
static struct rt_phy_ops phy_ops =
{
.init = rt_phy_init,
.read = rt_phy_read,
.write = rt_phy_write,
.loopback = rt_phy_loopback,
.get_link_status = get_link_status,
.get_link_speed_duplex = get_link_speed_duplex,
};
static int rt_phy_ksz8081_register( void )
{
phy_ksz8081.ops = &phy_ops;
rt_hw_phy_register(&phy_ksz8081, "rtt-phy");
return 1;
}
INIT_DEVICE_EXPORT(rt_phy_ksz8081_register);
#endif /* PHY_USING_KSZ8081 */
bsp/imxrt/tools/sdk_dist.py
浏览文件 @ 36346218
......@@ -21,3 +21,6 @@ def dist_do_building(BSP_ROOT, dist_dir=None):
print("=> copy bsp drivers")
bsp_copy_files(os.path.join(library_path, 'drivers'), os.path.join(library_dir, 'drivers'))
shutil.copyfile(os.path.join(library_path, 'Kconfig'), os.path.join(library_dir, 'Kconfig'))
print("=> copy bsp peripherals")
bsp_copy_files(os.path.join(library_path, 'peripherals'), os.path.join(library_dir, 'peripherals'))
bsp/k210/driver/drv_gpio.c
浏览文件 @ 36346218
......@@ -258,7 +258,7 @@ const static struct rt_pin_ops drv_pin_ops =
int rt_hw_pin_init(void)
{
rt_err_t ret = RT_EOK;
memset(pin_alloc_table, 0, sizeof pin_alloc_table);
memset(pin_alloc_table, -1, sizeof pin_alloc_table);
free_pin = GPIO_ALLOC_START;
ret = rt_device_pin_register("pin", &drv_pin_ops, RT_NULL);
......
bsp/nrf5x/libraries/drivers/SConscript
浏览文件 @ 36346218
......@@ -9,8 +9,10 @@ src = Split("""
""")
if GetDepend(['BSP_USING_UART']):
src += ['drv_uart.c']
if GetDepend(['NRFX_USING_UART']):
src += ['drv_uart.c']
else:
src += ['drv_uarte.c']
if GetDepend(['BSP_USING_ON_CHIP_FLASH']):
src += ['drv_flash.c']
......
bsp/nrf5x/libraries/drivers/drv_spi.c
浏览文件 @ 36346218
......@@ -6,6 +6,7 @@
* Change Logs:
* Date Author Notes
* 2020-05-22 Sherman first version
* 2020-11-02 xckhmf fixed bug
*/
#include <stdint.h>
......@@ -19,6 +20,7 @@
#ifdef BSP_USING_SPI
#if defined(BSP_USING_SPI0) || defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2)
static struct nrfx_drv_spi_config spi_config[] =
{
#ifdef BSP_USING_SPI0
......@@ -117,12 +119,12 @@ static rt_err_t spi_configure(struct rt_spi_device *device,
nrfx_spi_t spi = spi_bus_obj[index].spi;
nrfx_spi_config_t config = NRFX_SPI_DEFAULT_CONFIG(bsp_spi_pin[index].sck_pin,
bsp_spi_pin[index].mosi_pin, bsp_spi_pin[index].miso_pin, bsp_spi_pin[index].ss_pin);
bsp_spi_pin[index].mosi_pin, bsp_spi_pin[index].miso_pin, NRFX_SPI_PIN_NOT_USED);
/* spi config ss pin */
if(device->user_data != RT_NULL)
if(device->parent.user_data != RT_NULL)
{
config.ss_pin = (rt_uint8_t)device->user_data;
nrf_gpio_cfg_output((uint32_t)device->parent.user_data);
}
/* spi config bit order */
if(configuration->mode & RT_SPI_MSB)
......@@ -198,32 +200,43 @@ static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *
RT_ASSERT(device->bus->parent.user_data != RT_NULL);
rt_uint8_t index = spi_index_find(device->bus);
nrfx_err_t nrf_ret;
RT_ASSERT(index != 0xFF);
nrfx_spi_t * p_instance = &spi_bus_obj[index].spi;
nrfx_spi_xfer_desc_t p_xfer_desc;
if(message->cs_take == 1)
{
nrf_gpio_pin_clear((uint32_t)device->parent.user_data);
}
p_xfer_desc.p_rx_buffer = message->recv_buf;
p_xfer_desc.rx_length = message->length;
p_xfer_desc.p_tx_buffer = message->send_buf;
p_xfer_desc.tx_length = message->length ;
if(message->send_buf == RT_NULL)
{
p_xfer_desc.p_rx_buffer = message->recv_buf;
p_xfer_desc.rx_length = message->length;
p_xfer_desc.p_tx_buffer = RT_NULL;
p_xfer_desc.tx_length = 0;
}
else
if(message->recv_buf == RT_NULL)
{
p_xfer_desc.p_tx_buffer = message->send_buf;
p_xfer_desc.tx_length = message->length ;
p_xfer_desc.p_rx_buffer = RT_NULL;
p_xfer_desc.rx_length = 0;
p_xfer_desc.rx_length = 0;
}
nrfx_err_t nrf_ret = nrfx_spi_xfer(p_instance, &p_xfer_desc, 0);
if( NRFX_SUCCESS == nrf_ret)
return message->length;
else
nrf_ret = nrfx_spi_xfer(p_instance, &p_xfer_desc, 0);
if(message->cs_release == 1)
{
nrf_gpio_pin_set((uint32_t)device->parent.user_data);
}
if( NRFX_SUCCESS != nrf_ret)
{
return 0;
}
else
{
return message->length;
}
}
/* spi bus callback function */
......@@ -260,6 +273,7 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
{
RT_ASSERT(bus_name != RT_NULL);
RT_ASSERT(device_name != RT_NULL);
RT_ASSERT(ss_pin != RT_NULL);
rt_err_t result;
struct rt_spi_device *spi_device;
......@@ -267,8 +281,7 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
RT_ASSERT(spi_device != RT_NULL);
/* initialize the cs pin */
spi_device->user_data = (void*)ss_pin;
result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, RT_NULL);
result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void*)ss_pin);
if (result != RT_EOK)
{
LOG_E("%s attach to %s faild, %d", device_name, bus_name, result);
......@@ -278,4 +291,5 @@ rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name,
return result;
}
#endif /* BSP_USING_SPI0 || BSP_USING_SPI1 || BSP_USING_SPI2 */
#endif /*BSP_USING_SPI*/
bsp/nrf5x/libraries/drivers/drv_uarte.c 0 → 100644
浏览文件 @ 36346218
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-28 xckhmf Modify for <nrfx>
* 2020-10-31 xckhmf Support for UART1
*
*/
#include <rtdevice.h>
#include <nrfx_uarte.h>
#include "drv_uart.h"
#ifdef BSP_USING_UART
#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1)
typedef struct
{
struct rt_serial_device *serial;
nrfx_uarte_t uarte_instance;
uint8_t rx_length;
uint8_t tx_buffer[1];
uint8_t rx_buffer[1];
bool isInit;
uint32_t rx_pin;
uint32_t tx_pin;
} drv_uart_cb_t;
#ifdef BSP_USING_UART0
static struct rt_serial_device m_serial_0;
drv_uart_cb_t m_uarte0_cb = {
.uarte_instance = NRFX_UARTE_INSTANCE(0),
.rx_length = 0,
.rx_pin = BSP_UART0_RX_PIN,
.tx_pin = BSP_UART0_TX_PIN,
.isInit = false
};
#endif /* BSP_USING_UART0 */
#ifdef BSP_USING_UART1
static struct rt_serial_device m_serial_1;
drv_uart_cb_t m_uarte1_cb = {
.uarte_instance = NRFX_UARTE_INSTANCE(1),
.rx_length = 0,
.rx_pin = BSP_UART1_RX_PIN,
.tx_pin = BSP_UART1_TX_PIN,
.isInit = false
};
#endif /* BSP_USING_UART1 */
static void uarte_evt_handler(nrfx_uarte_event_t const * p_event,
void * p_context)
{
drv_uart_cb_t *p_cb = RT_NULL;
p_cb = (drv_uart_cb_t*)p_context;
switch (p_event->type)
{
case NRFX_UARTE_EVT_RX_DONE:
p_cb->rx_length = p_event->data.rxtx.bytes;
if(p_cb->serial->parent.open_flag&RT_DEVICE_FLAG_INT_RX)
{
rt_hw_serial_isr(p_cb->serial, RT_SERIAL_EVENT_RX_IND);
}
(void)nrfx_uarte_rx(&(p_cb->uarte_instance), p_cb->rx_buffer, 1);
break;
case NRFX_UARTE_EVT_ERROR:
(void)nrfx_uarte_rx(&(p_cb->uarte_instance), p_cb->rx_buffer, 1);
break;
case NRFX_UARTE_EVT_TX_DONE:
if(p_cb->serial->parent.open_flag&RT_DEVICE_FLAG_INT_TX)
{
rt_hw_serial_isr(p_cb->serial, RT_SERIAL_EVENT_TX_DONE);
}
break;
default:
break;
}
}
static rt_err_t _uart_cfg(struct rt_serial_device *serial, struct serial_configure *cfg)
{
nrfx_uarte_config_t config = NRFX_UARTE_DEFAULT_CONFIG(NRF_UARTE_PSEL_DISCONNECTED,\
NRF_UARTE_PSEL_DISCONNECTED);
drv_uart_cb_t *p_cb = RT_NULL;
RT_ASSERT(serial != RT_NULL);
RT_ASSERT(cfg != RT_NULL);
if (serial->parent.user_data == RT_NULL)
{
return -RT_ERROR;
}
p_cb = (drv_uart_cb_t*)serial->parent.user_data;
if(p_cb->isInit)
{
nrfx_uarte_uninit(&(p_cb->uarte_instance));
p_cb->isInit = false;
}
switch (cfg->baud_rate)
{
case BAUD_RATE_2400:
config.baudrate = NRF_UARTE_BAUDRATE_2400;
break;
case BAUD_RATE_4800:
config.baudrate = NRF_UARTE_BAUDRATE_4800;
break;
case BAUD_RATE_9600:
config.baudrate = NRF_UARTE_BAUDRATE_9600;
break;
case BAUD_RATE_19200:
config.baudrate = NRF_UARTE_BAUDRATE_19200;
break;
case BAUD_RATE_38400:
config.baudrate = NRF_UARTE_BAUDRATE_38400;
break;
case BAUD_RATE_57600:
config.baudrate = NRF_UARTE_BAUDRATE_57600;
break;
case BAUD_RATE_115200:
config.baudrate = NRF_UARTE_BAUDRATE_115200;
break;
case BAUD_RATE_230400:
config.baudrate = NRF_UARTE_BAUDRATE_230400;
break;
case BAUD_RATE_460800:
config.baudrate = NRF_UARTE_BAUDRATE_460800;
break;
case BAUD_RATE_921600:
config.baudrate = NRF_UARTE_BAUDRATE_921600;
break;
case BAUD_RATE_2000000:
case BAUD_RATE_3000000:
return -RT_EINVAL;
default:
config.baudrate = NRF_UARTE_BAUDRATE_115200;
break;
}
config.hal_cfg.parity = (cfg->parity == PARITY_NONE)?\
NRF_UARTE_PARITY_EXCLUDED:NRF_UARTE_PARITY_INCLUDED;
config.hal_cfg.hwfc = NRF_UARTE_HWFC_DISABLED;
config.pselrxd = p_cb->rx_pin;
config.pseltxd = p_cb->tx_pin;
config.p_context = (void *)p_cb;
nrfx_uarte_init(&(p_cb->uarte_instance),(nrfx_uarte_config_t const *)&config,uarte_evt_handler);
nrfx_uarte_rx(&(p_cb->uarte_instance),p_cb->rx_buffer,1);
p_cb->isInit = true;
return RT_EOK;
}
static rt_err_t _uart_ctrl(struct rt_serial_device *serial, int cmd, void *arg)
{
drv_uart_cb_t *p_cb = RT_NULL;
RT_ASSERT(serial != RT_NULL);
if (serial->parent.user_data == RT_NULL)
{
return -RT_ERROR;
}
p_cb = (drv_uart_cb_t*)serial->parent.user_data;
switch (cmd)
{
/* disable interrupt */
case RT_DEVICE_CTRL_CLR_INT:
break;
/* enable interrupt */
case RT_DEVICE_CTRL_SET_INT:
break;
case RT_DEVICE_CTRL_CUSTOM:
if ((rt_uint32_t)(arg) == UART_CONFIG_BAUD_RATE_9600)
{
p_cb->serial->config.baud_rate = 9600;
}
else if ((rt_uint32_t)(arg) == UART_CONFIG_BAUD_RATE_115200)
{
p_cb->serial->config.baud_rate = 115200;
}
_uart_cfg(serial, &(serial->config));
break;
case RT_DEVICE_CTRL_PIN:
_uart_cfg(serial, &(serial->config));
break;
case RT_DEVICE_POWERSAVE:
if(p_cb->isInit)
{
nrfx_uarte_uninit(&(p_cb->uarte_instance));
p_cb->isInit = false;
}
break;
case RT_DEVICE_WAKEUP:
_uart_cfg(serial, &(serial->config));
break;
default:
return -RT_ERROR;
}
return RT_EOK;
}
static int _uart_putc(struct rt_serial_device *serial, char c)
{
drv_uart_cb_t *p_cb = RT_NULL;
int rtn = -1;
RT_ASSERT(serial != RT_NULL);
if (serial->parent.user_data != RT_NULL)
{
p_cb = (drv_uart_cb_t*)serial->parent.user_data;
}
p_cb->tx_buffer[0] = c;
nrfx_uarte_tx(&(p_cb->uarte_instance),p_cb->tx_buffer,1);
if(!(serial->parent.open_flag&RT_DEVICE_FLAG_INT_TX))
{
while(nrfx_uarte_tx_in_progress(&(p_cb->uarte_instance)))
{
}
}
return rtn;
}
static int _uart_getc(struct rt_serial_device *serial)
{
int ch = -1;
drv_uart_cb_t *p_cb = RT_NULL;
RT_ASSERT(serial != RT_NULL);
if (serial->parent.user_data != RT_NULL)
{
p_cb = (drv_uart_cb_t*)serial->parent.user_data;
}
if(p_cb->rx_length)
{
ch = p_cb->rx_buffer[0];
p_cb->rx_length--;
}
return ch;
}
static struct rt_uart_ops _uart_ops = {
_uart_cfg,
_uart_ctrl,
_uart_putc,
_uart_getc
};
void rt_hw_uart_init(void)
{
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
#ifdef BSP_USING_UART0
m_serial_0.config = config;
m_serial_0.ops = &_uart_ops;
m_uarte0_cb.serial = &m_serial_0;
rt_hw_serial_register(&m_serial_0, "uart0", \
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX , &m_uarte0_cb);
#endif /* BSP_USING_UART0 */
#ifdef BSP_USING_UART1
m_serial_1.config = config;
m_serial_1.ops = &_uart_ops;
m_uarte1_cb.serial = &m_serial_1;
rt_hw_serial_register(&m_serial_1, "uart1", \
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX |RT_DEVICE_FLAG_INT_TX, &m_uarte1_cb);
#endif /* BSP_USING_UART1 */
}
#endif /* defined(BSP_USING_UART0) || defined(BSP_USING_UART1) */
#endif /* BSP_USING_UART */
bsp/nrf5x/libraries/drivers/drv_uarte.h 0 → 100644
浏览文件 @ 36346218
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-04-28 xckhmf Modify for <nrfx>
* 2020-10-31 xckhmf Support for UART1
*
*/
#ifndef __DRV_UART_H__
#define __DRV_UART_H__
#ifdef __cplusplus
extern "C" {
#endif
#define RT_DEVICE_CTRL_CUSTOM 0x20
#define RT_DEVICE_CTRL_PIN 0x21
#define RT_DEVICE_POWERSAVE 0x22
#define RT_DEVICE_WAKEUP 0x23
#define UART_CONFIG_BAUD_RATE_9600 1
#define UART_CONFIG_BAUD_RATE_115200 2
void rt_hw_uart_init(void);
#ifdef __cplusplus
}
#endif
#endif /* __DRV_UART_H__ */
bsp/nrf5x/nrf52832/.config
浏览文件 @ 36346218
......@@ -120,6 +120,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
......@@ -195,15 +196,12 @@ CONFIG_RT_USING_LIBC=y
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
......@@ -230,7 +228,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
......@@ -243,7 +240,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
......@@ -265,7 +262,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
#
# security packages
......@@ -274,7 +270,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
......@@ -309,8 +304,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
#
# system packages
......@@ -321,7 +314,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
......@@ -334,9 +326,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
#
# peripheral libraries and drivers
......@@ -378,7 +367,6 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
......@@ -386,11 +374,6 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
#
# miscellaneous packages
......@@ -427,31 +410,36 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# Hardware Drivers Config
#
CONFIG_SOC_NRF52832=y
CONFIG_NRFX_CLOCK_ENABLED=1
CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7
CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1
CONFIG_SOC_NORDIC=y
#
# Onboard Peripheral Drivers
#
# CONFIG_BSP_USING_JLINK_TO_USART is not set
# CONFIG_BSP_USING_QSPI_FLASH is not set
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
CONFIG_NRFX_GPIOTE_ENABLED=1
# CONFIG_BSP_USING_SAADC is not set
# CONFIG_BSP_USING_PWM is not set
# CONFIG_BSP_USING_SOFTDEVICE is not set
CONFIG_BSP_USING_UART=y
CONFIG_NRFX_USING_UART=y
# CONFIG_NRFX_USING_UARTE is not set
CONFIG_NRFX_UART_ENABLED=1
CONFIG_BSP_USING_UART0=y
CONFIG_NRFX_UART0_ENABLED=1
CONFIG_BSP_UART0_RX_PIN=8
CONFIG_BSP_UART0_TX_PIN=6
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
......@@ -463,3 +451,8 @@ CONFIG_MCU_FLASH_SIZE_KB=1024
CONFIG_MCU_SRAM_START_ADDRESS=0x20000000
CONFIG_MCU_SRAM_SIZE_KB=256
CONFIG_MCU_FLASH_PAGE_SIZE=0x1000
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
CONFIG_BLE_STACK_USING_NULL=y
# CONFIG_BSP_USING_SOFTDEVICE is not set
# CONFIG_BSP_USING_NIMBLE is not set
bsp/nrf5x/nrf52832/board/Kconfig
浏览文件 @ 36346218
......@@ -157,12 +157,24 @@ menu "On-chip Peripheral Drivers"
endif
menuconfig BSP_USING_UART
bool "Enable UART"
config BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
if BSP_USING_UART
choice
prompt "UART or UARTE"
default NRFX_USING_UART
help
Select the UART or UARTE
config NRFX_USING_UART
bool "UART"
config NRFX_USING_UARTE
bool "UARTE"
endchoice
endif
if BSP_USING_UART&&NRFX_USING_UART
config NRFX_UART_ENABLED
int
default 1
......@@ -183,9 +195,28 @@ menu "On-chip Peripheral Drivers"
range 0 31
default 6
endif
config BSP_USING_UART1
bool "Enable UART1"
default n
endif
if BSP_USING_UART&&NRFX_USING_UARTE
config NRFX_UARTE_ENABLED
int
default 1
config BSP_USING_UART0
bool "Enable UARTE0"
default n
if BSP_USING_UART0
config NRFX_UARTE0_ENABLED
int
default 1
config BSP_UART0_RX_PIN
int "uarte0 rx pin number"
range 0 31
default 8
config BSP_UART0_TX_PIN
int "uarte0 tx pin number"
range 0 31
default 6
endif
endif
config BSP_USING_SPI
......
bsp/nrf5x/nrf52832/rtconfig.h
浏览文件 @ 36346218
......@@ -152,6 +152,9 @@
/* Hardware Drivers Config */
#define SOC_NRF52832
#define NRFX_CLOCK_ENABLED 1
#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
#define NRFX_CLOCK_CONFIG_LF_SRC 1
#define SOC_NORDIC
/* Onboard Peripheral Drivers */
......@@ -160,8 +163,12 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define NRFX_GPIOTE_ENABLED 1
#define BSP_USING_UART
#define NRFX_USING_UART
#define NRFX_UART_ENABLED 1
#define BSP_USING_UART0
#define NRFX_UART0_ENABLED 1
#define BSP_UART0_RX_PIN 8
#define BSP_UART0_TX_PIN 6
......@@ -172,5 +179,6 @@
#define MCU_SRAM_START_ADDRESS 0x20000000
#define MCU_SRAM_SIZE_KB 256
#define MCU_FLASH_PAGE_SIZE 0x1000
#define BLE_STACK_USING_NULL
#endif
bsp/nrf5x/nrf52840/.config
浏览文件 @ 36346218
......@@ -65,7 +65,7 @@ CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_CONSOLE_DEVICE_NAME="uart1"
CONFIG_RT_VER_NUM=0x40003
# CONFIG_RT_USING_CPU_FFS is not set
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
......@@ -120,6 +120,7 @@ CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
......@@ -195,15 +196,12 @@ CONFIG_RT_USING_LIBC=y
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
......@@ -230,7 +228,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
......@@ -243,7 +240,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_TENCENT_IOTHUB is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
......@@ -273,7 +270,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
......@@ -308,7 +304,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_URLENCODE is not set
#
# system packages
......@@ -319,7 +314,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
......@@ -332,8 +326,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
#
# peripheral libraries and drivers
......@@ -353,8 +345,6 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRF5X_SDK_V1300 is not set
# CONFIG_PKG_USING_NRF5X_SDK_LATEST_VERSION is not set
CONFIG_PKG_USING_NRFX=y
CONFIG_PKG_NRFX_PATH="/packages/peripherals/nrfx"
CONFIG_PKG_USING_NRFX_V210=y
......@@ -384,10 +374,6 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
#
# miscellaneous packages
......@@ -429,6 +415,10 @@ CONFIG_PKG_NRFX_VER="v2.1.0"
# Hardware Drivers Config
#
CONFIG_SOC_NRF52840=y
CONFIG_NRFX_CLOCK_ENABLED=1
CONFIG_NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY=7
CONFIG_NRFX_CLOCK_CONFIG_LF_SRC=1
CONFIG_SOC_NORDIC=y
#
# Onboard Peripheral Drivers
......@@ -440,12 +430,17 @@ CONFIG_SOC_NRF52840=y
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_GPIO=y
# CONFIG_BSP_USING_SOFTDEVICE is not set
CONFIG_NRFX_GPIOTE_ENABLED=1
# CONFIG_BSP_USING_SAADC is not set
# CONFIG_BSP_USING_PWM is not set
CONFIG_BSP_USING_UART=y
CONFIG_NRFX_USING_UART=y
# CONFIG_NRFX_USING_UARTE is not set
CONFIG_NRFX_UART_ENABLED=1
CONFIG_BSP_USING_UART0=y
CONFIG_NRFX_UART0_ENABLED=1
CONFIG_BSP_UART0_RX_PIN=8
CONFIG_BSP_UART0_TX_PIN=6
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_SPI is not set
# CONFIG_BSP_USING_ON_CHIP_FLASH is not set
......@@ -457,3 +452,8 @@ CONFIG_MCU_FLASH_SIZE_KB=1024
CONFIG_MCU_SRAM_START_ADDRESS=0x20000000
CONFIG_MCU_SRAM_SIZE_KB=256
CONFIG_MCU_FLASH_PAGE_SIZE=0x1000
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_ONCHIP_RTC is not set
CONFIG_BLE_STACK_USING_NULL=y
# CONFIG_BSP_USING_SOFTDEVICE is not set
# CONFIG_BSP_USING_NIMBLE is not set
bsp/nrf5x/nrf52840/board/Kconfig
浏览文件 @ 36346218
......@@ -194,12 +194,24 @@ menu "On-chip Peripheral Drivers"
endif
menuconfig BSP_USING_UART
bool "Enable UART"
config BSP_USING_UART
bool "Enable UART"
default y
select RT_USING_SERIAL
if BSP_USING_UART
if BSP_USING_UART
choice
prompt "UART or UARTE"
default NRFX_USING_UART
help
Select the UART or UARTE
config NRFX_USING_UART
bool "UART"
config NRFX_USING_UARTE
bool "UARTE"
endchoice
endif
if BSP_USING_UART&&NRFX_USING_UART
config NRFX_UART_ENABLED
int
default 1
......@@ -220,9 +232,44 @@ menu "On-chip Peripheral Drivers"
range 0 31
default 6
endif
endif
if BSP_USING_UART&&NRFX_USING_UARTE
config NRFX_UARTE_ENABLED
int
default 1
config BSP_USING_UART0
bool "Enable UARTE0"
default n
if BSP_USING_UART0
config NRFX_UARTE0_ENABLED
int
default 1
config BSP_UART0_RX_PIN
int "uarte0 rx pin number"
range 0 31
default 8
config BSP_UART0_TX_PIN
int "uarte0 tx pin number"
range 0 31
default 6
endif
config BSP_USING_UART1
bool "Enable UART1"
default n
bool "Enable UARTE1"
default n
if BSP_USING_UART1
config NRFX_UARTE1_ENABLED
int
default 1
config BSP_UART1_RX_PIN
int "uarte1 rx pin number"
range 0 31
default 7
config BSP_UART1_TX_PIN
int "uarte1 tx pin number"
range 0 31
default 5
endif
endif
config BSP_USING_SPI
......
bsp/nrf5x/nrf52840/rtconfig.h
浏览文件 @ 36346218
......@@ -152,6 +152,10 @@
/* Hardware Drivers Config */
#define SOC_NRF52840
#define NRFX_CLOCK_ENABLED 1
#define NRFX_CLOCK_DEFAULT_CONFIG_IRQ_PRIORITY 7
#define NRFX_CLOCK_CONFIG_LF_SRC 1
#define SOC_NORDIC
/* Onboard Peripheral Drivers */
......@@ -159,8 +163,12 @@
/* On-chip Peripheral Drivers */
#define BSP_USING_GPIO
#define NRFX_GPIOTE_ENABLED 1
#define BSP_USING_UART
#define NRFX_USING_UART
#define NRFX_UART_ENABLED 1
#define BSP_USING_UART0
#define NRFX_UART0_ENABLED 1
#define BSP_UART0_RX_PIN 8
#define BSP_UART0_TX_PIN 6
......@@ -171,5 +179,6 @@
#define MCU_SRAM_START_ADDRESS 0x20000000
#define MCU_SRAM_SIZE_KB 256
#define MCU_FLASH_PAGE_SIZE 0x1000
#define BLE_STACK_USING_NULL
#endif
bsp/raspberry-pi/raspi4-32/.config
浏览文件 @ 36346218
......@@ -134,6 +134,7 @@ CONFIG_RT_USING_DFS_DEVFS=y
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
# CONFIG_RT_USING_DFS_NFS is not set
#
# Device Drivers
......@@ -208,17 +209,79 @@ CONFIG_RT_USING_POSIX=y
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
CONFIG_RT_USING_NETDEV=y
CONFIG_NETDEV_USING_IFCONFIG=y
CONFIG_NETDEV_USING_PING=y
CONFIG_NETDEV_USING_NETSTAT=y
CONFIG_NETDEV_USING_AUTO_DEFAULT=y
# CONFIG_NETDEV_USING_IPV6 is not set
CONFIG_NETDEV_IPV4=1
CONFIG_NETDEV_IPV6=0
# CONFIG_NETDEV_IPV6_SCOPES is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
CONFIG_RT_USING_LWIP=y
# CONFIG_RT_USING_LWIP141 is not set
CONFIG_RT_USING_LWIP202=y
# CONFIG_RT_USING_LWIP212 is not set
# CONFIG_RT_USING_LWIP_IPV6 is not set
CONFIG_RT_LWIP_MEM_ALIGNMENT=4
CONFIG_RT_LWIP_IGMP=y
CONFIG_RT_LWIP_ICMP=y
# CONFIG_RT_LWIP_SNMP is not set
CONFIG_RT_LWIP_DNS=y
CONFIG_RT_LWIP_DHCP=y
CONFIG_IP_SOF_BROADCAST=1
CONFIG_IP_SOF_BROADCAST_RECV=1
#
# Static IPv4 Address
#
CONFIG_RT_LWIP_IPADDR="192.168.1.30"
CONFIG_RT_LWIP_GWADDR="192.168.1.1"
CONFIG_RT_LWIP_MSKADDR="255.255.255.0"
CONFIG_RT_LWIP_UDP=y
CONFIG_RT_LWIP_TCP=y
CONFIG_RT_LWIP_RAW=y
# CONFIG_RT_LWIP_PPP is not set
CONFIG_RT_MEMP_NUM_NETCONN=8
CONFIG_RT_LWIP_PBUF_NUM=16
CONFIG_RT_LWIP_RAW_PCB_NUM=4
CONFIG_RT_LWIP_UDP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_PCB_NUM=4
CONFIG_RT_LWIP_TCP_SEG_NUM=40
CONFIG_RT_LWIP_TCP_SND_BUF=8196
CONFIG_RT_LWIP_TCP_WND=8196
CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10
CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8
CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024
# CONFIG_LWIP_NO_RX_THREAD is not set
# CONFIG_LWIP_NO_TX_THREAD is not set
CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12
CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024
CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8
# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set
CONFIG_LWIP_NETIF_STATUS_CALLBACK=1
CONFIG_LWIP_NETIF_LINK_CALLBACK=1
CONFIG_SO_REUSE=1
CONFIG_LWIP_SO_RCVTIMEO=1
CONFIG_LWIP_SO_SNDTIMEO=1
CONFIG_LWIP_SO_RCVBUF=1
CONFIG_LWIP_SO_LINGER=0
# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set
CONFIG_LWIP_NETIF_LOOPBACK=0
# CONFIG_RT_LWIP_STATS is not set
# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set
CONFIG_RT_LWIP_USING_PING=y
# CONFIG_RT_LWIP_DEBUG is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
# CONFIG_LWIP_USING_DHCPD is not set
#
# VBUS(Virtual Software BUS)
......@@ -497,6 +560,8 @@ CONFIG_RT_USING_POSIX=y
#
# Network Utilities
#
# CONFIG_PKG_USING_MDNS is not set
# CONFIG_PKG_USING_UPNP is not set
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
......
bsp/raspberry-pi/raspi4-32/README.md
浏览文件 @ 36346218
......@@ -128,6 +128,7 @@ msh />
| WATCHDOG | 支持 | - |
| HDMI | 支持 | - |
| SDIO | 支持 | - |
| ETH | 支持 | - |
## 5. 注意事项
......
bsp/raspberry-pi/raspi4-32/driver/board.c
浏览文件 @ 36346218
......@@ -19,8 +19,9 @@
struct mem_desc platform_mem_desc[] = {
{0x0, 0x6400000, 0x0, NORMAL_MEM},
{0x8000000, 0x8100000, 0x8000000, DEVICE_MEM}, //mbox msg
{0x8000000, 0x8800000, 0x8000000, DEVICE_MEM}, //mbox msg
{0x0EA00000, 0x0EE00000, 0x0EA00000, DEVICE_MEM}, //framebuffer
{0xFD500000, 0xFDA00000, 0xFD500000, DEVICE_MEM}, //gmac
{0xFE000000, 0xFE400000, 0xFE000000, DEVICE_MEM}, //peripheral
{0xFF800000, 0xFFA00000, 0xFF800000, DEVICE_MEM} //gic
};
......
bsp/raspberry-pi/raspi4-32/driver/drv_eth.c 0 → 100644
浏览文件 @ 36346218
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-10-30 bigmagic first version
*/
#include <rthw.h>
#include <stdint.h>
#include <rtthread.h>
#include <lwip/sys.h>
#include <netif/ethernetif.h>
#include "mbox.h"
#include "raspi4.h"
#include "drv_eth.h"
#define RECV_CACHE_BUF (1024)
#define SEND_DATA_NO_CACHE (0x08200000)
#define RECV_DATA_NO_CACHE (0x08400000)
#define DMA_DISC_ADDR_SIZE (4 * 1024 *1024)
#define RX_DESC_BASE (MAC_REG + GENET_RX_OFF)
#define TX_DESC_BASE (MAC_REG + GENET_TX_OFF)
#define MAX_ADDR_LEN (6)
#define upper_32_bits(n) ((rt_uint32_t)(((n) >> 16) >> 16))
#define lower_32_bits(n) ((rt_uint32_t)(n))
#define BIT(nr) (1UL << (nr))
static rt_uint32_t tx_index = 0;
static rt_uint32_t rx_index = 0;
static rt_uint32_t index_flag = 0;
static rt_uint32_t send_cache_pbuf[RECV_CACHE_BUF];
struct rt_eth_dev
{
struct eth_device parent;
rt_uint8_t dev_addr[MAX_ADDR_LEN];
char *name;
void *iobase;
int state;
int index;
struct rt_timer link_timer;
struct rt_timer rx_poll_timer;
void *priv;
};
static struct rt_eth_dev eth_dev;
static struct rt_semaphore sem_lock;
static inline rt_uint32_t read32(void *addr)
{
return (*((volatile unsigned int*)(addr)));
}
static inline void write32(void *addr, rt_uint32_t value)
{
(*((volatile unsigned int*)(addr))) = value;
}
void eth_rx_irq(void *param)
{
eth_device_ready(&eth_dev.parent);
}
/* We only support RGMII (as used on the RPi4). */
static int bcmgenet_interface_set(void)
{
int phy_mode = PHY_INTERFACE_MODE_RGMII;
switch (phy_mode) {
case PHY_INTERFACE_MODE_RGMII:
case PHY_INTERFACE_MODE_RGMII_RXID:
write32(MAC_REG + SYS_PORT_CTRL,PORT_MODE_EXT_GPHY);
break;
default:
rt_kprintf("unknown phy mode: %d\n", MAC_REG);
return -1;
}
return 0;
}
static void bcmgenet_umac_reset(void)
{
rt_uint32_t reg;
reg = read32(MAC_REG + SYS_RBUF_FLUSH_CTRL);
reg |= BIT(1);
write32((MAC_REG + SYS_RBUF_FLUSH_CTRL), reg);
reg &= ~BIT(1);
write32((MAC_REG + SYS_RBUF_FLUSH_CTRL),reg);
DELAY_MICROS(10);
write32((MAC_REG + SYS_RBUF_FLUSH_CTRL),0);
DELAY_MICROS(10);
write32(MAC_REG + UMAC_CMD, 0);
write32(MAC_REG + UMAC_CMD, (CMD_SW_RESET | CMD_LCL_LOOP_EN));
DELAY_MICROS(2);
write32(MAC_REG + UMAC_CMD, 0);
/* clear tx/rx counter */
write32(MAC_REG + UMAC_MIB_CTRL, MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT);
write32(MAC_REG + UMAC_MIB_CTRL, 0);
write32(MAC_REG + UMAC_MAX_FRAME_LEN, ENET_MAX_MTU_SIZE);
/* init rx registers, enable ip header optimization */
reg = read32(MAC_REG + RBUF_CTRL);
reg |= RBUF_ALIGN_2B;
write32(MAC_REG + RBUF_CTRL, reg);
write32(MAC_REG + RBUF_TBUF_SIZE_CTRL, 1);
}
static void bcmgenet_disable_dma(void)
{
rt_uint32_t tdma_reg = 0, rdma_reg = 0;
tdma_reg = read32(MAC_REG + TDMA_REG_BASE + DMA_CTRL);
tdma_reg &= ~(1UL << DMA_EN);
write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, tdma_reg);
rdma_reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL);
rdma_reg &= ~(1UL << DMA_EN);
write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, rdma_reg);
write32(MAC_REG + UMAC_TX_FLUSH, 1);
DELAY_MICROS(100);
write32(MAC_REG + UMAC_TX_FLUSH, 0);
}
static void bcmgenet_enable_dma(void)
{
rt_uint32_t reg = 0;
rt_uint32_t dma_ctrl = 0;
dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN;
write32(MAC_REG + TDMA_REG_BASE + DMA_CTRL, dma_ctrl);
reg = read32(MAC_REG + RDMA_REG_BASE + DMA_CTRL);
write32(MAC_REG + RDMA_REG_BASE + DMA_CTRL, dma_ctrl | reg);
}
static int bcmgenet_mdio_write(rt_uint32_t addr, rt_uint32_t reg, rt_uint32_t value)
{
int count = 10000;
rt_uint32_t val;
val = MDIO_WR | (addr << MDIO_PMD_SHIFT) |(reg << MDIO_REG_SHIFT) | (0xffff & value);
write32(MAC_REG + MDIO_CMD, val);
rt_uint32_t reg_val = read32(MAC_REG + MDIO_CMD);
reg_val = reg_val | MDIO_START_BUSY;
write32(MAC_REG + MDIO_CMD, reg_val);
while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count))
DELAY_MICROS(1);
reg_val = read32(MAC_REG + MDIO_CMD);
return reg_val & 0xffff;
}
static int bcmgenet_mdio_read(rt_uint32_t addr, rt_uint32_t reg)
{
int count = 10000;
rt_uint32_t val = 0;
rt_uint32_t reg_val = 0;
val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
write32(MAC_REG + MDIO_CMD, val);
reg_val = read32(MAC_REG + MDIO_CMD);
reg_val = reg_val | MDIO_START_BUSY;
write32(MAC_REG + MDIO_CMD, reg_val);
while ((read32(MAC_REG + MDIO_CMD) & MDIO_START_BUSY) && (--count))
DELAY_MICROS(1);
reg_val = read32(MAC_REG + MDIO_CMD);
return reg_val & 0xffff;
}
static int bcmgenet_gmac_write_hwaddr(void)
{
//{0xdc,0xa6,0x32,0x28,0x22,0x50};
rt_uint8_t addr[6];
rt_uint32_t reg;
bcm271x_mbox_hardware_get_mac_address(&addr[0]);
reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
write32(MAC_REG + UMAC_MAC0, reg);
reg = addr[4] << 8 | addr[5];
write32(MAC_REG + UMAC_MAC1, reg);
return 0;
}
static int get_ethernet_uid(void)
{
rt_uint32_t uid_high = 0;
rt_uint32_t uid_low = 0;
rt_uint32_t uid = 0;
uid_high = bcmgenet_mdio_read(1, BCM54213PE_PHY_IDENTIFIER_HIGH);
uid_low = bcmgenet_mdio_read(1, BCM54213PE_PHY_IDENTIFIER_LOW);
uid = (uid_high << 16 | uid_low);
if(BCM54213PE_VERSION_B1 == uid)
{
rt_kprintf("version is B1\n");
}
return uid;
}
static void bcmgenet_mdio_init(void)
{
rt_uint32_t ret = 0;
/*get ethernet uid*/
ret = get_ethernet_uid();
if(ret == 0)
{
return;
}
/* reset phy */
bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET);
/* read control reg */
bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL);
/* reset phy again */
bcmgenet_mdio_write(1, BCM54213PE_MII_CONTROL, MII_CONTROL_PHY_RESET);
/* read control reg */
bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL);
/* read status reg */
bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS);
/* read status reg */
bcmgenet_mdio_read(1, BCM54213PE_IEEE_EXTENDED_STATUS);
bcmgenet_mdio_read(1, BCM54213PE_AUTO_NEGOTIATION_ADV);
bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS);
bcmgenet_mdio_read(1, BCM54213PE_CONTROL);
/* half full duplex capability */
bcmgenet_mdio_write(1, BCM54213PE_CONTROL, (CONTROL_HALF_DUPLEX_CAPABILITY | CONTROL_FULL_DUPLEX_CAPABILITY));
bcmgenet_mdio_read(1, BCM54213PE_MII_CONTROL);
/* set mii control */
bcmgenet_mdio_write(1,BCM54213PE_MII_CONTROL,(MII_CONTROL_AUTO_NEGOTIATION_ENABLED | MII_CONTROL_AUTO_NEGOTIATION_RESTART| MII_CONTROL_PHY_FULL_DUPLEX| MII_CONTROL_SPEED_SELECTION));
}
static void rx_ring_init(void)
{
write32(MAC_REG + RDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
write32(MAC_REG + RDMA_RING_REG_BASE + DMA_START_ADDR,0x0 );
write32(MAC_REG + RDMA_READ_PTR, 0x0);
write32(MAC_REG + RDMA_WRITE_PTR, 0x0);
write32(MAC_REG + RDMA_RING_REG_BASE + DMA_END_ADDR, RX_DESCS * DMA_DESC_SIZE / 4 - 1);
write32(MAC_REG + RDMA_PROD_INDEX, 0x0);
write32(MAC_REG + RDMA_CONS_INDEX, 0x0);
write32(MAC_REG + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
write32(MAC_REG + RDMA_XON_XOFF_THRESH, DMA_FC_THRESH_VALUE);
write32(MAC_REG + RDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q);
}
static void tx_ring_init(void)
{
write32(MAC_REG + TDMA_REG_BASE + DMA_SCB_BURST_SIZE, DMA_MAX_BURST_LENGTH);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_START_ADDR, 0x0);
write32(MAC_REG + TDMA_READ_PTR, 0x0);
write32(MAC_REG + TDMA_READ_PTR, 0x0);
write32(MAC_REG + TDMA_READ_PTR, 0x0);
write32(MAC_REG + TDMA_WRITE_PTR, 0x0);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_END_ADDR,TX_DESCS * DMA_DESC_SIZE / 4 - 1);
write32(MAC_REG + TDMA_PROD_INDEX, 0x0);
write32(MAC_REG + TDMA_CONS_INDEX, 0x0);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH,0x1);
write32(MAC_REG + TDMA_FLOW_PERIOD,0x0);
write32(MAC_REG + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE, (TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH);
write32(MAC_REG + TDMA_REG_BASE + DMA_RING_CFG,1 << DEFAULT_Q);
}
static void rx_descs_init(void)
{
char *rxbuffs = (char *)RECV_DATA_NO_CACHE;
rt_uint32_t len_stat, i;
void *desc_base = (void *)RX_DESC_BASE;
len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN;
for (i = 0; i < RX_DESCS; i++) {
write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO), lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]));
write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI),upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]));
write32((desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS),len_stat);
}
}
static int phy_startup(void)
{
int count = 1000000;
while ((bcmgenet_mdio_read(1, BCM54213PE_MII_STATUS) & MII_STATUS_LINK_UP) && (--count))
DELAY_MICROS(1);
if(count > 0)
{
rt_kprintf("bcmgenet: PHY startup ok!\n");
}
else
{
rt_kprintf("bcmgenet: PHY startup err!\n");
return 1;
}
if(bcmgenet_mdio_read(1, BCM54213PE_STATUS) == 0)
{
//todo
}
else
{
rt_kprintf("bcmgenet: BCM54213PE_STATUS err!\n");
}
if(bcmgenet_mdio_read(1, BCM54213PE_CONTROL) == (CONTROL_FULL_DUPLEX_CAPABILITY| CONTROL_HALF_DUPLEX_CAPABILITY))
{
//todo
}
else
{
rt_kprintf("bcmgenet: BCM54213PE_CONTROL err!\n");
}
return 0;
}
static int bcmgenet_adjust_link(void)
{
rt_uint32_t speed;
rt_uint32_t phy_dev_speed = SPEED_100;
switch (phy_dev_speed) {
case SPEED_1000:
speed = UMAC_SPEED_1000;
break;
case SPEED_100:
speed = UMAC_SPEED_100;
break;
case SPEED_10:
speed = UMAC_SPEED_10;
break;
default:
rt_kprintf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev_speed);
return -1;
}
rt_uint32_t reg1 = read32(MAC_REG + EXT_RGMII_OOB_CTRL);
//reg1 &= ~(1UL << OOB_DISABLE);
//rt_kprintf("OOB_DISABLE is %d\n", OOB_DISABLE);
reg1 |= (RGMII_LINK | RGMII_MODE_EN | ID_MODE_DIS);
write32(MAC_REG + EXT_RGMII_OOB_CTRL, reg1);
DELAY_MICROS(1000);
write32(MAC_REG + UMAC_CMD, speed << CMD_SPEED_SHIFT);
return 0;
}
static int bcmgenet_gmac_eth_start(void)
{
rt_uint32_t ret;
rt_uint32_t count = 10000;
bcmgenet_umac_reset();
bcmgenet_gmac_write_hwaddr();
/* Disable RX/TX DMA and flush TX queues */
bcmgenet_disable_dma();
rx_ring_init();
rx_descs_init();
tx_ring_init();
/* Enable RX/TX DMA */
bcmgenet_enable_dma();
/* read PHY properties over the wire from generic PHY set-up */
ret = phy_startup();
if (ret) {
rt_kprintf("bcmgenet: PHY startup failed: %d\n", ret);
return ret;
}
/* Update MAC registers based on PHY property */
ret = bcmgenet_adjust_link();
if (ret) {
rt_kprintf("bcmgenet: adjust PHY link failed: %d\n", ret);
return ret;
}
/* wait tx index clear */
while ((read32(MAC_REG + TDMA_CONS_INDEX) != 0) && (--count))
DELAY_MICROS(1);
tx_index = read32(MAC_REG + TDMA_CONS_INDEX);
write32(MAC_REG + TDMA_PROD_INDEX, tx_index);
index_flag = read32(MAC_REG + RDMA_PROD_INDEX);
rx_index = index_flag % 256;
write32(MAC_REG + RDMA_CONS_INDEX, index_flag);
write32(MAC_REG + RDMA_PROD_INDEX, index_flag);
/* Enable Rx/Tx */
rt_uint32_t rx_tx_en;
rx_tx_en = read32(MAC_REG + UMAC_CMD);
rx_tx_en |= (CMD_TX_EN | CMD_RX_EN);
write32(MAC_REG + UMAC_CMD, rx_tx_en);
return 0;
}
static rt_uint32_t prev_recv_cnt = 0;
static rt_uint32_t cur_recv_cnt = 0;
static rt_uint32_t bcmgenet_gmac_eth_recv(rt_uint8_t **packetp)
{
void* desc_base;
rt_uint32_t length = 0, addr = 0;
rt_uint32_t prod_index = read32(MAC_REG + RDMA_PROD_INDEX);
//get next
if(prod_index == index_flag)
{
cur_recv_cnt = index_flag;
//no buff
return 0;
}
else
{
if(prev_recv_cnt == prod_index)
{
return 0;
}
desc_base = RX_DESC_BASE + rx_index * DMA_DESC_SIZE;
length = read32(desc_base + DMA_DESC_LENGTH_STATUS);
length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK;
addr = read32(desc_base + DMA_DESC_ADDRESS_LO);
/* To cater for the IP headepr alignment the hardware does.
* This would actually not be needed if we don't program
* RBUF_ALIGN_2B
*/
*packetp = (rt_uint8_t *)(addr + RX_BUF_OFFSET);
rx_index = rx_index + 1;
if(rx_index >= 256)
{
rx_index = 0;
}
write32(MAC_REG + RDMA_CONS_INDEX, cur_recv_cnt);
cur_recv_cnt = cur_recv_cnt + 1;
prev_recv_cnt = cur_recv_cnt;
return length;
}
}
static int bcmgenet_gmac_eth_send(void *packet, int length)
{
void* desc_base = (TX_DESC_BASE + tx_index * DMA_DESC_SIZE);
rt_uint32_t len_stat = length << DMA_BUFLENGTH_SHIFT;
rt_uint32_t prod_index, cons;
rt_uint32_t tries = 100;
prod_index = read32(MAC_REG + TDMA_PROD_INDEX);
len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
write32((desc_base + DMA_DESC_ADDRESS_LO),SEND_DATA_NO_CACHE);
write32((desc_base + DMA_DESC_ADDRESS_HI),0);
write32((desc_base + DMA_DESC_LENGTH_STATUS),len_stat);
if(++tx_index>= TX_DESCS)
{
tx_index = 0;
}
prod_index++;
/* Start Transmisson */
write32(MAC_REG + TDMA_PROD_INDEX,prod_index);
do {
cons = read32(MAC_REG + TDMA_CONS_INDEX);
} while ((cons & 0xffff) < prod_index && --tries);
if (!tries)
{
return -1;
}
return 0;
}
static rt_err_t bcmgenet_eth_init(rt_device_t device)
{
struct eth_device *eth_device = (struct eth_device *)device;
RT_ASSERT(eth_device != RT_NULL);
rt_uint32_t ret = 0;
rt_uint32_t hw_reg = 0;
struct rt_eth_dev *dev = &eth_dev;
/* Read GENET HW version */
rt_uint8_t major = 0;
hw_reg = read32(MAC_REG + SYS_REV_CTRL);
major = (hw_reg >> 24) & 0x0f;
if (major != 6) {
if (major == 5)
major = 4;
else if (major == 0)
major = 1;
rt_kprintf("Uns upported GENETv%d.%d\n", major, (hw_reg >> 16) & 0x0f);
return RT_ERROR;
}
/* set interface */
ret = bcmgenet_interface_set();
if (ret)
{
return ret;
}
/* rbuf clear */
write32(MAC_REG + SYS_RBUF_FLUSH_CTRL, 0);
/* disable MAC while updating its registers */
write32(MAC_REG + UMAC_CMD, 0);
/* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
write32(MAC_REG + UMAC_CMD, CMD_SW_RESET | CMD_LCL_LOOP_EN);
bcmgenet_mdio_init();
bcmgenet_gmac_write_hwaddr();
bcmgenet_gmac_write_hwaddr();
bcmgenet_gmac_eth_start();
//irq or poll
rt_timer_init(&dev->rx_poll_timer, "rx_poll_timer",
eth_rx_irq,
NULL,
1,
RT_TIMER_FLAG_PERIODIC);
rt_timer_start(&dev->rx_poll_timer);
return RT_EOK;
}
static rt_err_t bcmgenet_eth_control(rt_device_t dev, int cmd, void *args)
{
switch (cmd)
{
case NIOCTL_GADDR:
if (args) rt_memcpy(args, eth_dev.dev_addr, 6);
else return -RT_ERROR;
break;
default :
break;
}
return RT_EOK;
}
rt_err_t rt_eth_tx(rt_device_t device, struct pbuf *p)
{
rt_uint32_t sendbuf = SEND_DATA_NO_CACHE;
/* lock eth device */
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
//struct rt_eth_dev *dev = (struct rt_eth_dev *) device;
pbuf_copy_partial(p, (void *)&send_cache_pbuf[0], p->tot_len, 0);
rt_memcpy((void *)sendbuf, send_cache_pbuf, p->tot_len);
bcmgenet_gmac_eth_send((void *)sendbuf, p->tot_len);
rt_sem_release(&sem_lock);
return RT_EOK;
}
char recv_data[RX_BUF_LENGTH];
struct pbuf *rt_eth_rx(rt_device_t device)
{
int recv_len = 0;
rt_uint32_t addr_point[8];
struct pbuf *pbuf = RT_NULL;
rt_sem_take(&sem_lock, RT_WAITING_FOREVER);
recv_len = bcmgenet_gmac_eth_recv((rt_uint8_t **)&addr_point[0]);
if(recv_len > 0)
{
pbuf = pbuf_alloc(PBUF_LINK, recv_len, PBUF_RAM);
rt_memcpy(pbuf->payload, (char *)addr_point[0], recv_len);
}
rt_sem_release(&sem_lock);
return pbuf;
}
int rt_hw_eth_init(void)
{
rt_uint8_t mac_addr[6];
rt_sem_init(&sem_lock, "eth_lock", 1, RT_IPC_FLAG_FIFO);
memset(&eth_dev, 0, sizeof(eth_dev));
memset((void *)SEND_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE));
memset((void *)RECV_DATA_NO_CACHE, 0, sizeof(DMA_DISC_ADDR_SIZE));
bcm271x_mbox_hardware_get_mac_address(&mac_addr[0]);
eth_dev.iobase = MAC_REG;
eth_dev.name = "e0";
eth_dev.dev_addr[0] = mac_addr[0];
eth_dev.dev_addr[1] = mac_addr[1];
eth_dev.dev_addr[2] = mac_addr[2];
eth_dev.dev_addr[3] = mac_addr[3];
eth_dev.dev_addr[4] = mac_addr[4];
eth_dev.dev_addr[5] = mac_addr[5];
eth_dev.parent.parent.type = RT_Device_Class_NetIf;
eth_dev.parent.parent.init = bcmgenet_eth_init;
eth_dev.parent.parent.open = RT_NULL;
eth_dev.parent.parent.close = RT_NULL;
eth_dev.parent.parent.read = RT_NULL;
eth_dev.parent.parent.write = RT_NULL;
eth_dev.parent.parent.control = bcmgenet_eth_control;
eth_dev.parent.parent.user_data = RT_NULL;
eth_dev.parent.eth_tx = rt_eth_tx;
eth_dev.parent.eth_rx = rt_eth_rx;
eth_device_init(&(eth_dev.parent), "e0");
eth_device_linkchange(&eth_dev.parent, RT_TRUE); //linkup the e0 for lwip to check
return 0;
}
INIT_COMPONENT_EXPORT(rt_hw_eth_init);
bsp/raspberry-pi/raspi4-32/driver/drv_eth.h 0 → 100644
浏览文件 @ 36346218
/*
* Copyright (c) 2006-2020, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-10-30 bigmagic first version
*/
#ifndef __DRV_ETH_H__
#define __DRV_ETH_H__
#define MAC_REG (void *)(0xfd580000)
//#define BIT(nr) (1UL << (nr))
#define SYS_REV_CTRL (0x00)
#define SYS_PORT_CTRL (0x04)
#define PORT_MODE_EXT_GPHY (3)
#define GENET_SYS_OFF (0x0000)
#define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08)
#define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c)
#define GENET_EXT_OFF (0x0080)
#define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c)
#define RGMII_LINK BIT(4)
#define OOB_DISABLE BIT(5)
#define RGMII_MODE_EN BIT(6)
#define ID_MODE_DIS BIT(16)
#define GENET_RBUF_OFF (0x0300)
#define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4)
#define RBUF_CTRL (GENET_RBUF_OFF + 0x00)
#define RBUF_ALIGN_2B BIT(1)
#define GENET_UMAC_OFF (0x0800)
#define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580)
#define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014)
#define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c)
#define UMAC_MAC1 (GENET_UMAC_OFF + 0x010)
#define UMAC_CMD (GENET_UMAC_OFF + 0x008)
#define MDIO_CMD (GENET_UMAC_OFF + 0x614)
#define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334)
#define MDIO_START_BUSY BIT(29)
#define MDIO_READ_FAIL BIT(28)
#define MDIO_RD (2 << 26)
#define MDIO_WR BIT(26)
#define MDIO_PMD_SHIFT (21)
#define MDIO_PMD_MASK (0x1f)
#define MDIO_REG_SHIFT (16)
#define MDIO_REG_MASK (0x1f)
#define CMD_TX_EN BIT(0)
#define CMD_RX_EN BIT(1)
#define UMAC_SPEED_10 (0)
#define UMAC_SPEED_100 (1)
#define UMAC_SPEED_1000 (2)
#define UMAC_SPEED_2500 (3)
#define CMD_SPEED_SHIFT (2)
#define CMD_SPEED_MASK (3)
#define CMD_SW_RESET BIT(13)
#define CMD_LCL_LOOP_EN BIT(15)
#define CMD_TX_EN BIT(0)
#define CMD_RX_EN BIT(1)
#define MIB_RESET_RX BIT(0)
#define MIB_RESET_RUNT BIT(1)
#define MIB_RESET_TX BIT(2)
/* total number of Buffer Descriptors, same for Rx/Tx */
#define TOTAL_DESCS (256)
#define RX_DESCS TOTAL_DESCS
#define TX_DESCS TOTAL_DESCS
#define DEFAULT_Q (0x10)
#define ETH_DATA_LEN (1500)
#define ETH_HLEN (14)
#define VLAN_HLEN (4)
#define ETH_FCS_LEN (4)
/* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
* 1536 is multiple of 256 bytes
*/
#define ENET_BRCM_TAG_LEN (6)
#define ENET_PAD (8)
#define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \
VLAN_HLEN + ENET_BRCM_TAG_LEN + \
ETH_FCS_LEN + ENET_PAD)
/* Tx/Rx Dma Descriptor common bits */
#define DMA_EN BIT(0)
#define DMA_RING_BUF_EN_SHIFT (0x01)
#define DMA_RING_BUF_EN_MASK (0xffff)
#define DMA_BUFLENGTH_MASK (0x0fff)
#define DMA_BUFLENGTH_SHIFT (16)
#define DMA_RING_SIZE_SHIFT (16)
#define DMA_OWN (0x8000)
#define DMA_EOP (0x4000)
#define DMA_SOP (0x2000)
#define DMA_WRAP (0x1000)
#define DMA_MAX_BURST_LENGTH (0x8)
/* Tx specific DMA descriptor bits */
#define DMA_TX_UNDERRUN (0x0200)
#define DMA_TX_APPEND_CRC (0x0040)
#define DMA_TX_OW_CRC (0x0020)
#define DMA_TX_DO_CSUM (0x0010)
#define DMA_TX_QTAG_SHIFT (7)
/* DMA rings size */
#define DMA_RING_SIZE (0x40)
#define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1))
/* DMA descriptor */
#define DMA_DESC_LENGTH_STATUS (0x00)
#define DMA_DESC_ADDRESS_LO (0x04)
#define DMA_DESC_ADDRESS_HI (0x08)
#define DMA_DESC_SIZE (12)
#define GENET_RX_OFF (0x2000)
#define GENET_RDMA_REG_OFF \
(GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
#define GENET_TX_OFF (0x4000)
#define GENET_TDMA_REG_OFF \
(GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
#define DMA_FC_THRESH_HI (RX_DESCS >> 4)
#define DMA_FC_THRESH_LO (5)
#define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \
DMA_FC_THRESH_HI)
#define DMA_XOFF_THRESHOLD_SHIFT (16)
#define TDMA_RING_REG_BASE \
(GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
#define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00)
#define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08)
#define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c)
#define DMA_RING_BUF_SIZE (0x10)
#define DMA_START_ADDR (0x14)
#define DMA_END_ADDR (0x1c)
#define DMA_MBUF_DONE_THRESH (0x24)
#define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28)
#define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c)
#define RDMA_RING_REG_BASE \
(GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
#define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00)
#define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08)
#define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c)
#define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28)
#define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c)
#define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE)
#define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE)
#define DMA_RING_CFG (0x00)
#define DMA_CTRL (0x04)
#define DMA_SCB_BURST_SIZE (0x0c)
#define RX_BUF_LENGTH (2048)
#define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS)
#define RX_BUF_OFFSET (2)
#define PHY_INTERFACE_MODE_RGMII (7)
#define PHY_INTERFACE_MODE_RGMII_RXID (9)
#define BCM54213PE_MII_CONTROL (0x00)
#define BCM54213PE_MII_STATUS (0x01)
#define BCM54213PE_PHY_IDENTIFIER_HIGH (0x02)
#define BCM54213PE_PHY_IDENTIFIER_LOW (0x03)
#define BCM54213PE_AUTO_NEGOTIATION_ADV (0x04)
#define BCM54213PE_AUTO_NEGOTIATION_LINK (0x05)
#define BCM54213PE_AUTO_NEGOTIATION_EXPANSION (0x06)
#define BCM54213PE_NEXT_PAGE_TX (0x07)
#define BCM54213PE_PARTNER_RX (0x08)
#define BCM54213PE_CONTROL (0x09)
#define BCM54213PE_STATUS (0x0A)
#define BCM54213PE_IEEE_EXTENDED_STATUS (0x0F)
#define BCM54213PE_PHY_EXTENDED_CONTROL (0x10)
#define BCM54213PE_PHY_EXTENDED_STATUS (0x11)
#define BCM54213PE_RECEIVE_ERROR_COUNTER (0x12)
#define BCM54213PE_FALSE_C_S_COUNTER (0x13)
#define BCM54213PE_RECEIVE_NOT_OK_COUNTER (0x14)
#define BCM54213PE_VERSION_B1 (0x600d84a2)
#define BCM54213PE_VERSION_X (0x600d84a0)
//BCM54213PE_MII_CONTROL
#define MII_CONTROL_PHY_RESET (1 << 15)
#define MII_CONTROL_AUTO_NEGOTIATION_ENABLED (1 << 12)
#define MII_CONTROL_AUTO_NEGOTIATION_RESTART (1 << 9)
#define MII_CONTROL_PHY_FULL_DUPLEX (1 << 8)
#define MII_CONTROL_SPEED_SELECTION (1 << 6)
//BCM54213PE_MII_STATUS
#define MII_STATUS_LINK_UP (1 << 2)
//BCM54213PE_CONTROL
#define CONTROL_FULL_DUPLEX_CAPABILITY (1 << 9)
#define CONTROL_HALF_DUPLEX_CAPABILITY (1 << 8)
#define SPEED_1000 (1000)
#define SPEED_100 (100)
#define SPEED_10 (10)
#endif/* __DRV_ETH_H__ */
bsp/raspberry-pi/raspi4-32/rtconfig.h
浏览文件 @ 36346218
......@@ -122,9 +122,57 @@
/* Network interface device */
#define RT_USING_NETDEV
#define NETDEV_USING_IFCONFIG
#define NETDEV_USING_PING
#define NETDEV_USING_NETSTAT
#define NETDEV_USING_AUTO_DEFAULT
#define NETDEV_IPV4 1
#define NETDEV_IPV6 0
/* light weight TCP/IP stack */
#define RT_USING_LWIP
#define RT_USING_LWIP202
#define RT_LWIP_MEM_ALIGNMENT 4
#define RT_LWIP_IGMP
#define RT_LWIP_ICMP
#define RT_LWIP_DNS
#define RT_LWIP_DHCP
#define IP_SOF_BROADCAST 1
#define IP_SOF_BROADCAST_RECV 1
/* Static IPv4 Address */
#define RT_LWIP_IPADDR "192.168.1.30"
#define RT_LWIP_GWADDR "192.168.1.1"
#define RT_LWIP_MSKADDR "255.255.255.0"
#define RT_LWIP_UDP
#define RT_LWIP_TCP
#define RT_LWIP_RAW
#define RT_MEMP_NUM_NETCONN 8
#define RT_LWIP_PBUF_NUM 16
#define RT_LWIP_RAW_PCB_NUM 4
#define RT_LWIP_UDP_PCB_NUM 4
#define RT_LWIP_TCP_PCB_NUM 4
#define RT_LWIP_TCP_SEG_NUM 40
#define RT_LWIP_TCP_SND_BUF 8196
#define RT_LWIP_TCP_WND 8196
#define RT_LWIP_TCPTHREAD_PRIORITY 10
#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8
#define RT_LWIP_TCPTHREAD_STACKSIZE 1024
#define RT_LWIP_ETHTHREAD_PRIORITY 12
#define RT_LWIP_ETHTHREAD_STACKSIZE 1024
#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8
#define LWIP_NETIF_STATUS_CALLBACK 1
#define LWIP_NETIF_LINK_CALLBACK 1
#define SO_REUSE 1
#define LWIP_SO_RCVTIMEO 1
#define LWIP_SO_SNDTIMEO 1
#define LWIP_SO_RCVBUF 1
#define LWIP_SO_LINGER 0
#define LWIP_NETIF_LOOPBACK 0
#define RT_LWIP_USING_PING
/* AT commands */
......
bsp/smartfusion2/CMSIS/SConscript 0 → 100644
浏览文件 @ 36346218
from building import *
import rtconfig
cwd = GetCurrentDir()
src = Glob('*.c')
if rtconfig.CROSS_TOOL == 'gcc':
src += ['startup_gcc/startup_m2sxxx.S']
elif rtconfig.CROSS_TOOL == 'keil':
src += ['startup_arm/startup_m2sxxx.s']
CPPPATH = [cwd]
group = DefineGroup('CMSIS', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
bsp/smartfusion2/CMSIS/core_cm3.c 0 → 100644
浏览文件 @ 36346218
此差异已折叠。
bsp/smartfusion2/CMSIS/core_cm3.h 0 → 100644
浏览文件 @ 36346218
此差异已折叠。
bsp/smartfusion2/CMSIS/hw_reg_io.h 0 → 100644
浏览文件 @ 36346218
/*******************************************************************************
* (c) Copyright 2011-2013 Microsemi SoC Products Group. All rights reserved.
*
* SmartFusion2 Cortex Microcontroller Software Interface - Peripheral
* Access Layer.
*
* This file provides interfaces to perform register and register bit level
* read / write operations. These interfaces support bit-banding in case of
* Cortex-M3 CPU.
*
* SVN $Revision: 5263 $
* SVN $Date: 2013-03-21 14:44:58 +0000 (Thu, 21 Mar 2013) $
*/
#ifndef HW_REG_IO_H_
#define HW_REG_IO_H_
#include <stdint.h> /* Include standard types */
#if defined ( __CC_ARM )
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#endif
/*****************************************************************************************
* Definitions for register access
*/
#define HW_REG(addr) (*((volatile uint32_t *) (addr)))
static __INLINE void write_reg32(volatile uint32_t * reg, uint32_t val)
{
HW_REG(reg) = val;
}
static __INLINE void write_reg16(volatile uint16_t * reg, uint16_t val)
{
HW_REG(reg) = val;
}
static __INLINE void write_reg8(volatile uint8_t * reg, uint8_t val)
{
HW_REG(reg) = val;
}
static __INLINE uint32_t read_reg32(volatile uint32_t * reg)
{
return ( HW_REG(reg) );
}
static __INLINE uint16_t read_reg16(volatile uint16_t * reg)
{
return ( HW_REG(reg) );
}
static __INLINE uint8_t read_reg8(volatile uint8_t * reg)
{
return ( HW_REG(reg) );
}
/*****************************************************************************************
* Definitions for register bits access using bit-band aliases for Cortex-M3
*/
#define BITBAND(addr,bitnum) (((uint32_t)addr & 0xF0000000)+0x02000000+(((uint32_t)addr & 0xFFFFF)<<5)+(bitnum<<2))
#define HW_REG_BIT(reg,bitnum) (*(volatile unsigned int *)((BITBAND(reg,bitnum))))
/*****************************************************************************************
* Functions to set a bit field in Cortex-M3
*/
static __INLINE void set_bit_reg32(volatile uint32_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x1;
}
static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x1;
}
/*****************************************************************************************
* Functions to clear a bit field in Cortex-M3
*/
static __INLINE void clear_bit_reg32(volatile uint32_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x0;
}
static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
HW_REG_BIT(reg,bit) = 0x0;
}
/*****************************************************************************************
* Functions to read a bit field in Cortex-M3
*/
static __INLINE uint8_t read_bit_reg32(volatile uint32_t * reg, uint8_t bit)
{
return (HW_REG_BIT(reg,bit));
}
static __INLINE uint8_t read_bit_reg16(volatile uint16_t * reg, uint8_t bit)
{
return (HW_REG_BIT(reg,bit));
}
static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)
{
return (HW_REG_BIT(reg,bit));
}
#endif /* HW_REG_IO_H_ */
bsp/smartfusion2/CMSIS/m2sxxx.h 0 → 100644
浏览文件 @ 36346218
此差异已折叠。
bsp/smartfusion2/CMSIS/mss_assert.h 0 → 100644
浏览文件 @ 36346218
/*******************************************************************************
* (c) Copyright 2009-2013 Microsemi SoC Products Group. All rights reserved.
*
* Assertion implementation.
*
* This file provides the implementation of the ASSERT macro. This file can be
* modified to cater for project specific requirements regarding the way
* assertions are handled.
*
* SVN $Revision: 6422 $
* SVN $Date: 2014-05-14 14:37:56 +0100 (Wed, 14 May 2014) $
*/
#ifndef __MSS_ASSERT_H_
#define __MSS_ASSERT_H_
#if defined(NDEBUG)
#define ASSERT(CHECK)
#else /* NDEBUG */
#include <assert.h>
#if defined ( __GNUC__ )
/*
* SoftConsole assertion handling
*/
#define ASSERT(CHECK) \
do { \
if (!(CHECK)) \
{ \
__asm volatile ("BKPT\n\t"); \
} \
} while (0);
#elif defined ( __ICCARM__ )
/*
* IAR Embedded Workbench assertion handling.
* Call C library assert function which should result in error message
* displayed in debugger.
*/
#define ASSERT(X) assert(X)
#else
/*
* Keil assertion handling.
* Call C library assert function which should result in error message
* displayed in debugger.
*/
#ifndef __MICROLIB
#define ASSERT(X) assert(X)
#else
#define ASSERT(X)
#endif
#endif /* Tool Chain */
#endif /* NDEBUG */
#endif /* __MSS_ASSERT_H_ */
bsp/smartfusion2/CMSIS/startup_arm/low_level_init.c 0 → 100644
浏览文件 @ 36346218
/*******************************************************************************
* (c) Copyright 2014 Microsemi SoC Products Group. All rights reserved.
*
* Keil-MDK specific system initialization.
*
* SVN $Revision: 7375 $
* SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $
*/
#ifdef MSCC_NO_RELATIVE_PATHS
#include "m2sxxx.h"
#else
#include "..\m2sxxx.h"
#endif
#define ENVM_BASE_ADDRESS 0x60000000U
#define MDDR_BASE_ADDRESS 0xA0000000U
//extern unsigned int Image$$ER_RW$$Base;
//extern unsigned int Image$$ER_RO$$Base;
/*==============================================================================
* The __low_level_init() function is called after SystemInit. Therefore, the
* external RAM should be configured at this stage if it is used.
*/
/* void low_level_init(void)
{
volatile unsigned int rw_region_base;
volatile unsigned int readonly_region_base;
rw_region_base = (unsigned int)&Image$$ER_RW$$Base;
if (rw_region_base >= MDDR_BASE_ADDRESS)
{
/ --------------------------------------------------------------------------
* Remap MDDR to address 0x00000000.
/
SYSREG->ESRAM_CR = 0u;
SYSREG->ENVM_REMAP_BASE_CR = 0u;
SYSREG->DDR_CR = 1u;
}
readonly_region_base = (unsigned int)&Image$$ER_RO$$Base;
SCB->VTOR = readonly_region_base;
} */
bsp/smartfusion2/CMSIS/startup_arm/retarget.c 0 → 100644
浏览文件 @ 36346218
/*******************************************************************************
* (c) Copyright 2013 Microsemi SoC Products Group. All rights reserved.
*
* Redirection of the standard library I/O to one of the SmartFusion2
* MMUART.
*
* SVN $Revision: 7375 $
* SVN $Date: 2015-05-01 14:57:40 +0100 (Fri, 01 May 2015) $
*/
/*==============================================================================
* The content of this source file will only be compiled if either one of the
* following two defined symbols are defined in the project settings:
* - MICROSEMI_STDIO_THRU_MMUART0
* - MICROSEMI_STDIO_THRU_MMUART1
*
*/
#ifdef MICROSEMI_STDIO_THRU_MMUART0
#ifndef MICROSEMI_STDIO_THRU_UART
#define MICROSEMI_STDIO_THRU_UART
#endif
#endif /* MICROSEMI_STDIO_THRU_MMUART0 */
#ifdef MICROSEMI_STDIO_THRU_MMUART1
#ifndef MICROSEMI_STDIO_THRU_UART
#define MICROSEMI_STDIO_THRU_UART
#endif
#endif /* MICROSEMI_STDIO_THRU_MMUART1 */
/*==============================================================================
* Actual implementation.
*/
#ifdef MICROSEMI_STDIO_THRU_UART
#include <stdio.h>
#include <rt_misc.h>
#include "m2sxxx.h"
#include "mss_uart.h"
#include "core_uart_apb.h"
/*
* The baud rate will default to 57600 baud if no baud rate is specified though the
* MICROSEMI_STDIO_BAUD_RATE define.
*/
#ifndef MICROSEMI_STDIO_BAUD_RATE
#define MICROSEMI_STDIO_BAUD_RATE MSS_UART_115200_BAUD
#endif
#ifdef MICROSEMI_STDIO_THRU_MMUART0
static mss_uart_instance_t * const gp_my_uart = &g_mss_uart0;
#else
static mss_uart_instance_t * const gp_my_uart = &g_mss_uart1;
#endif
/*==============================================================================
* Flag used to indicate if the UART driver needs to be initialized.
*/
static int g_stdio_uart_init_done = 0;
#define LSR_THRE_MASK 0x20u
/*
* Disable semihosting apis
*/
#pragma import(__use_no_semihosting_swi)
/*==============================================================================
* sendchar()
*/
int sendchar(int ch)
{
uint32_t tx_ready;
//第一次调用时，初始化串口
if(!g_stdio_uart_init_done)
{
MSS_UART_init(gp_my_uart,
MICROSEMI_STDIO_BAUD_RATE,
MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY);
g_stdio_uart_init_done = 1;
}
do {
tx_ready = gp_my_uart->hw_reg->LSR & LSR_THRE_MASK;
} while(!tx_ready);
gp_my_uart->hw_reg->THR = ch;
return (ch);
}
/*==============================================================================
*
*/
struct __FILE { int handle; /* Add whatever you need here */ };
FILE __stdout;
FILE __stdin;
/*==============================================================================
* fputc()
*/
int fputc(int ch, FILE *f)
{
return (sendchar(ch));
}
/*==============================================================================
* fgetc()
*/
int fgetc(FILE *f)
{
uint8_t rx_size;
uint8_t rx_byte;
do {
rx_size = MSS_UART_get_rx(gp_my_uart, &rx_byte, 1);
} while(0u == rx_size);
return rx_byte;
}
/*==============================================================================
* ferror()
*/
int ferror(FILE *f)
{
/* Your implementation of ferror */
return EOF;
}
/*==============================================================================
* _ttywrch()
*/
void _ttywrch(int ch)
{
sendchar(ch);
}
/*==============================================================================
* _sys_exit()
*/
void _sys_exit(int return_code)
{
for(;;)
{
; /* endless loop */
}
}
#endif /* MICROSEMI_STDIO_THRU_UART */
bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_esram_debug.sct 0 → 100644
浏览文件 @ 36346218
;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for debugging code executing in internal eSRAM.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; * Some current (April 2015) dev kit memory map possibilities are
; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
; * --Some older physical memory map possibilities are
; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
; eNVM=256KB eRAM=64KB External memory = 64MB
RAM_LOAD 0x20000000 0x10000
{
; First half of RAM allocated to RO Execute and data
ER_RO 0x20000000 0x8000
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file
; Second half of RAM allocated to RW data, heap and stack
ER_RW 0x20008000 0x8000
{
.ANY (+RW +ZI)
}
}
bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_execute_in_place.sct 0 → 100644
浏览文件 @ 36346218
;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for executing code in internal eNVM.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; * Some current (April 2015) dev kit memory map possibilities are
; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
; * --Some older physical memory map possibilities are
; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
; eNVM=256KB eRAM=64KB External memory = 64MB
FLASH_LOAD 0x00000000 0x40000
{
; All R only code/data is located in ENVM
ER_RO 0x00000000 0x40000
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file
ER_RW 0x20000000 0x10000
{
.ANY (+RW +ZI)
}
}
bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_mddr_debug.sct 0 → 100644
浏览文件 @ 36346218
;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for debugging code executing in external MDDR.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; * Some current (April 2015) dev kit memory map possibilities are
; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
; * --Some older physical memory map possibilities are
; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
; eNVM=256KB eRAM=64KB External memory = 64MB
; Extern RAM 64M in total
; allocate 1/2 to progam, 1/2 to variable data
RAM_LOAD 0x00000000 0x04000000
{
; Total = 64MB (lowest common amount accross dev kits) 32MB - First half of external memory allocated to RO Code
ER_RO 0x00000000 0x02000000
{
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file as is the case below
STACKS 0x20000000 UNINIT
{
startup_m2sxxx.o (STACK)
}
; 32 MB- Second half of external memory allocated to RW data
ER_RW 0xA2000000 0x02000000
{
.ANY (+RW +ZI)
}
}
bsp/smartfusion2/CMSIS/startup_arm/smartfusion2_relocate_to_external_ram.sct 0 → 100644
浏览文件 @ 36346218
;*******************************************************************************
; (c) Copyright 2015 Microsemi SoC Products Group. All rights reserved.
; SmartFusion2 scatter file for relocating code to external RAM.
;
; SVN $Revision: 7419 $
; SVN $Date: 2015-05-15 16:50:21 +0100 (Fri, 15 May 2015) $
;
; * Some current (April 2015) dev kit memory map possibilities are
; * --Type-------Device-----------address start---address end----size---Dbus--RAM IC-------SF2--Comment---------------
; * --eNVM-------M2S010-----------0x60000000------0x6007FFFF-----256KB---------------------010------------------------
; * --eNVM-------M2S090-----------0x60000000------0x6007FFFF-----512KB---------------------090------------------------
; * --eSRAM------M2Sxxx-----------0x20000000------0x2000FFFF-----64KB----------------------xxx--All have same amount--
; * --eSRAM------M2Sxxx-----------0x20000000------0x20013FFF-----80KB----------------------xxx--If ECC/SECDED not used
; * --Fabric-----M2S010-----------0x30000000------0x6007FFFF-----400Kb---------------------010--note-K bits-----------
; * --Fabric-----M2S090-----------0x30000000------0x6007FFFF-----2074Kb--------------------090--note-K bits-----------
; * --LPDDR------STARTER-KIT------0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----050------------------------
; * --LPDDR------484-STARTER-KIT--0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16-----010------------------------
; * --LPDDR------SEC-EVAL-KIT-----0xA0000000------0xA3FFFFFF-----64MB---16--MT46H32M16LF---090--Security eval kit-----
; * --DDR3-------ADevKit----------0xA0000000------0xBFFFFFFF-----1GB----32--MT41K256M8DA---150------------------------
; * --Some older physical memory map possibilities are
; * --Type-------location---------address start---address end----size---Dbus---RAM IC------SF2--Comment--------------
; * --LPDDR------EVAL KIT---------0xA0000000------0xA3FFFFFF-----64MB-=-16--MT46H32M16LF---025--Eval Kit--------------
; * --DDR3-------DevKit-----------0xA0000000------0xAFFFFFFF-----512MB--16--MT41K256M8DA---050------------------------
;
; Example linker scripts use lowest practicl values so will work accross dev kits
; eNVM=256KB eRAM=64KB External memory = 64MB
FLASH_LOAD 0x60000000 0x40000
{
; All code required on start-up located here before relocation has occured
ER_RO 0x60000000 0x40000
{
*.o (RESET, +First)
*(InRoot$$Sections)
startup_m2sxxx.o
system_m2sxxx.o
sys_config.o
low_level_init.o
sys_config_SERDESIF_?.o
mscc_post_hw_cfg_init.o
ecc_error_handler.o
}
; MDDR_RAM 0xA0000000 0x4000000
; -MDDR is mapped to address space from 0 on startup
; This allows the use of cache which is restriced to this area.
; Code is copied to RAM_EXEC space on startup by boot code.
RAM_EXEC 0x00000000 0x00040000
{
.ANY (+RO)
}
; Heap size is defined in startup_m2sxxx.s
; Heap will be added after RW data in ER_RW unless explicitly
; allocated a meemory region in .sct file
; Stack size is defined in startup_m2sxxx.s
; Stack will be added after heap in ER_RW unless explicitly
; allocated a memory region in .sct file as is the case below
STACKS 0x20000000 UNINIT
{
startup_m2sxxx.o (STACK)
}
; All internal RAM has been allocatd to the stack
; INTERNAL_RAM 0x20008000 0x10000
; {
; .ANY (+RW +ZI)
; }
; MDDR_RAM 0xA0000000 0x4000000 So use top half of this for RW data
; Bottom half has been assigned to R only code already
ER_RW 0xA2000000 0x2000000
{
.ANY (+RW +ZI)
}
}
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/*******************************************************************************
* (c) Copyright 2012-2013 Microsemi SoC Products Group. All rights reserved.
*
* SmartFusion2 CMSIS system initialization.
*
* SVN $Revision: 5280 $
* SVN $Date: 2013-03-22 20:51:50 +0000 (Fri, 22 Mar 2013) $
*/
#ifndef SYSTEM_M2SXXX_H
#define SYSTEM_M2SXXX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Standard CMSIS global variables. */
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/* SmartFusion2 specific clocks. */
extern uint32_t g_FrequencyPCLK0; /*!< Clock frequency of APB bus 0. */
extern uint32_t g_FrequencyPCLK1; /*!< Clock frequency of APB bus 1. */
extern uint32_t g_FrequencyPCLK2; /*!< Clock frequency of APB bus 2. */
extern uint32_t g_FrequencyFIC0; /*!< Clock frequecny of FPGA fabric interface controller 1. */
extern uint32_t g_FrequencyFIC1; /*!< Clock frequecny of FPGA fabric inteface controller 2. */
extern uint32_t g_FrequencyFIC64; /*!< Clock frequecny of 64-bit FPGA fabric interface controller. */
/***************************************************************************//**
* The SystemInit() is a standard CMSIS function called during system startup.
* It is meant to perform low level hardware setup such as configuring DDR and
* SERDES controllers.
*/
void SystemInit(void);
/***************************************************************************//**
* The SystemCoreClockUpdate() is a standard CMSIS function which can be called
* by the application in order to ensure that the SystemCoreClock global
* variable contains the up to date Cortex-M3 core frequency. Calling this
* function also updates the global variables containing the frequencies of the
* APB busses connecting the peripherals.
*/
void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif
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